sdhc.c revision 1.51.2.2
1 /* $NetBSD: sdhc.c,v 1.51.2.2 2015/06/06 14:40:13 skrll Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.51.2.2 2015/06/06 14:40:13 skrll Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/kthread.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/sdmmc/sdhcreg.h> 42 #include <dev/sdmmc/sdhcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #ifdef SDHC_DEBUG 48 int sdhcdebug = 1; 49 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50 void sdhc_dump_regs(struct sdhc_host *); 51 #else 52 #define DPRINTF(n,s) do {} while (0) 53 #endif 54 55 #define SDHC_COMMAND_TIMEOUT hz 56 #define SDHC_BUFFER_TIMEOUT hz 57 #define SDHC_TRANSFER_TIMEOUT hz 58 #define SDHC_DMA_TIMEOUT hz 59 60 struct sdhc_host { 61 struct sdhc_softc *sc; /* host controller device */ 62 63 bus_space_tag_t iot; /* host register set tag */ 64 bus_space_handle_t ioh; /* host register set handle */ 65 bus_size_t ios; /* host register space size */ 66 bus_dma_tag_t dmat; /* host DMA tag */ 67 68 device_t sdmmc; /* generic SD/MMC device */ 69 70 struct kmutex host_mtx; 71 72 u_int clkbase; /* base clock frequency in KHz */ 73 int maxblklen; /* maximum block length */ 74 uint32_t ocr; /* OCR value from capabilities */ 75 76 uint8_t regs[14]; /* host controller state */ 77 78 uint16_t intr_status; /* soft interrupt status */ 79 uint16_t intr_error_status; /* soft error status */ 80 struct kmutex intr_mtx; 81 struct kcondvar intr_cv; 82 83 int specver; /* spec. version */ 84 85 uint32_t flags; /* flags for this host */ 86 #define SHF_USE_DMA 0x0001 87 #define SHF_USE_4BIT_MODE 0x0002 88 #define SHF_USE_8BIT_MODE 0x0004 89 #define SHF_MODE_DMAEN 0x0008 /* needs SDHC_DMA_ENABLE in mode */ 90 }; 91 92 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 93 94 static uint8_t 95 hread1(struct sdhc_host *hp, bus_size_t reg) 96 { 97 98 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 99 return bus_space_read_1(hp->iot, hp->ioh, reg); 100 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 101 } 102 103 static uint16_t 104 hread2(struct sdhc_host *hp, bus_size_t reg) 105 { 106 107 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 108 return bus_space_read_2(hp->iot, hp->ioh, reg); 109 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 110 } 111 112 #define HREAD1(hp, reg) hread1(hp, reg) 113 #define HREAD2(hp, reg) hread2(hp, reg) 114 #define HREAD4(hp, reg) \ 115 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 116 117 118 static void 119 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 120 { 121 122 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 123 bus_space_write_1(hp->iot, hp->ioh, o, val); 124 } else { 125 const size_t shift = 8 * (o & 3); 126 o &= -4; 127 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 128 tmp = (val << shift) | (tmp & ~(0xff << shift)); 129 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 130 } 131 } 132 133 static void 134 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 135 { 136 137 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 138 bus_space_write_2(hp->iot, hp->ioh, o, val); 139 } else { 140 const size_t shift = 8 * (o & 2); 141 o &= -4; 142 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 143 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 144 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 145 } 146 } 147 148 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 149 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 150 #define HWRITE4(hp, reg, val) \ 151 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 152 153 #define HCLR1(hp, reg, bits) \ 154 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 155 #define HCLR2(hp, reg, bits) \ 156 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 157 #define HCLR4(hp, reg, bits) \ 158 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 159 #define HSET1(hp, reg, bits) \ 160 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 161 #define HSET2(hp, reg, bits) \ 162 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 163 #define HSET4(hp, reg, bits) \ 164 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 165 166 static int sdhc_host_reset(sdmmc_chipset_handle_t); 167 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 168 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 169 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 170 static int sdhc_card_detect(sdmmc_chipset_handle_t); 171 static int sdhc_write_protect(sdmmc_chipset_handle_t); 172 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 173 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 174 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 175 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 176 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 177 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 178 static void sdhc_exec_command(sdmmc_chipset_handle_t, 179 struct sdmmc_command *); 180 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 181 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 182 static int sdhc_soft_reset(struct sdhc_host *, int); 183 static int sdhc_wait_intr(struct sdhc_host *, int, int); 184 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 185 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 186 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 187 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 188 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 189 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 190 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 191 192 193 static struct sdmmc_chip_functions sdhc_functions = { 194 /* host controller reset */ 195 sdhc_host_reset, 196 197 /* host controller capabilities */ 198 sdhc_host_ocr, 199 sdhc_host_maxblklen, 200 201 /* card detection */ 202 sdhc_card_detect, 203 204 /* write protect */ 205 sdhc_write_protect, 206 207 /* bus power, clock frequency and width */ 208 sdhc_bus_power, 209 sdhc_bus_clock, 210 sdhc_bus_width, 211 sdhc_bus_rod, 212 213 /* command execution */ 214 sdhc_exec_command, 215 216 /* card interrupt */ 217 sdhc_card_enable_intr, 218 sdhc_card_intr_ack 219 }; 220 221 static int 222 sdhc_cfprint(void *aux, const char *pnp) 223 { 224 const struct sdmmcbus_attach_args * const saa = aux; 225 const struct sdhc_host * const hp = saa->saa_sch; 226 227 if (pnp) { 228 aprint_normal("sdmmc at %s", pnp); 229 } 230 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 231 if (hp->sc->sc_host[host] == hp) { 232 aprint_normal(" slot %zu", host); 233 } 234 } 235 236 return UNCONF; 237 } 238 239 /* 240 * Called by attachment driver. For each SD card slot there is one SD 241 * host controller standard register set. (1.3) 242 */ 243 int 244 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 245 bus_space_handle_t ioh, bus_size_t iosize) 246 { 247 struct sdmmcbus_attach_args saa; 248 struct sdhc_host *hp; 249 uint32_t caps; 250 uint16_t sdhcver; 251 252 /* Allocate one more host structure. */ 253 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 254 if (hp == NULL) { 255 aprint_error_dev(sc->sc_dev, 256 "couldn't alloc memory (sdhc host)\n"); 257 goto err1; 258 } 259 sc->sc_host[sc->sc_nhosts++] = hp; 260 261 /* Fill in the new host structure. */ 262 hp->sc = sc; 263 hp->iot = iot; 264 hp->ioh = ioh; 265 hp->ios = iosize; 266 hp->dmat = sc->sc_dmat; 267 268 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 269 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 270 cv_init(&hp->intr_cv, "sdhcintr"); 271 272 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 273 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); 274 } else { 275 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 276 } 277 aprint_normal_dev(sc->sc_dev, "SDHC "); 278 hp->specver = SDHC_SPEC_VERSION(sdhcver); 279 switch (SDHC_SPEC_VERSION(sdhcver)) { 280 case SDHC_SPEC_VERS_100: 281 aprint_normal("1.0"); 282 break; 283 284 case SDHC_SPEC_VERS_200: 285 aprint_normal("2.0"); 286 break; 287 288 case SDHC_SPEC_VERS_300: 289 aprint_normal("3.0"); 290 break; 291 292 case SDHC_SPEC_VERS_400: 293 aprint_normal("4.0"); 294 break; 295 296 default: 297 aprint_normal("unknown version(0x%x)", 298 SDHC_SPEC_VERSION(sdhcver)); 299 break; 300 } 301 aprint_normal(", rev %u", SDHC_VENDOR_VERSION(sdhcver)); 302 303 /* 304 * Reset the host controller and enable interrupts. 305 */ 306 (void)sdhc_host_reset(hp); 307 308 /* Determine host capabilities. */ 309 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 310 caps = sc->sc_caps; 311 } else { 312 mutex_enter(&hp->host_mtx); 313 caps = HREAD4(hp, SDHC_CAPABILITIES); 314 mutex_exit(&hp->host_mtx); 315 } 316 317 /* 318 * Use DMA if the host system and the controller support it. 319 * Suports integrated or external DMA egine, with or without 320 * SDHC_DMA_ENABLE in the command. 321 */ 322 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 323 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 324 ISSET(caps, SDHC_DMA_SUPPORT)))) { 325 SET(hp->flags, SHF_USE_DMA); 326 if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) || 327 ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN)) 328 SET(hp->flags, SHF_MODE_DMAEN); 329 330 aprint_normal(", DMA"); 331 } else { 332 aprint_normal(", PIO"); 333 } 334 335 /* 336 * Determine the base clock frequency. (2.2.24) 337 */ 338 if (hp->specver >= SDHC_SPEC_VERS_300) { 339 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 340 } else { 341 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 342 } 343 if (hp->clkbase == 0 || 344 ISSET(sc->sc_flags, SDHC_FLAG_NO_CLKBASE)) { 345 if (sc->sc_clkbase == 0) { 346 /* The attachment driver must tell us. */ 347 aprint_error_dev(sc->sc_dev, 348 "unknown base clock frequency\n"); 349 goto err; 350 } 351 hp->clkbase = sc->sc_clkbase; 352 } 353 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 354 /* SDHC 1.0 supports only 10-63 MHz. */ 355 aprint_error_dev(sc->sc_dev, 356 "base clock frequency out of range: %u MHz\n", 357 hp->clkbase / 1000); 358 goto err; 359 } 360 aprint_normal(", %u kHz", hp->clkbase); 361 362 /* 363 * XXX Set the data timeout counter value according to 364 * capabilities. (2.2.15) 365 */ 366 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 367 #if 1 368 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 369 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 370 #endif 371 372 if (ISSET(caps, SDHC_EMBEDDED_SLOT)) 373 aprint_normal(", embedded slot"); 374 375 /* 376 * Determine SD bus voltage levels supported by the controller. 377 */ 378 aprint_normal(","); 379 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V) && 380 (hp->specver < SDHC_SPEC_VERS_300 || 381 ISSET(caps, SDHC_EMBEDDED_SLOT))) { 382 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 383 aprint_normal(" 1.8V"); 384 } 385 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 386 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 387 aprint_normal(" 3.0V"); 388 } 389 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 390 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 391 aprint_normal(" 3.3V"); 392 } 393 394 /* 395 * Determine the maximum block length supported by the host 396 * controller. (2.2.24) 397 */ 398 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 399 case SDHC_MAX_BLK_LEN_512: 400 hp->maxblklen = 512; 401 break; 402 403 case SDHC_MAX_BLK_LEN_1024: 404 hp->maxblklen = 1024; 405 break; 406 407 case SDHC_MAX_BLK_LEN_2048: 408 hp->maxblklen = 2048; 409 break; 410 411 case SDHC_MAX_BLK_LEN_4096: 412 hp->maxblklen = 4096; 413 break; 414 415 default: 416 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 417 goto err; 418 } 419 aprint_normal(", %u byte blocks", hp->maxblklen); 420 aprint_normal("\n"); 421 422 /* 423 * Attach the generic SD/MMC bus driver. (The bus driver must 424 * not invoke any chipset functions before it is attached.) 425 */ 426 memset(&saa, 0, sizeof(saa)); 427 saa.saa_busname = "sdmmc"; 428 saa.saa_sct = &sdhc_functions; 429 saa.saa_sch = hp; 430 saa.saa_dmat = hp->dmat; 431 saa.saa_clkmax = hp->clkbase; 432 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 433 saa.saa_clkmin = hp->clkbase / 256 / 2046; 434 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 435 saa.saa_clkmin = hp->clkbase / 256 / 16; 436 else if (hp->sc->sc_clkmsk != 0) 437 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 438 (ffs(hp->sc->sc_clkmsk) - 1)); 439 else if (hp->specver >= SDHC_SPEC_VERS_300) 440 saa.saa_clkmin = hp->clkbase / 0x3ff; 441 else 442 saa.saa_clkmin = hp->clkbase / 256; 443 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 444 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 445 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 446 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 447 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 448 if (ISSET(hp->flags, SHF_USE_DMA)) { 449 saa.saa_caps |= SMC_CAPS_DMA; 450 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 451 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 452 } 453 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 454 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 455 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 456 457 return 0; 458 459 err: 460 cv_destroy(&hp->intr_cv); 461 mutex_destroy(&hp->intr_mtx); 462 mutex_destroy(&hp->host_mtx); 463 free(hp, M_DEVBUF); 464 sc->sc_host[--sc->sc_nhosts] = NULL; 465 err1: 466 return 1; 467 } 468 469 int 470 sdhc_detach(struct sdhc_softc *sc, int flags) 471 { 472 struct sdhc_host *hp; 473 int rv = 0; 474 475 for (size_t n = 0; n < sc->sc_nhosts; n++) { 476 hp = sc->sc_host[n]; 477 if (hp == NULL) 478 continue; 479 if (hp->sdmmc != NULL) { 480 rv = config_detach(hp->sdmmc, flags); 481 if (rv) 482 break; 483 hp->sdmmc = NULL; 484 } 485 /* disable interrupts */ 486 if ((flags & DETACH_FORCE) == 0) { 487 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 488 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 489 } else { 490 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 491 } 492 sdhc_soft_reset(hp, SDHC_RESET_ALL); 493 } 494 cv_destroy(&hp->intr_cv); 495 mutex_destroy(&hp->intr_mtx); 496 mutex_destroy(&hp->host_mtx); 497 if (hp->ios > 0) { 498 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 499 hp->ios = 0; 500 } 501 free(hp, M_DEVBUF); 502 sc->sc_host[n] = NULL; 503 } 504 505 return rv; 506 } 507 508 bool 509 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 510 { 511 struct sdhc_softc *sc = device_private(dev); 512 struct sdhc_host *hp; 513 size_t i; 514 515 /* XXX poll for command completion or suspend command 516 * in progress */ 517 518 /* Save the host controller state. */ 519 for (size_t n = 0; n < sc->sc_nhosts; n++) { 520 hp = sc->sc_host[n]; 521 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 522 for (i = 0; i < sizeof hp->regs; i += 4) { 523 uint32_t v = HREAD4(hp, i); 524 hp->regs[i + 0] = (v >> 0); 525 hp->regs[i + 1] = (v >> 8); 526 if (i + 3 < sizeof hp->regs) { 527 hp->regs[i + 2] = (v >> 16); 528 hp->regs[i + 3] = (v >> 24); 529 } 530 } 531 } else { 532 for (i = 0; i < sizeof hp->regs; i++) { 533 hp->regs[i] = HREAD1(hp, i); 534 } 535 } 536 } 537 return true; 538 } 539 540 bool 541 sdhc_resume(device_t dev, const pmf_qual_t *qual) 542 { 543 struct sdhc_softc *sc = device_private(dev); 544 struct sdhc_host *hp; 545 size_t i; 546 547 /* Restore the host controller state. */ 548 for (size_t n = 0; n < sc->sc_nhosts; n++) { 549 hp = sc->sc_host[n]; 550 (void)sdhc_host_reset(hp); 551 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 552 for (i = 0; i < sizeof hp->regs; i += 4) { 553 if (i + 3 < sizeof hp->regs) { 554 HWRITE4(hp, i, 555 (hp->regs[i + 0] << 0) 556 | (hp->regs[i + 1] << 8) 557 | (hp->regs[i + 2] << 16) 558 | (hp->regs[i + 3] << 24)); 559 } else { 560 HWRITE4(hp, i, 561 (hp->regs[i + 0] << 0) 562 | (hp->regs[i + 1] << 8)); 563 } 564 } 565 } else { 566 for (i = 0; i < sizeof hp->regs; i++) { 567 HWRITE1(hp, i, hp->regs[i]); 568 } 569 } 570 } 571 return true; 572 } 573 574 bool 575 sdhc_shutdown(device_t dev, int flags) 576 { 577 struct sdhc_softc *sc = device_private(dev); 578 struct sdhc_host *hp; 579 580 /* XXX chip locks up if we don't disable it before reboot. */ 581 for (size_t i = 0; i < sc->sc_nhosts; i++) { 582 hp = sc->sc_host[i]; 583 (void)sdhc_host_reset(hp); 584 } 585 return true; 586 } 587 588 /* 589 * Reset the host controller. Called during initialization, when 590 * cards are removed, upon resume, and during error recovery. 591 */ 592 static int 593 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 594 { 595 struct sdhc_host *hp = (struct sdhc_host *)sch; 596 uint32_t sdhcimask; 597 int error; 598 599 /* Don't lock. */ 600 601 /* Disable all interrupts. */ 602 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 603 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 604 } else { 605 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 606 } 607 608 /* 609 * Reset the entire host controller and wait up to 100ms for 610 * the controller to clear the reset bit. 611 */ 612 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 613 if (error) 614 goto out; 615 616 /* Set data timeout counter value to max for now. */ 617 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 618 #if 1 619 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 620 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 621 #endif 622 623 /* Enable interrupts. */ 624 mutex_enter(&hp->intr_mtx); 625 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 626 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 627 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 628 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 629 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 630 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 631 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 632 sdhcimask ^= 633 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 634 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 635 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 636 } else { 637 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 638 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 639 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 640 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 641 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 642 } 643 mutex_exit(&hp->intr_mtx); 644 645 out: 646 return error; 647 } 648 649 static int 650 sdhc_host_reset(sdmmc_chipset_handle_t sch) 651 { 652 struct sdhc_host *hp = (struct sdhc_host *)sch; 653 int error; 654 655 mutex_enter(&hp->host_mtx); 656 error = sdhc_host_reset1(sch); 657 mutex_exit(&hp->host_mtx); 658 659 return error; 660 } 661 662 static uint32_t 663 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 664 { 665 struct sdhc_host *hp = (struct sdhc_host *)sch; 666 667 return hp->ocr; 668 } 669 670 static int 671 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 672 { 673 struct sdhc_host *hp = (struct sdhc_host *)sch; 674 675 return hp->maxblklen; 676 } 677 678 /* 679 * Return non-zero if the card is currently inserted. 680 */ 681 static int 682 sdhc_card_detect(sdmmc_chipset_handle_t sch) 683 { 684 struct sdhc_host *hp = (struct sdhc_host *)sch; 685 int r; 686 687 if (hp->sc->sc_vendor_card_detect) 688 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 689 690 mutex_enter(&hp->host_mtx); 691 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 692 mutex_exit(&hp->host_mtx); 693 694 return r ? 1 : 0; 695 } 696 697 /* 698 * Return non-zero if the card is currently write-protected. 699 */ 700 static int 701 sdhc_write_protect(sdmmc_chipset_handle_t sch) 702 { 703 struct sdhc_host *hp = (struct sdhc_host *)sch; 704 int r; 705 706 if (hp->sc->sc_vendor_write_protect) 707 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 708 709 mutex_enter(&hp->host_mtx); 710 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 711 mutex_exit(&hp->host_mtx); 712 713 return r ? 0 : 1; 714 } 715 716 /* 717 * Set or change SD bus voltage and enable or disable SD bus power. 718 * Return zero on success. 719 */ 720 static int 721 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 722 { 723 struct sdhc_host *hp = (struct sdhc_host *)sch; 724 uint8_t vdd; 725 int error = 0; 726 const uint32_t pcmask = 727 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 728 729 mutex_enter(&hp->host_mtx); 730 731 /* 732 * Disable bus power before voltage change. 733 */ 734 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 735 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 736 HWRITE1(hp, SDHC_POWER_CTL, 0); 737 738 /* If power is disabled, reset the host and return now. */ 739 if (ocr == 0) { 740 (void)sdhc_host_reset1(hp); 741 goto out; 742 } 743 744 /* 745 * Select the lowest voltage according to capabilities. 746 */ 747 ocr &= hp->ocr; 748 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 749 vdd = SDHC_VOLTAGE_1_8V; 750 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 751 vdd = SDHC_VOLTAGE_3_0V; 752 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 753 vdd = SDHC_VOLTAGE_3_3V; 754 } else { 755 /* Unsupported voltage level requested. */ 756 error = EINVAL; 757 goto out; 758 } 759 760 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 761 /* 762 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 763 * voltage ramp until power rises. 764 */ 765 766 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SINGLE_POWER_WRITE)) { 767 HWRITE1(hp, SDHC_POWER_CTL, 768 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 769 } else { 770 HWRITE1(hp, SDHC_POWER_CTL, 771 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 772 sdmmc_delay(1); 773 HWRITE1(hp, SDHC_POWER_CTL, 774 (vdd << SDHC_VOLTAGE_SHIFT)); 775 sdmmc_delay(1); 776 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 777 sdmmc_delay(10000); 778 } 779 780 /* 781 * The host system may not power the bus due to battery low, 782 * etc. In that case, the host controller should clear the 783 * bus power bit. 784 */ 785 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 786 error = ENXIO; 787 goto out; 788 } 789 } 790 791 out: 792 mutex_exit(&hp->host_mtx); 793 794 return error; 795 } 796 797 /* 798 * Return the smallest possible base clock frequency divisor value 799 * for the CLOCK_CTL register to produce `freq' (KHz). 800 */ 801 static bool 802 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 803 { 804 u_int div; 805 806 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 807 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 808 if ((hp->clkbase / div) <= freq) { 809 *divp = SDHC_SDCLK_CGM 810 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 811 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 812 //freq = hp->clkbase / div; 813 return true; 814 } 815 } 816 /* No divisor found. */ 817 return false; 818 } 819 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 820 u_int dvs = (hp->clkbase + freq - 1) / freq; 821 u_int roundup = dvs & 1; 822 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 823 if (dvs + roundup <= 16) { 824 dvs += roundup - 1; 825 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 826 | (dvs << SDHC_SDCLK_DVS_SHIFT); 827 DPRINTF(2, 828 ("%s: divisor for freq %u is %u * %u\n", 829 HDEVNAME(hp), freq, div * 2, dvs + 1)); 830 //freq = hp->clkbase / (div * 2) * (dvs + 1); 831 return true; 832 } 833 /* 834 * If we drop bits, we need to round up the divisor. 835 */ 836 roundup |= dvs & 1; 837 } 838 /* No divisor found. */ 839 return false; 840 } 841 if (hp->sc->sc_clkmsk != 0) { 842 div = howmany(hp->clkbase, freq); 843 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 844 return false; 845 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 846 //freq = hp->clkbase / div; 847 return true; 848 } 849 if (hp->specver >= SDHC_SPEC_VERS_300) { 850 div = howmany(hp->clkbase, freq); 851 div = div > 1 ? howmany(div, 2) : 0; 852 if (div > 0x3ff) 853 return false; 854 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 855 << SDHC_SDCLK_XDIV_SHIFT) | 856 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 857 << SDHC_SDCLK_DIV_SHIFT); 858 //freq = hp->clkbase / div; 859 return true; 860 } else { 861 for (div = 1; div <= 256; div *= 2) { 862 if ((hp->clkbase / div) <= freq) { 863 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 864 //freq = hp->clkbase / div; 865 return true; 866 } 867 } 868 /* No divisor found. */ 869 return false; 870 } 871 /* No divisor found. */ 872 return false; 873 } 874 875 /* 876 * Set or change SDCLK frequency or disable the SD clock. 877 * Return zero on success. 878 */ 879 static int 880 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 881 { 882 struct sdhc_host *hp = (struct sdhc_host *)sch; 883 u_int div; 884 u_int timo; 885 int16_t reg; 886 int error = 0; 887 #ifdef DIAGNOSTIC 888 bool present; 889 890 mutex_enter(&hp->host_mtx); 891 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 892 mutex_exit(&hp->host_mtx); 893 894 /* Must not stop the clock if commands are in progress. */ 895 if (present && sdhc_card_detect(hp)) { 896 aprint_normal_dev(hp->sc->sc_dev, 897 "%s: command in progress\n", __func__); 898 } 899 #endif 900 901 mutex_enter(&hp->host_mtx); 902 903 if (hp->sc->sc_vendor_bus_clock) { 904 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 905 if (error != 0) 906 goto out; 907 } 908 909 /* 910 * Stop SD clock before changing the frequency. 911 */ 912 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 913 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 914 if (freq == SDMMC_SDCLK_OFF) { 915 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 916 goto out; 917 } 918 } else { 919 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 920 if (freq == SDMMC_SDCLK_OFF) 921 goto out; 922 } 923 924 /* 925 * Set the minimum base clock frequency divisor. 926 */ 927 if (!sdhc_clock_divisor(hp, freq, &div)) { 928 /* Invalid base clock frequency or `freq' value. */ 929 error = EINVAL; 930 goto out; 931 } 932 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 933 HWRITE4(hp, SDHC_CLOCK_CTL, 934 div | (SDHC_TIMEOUT_MAX << 16)); 935 } else { 936 reg = HREAD2(hp, SDHC_CLOCK_CTL); 937 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 938 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 939 } 940 941 /* 942 * Start internal clock. Wait 10ms for stabilization. 943 */ 944 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 945 sdmmc_delay(10000); 946 HSET4(hp, SDHC_CLOCK_CTL, 947 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 948 } else { 949 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 950 for (timo = 1000; timo > 0; timo--) { 951 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 952 SDHC_INTCLK_STABLE)) 953 break; 954 sdmmc_delay(10); 955 } 956 if (timo == 0) { 957 error = ETIMEDOUT; 958 goto out; 959 } 960 } 961 962 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 963 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 964 /* 965 * Sending 80 clocks at 400kHz takes 200us. 966 * So delay for that time + slop and then 967 * check a few times for completion. 968 */ 969 sdmmc_delay(210); 970 for (timo = 10; timo > 0; timo--) { 971 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 972 SDHC_INIT_ACTIVE)) 973 break; 974 sdmmc_delay(10); 975 } 976 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 977 978 /* 979 * Enable SD clock. 980 */ 981 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 982 } else { 983 /* 984 * Enable SD clock. 985 */ 986 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 987 988 if (freq > 25000 && 989 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 990 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 991 else 992 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 993 } 994 995 out: 996 mutex_exit(&hp->host_mtx); 997 998 return error; 999 } 1000 1001 static int 1002 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 1003 { 1004 struct sdhc_host *hp = (struct sdhc_host *)sch; 1005 int reg; 1006 1007 switch (width) { 1008 case 1: 1009 case 4: 1010 break; 1011 1012 case 8: 1013 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 1014 break; 1015 /* FALLTHROUGH */ 1016 default: 1017 DPRINTF(0,("%s: unsupported bus width (%d)\n", 1018 HDEVNAME(hp), width)); 1019 return 1; 1020 } 1021 1022 mutex_enter(&hp->host_mtx); 1023 reg = HREAD1(hp, SDHC_HOST_CTL); 1024 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1025 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 1026 if (width == 4) 1027 reg |= SDHC_4BIT_MODE; 1028 else if (width == 8) 1029 reg |= SDHC_ESDHC_8BIT_MODE; 1030 } else { 1031 reg &= ~SDHC_4BIT_MODE; 1032 if (hp->specver >= SDHC_SPEC_VERS_300) { 1033 reg &= ~SDHC_8BIT_MODE; 1034 } 1035 if (width == 4) { 1036 reg |= SDHC_4BIT_MODE; 1037 } else if (width == 8 && hp->specver >= SDHC_SPEC_VERS_300) { 1038 reg |= SDHC_8BIT_MODE; 1039 } 1040 } 1041 HWRITE1(hp, SDHC_HOST_CTL, reg); 1042 mutex_exit(&hp->host_mtx); 1043 1044 return 0; 1045 } 1046 1047 static int 1048 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1049 { 1050 struct sdhc_host *hp = (struct sdhc_host *)sch; 1051 1052 if (hp->sc->sc_vendor_rod) 1053 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1054 1055 return 0; 1056 } 1057 1058 static void 1059 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1060 { 1061 struct sdhc_host *hp = (struct sdhc_host *)sch; 1062 1063 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1064 mutex_enter(&hp->intr_mtx); 1065 if (enable) { 1066 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1067 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1068 } else { 1069 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1070 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1071 } 1072 mutex_exit(&hp->intr_mtx); 1073 } 1074 } 1075 1076 static void 1077 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1078 { 1079 struct sdhc_host *hp = (struct sdhc_host *)sch; 1080 1081 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1082 mutex_enter(&hp->intr_mtx); 1083 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1084 mutex_exit(&hp->intr_mtx); 1085 } 1086 } 1087 1088 static int 1089 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1090 { 1091 uint32_t state; 1092 int timeout; 1093 1094 for (timeout = 10; timeout > 0; timeout--) { 1095 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 1096 return 0; 1097 sdmmc_delay(10000); 1098 } 1099 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 1100 value, state)); 1101 return ETIMEDOUT; 1102 } 1103 1104 static void 1105 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1106 { 1107 struct sdhc_host *hp = (struct sdhc_host *)sch; 1108 int error; 1109 1110 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1111 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1112 mutex_enter(&hp->intr_mtx); 1113 if (ISSET(hp->flags, SHF_USE_DMA)) { 1114 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1115 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1116 } else { 1117 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1118 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1119 } 1120 mutex_exit(&hp->intr_mtx); 1121 } 1122 1123 /* 1124 * Start the MMC command, or mark `cmd' as failed and return. 1125 */ 1126 error = sdhc_start_command(hp, cmd); 1127 if (error) { 1128 cmd->c_error = error; 1129 goto out; 1130 } 1131 1132 /* 1133 * Wait until the command phase is done, or until the command 1134 * is marked done for any other reason. 1135 */ 1136 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1137 cmd->c_error = ETIMEDOUT; 1138 goto out; 1139 } 1140 1141 /* 1142 * The host controller removes bits [0:7] from the response 1143 * data (CRC) and we pass the data up unchanged to the bus 1144 * driver (without padding). 1145 */ 1146 mutex_enter(&hp->host_mtx); 1147 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1148 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1149 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1150 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1151 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1152 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1153 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1154 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1155 (cmd->c_resp[1] << 24); 1156 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1157 (cmd->c_resp[2] << 24); 1158 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1159 (cmd->c_resp[3] << 24); 1160 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1161 } 1162 } 1163 } 1164 mutex_exit(&hp->host_mtx); 1165 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1166 1167 /* 1168 * If the command has data to transfer in any direction, 1169 * execute the transfer now. 1170 */ 1171 if (cmd->c_error == 0 && cmd->c_data != NULL) 1172 sdhc_transfer_data(hp, cmd); 1173 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1174 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10)) { 1175 cmd->c_error = ETIMEDOUT; 1176 goto out; 1177 } 1178 } 1179 1180 out: 1181 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1182 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1183 mutex_enter(&hp->host_mtx); 1184 /* Turn off the LED. */ 1185 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1186 mutex_exit(&hp->host_mtx); 1187 } 1188 SET(cmd->c_flags, SCF_ITSDONE); 1189 1190 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1191 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1192 cmd->c_flags, cmd->c_error)); 1193 } 1194 1195 static int 1196 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1197 { 1198 struct sdhc_softc * const sc = hp->sc; 1199 uint16_t blksize = 0; 1200 uint16_t blkcount = 0; 1201 uint16_t mode; 1202 uint16_t command; 1203 int error; 1204 1205 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1206 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1207 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1208 1209 /* 1210 * The maximum block length for commands should be the minimum 1211 * of the host buffer size and the card buffer size. (1.7.2) 1212 */ 1213 1214 /* Fragment the data into proper blocks. */ 1215 if (cmd->c_datalen > 0) { 1216 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1217 blkcount = cmd->c_datalen / blksize; 1218 if (cmd->c_datalen % blksize > 0) { 1219 /* XXX: Split this command. (1.7.4) */ 1220 aprint_error_dev(sc->sc_dev, 1221 "data not a multiple of %u bytes\n", blksize); 1222 return EINVAL; 1223 } 1224 } 1225 1226 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1227 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1228 aprint_error_dev(sc->sc_dev, "too much data\n"); 1229 return EINVAL; 1230 } 1231 1232 /* Prepare transfer mode register value. (2.2.5) */ 1233 mode = SDHC_BLOCK_COUNT_ENABLE; 1234 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1235 mode |= SDHC_READ_MODE; 1236 if (blkcount > 1) { 1237 mode |= SDHC_MULTI_BLOCK_MODE; 1238 /* XXX only for memory commands? */ 1239 mode |= SDHC_AUTO_CMD12_ENABLE; 1240 } 1241 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1242 ISSET(hp->flags, SHF_MODE_DMAEN)) { 1243 mode |= SDHC_DMA_ENABLE; 1244 } 1245 1246 /* 1247 * Prepare command register value. (2.2.6) 1248 */ 1249 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1250 1251 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1252 command |= SDHC_CRC_CHECK_ENABLE; 1253 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1254 command |= SDHC_INDEX_CHECK_ENABLE; 1255 if (cmd->c_data != NULL) 1256 command |= SDHC_DATA_PRESENT_SELECT; 1257 1258 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1259 command |= SDHC_NO_RESPONSE; 1260 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1261 command |= SDHC_RESP_LEN_136; 1262 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1263 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1264 else 1265 command |= SDHC_RESP_LEN_48; 1266 1267 /* Wait until command and data inhibit bits are clear. (1.5) */ 1268 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1269 if (error) 1270 return error; 1271 1272 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1273 HDEVNAME(hp), blksize, blkcount, mode, command)); 1274 1275 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1276 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1277 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1278 } 1279 1280 mutex_enter(&hp->host_mtx); 1281 1282 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1283 /* Alert the user not to remove the card. */ 1284 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1285 } 1286 1287 /* Set DMA start address. */ 1288 if (ISSET(mode, SDHC_DMA_ENABLE) && 1289 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) 1290 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1291 1292 /* 1293 * Start a CPU data transfer. Writing to the high order byte 1294 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1295 */ 1296 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1297 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1298 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1299 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1300 } else { 1301 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1302 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1303 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1304 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1305 HWRITE2(hp, SDHC_COMMAND, command); 1306 } 1307 1308 mutex_exit(&hp->host_mtx); 1309 1310 return 0; 1311 } 1312 1313 static void 1314 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1315 { 1316 struct sdhc_softc *sc = hp->sc; 1317 int error; 1318 1319 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1320 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1321 1322 #ifdef SDHC_DEBUG 1323 /* XXX I forgot why I wanted to know when this happens :-( */ 1324 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1325 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1326 aprint_error_dev(hp->sc->sc_dev, 1327 "CMD52/53 error response flags %#x\n", 1328 MMC_R1(cmd->c_resp) & 0xff00); 1329 } 1330 #endif 1331 1332 if (cmd->c_dmamap != NULL) { 1333 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1334 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd); 1335 if (error == 0 && !sdhc_wait_intr(hp, 1336 SDHC_TRANSFER_COMPLETE, SDHC_TRANSFER_TIMEOUT)) { 1337 error = ETIMEDOUT; 1338 } 1339 } else { 1340 error = sdhc_transfer_data_dma(hp, cmd); 1341 } 1342 } else 1343 error = sdhc_transfer_data_pio(hp, cmd); 1344 if (error) 1345 cmd->c_error = error; 1346 SET(cmd->c_flags, SCF_ITSDONE); 1347 1348 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1349 HDEVNAME(hp), cmd->c_error)); 1350 } 1351 1352 static int 1353 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1354 { 1355 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1356 bus_addr_t posaddr; 1357 bus_addr_t segaddr; 1358 bus_size_t seglen; 1359 u_int seg = 0; 1360 int error = 0; 1361 int status; 1362 1363 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1364 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1365 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1366 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1367 1368 for (;;) { 1369 status = sdhc_wait_intr(hp, 1370 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1371 SDHC_DMA_TIMEOUT); 1372 1373 if (status & SDHC_TRANSFER_COMPLETE) { 1374 break; 1375 } 1376 if (!status) { 1377 error = ETIMEDOUT; 1378 break; 1379 } 1380 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1381 continue; 1382 } 1383 1384 /* DMA Interrupt (boundary crossing) */ 1385 1386 segaddr = dm_segs[seg].ds_addr; 1387 seglen = dm_segs[seg].ds_len; 1388 mutex_enter(&hp->host_mtx); 1389 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1390 mutex_exit(&hp->host_mtx); 1391 1392 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1393 continue; 1394 } 1395 mutex_enter(&hp->host_mtx); 1396 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1397 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1398 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1399 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1400 mutex_exit(&hp->host_mtx); 1401 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1402 } 1403 1404 return error; 1405 } 1406 1407 static int 1408 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1409 { 1410 uint8_t *data = cmd->c_data; 1411 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1412 u_int len, datalen; 1413 u_int imask; 1414 u_int pmask; 1415 int error = 0; 1416 1417 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1418 imask = SDHC_BUFFER_READ_READY; 1419 pmask = SDHC_BUFFER_READ_ENABLE; 1420 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1421 pio_func = esdhc_read_data_pio; 1422 } else { 1423 pio_func = sdhc_read_data_pio; 1424 } 1425 } else { 1426 imask = SDHC_BUFFER_WRITE_READY; 1427 pmask = SDHC_BUFFER_WRITE_ENABLE; 1428 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1429 pio_func = esdhc_write_data_pio; 1430 } else { 1431 pio_func = sdhc_write_data_pio; 1432 } 1433 } 1434 datalen = cmd->c_datalen; 1435 1436 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1437 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1438 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1439 1440 while (datalen > 0) { 1441 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1442 mutex_enter(&hp->intr_mtx); 1443 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1444 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1445 } else { 1446 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1447 } 1448 mutex_exit(&hp->intr_mtx); 1449 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1450 error = ETIMEDOUT; 1451 break; 1452 } 1453 1454 error = sdhc_wait_state(hp, pmask, pmask); 1455 if (error) 1456 break; 1457 } 1458 1459 len = MIN(datalen, cmd->c_blklen); 1460 (*pio_func)(hp, data, len); 1461 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1462 HDEVNAME(hp), len, data)); 1463 1464 data += len; 1465 datalen -= len; 1466 } 1467 1468 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1469 SDHC_TRANSFER_TIMEOUT)) 1470 error = ETIMEDOUT; 1471 1472 return error; 1473 } 1474 1475 static void 1476 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1477 { 1478 1479 if (((__uintptr_t)data & 3) == 0) { 1480 while (datalen > 3) { 1481 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1482 data += 4; 1483 datalen -= 4; 1484 } 1485 if (datalen > 1) { 1486 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1487 data += 2; 1488 datalen -= 2; 1489 } 1490 if (datalen > 0) { 1491 *data = HREAD1(hp, SDHC_DATA); 1492 data += 1; 1493 datalen -= 1; 1494 } 1495 } else if (((__uintptr_t)data & 1) == 0) { 1496 while (datalen > 1) { 1497 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1498 data += 2; 1499 datalen -= 2; 1500 } 1501 if (datalen > 0) { 1502 *data = HREAD1(hp, SDHC_DATA); 1503 data += 1; 1504 datalen -= 1; 1505 } 1506 } else { 1507 while (datalen > 0) { 1508 *data = HREAD1(hp, SDHC_DATA); 1509 data += 1; 1510 datalen -= 1; 1511 } 1512 } 1513 } 1514 1515 static void 1516 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1517 { 1518 1519 if (((__uintptr_t)data & 3) == 0) { 1520 while (datalen > 3) { 1521 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 1522 data += 4; 1523 datalen -= 4; 1524 } 1525 if (datalen > 1) { 1526 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1527 data += 2; 1528 datalen -= 2; 1529 } 1530 if (datalen > 0) { 1531 HWRITE1(hp, SDHC_DATA, *data); 1532 data += 1; 1533 datalen -= 1; 1534 } 1535 } else if (((__uintptr_t)data & 1) == 0) { 1536 while (datalen > 1) { 1537 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1538 data += 2; 1539 datalen -= 2; 1540 } 1541 if (datalen > 0) { 1542 HWRITE1(hp, SDHC_DATA, *data); 1543 data += 1; 1544 datalen -= 1; 1545 } 1546 } else { 1547 while (datalen > 0) { 1548 HWRITE1(hp, SDHC_DATA, *data); 1549 data += 1; 1550 datalen -= 1; 1551 } 1552 } 1553 } 1554 1555 static void 1556 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1557 { 1558 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1559 uint32_t v; 1560 1561 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1562 size_t count = 0; 1563 1564 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1565 if (count == 0) { 1566 /* 1567 * If we've drained "watermark" words, we need to wait 1568 * a little bit so the read FIFO can refill. 1569 */ 1570 sdmmc_delay(10); 1571 count = watermark; 1572 } 1573 v = HREAD4(hp, SDHC_DATA); 1574 v = le32toh(v); 1575 *(uint32_t *)data = v; 1576 data += 4; 1577 datalen -= 4; 1578 status = HREAD2(hp, SDHC_NINTR_STATUS); 1579 count--; 1580 } 1581 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1582 if (count == 0) { 1583 sdmmc_delay(10); 1584 } 1585 v = HREAD4(hp, SDHC_DATA); 1586 v = le32toh(v); 1587 do { 1588 *data++ = v; 1589 v >>= 8; 1590 } while (--datalen > 0); 1591 } 1592 } 1593 1594 static void 1595 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1596 { 1597 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1598 uint32_t v; 1599 1600 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1601 size_t count = watermark; 1602 1603 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1604 if (count == 0) { 1605 sdmmc_delay(10); 1606 count = watermark; 1607 } 1608 v = *(uint32_t *)data; 1609 v = htole32(v); 1610 HWRITE4(hp, SDHC_DATA, v); 1611 data += 4; 1612 datalen -= 4; 1613 status = HREAD2(hp, SDHC_NINTR_STATUS); 1614 count--; 1615 } 1616 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1617 if (count == 0) { 1618 sdmmc_delay(10); 1619 } 1620 v = *(uint32_t *)data; 1621 v = htole32(v); 1622 HWRITE4(hp, SDHC_DATA, v); 1623 } 1624 } 1625 1626 /* Prepare for another command. */ 1627 static int 1628 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1629 { 1630 int timo; 1631 1632 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1633 1634 /* Request the reset. */ 1635 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1636 1637 /* 1638 * If necessary, wait for the controller to set the bits to 1639 * acknowledge the reset. 1640 */ 1641 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 1642 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 1643 for (timo = 10000; timo > 0; timo--) { 1644 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1645 break; 1646 /* Short delay because I worry we may miss it... */ 1647 sdmmc_delay(1); 1648 } 1649 if (timo == 0) 1650 return ETIMEDOUT; 1651 } 1652 1653 /* 1654 * Wait for the controller to clear the bits to indicate that 1655 * the reset has completed. 1656 */ 1657 for (timo = 10; timo > 0; timo--) { 1658 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1659 break; 1660 sdmmc_delay(10000); 1661 } 1662 if (timo == 0) { 1663 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1664 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1665 return ETIMEDOUT; 1666 } 1667 1668 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1669 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1670 } 1671 1672 return 0; 1673 } 1674 1675 static int 1676 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1677 { 1678 int status; 1679 1680 mask |= SDHC_ERROR_INTERRUPT; 1681 1682 mutex_enter(&hp->intr_mtx); 1683 status = hp->intr_status & mask; 1684 while (status == 0) { 1685 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1686 == EWOULDBLOCK) { 1687 status |= SDHC_ERROR_INTERRUPT; 1688 break; 1689 } 1690 status = hp->intr_status & mask; 1691 } 1692 hp->intr_status &= ~status; 1693 1694 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1695 hp->intr_error_status)); 1696 1697 /* Command timeout has higher priority than command complete. */ 1698 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1699 hp->intr_error_status = 0; 1700 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1701 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1702 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1703 } 1704 status = 0; 1705 } 1706 mutex_exit(&hp->intr_mtx); 1707 1708 return status; 1709 } 1710 1711 /* 1712 * Established by attachment driver at interrupt priority IPL_SDMMC. 1713 */ 1714 int 1715 sdhc_intr(void *arg) 1716 { 1717 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1718 struct sdhc_host *hp; 1719 int done = 0; 1720 uint16_t status; 1721 uint16_t error; 1722 1723 /* We got an interrupt, but we don't know from which slot. */ 1724 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1725 hp = sc->sc_host[host]; 1726 if (hp == NULL) 1727 continue; 1728 1729 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1730 /* Find out which interrupts are pending. */ 1731 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1732 status = xstatus; 1733 error = xstatus >> 16; 1734 if (error) 1735 xstatus |= SDHC_ERROR_INTERRUPT; 1736 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1737 continue; /* no interrupt for us */ 1738 /* Acknowledge the interrupts we are about to handle. */ 1739 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1740 } else { 1741 /* Find out which interrupts are pending. */ 1742 error = 0; 1743 status = HREAD2(hp, SDHC_NINTR_STATUS); 1744 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1745 continue; /* no interrupt for us */ 1746 /* Acknowledge the interrupts we are about to handle. */ 1747 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1748 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1749 /* Acknowledge error interrupts. */ 1750 error = HREAD2(hp, SDHC_EINTR_STATUS); 1751 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1752 } 1753 } 1754 1755 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1756 status, error)); 1757 1758 mutex_enter(&hp->intr_mtx); 1759 1760 /* Claim this interrupt. */ 1761 done = 1; 1762 1763 /* 1764 * Service error interrupts. 1765 */ 1766 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1767 SDHC_DATA_TIMEOUT_ERROR)) { 1768 hp->intr_error_status |= error; 1769 hp->intr_status |= status; 1770 cv_broadcast(&hp->intr_cv); 1771 } 1772 1773 /* 1774 * Wake up the sdmmc event thread to scan for cards. 1775 */ 1776 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1777 if (hp->sdmmc != NULL) { 1778 sdmmc_needs_discover(hp->sdmmc); 1779 } 1780 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1781 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1782 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1783 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1784 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1785 } 1786 } 1787 1788 /* 1789 * Wake up the blocking process to service command 1790 * related interrupt(s). 1791 */ 1792 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1793 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1794 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1795 hp->intr_status |= status; 1796 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1797 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1798 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1799 } 1800 cv_broadcast(&hp->intr_cv); 1801 } 1802 1803 /* 1804 * Service SD card interrupts. 1805 */ 1806 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1807 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1808 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1809 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1810 sdmmc_card_intr(hp->sdmmc); 1811 } 1812 mutex_exit(&hp->intr_mtx); 1813 } 1814 1815 return done; 1816 } 1817 1818 #ifdef SDHC_DEBUG 1819 void 1820 sdhc_dump_regs(struct sdhc_host *hp) 1821 { 1822 1823 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1824 HREAD4(hp, SDHC_PRESENT_STATE)); 1825 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1826 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1827 HREAD1(hp, SDHC_POWER_CTL)); 1828 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1829 HREAD2(hp, SDHC_NINTR_STATUS)); 1830 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1831 HREAD2(hp, SDHC_EINTR_STATUS)); 1832 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1833 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1834 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1835 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1836 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1837 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1838 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1839 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1840 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1841 HREAD4(hp, SDHC_CAPABILITIES)); 1842 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1843 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1844 } 1845 #endif 1846
Indexes created Thu Oct 23 22:10:10 GMT 2025