sdhc.c revision 1.63
1 /* $NetBSD: sdhc.c,v 1.63 2015/07/29 12:11:13 jmcneill Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.63 2015/07/29 12:11:13 jmcneill Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 40 #include <dev/sdmmc/sdhcreg.h> 41 #include <dev/sdmmc/sdhcvar.h> 42 #include <dev/sdmmc/sdmmcchip.h> 43 #include <dev/sdmmc/sdmmcreg.h> 44 #include <dev/sdmmc/sdmmcvar.h> 45 46 #ifdef SDHC_DEBUG 47 int sdhcdebug = 1; 48 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 49 void sdhc_dump_regs(struct sdhc_host *); 50 #else 51 #define DPRINTF(n,s) do {} while (0) 52 #endif 53 54 #define SDHC_COMMAND_TIMEOUT hz 55 #define SDHC_BUFFER_TIMEOUT hz 56 #define SDHC_TRANSFER_TIMEOUT hz 57 #define SDHC_DMA_TIMEOUT (hz*3) 58 59 struct sdhc_host { 60 struct sdhc_softc *sc; /* host controller device */ 61 62 bus_space_tag_t iot; /* host register set tag */ 63 bus_space_handle_t ioh; /* host register set handle */ 64 bus_size_t ios; /* host register space size */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 struct kmutex host_mtx; 70 71 u_int clkbase; /* base clock frequency in KHz */ 72 int maxblklen; /* maximum block length */ 73 uint32_t ocr; /* OCR value from capabilities */ 74 75 uint8_t regs[14]; /* host controller state */ 76 77 uint16_t intr_status; /* soft interrupt status */ 78 uint16_t intr_error_status; /* soft error status */ 79 struct kmutex intr_mtx; 80 struct kcondvar intr_cv; 81 82 int specver; /* spec. version */ 83 84 uint32_t flags; /* flags for this host */ 85 #define SHF_USE_DMA 0x0001 86 #define SHF_USE_4BIT_MODE 0x0002 87 #define SHF_USE_8BIT_MODE 0x0004 88 #define SHF_MODE_DMAEN 0x0008 /* needs SDHC_DMA_ENABLE in mode */ 89 #define SHF_USE_ADMA2_32 0x0010 90 #define SHF_USE_ADMA2_64 0x0020 91 #define SHF_USE_ADMA2_MASK 0x0030 92 93 bus_dmamap_t adma_map; 94 bus_dma_segment_t adma_segs[1]; 95 void *adma2; 96 }; 97 98 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 99 100 static uint8_t 101 hread1(struct sdhc_host *hp, bus_size_t reg) 102 { 103 104 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 105 return bus_space_read_1(hp->iot, hp->ioh, reg); 106 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 107 } 108 109 static uint16_t 110 hread2(struct sdhc_host *hp, bus_size_t reg) 111 { 112 113 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 114 return bus_space_read_2(hp->iot, hp->ioh, reg); 115 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 116 } 117 118 #define HREAD1(hp, reg) hread1(hp, reg) 119 #define HREAD2(hp, reg) hread2(hp, reg) 120 #define HREAD4(hp, reg) \ 121 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 122 123 124 static void 125 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 126 { 127 128 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 129 bus_space_write_1(hp->iot, hp->ioh, o, val); 130 } else { 131 const size_t shift = 8 * (o & 3); 132 o &= -4; 133 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 134 tmp = (val << shift) | (tmp & ~(0xff << shift)); 135 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 136 } 137 } 138 139 static void 140 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 141 { 142 143 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 144 bus_space_write_2(hp->iot, hp->ioh, o, val); 145 } else { 146 const size_t shift = 8 * (o & 2); 147 o &= -4; 148 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 149 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 150 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 151 } 152 } 153 154 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 155 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 156 #define HWRITE4(hp, reg, val) \ 157 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 158 159 #define HCLR1(hp, reg, bits) \ 160 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 161 #define HCLR2(hp, reg, bits) \ 162 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 163 #define HCLR4(hp, reg, bits) \ 164 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 165 #define HSET1(hp, reg, bits) \ 166 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 167 #define HSET2(hp, reg, bits) \ 168 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 169 #define HSET4(hp, reg, bits) \ 170 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 171 172 static int sdhc_host_reset(sdmmc_chipset_handle_t); 173 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 174 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 175 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 176 static int sdhc_card_detect(sdmmc_chipset_handle_t); 177 static int sdhc_write_protect(sdmmc_chipset_handle_t); 178 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 179 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 180 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 181 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 182 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 183 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 184 static void sdhc_exec_command(sdmmc_chipset_handle_t, 185 struct sdmmc_command *); 186 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 187 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 188 static int sdhc_soft_reset(struct sdhc_host *, int); 189 static int sdhc_wait_intr(struct sdhc_host *, int, int); 190 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 191 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 192 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 193 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 194 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 195 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 196 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 197 198 static struct sdmmc_chip_functions sdhc_functions = { 199 /* host controller reset */ 200 .host_reset = sdhc_host_reset, 201 202 /* host controller capabilities */ 203 .host_ocr = sdhc_host_ocr, 204 .host_maxblklen = sdhc_host_maxblklen, 205 206 /* card detection */ 207 .card_detect = sdhc_card_detect, 208 209 /* write protect */ 210 .write_protect = sdhc_write_protect, 211 212 /* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */ 213 .bus_power = sdhc_bus_power, 214 .bus_clock = sdhc_bus_clock, 215 .bus_width = sdhc_bus_width, 216 .bus_rod = sdhc_bus_rod, 217 218 /* command execution */ 219 .exec_command = sdhc_exec_command, 220 221 /* card interrupt */ 222 .card_enable_intr = sdhc_card_enable_intr, 223 .card_intr_ack = sdhc_card_intr_ack 224 }; 225 226 static int 227 sdhc_cfprint(void *aux, const char *pnp) 228 { 229 const struct sdmmcbus_attach_args * const saa = aux; 230 const struct sdhc_host * const hp = saa->saa_sch; 231 232 if (pnp) { 233 aprint_normal("sdmmc at %s", pnp); 234 } 235 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 236 if (hp->sc->sc_host[host] == hp) { 237 aprint_normal(" slot %zu", host); 238 } 239 } 240 241 return UNCONF; 242 } 243 244 /* 245 * Called by attachment driver. For each SD card slot there is one SD 246 * host controller standard register set. (1.3) 247 */ 248 int 249 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 250 bus_space_handle_t ioh, bus_size_t iosize) 251 { 252 struct sdmmcbus_attach_args saa; 253 struct sdhc_host *hp; 254 uint32_t caps; 255 uint16_t sdhcver; 256 int error; 257 258 /* Allocate one more host structure. */ 259 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 260 if (hp == NULL) { 261 aprint_error_dev(sc->sc_dev, 262 "couldn't alloc memory (sdhc host)\n"); 263 goto err1; 264 } 265 sc->sc_host[sc->sc_nhosts++] = hp; 266 267 /* Fill in the new host structure. */ 268 hp->sc = sc; 269 hp->iot = iot; 270 hp->ioh = ioh; 271 hp->ios = iosize; 272 hp->dmat = sc->sc_dmat; 273 274 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 275 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 276 cv_init(&hp->intr_cv, "sdhcintr"); 277 278 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 279 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); 280 } else { 281 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 282 } 283 aprint_normal_dev(sc->sc_dev, "SDHC "); 284 hp->specver = SDHC_SPEC_VERSION(sdhcver); 285 switch (SDHC_SPEC_VERSION(sdhcver)) { 286 case SDHC_SPEC_VERS_100: 287 aprint_normal("1.0"); 288 break; 289 290 case SDHC_SPEC_VERS_200: 291 aprint_normal("2.0"); 292 break; 293 294 case SDHC_SPEC_VERS_300: 295 aprint_normal("3.0"); 296 break; 297 298 case SDHC_SPEC_VERS_400: 299 aprint_normal("4.0"); 300 break; 301 302 default: 303 aprint_normal("unknown version(0x%x)", 304 SDHC_SPEC_VERSION(sdhcver)); 305 break; 306 } 307 aprint_normal(", rev %u", SDHC_VENDOR_VERSION(sdhcver)); 308 309 /* 310 * Reset the host controller and enable interrupts. 311 */ 312 (void)sdhc_host_reset(hp); 313 314 /* Determine host capabilities. */ 315 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 316 caps = sc->sc_caps; 317 } else { 318 mutex_enter(&hp->host_mtx); 319 caps = HREAD4(hp, SDHC_CAPABILITIES); 320 mutex_exit(&hp->host_mtx); 321 } 322 323 /* 324 * Use DMA if the host system and the controller support it. 325 * Suports integrated or external DMA egine, with or without 326 * SDHC_DMA_ENABLE in the command. 327 */ 328 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 329 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 330 ISSET(caps, SDHC_DMA_SUPPORT)))) { 331 SET(hp->flags, SHF_USE_DMA); 332 333 if (ISSET(sc->sc_flags, SDHC_FLAG_USE_ADMA2) && 334 ISSET(caps, SDHC_ADMA2_SUPP)) { 335 SET(hp->flags, SHF_MODE_DMAEN); 336 /* 337 * 64-bit mode was present in the 2.00 spec, removed 338 * from 3.00, and re-added in 4.00 with a different 339 * descriptor layout. We only support 2.00 and 3.00 340 * descriptors for now. 341 */ 342 if (hp->specver == SDHC_SPEC_VERS_200 && 343 ISSET(caps, SDHC_64BIT_SYS_BUS)) { 344 SET(hp->flags, SHF_USE_ADMA2_64); 345 aprint_normal(", 64-bit ADMA2"); 346 } else { 347 SET(hp->flags, SHF_USE_ADMA2_32); 348 aprint_normal(", 32-bit ADMA2"); 349 } 350 } else { 351 if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) || 352 ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN)) 353 SET(hp->flags, SHF_MODE_DMAEN); 354 aprint_normal(", SDMA"); 355 } 356 } else { 357 aprint_normal(", PIO"); 358 } 359 360 /* 361 * Determine the base clock frequency. (2.2.24) 362 */ 363 if (hp->specver >= SDHC_SPEC_VERS_300) { 364 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 365 } else { 366 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 367 } 368 if (hp->clkbase == 0 || 369 ISSET(sc->sc_flags, SDHC_FLAG_NO_CLKBASE)) { 370 if (sc->sc_clkbase == 0) { 371 /* The attachment driver must tell us. */ 372 aprint_error_dev(sc->sc_dev, 373 "unknown base clock frequency\n"); 374 goto err; 375 } 376 hp->clkbase = sc->sc_clkbase; 377 } 378 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 379 /* SDHC 1.0 supports only 10-63 MHz. */ 380 aprint_error_dev(sc->sc_dev, 381 "base clock frequency out of range: %u MHz\n", 382 hp->clkbase / 1000); 383 goto err; 384 } 385 aprint_normal(", %u kHz", hp->clkbase); 386 387 /* 388 * XXX Set the data timeout counter value according to 389 * capabilities. (2.2.15) 390 */ 391 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 392 #if 1 393 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 394 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 395 #endif 396 397 if (ISSET(caps, SDHC_EMBEDDED_SLOT)) 398 aprint_normal(", embedded slot"); 399 400 /* 401 * Determine SD bus voltage levels supported by the controller. 402 */ 403 aprint_normal(","); 404 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V) && 405 (hp->specver < SDHC_SPEC_VERS_300 || 406 ISSET(caps, SDHC_EMBEDDED_SLOT))) { 407 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 408 aprint_normal(" 1.8V"); 409 } 410 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 411 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 412 aprint_normal(" 3.0V"); 413 } 414 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 415 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 416 aprint_normal(" 3.3V"); 417 } 418 419 /* 420 * Determine the maximum block length supported by the host 421 * controller. (2.2.24) 422 */ 423 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 424 case SDHC_MAX_BLK_LEN_512: 425 hp->maxblklen = 512; 426 break; 427 428 case SDHC_MAX_BLK_LEN_1024: 429 hp->maxblklen = 1024; 430 break; 431 432 case SDHC_MAX_BLK_LEN_2048: 433 hp->maxblklen = 2048; 434 break; 435 436 case SDHC_MAX_BLK_LEN_4096: 437 hp->maxblklen = 4096; 438 break; 439 440 default: 441 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 442 goto err; 443 } 444 aprint_normal(", %u byte blocks", hp->maxblklen); 445 aprint_normal("\n"); 446 447 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 448 int rseg; 449 450 /* Allocate ADMA2 descriptor memory */ 451 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 452 PAGE_SIZE, hp->adma_segs, 1, &rseg, BUS_DMA_WAITOK); 453 if (error) { 454 aprint_error_dev(sc->sc_dev, 455 "ADMA2 dmamem_alloc failed (%d)\n", error); 456 goto adma_done; 457 } 458 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 459 PAGE_SIZE, (void **)&hp->adma2, BUS_DMA_WAITOK); 460 if (error) { 461 aprint_error_dev(sc->sc_dev, 462 "ADMA2 dmamem_map failed (%d)\n", error); 463 goto adma_done; 464 } 465 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 466 0, BUS_DMA_WAITOK, &hp->adma_map); 467 if (error) { 468 aprint_error_dev(sc->sc_dev, 469 "ADMA2 dmamap_create failed (%d)\n", error); 470 goto adma_done; 471 } 472 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 473 hp->adma2, PAGE_SIZE, NULL, 474 BUS_DMA_WAITOK|BUS_DMA_WRITE); 475 if (error) { 476 aprint_error_dev(sc->sc_dev, 477 "ADMA2 dmamap_load failed (%d)\n", error); 478 goto adma_done; 479 } 480 481 memset(hp->adma2, 0, PAGE_SIZE); 482 483 adma_done: 484 if (error) 485 CLR(hp->flags, SHF_USE_ADMA2_MASK); 486 } 487 488 /* 489 * Attach the generic SD/MMC bus driver. (The bus driver must 490 * not invoke any chipset functions before it is attached.) 491 */ 492 memset(&saa, 0, sizeof(saa)); 493 saa.saa_busname = "sdmmc"; 494 saa.saa_sct = &sdhc_functions; 495 saa.saa_sch = hp; 496 saa.saa_dmat = hp->dmat; 497 saa.saa_clkmax = hp->clkbase; 498 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 499 saa.saa_clkmin = hp->clkbase / 256 / 2046; 500 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 501 saa.saa_clkmin = hp->clkbase / 256 / 16; 502 else if (hp->sc->sc_clkmsk != 0) 503 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 504 (ffs(hp->sc->sc_clkmsk) - 1)); 505 else if (hp->specver >= SDHC_SPEC_VERS_300) 506 saa.saa_clkmin = hp->clkbase / 0x3ff; 507 else 508 saa.saa_clkmin = hp->clkbase / 256; 509 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 510 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 511 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 512 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 513 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 514 if (ISSET(hp->flags, SHF_USE_DMA)) { 515 saa.saa_caps |= SMC_CAPS_DMA; 516 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 517 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 518 } 519 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 520 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 521 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 522 523 return 0; 524 525 err: 526 cv_destroy(&hp->intr_cv); 527 mutex_destroy(&hp->intr_mtx); 528 mutex_destroy(&hp->host_mtx); 529 free(hp, M_DEVBUF); 530 sc->sc_host[--sc->sc_nhosts] = NULL; 531 err1: 532 return 1; 533 } 534 535 int 536 sdhc_detach(struct sdhc_softc *sc, int flags) 537 { 538 struct sdhc_host *hp; 539 int rv = 0; 540 541 for (size_t n = 0; n < sc->sc_nhosts; n++) { 542 hp = sc->sc_host[n]; 543 if (hp == NULL) 544 continue; 545 if (hp->sdmmc != NULL) { 546 rv = config_detach(hp->sdmmc, flags); 547 if (rv) 548 break; 549 hp->sdmmc = NULL; 550 } 551 /* disable interrupts */ 552 if ((flags & DETACH_FORCE) == 0) { 553 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 554 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 555 } else { 556 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 557 } 558 sdhc_soft_reset(hp, SDHC_RESET_ALL); 559 } 560 cv_destroy(&hp->intr_cv); 561 mutex_destroy(&hp->intr_mtx); 562 mutex_destroy(&hp->host_mtx); 563 if (hp->ios > 0) { 564 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 565 hp->ios = 0; 566 } 567 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 568 bus_dmamap_unload(sc->sc_dmat, hp->adma_map); 569 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 570 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 571 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, 1); 572 } 573 free(hp, M_DEVBUF); 574 sc->sc_host[n] = NULL; 575 } 576 577 return rv; 578 } 579 580 bool 581 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 582 { 583 struct sdhc_softc *sc = device_private(dev); 584 struct sdhc_host *hp; 585 size_t i; 586 587 /* XXX poll for command completion or suspend command 588 * in progress */ 589 590 /* Save the host controller state. */ 591 for (size_t n = 0; n < sc->sc_nhosts; n++) { 592 hp = sc->sc_host[n]; 593 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 594 for (i = 0; i < sizeof hp->regs; i += 4) { 595 uint32_t v = HREAD4(hp, i); 596 hp->regs[i + 0] = (v >> 0); 597 hp->regs[i + 1] = (v >> 8); 598 if (i + 3 < sizeof hp->regs) { 599 hp->regs[i + 2] = (v >> 16); 600 hp->regs[i + 3] = (v >> 24); 601 } 602 } 603 } else { 604 for (i = 0; i < sizeof hp->regs; i++) { 605 hp->regs[i] = HREAD1(hp, i); 606 } 607 } 608 } 609 return true; 610 } 611 612 bool 613 sdhc_resume(device_t dev, const pmf_qual_t *qual) 614 { 615 struct sdhc_softc *sc = device_private(dev); 616 struct sdhc_host *hp; 617 size_t i; 618 619 /* Restore the host controller state. */ 620 for (size_t n = 0; n < sc->sc_nhosts; n++) { 621 hp = sc->sc_host[n]; 622 (void)sdhc_host_reset(hp); 623 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 624 for (i = 0; i < sizeof hp->regs; i += 4) { 625 if (i + 3 < sizeof hp->regs) { 626 HWRITE4(hp, i, 627 (hp->regs[i + 0] << 0) 628 | (hp->regs[i + 1] << 8) 629 | (hp->regs[i + 2] << 16) 630 | (hp->regs[i + 3] << 24)); 631 } else { 632 HWRITE4(hp, i, 633 (hp->regs[i + 0] << 0) 634 | (hp->regs[i + 1] << 8)); 635 } 636 } 637 } else { 638 for (i = 0; i < sizeof hp->regs; i++) { 639 HWRITE1(hp, i, hp->regs[i]); 640 } 641 } 642 } 643 return true; 644 } 645 646 bool 647 sdhc_shutdown(device_t dev, int flags) 648 { 649 struct sdhc_softc *sc = device_private(dev); 650 struct sdhc_host *hp; 651 652 /* XXX chip locks up if we don't disable it before reboot. */ 653 for (size_t i = 0; i < sc->sc_nhosts; i++) { 654 hp = sc->sc_host[i]; 655 (void)sdhc_host_reset(hp); 656 } 657 return true; 658 } 659 660 /* 661 * Reset the host controller. Called during initialization, when 662 * cards are removed, upon resume, and during error recovery. 663 */ 664 static int 665 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 666 { 667 struct sdhc_host *hp = (struct sdhc_host *)sch; 668 uint32_t sdhcimask; 669 int error; 670 671 /* Don't lock. */ 672 673 /* Disable all interrupts. */ 674 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 675 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 676 } else { 677 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 678 } 679 680 /* 681 * Reset the entire host controller and wait up to 100ms for 682 * the controller to clear the reset bit. 683 */ 684 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 685 if (error) 686 goto out; 687 688 /* Set data timeout counter value to max for now. */ 689 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 690 #if 1 691 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 692 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 693 #endif 694 695 /* Enable interrupts. */ 696 mutex_enter(&hp->intr_mtx); 697 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 698 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 699 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 700 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 701 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 702 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 703 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 704 sdhcimask ^= 705 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 706 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 707 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 708 } else { 709 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 710 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 711 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 712 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 713 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 714 } 715 mutex_exit(&hp->intr_mtx); 716 717 out: 718 return error; 719 } 720 721 static int 722 sdhc_host_reset(sdmmc_chipset_handle_t sch) 723 { 724 struct sdhc_host *hp = (struct sdhc_host *)sch; 725 int error; 726 727 mutex_enter(&hp->host_mtx); 728 error = sdhc_host_reset1(sch); 729 mutex_exit(&hp->host_mtx); 730 731 return error; 732 } 733 734 static uint32_t 735 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 736 { 737 struct sdhc_host *hp = (struct sdhc_host *)sch; 738 739 return hp->ocr; 740 } 741 742 static int 743 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 744 { 745 struct sdhc_host *hp = (struct sdhc_host *)sch; 746 747 return hp->maxblklen; 748 } 749 750 /* 751 * Return non-zero if the card is currently inserted. 752 */ 753 static int 754 sdhc_card_detect(sdmmc_chipset_handle_t sch) 755 { 756 struct sdhc_host *hp = (struct sdhc_host *)sch; 757 int r; 758 759 if (hp->sc->sc_vendor_card_detect) 760 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 761 762 mutex_enter(&hp->host_mtx); 763 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 764 mutex_exit(&hp->host_mtx); 765 766 return r ? 1 : 0; 767 } 768 769 /* 770 * Return non-zero if the card is currently write-protected. 771 */ 772 static int 773 sdhc_write_protect(sdmmc_chipset_handle_t sch) 774 { 775 struct sdhc_host *hp = (struct sdhc_host *)sch; 776 int r; 777 778 if (hp->sc->sc_vendor_write_protect) 779 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 780 781 mutex_enter(&hp->host_mtx); 782 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 783 mutex_exit(&hp->host_mtx); 784 785 return r ? 0 : 1; 786 } 787 788 /* 789 * Set or change SD bus voltage and enable or disable SD bus power. 790 * Return zero on success. 791 */ 792 static int 793 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 794 { 795 struct sdhc_host *hp = (struct sdhc_host *)sch; 796 uint8_t vdd; 797 int error = 0; 798 const uint32_t pcmask = 799 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 800 801 mutex_enter(&hp->host_mtx); 802 803 /* 804 * Disable bus power before voltage change. 805 */ 806 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 807 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 808 HWRITE1(hp, SDHC_POWER_CTL, 0); 809 810 /* If power is disabled, reset the host and return now. */ 811 if (ocr == 0) { 812 (void)sdhc_host_reset1(hp); 813 goto out; 814 } 815 816 /* 817 * Select the lowest voltage according to capabilities. 818 */ 819 ocr &= hp->ocr; 820 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 821 vdd = SDHC_VOLTAGE_1_8V; 822 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 823 vdd = SDHC_VOLTAGE_3_0V; 824 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 825 vdd = SDHC_VOLTAGE_3_3V; 826 } else { 827 /* Unsupported voltage level requested. */ 828 error = EINVAL; 829 goto out; 830 } 831 832 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 833 /* 834 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 835 * voltage ramp until power rises. 836 */ 837 838 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SINGLE_POWER_WRITE)) { 839 HWRITE1(hp, SDHC_POWER_CTL, 840 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 841 } else { 842 HWRITE1(hp, SDHC_POWER_CTL, 843 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 844 sdmmc_delay(1); 845 HWRITE1(hp, SDHC_POWER_CTL, 846 (vdd << SDHC_VOLTAGE_SHIFT)); 847 sdmmc_delay(1); 848 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 849 sdmmc_delay(10000); 850 } 851 852 /* 853 * The host system may not power the bus due to battery low, 854 * etc. In that case, the host controller should clear the 855 * bus power bit. 856 */ 857 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 858 error = ENXIO; 859 goto out; 860 } 861 } 862 863 out: 864 mutex_exit(&hp->host_mtx); 865 866 return error; 867 } 868 869 /* 870 * Return the smallest possible base clock frequency divisor value 871 * for the CLOCK_CTL register to produce `freq' (KHz). 872 */ 873 static bool 874 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 875 { 876 u_int div; 877 878 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 879 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 880 if ((hp->clkbase / div) <= freq) { 881 *divp = SDHC_SDCLK_CGM 882 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 883 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 884 //freq = hp->clkbase / div; 885 return true; 886 } 887 } 888 /* No divisor found. */ 889 return false; 890 } 891 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 892 u_int dvs = (hp->clkbase + freq - 1) / freq; 893 u_int roundup = dvs & 1; 894 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 895 if (dvs + roundup <= 16) { 896 dvs += roundup - 1; 897 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 898 | (dvs << SDHC_SDCLK_DVS_SHIFT); 899 DPRINTF(2, 900 ("%s: divisor for freq %u is %u * %u\n", 901 HDEVNAME(hp), freq, div * 2, dvs + 1)); 902 //freq = hp->clkbase / (div * 2) * (dvs + 1); 903 return true; 904 } 905 /* 906 * If we drop bits, we need to round up the divisor. 907 */ 908 roundup |= dvs & 1; 909 } 910 /* No divisor found. */ 911 return false; 912 } 913 if (hp->sc->sc_clkmsk != 0) { 914 div = howmany(hp->clkbase, freq); 915 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 916 return false; 917 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 918 //freq = hp->clkbase / div; 919 return true; 920 } 921 if (hp->specver >= SDHC_SPEC_VERS_300) { 922 div = howmany(hp->clkbase, freq); 923 div = div > 1 ? howmany(div, 2) : 0; 924 if (div > 0x3ff) 925 return false; 926 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 927 << SDHC_SDCLK_XDIV_SHIFT) | 928 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 929 << SDHC_SDCLK_DIV_SHIFT); 930 //freq = hp->clkbase / div; 931 return true; 932 } else { 933 for (div = 1; div <= 256; div *= 2) { 934 if ((hp->clkbase / div) <= freq) { 935 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 936 //freq = hp->clkbase / div; 937 return true; 938 } 939 } 940 /* No divisor found. */ 941 return false; 942 } 943 /* No divisor found. */ 944 return false; 945 } 946 947 /* 948 * Set or change SDCLK frequency or disable the SD clock. 949 * Return zero on success. 950 */ 951 static int 952 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 953 { 954 struct sdhc_host *hp = (struct sdhc_host *)sch; 955 u_int div; 956 u_int timo; 957 int16_t reg; 958 int error = 0; 959 #ifdef DIAGNOSTIC 960 bool present; 961 962 mutex_enter(&hp->host_mtx); 963 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 964 mutex_exit(&hp->host_mtx); 965 966 /* Must not stop the clock if commands are in progress. */ 967 if (present && sdhc_card_detect(hp)) { 968 aprint_normal_dev(hp->sc->sc_dev, 969 "%s: command in progress\n", __func__); 970 } 971 #endif 972 973 mutex_enter(&hp->host_mtx); 974 975 if (hp->sc->sc_vendor_bus_clock) { 976 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 977 if (error != 0) 978 goto out; 979 } 980 981 /* 982 * Stop SD clock before changing the frequency. 983 */ 984 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 985 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 986 if (freq == SDMMC_SDCLK_OFF) { 987 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 988 goto out; 989 } 990 } else { 991 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 992 if (freq == SDMMC_SDCLK_OFF) 993 goto out; 994 } 995 996 /* 997 * Set the minimum base clock frequency divisor. 998 */ 999 if (!sdhc_clock_divisor(hp, freq, &div)) { 1000 /* Invalid base clock frequency or `freq' value. */ 1001 error = EINVAL; 1002 goto out; 1003 } 1004 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1005 HWRITE4(hp, SDHC_CLOCK_CTL, 1006 div | (SDHC_TIMEOUT_MAX << 16)); 1007 } else { 1008 reg = HREAD2(hp, SDHC_CLOCK_CTL); 1009 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 1010 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 1011 } 1012 1013 /* 1014 * Start internal clock. Wait 10ms for stabilization. 1015 */ 1016 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1017 sdmmc_delay(10000); 1018 HSET4(hp, SDHC_CLOCK_CTL, 1019 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 1020 } else { 1021 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 1022 for (timo = 1000; timo > 0; timo--) { 1023 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 1024 SDHC_INTCLK_STABLE)) 1025 break; 1026 sdmmc_delay(10); 1027 } 1028 if (timo == 0) { 1029 error = ETIMEDOUT; 1030 goto out; 1031 } 1032 } 1033 1034 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1035 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 1036 /* 1037 * Sending 80 clocks at 400kHz takes 200us. 1038 * So delay for that time + slop and then 1039 * check a few times for completion. 1040 */ 1041 sdmmc_delay(210); 1042 for (timo = 10; timo > 0; timo--) { 1043 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 1044 SDHC_INIT_ACTIVE)) 1045 break; 1046 sdmmc_delay(10); 1047 } 1048 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 1049 1050 /* 1051 * Enable SD clock. 1052 */ 1053 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1054 } else { 1055 /* 1056 * Enable SD clock. 1057 */ 1058 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1059 1060 if (freq > 25000 && 1061 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 1062 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1063 else 1064 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1065 } 1066 1067 out: 1068 mutex_exit(&hp->host_mtx); 1069 1070 return error; 1071 } 1072 1073 static int 1074 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 1075 { 1076 struct sdhc_host *hp = (struct sdhc_host *)sch; 1077 int reg; 1078 1079 switch (width) { 1080 case 1: 1081 case 4: 1082 break; 1083 1084 case 8: 1085 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 1086 break; 1087 /* FALLTHROUGH */ 1088 default: 1089 DPRINTF(0,("%s: unsupported bus width (%d)\n", 1090 HDEVNAME(hp), width)); 1091 return 1; 1092 } 1093 1094 mutex_enter(&hp->host_mtx); 1095 reg = HREAD1(hp, SDHC_HOST_CTL); 1096 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1097 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 1098 if (width == 4) 1099 reg |= SDHC_4BIT_MODE; 1100 else if (width == 8) 1101 reg |= SDHC_ESDHC_8BIT_MODE; 1102 } else { 1103 reg &= ~SDHC_4BIT_MODE; 1104 if (hp->specver >= SDHC_SPEC_VERS_300) { 1105 reg &= ~SDHC_8BIT_MODE; 1106 } 1107 if (width == 4) { 1108 reg |= SDHC_4BIT_MODE; 1109 } else if (width == 8 && hp->specver >= SDHC_SPEC_VERS_300) { 1110 reg |= SDHC_8BIT_MODE; 1111 } 1112 } 1113 HWRITE1(hp, SDHC_HOST_CTL, reg); 1114 mutex_exit(&hp->host_mtx); 1115 1116 return 0; 1117 } 1118 1119 static int 1120 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1121 { 1122 struct sdhc_host *hp = (struct sdhc_host *)sch; 1123 1124 if (hp->sc->sc_vendor_rod) 1125 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1126 1127 return 0; 1128 } 1129 1130 static void 1131 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1132 { 1133 struct sdhc_host *hp = (struct sdhc_host *)sch; 1134 1135 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1136 mutex_enter(&hp->intr_mtx); 1137 if (enable) { 1138 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1139 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1140 } else { 1141 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1142 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1143 } 1144 mutex_exit(&hp->intr_mtx); 1145 } 1146 } 1147 1148 static void 1149 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1150 { 1151 struct sdhc_host *hp = (struct sdhc_host *)sch; 1152 1153 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1154 mutex_enter(&hp->intr_mtx); 1155 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1156 mutex_exit(&hp->intr_mtx); 1157 } 1158 } 1159 1160 static int 1161 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1162 { 1163 uint32_t state; 1164 int timeout; 1165 1166 for (timeout = 10; timeout > 0; timeout--) { 1167 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 1168 return 0; 1169 sdmmc_delay(10000); 1170 } 1171 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 1172 value, state)); 1173 return ETIMEDOUT; 1174 } 1175 1176 static void 1177 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1178 { 1179 struct sdhc_host *hp = (struct sdhc_host *)sch; 1180 int error; 1181 1182 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1183 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1184 mutex_enter(&hp->intr_mtx); 1185 if (ISSET(hp->flags, SHF_USE_DMA)) { 1186 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1187 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1188 } else { 1189 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1190 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1191 } 1192 mutex_exit(&hp->intr_mtx); 1193 } 1194 1195 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_TIMEOUT)) { 1196 const uint16_t eintr = SDHC_CMD_TIMEOUT_ERROR; 1197 if (cmd->c_data != NULL) { 1198 HCLR2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1199 HCLR2(hp, SDHC_EINTR_STATUS_EN, eintr); 1200 } else { 1201 HSET2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1202 HSET2(hp, SDHC_EINTR_STATUS_EN, eintr); 1203 } 1204 } 1205 1206 /* 1207 * Start the MMC command, or mark `cmd' as failed and return. 1208 */ 1209 error = sdhc_start_command(hp, cmd); 1210 if (error) { 1211 cmd->c_error = error; 1212 goto out; 1213 } 1214 1215 /* 1216 * Wait until the command phase is done, or until the command 1217 * is marked done for any other reason. 1218 */ 1219 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1220 cmd->c_error = ETIMEDOUT; 1221 goto out; 1222 } 1223 1224 /* 1225 * The host controller removes bits [0:7] from the response 1226 * data (CRC) and we pass the data up unchanged to the bus 1227 * driver (without padding). 1228 */ 1229 mutex_enter(&hp->host_mtx); 1230 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1231 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1232 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1233 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1234 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1235 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1236 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1237 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1238 (cmd->c_resp[1] << 24); 1239 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1240 (cmd->c_resp[2] << 24); 1241 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1242 (cmd->c_resp[3] << 24); 1243 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1244 } 1245 } 1246 } 1247 mutex_exit(&hp->host_mtx); 1248 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1249 1250 /* 1251 * If the command has data to transfer in any direction, 1252 * execute the transfer now. 1253 */ 1254 if (cmd->c_error == 0 && cmd->c_data != NULL) 1255 sdhc_transfer_data(hp, cmd); 1256 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1257 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10)) { 1258 cmd->c_error = ETIMEDOUT; 1259 goto out; 1260 } 1261 } 1262 1263 out: 1264 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1265 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1266 mutex_enter(&hp->host_mtx); 1267 /* Turn off the LED. */ 1268 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1269 mutex_exit(&hp->host_mtx); 1270 } 1271 SET(cmd->c_flags, SCF_ITSDONE); 1272 1273 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1274 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1275 cmd->c_flags, cmd->c_error)); 1276 } 1277 1278 static int 1279 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1280 { 1281 struct sdhc_softc * const sc = hp->sc; 1282 uint16_t blksize = 0; 1283 uint16_t blkcount = 0; 1284 uint16_t mode; 1285 uint16_t command; 1286 int error; 1287 1288 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1289 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1290 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1291 1292 /* 1293 * The maximum block length for commands should be the minimum 1294 * of the host buffer size and the card buffer size. (1.7.2) 1295 */ 1296 1297 /* Fragment the data into proper blocks. */ 1298 if (cmd->c_datalen > 0) { 1299 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1300 blkcount = cmd->c_datalen / blksize; 1301 if (cmd->c_datalen % blksize > 0) { 1302 /* XXX: Split this command. (1.7.4) */ 1303 aprint_error_dev(sc->sc_dev, 1304 "data not a multiple of %u bytes\n", blksize); 1305 return EINVAL; 1306 } 1307 } 1308 1309 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1310 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1311 aprint_error_dev(sc->sc_dev, "too much data\n"); 1312 return EINVAL; 1313 } 1314 1315 /* Prepare transfer mode register value. (2.2.5) */ 1316 mode = SDHC_BLOCK_COUNT_ENABLE; 1317 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1318 mode |= SDHC_READ_MODE; 1319 if (blkcount > 1) { 1320 mode |= SDHC_MULTI_BLOCK_MODE; 1321 /* XXX only for memory commands? */ 1322 mode |= SDHC_AUTO_CMD12_ENABLE; 1323 } 1324 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1325 ISSET(hp->flags, SHF_MODE_DMAEN)) { 1326 mode |= SDHC_DMA_ENABLE; 1327 } 1328 1329 /* 1330 * Prepare command register value. (2.2.6) 1331 */ 1332 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1333 1334 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1335 command |= SDHC_CRC_CHECK_ENABLE; 1336 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1337 command |= SDHC_INDEX_CHECK_ENABLE; 1338 if (cmd->c_data != NULL) 1339 command |= SDHC_DATA_PRESENT_SELECT; 1340 1341 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1342 command |= SDHC_NO_RESPONSE; 1343 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1344 command |= SDHC_RESP_LEN_136; 1345 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1346 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1347 else 1348 command |= SDHC_RESP_LEN_48; 1349 1350 /* Wait until command and data inhibit bits are clear. (1.5) */ 1351 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1352 if (error) 1353 return error; 1354 1355 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1356 HDEVNAME(hp), blksize, blkcount, mode, command)); 1357 1358 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1359 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1360 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1361 } 1362 1363 mutex_enter(&hp->host_mtx); 1364 1365 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1366 /* Alert the user not to remove the card. */ 1367 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1368 } 1369 1370 /* Set DMA start address. */ 1371 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK) && cmd->c_datalen > 0) { 1372 for (int seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 1373 paddr_t paddr = 1374 cmd->c_dmamap->dm_segs[seg].ds_addr; 1375 uint16_t len = 1376 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1377 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1378 uint16_t attr = 1379 SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1380 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 1381 attr |= SDHC_ADMA2_END; 1382 } 1383 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1384 struct sdhc_adma2_descriptor32 *desc = 1385 hp->adma2; 1386 desc[seg].attribute = htole16(attr); 1387 desc[seg].length = htole16(len); 1388 desc[seg].address = htole32(paddr); 1389 } else { 1390 struct sdhc_adma2_descriptor64 *desc = 1391 hp->adma2; 1392 desc[seg].attribute = htole16(attr); 1393 desc[seg].length = htole16(len); 1394 desc[seg].address = htole32(paddr & 0xffffffff); 1395 desc[seg].address_hi = htole32( 1396 (uint64_t)paddr >> 32); 1397 } 1398 } 1399 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1400 struct sdhc_adma2_descriptor32 *desc = hp->adma2; 1401 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1402 } else { 1403 struct sdhc_adma2_descriptor64 *desc = hp->adma2; 1404 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1405 } 1406 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1407 BUS_DMASYNC_PREWRITE); 1408 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1409 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2); 1410 1411 const paddr_t desc_addr = hp->adma_map->dm_segs[0].ds_addr; 1412 1413 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff); 1414 if (ISSET(hp->flags, SHF_USE_ADMA2_64)) { 1415 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4, 1416 (uint64_t)desc_addr >> 32); 1417 } 1418 } else if (ISSET(mode, SDHC_DMA_ENABLE) && 1419 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) { 1420 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1421 } 1422 1423 /* 1424 * Start a CPU data transfer. Writing to the high order byte 1425 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1426 */ 1427 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1428 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1429 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1430 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1431 } else { 1432 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1433 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1434 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1435 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1436 HWRITE2(hp, SDHC_COMMAND, command); 1437 } 1438 1439 mutex_exit(&hp->host_mtx); 1440 1441 return 0; 1442 } 1443 1444 static void 1445 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1446 { 1447 struct sdhc_softc *sc = hp->sc; 1448 int error; 1449 1450 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1451 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1452 1453 #ifdef SDHC_DEBUG 1454 /* XXX I forgot why I wanted to know when this happens :-( */ 1455 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1456 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1457 aprint_error_dev(hp->sc->sc_dev, 1458 "CMD52/53 error response flags %#x\n", 1459 MMC_R1(cmd->c_resp) & 0xff00); 1460 } 1461 #endif 1462 1463 if (cmd->c_dmamap != NULL) { 1464 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1465 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd); 1466 if (error == 0 && !sdhc_wait_intr(hp, 1467 SDHC_TRANSFER_COMPLETE, SDHC_DMA_TIMEOUT)) { 1468 error = ETIMEDOUT; 1469 } 1470 } else { 1471 error = sdhc_transfer_data_dma(hp, cmd); 1472 } 1473 } else 1474 error = sdhc_transfer_data_pio(hp, cmd); 1475 if (error) 1476 cmd->c_error = error; 1477 SET(cmd->c_flags, SCF_ITSDONE); 1478 1479 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1480 HDEVNAME(hp), cmd->c_error)); 1481 } 1482 1483 static int 1484 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1485 { 1486 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1487 bus_addr_t posaddr; 1488 bus_addr_t segaddr; 1489 bus_size_t seglen; 1490 u_int seg = 0; 1491 int error = 0; 1492 int status; 1493 1494 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1495 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1496 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1497 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1498 1499 for (;;) { 1500 status = sdhc_wait_intr(hp, 1501 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1502 SDHC_DMA_TIMEOUT); 1503 1504 if (status & SDHC_TRANSFER_COMPLETE) { 1505 break; 1506 } 1507 if (!status) { 1508 error = ETIMEDOUT; 1509 break; 1510 } 1511 1512 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1513 continue; 1514 } 1515 1516 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1517 continue; 1518 } 1519 1520 /* DMA Interrupt (boundary crossing) */ 1521 1522 segaddr = dm_segs[seg].ds_addr; 1523 seglen = dm_segs[seg].ds_len; 1524 mutex_enter(&hp->host_mtx); 1525 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1526 mutex_exit(&hp->host_mtx); 1527 1528 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1529 continue; 1530 } 1531 mutex_enter(&hp->host_mtx); 1532 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1533 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1534 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1535 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1536 mutex_exit(&hp->host_mtx); 1537 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1538 } 1539 1540 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1541 bus_dmamap_sync(hp->sc->sc_dmat, hp->adma_map, 0, 1542 PAGE_SIZE, BUS_DMASYNC_POSTWRITE); 1543 } 1544 1545 return error; 1546 } 1547 1548 static int 1549 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1550 { 1551 uint8_t *data = cmd->c_data; 1552 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1553 u_int len, datalen; 1554 u_int imask; 1555 u_int pmask; 1556 int error = 0; 1557 1558 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1559 imask = SDHC_BUFFER_READ_READY; 1560 pmask = SDHC_BUFFER_READ_ENABLE; 1561 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1562 pio_func = esdhc_read_data_pio; 1563 } else { 1564 pio_func = sdhc_read_data_pio; 1565 } 1566 } else { 1567 imask = SDHC_BUFFER_WRITE_READY; 1568 pmask = SDHC_BUFFER_WRITE_ENABLE; 1569 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1570 pio_func = esdhc_write_data_pio; 1571 } else { 1572 pio_func = sdhc_write_data_pio; 1573 } 1574 } 1575 datalen = cmd->c_datalen; 1576 1577 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1578 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1579 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1580 1581 while (datalen > 0) { 1582 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1583 mutex_enter(&hp->intr_mtx); 1584 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1585 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1586 } else { 1587 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1588 } 1589 mutex_exit(&hp->intr_mtx); 1590 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1591 error = ETIMEDOUT; 1592 break; 1593 } 1594 1595 error = sdhc_wait_state(hp, pmask, pmask); 1596 if (error) 1597 break; 1598 } 1599 1600 len = MIN(datalen, cmd->c_blklen); 1601 (*pio_func)(hp, data, len); 1602 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1603 HDEVNAME(hp), len, data)); 1604 1605 data += len; 1606 datalen -= len; 1607 } 1608 1609 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1610 SDHC_TRANSFER_TIMEOUT)) 1611 error = ETIMEDOUT; 1612 1613 return error; 1614 } 1615 1616 static void 1617 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1618 { 1619 1620 if (((__uintptr_t)data & 3) == 0) { 1621 while (datalen > 3) { 1622 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1623 data += 4; 1624 datalen -= 4; 1625 } 1626 if (datalen > 1) { 1627 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1628 data += 2; 1629 datalen -= 2; 1630 } 1631 if (datalen > 0) { 1632 *data = HREAD1(hp, SDHC_DATA); 1633 data += 1; 1634 datalen -= 1; 1635 } 1636 } else if (((__uintptr_t)data & 1) == 0) { 1637 while (datalen > 1) { 1638 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1639 data += 2; 1640 datalen -= 2; 1641 } 1642 if (datalen > 0) { 1643 *data = HREAD1(hp, SDHC_DATA); 1644 data += 1; 1645 datalen -= 1; 1646 } 1647 } else { 1648 while (datalen > 0) { 1649 *data = HREAD1(hp, SDHC_DATA); 1650 data += 1; 1651 datalen -= 1; 1652 } 1653 } 1654 } 1655 1656 static void 1657 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1658 { 1659 1660 if (((__uintptr_t)data & 3) == 0) { 1661 while (datalen > 3) { 1662 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 1663 data += 4; 1664 datalen -= 4; 1665 } 1666 if (datalen > 1) { 1667 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1668 data += 2; 1669 datalen -= 2; 1670 } 1671 if (datalen > 0) { 1672 HWRITE1(hp, SDHC_DATA, *data); 1673 data += 1; 1674 datalen -= 1; 1675 } 1676 } else if (((__uintptr_t)data & 1) == 0) { 1677 while (datalen > 1) { 1678 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1679 data += 2; 1680 datalen -= 2; 1681 } 1682 if (datalen > 0) { 1683 HWRITE1(hp, SDHC_DATA, *data); 1684 data += 1; 1685 datalen -= 1; 1686 } 1687 } else { 1688 while (datalen > 0) { 1689 HWRITE1(hp, SDHC_DATA, *data); 1690 data += 1; 1691 datalen -= 1; 1692 } 1693 } 1694 } 1695 1696 static void 1697 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1698 { 1699 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1700 uint32_t v; 1701 1702 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1703 size_t count = 0; 1704 1705 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1706 if (count == 0) { 1707 /* 1708 * If we've drained "watermark" words, we need to wait 1709 * a little bit so the read FIFO can refill. 1710 */ 1711 sdmmc_delay(10); 1712 count = watermark; 1713 } 1714 v = HREAD4(hp, SDHC_DATA); 1715 v = le32toh(v); 1716 *(uint32_t *)data = v; 1717 data += 4; 1718 datalen -= 4; 1719 status = HREAD2(hp, SDHC_NINTR_STATUS); 1720 count--; 1721 } 1722 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1723 if (count == 0) { 1724 sdmmc_delay(10); 1725 } 1726 v = HREAD4(hp, SDHC_DATA); 1727 v = le32toh(v); 1728 do { 1729 *data++ = v; 1730 v >>= 8; 1731 } while (--datalen > 0); 1732 } 1733 } 1734 1735 static void 1736 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1737 { 1738 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1739 uint32_t v; 1740 1741 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1742 size_t count = watermark; 1743 1744 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1745 if (count == 0) { 1746 sdmmc_delay(10); 1747 count = watermark; 1748 } 1749 v = *(uint32_t *)data; 1750 v = htole32(v); 1751 HWRITE4(hp, SDHC_DATA, v); 1752 data += 4; 1753 datalen -= 4; 1754 status = HREAD2(hp, SDHC_NINTR_STATUS); 1755 count--; 1756 } 1757 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1758 if (count == 0) { 1759 sdmmc_delay(10); 1760 } 1761 v = *(uint32_t *)data; 1762 v = htole32(v); 1763 HWRITE4(hp, SDHC_DATA, v); 1764 } 1765 } 1766 1767 /* Prepare for another command. */ 1768 static int 1769 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1770 { 1771 int timo; 1772 1773 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1774 1775 /* Request the reset. */ 1776 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1777 1778 /* 1779 * If necessary, wait for the controller to set the bits to 1780 * acknowledge the reset. 1781 */ 1782 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 1783 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 1784 for (timo = 10000; timo > 0; timo--) { 1785 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1786 break; 1787 /* Short delay because I worry we may miss it... */ 1788 sdmmc_delay(1); 1789 } 1790 if (timo == 0) 1791 return ETIMEDOUT; 1792 } 1793 1794 /* 1795 * Wait for the controller to clear the bits to indicate that 1796 * the reset has completed. 1797 */ 1798 for (timo = 10; timo > 0; timo--) { 1799 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1800 break; 1801 sdmmc_delay(10000); 1802 } 1803 if (timo == 0) { 1804 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1805 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1806 return ETIMEDOUT; 1807 } 1808 1809 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1810 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1811 } 1812 1813 return 0; 1814 } 1815 1816 static int 1817 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1818 { 1819 int status; 1820 1821 mask |= SDHC_ERROR_INTERRUPT; 1822 1823 mutex_enter(&hp->intr_mtx); 1824 status = hp->intr_status & mask; 1825 while (status == 0) { 1826 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1827 == EWOULDBLOCK) { 1828 status |= SDHC_ERROR_INTERRUPT; 1829 break; 1830 } 1831 status = hp->intr_status & mask; 1832 } 1833 hp->intr_status &= ~status; 1834 1835 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1836 hp->intr_error_status)); 1837 1838 /* Command timeout has higher priority than command complete. */ 1839 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1840 hp->intr_error_status = 0; 1841 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1842 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1843 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1844 } 1845 status = 0; 1846 } 1847 mutex_exit(&hp->intr_mtx); 1848 1849 return status; 1850 } 1851 1852 /* 1853 * Established by attachment driver at interrupt priority IPL_SDMMC. 1854 */ 1855 int 1856 sdhc_intr(void *arg) 1857 { 1858 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1859 struct sdhc_host *hp; 1860 int done = 0; 1861 uint16_t status; 1862 uint16_t error; 1863 1864 /* We got an interrupt, but we don't know from which slot. */ 1865 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1866 hp = sc->sc_host[host]; 1867 if (hp == NULL) 1868 continue; 1869 1870 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1871 /* Find out which interrupts are pending. */ 1872 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1873 status = xstatus; 1874 error = xstatus >> 16; 1875 if (error) 1876 xstatus |= SDHC_ERROR_INTERRUPT; 1877 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1878 continue; /* no interrupt for us */ 1879 /* Acknowledge the interrupts we are about to handle. */ 1880 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1881 } else { 1882 /* Find out which interrupts are pending. */ 1883 error = 0; 1884 status = HREAD2(hp, SDHC_NINTR_STATUS); 1885 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1886 continue; /* no interrupt for us */ 1887 /* Acknowledge the interrupts we are about to handle. */ 1888 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1889 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1890 /* Acknowledge error interrupts. */ 1891 error = HREAD2(hp, SDHC_EINTR_STATUS); 1892 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1893 } 1894 } 1895 1896 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1897 status, error)); 1898 1899 mutex_enter(&hp->intr_mtx); 1900 1901 /* Claim this interrupt. */ 1902 done = 1; 1903 1904 if (ISSET(error, SDHC_ADMA_ERROR)) { 1905 uint8_t adma_err = HREAD1(hp, SDHC_ADMA_ERROR_STATUS); 1906 printf("%s: ADMA error, status %02x\n", HDEVNAME(hp), 1907 adma_err); 1908 } 1909 1910 /* 1911 * Service error interrupts. 1912 */ 1913 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1914 SDHC_DATA_TIMEOUT_ERROR)) { 1915 hp->intr_error_status |= error; 1916 hp->intr_status |= status; 1917 cv_broadcast(&hp->intr_cv); 1918 } 1919 1920 /* 1921 * Wake up the sdmmc event thread to scan for cards. 1922 */ 1923 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1924 if (hp->sdmmc != NULL) { 1925 sdmmc_needs_discover(hp->sdmmc); 1926 } 1927 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1928 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1929 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1930 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1931 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1932 } 1933 } 1934 1935 /* 1936 * Wake up the blocking process to service command 1937 * related interrupt(s). 1938 */ 1939 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1940 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1941 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1942 hp->intr_status |= status; 1943 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1944 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1945 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1946 } 1947 cv_broadcast(&hp->intr_cv); 1948 } 1949 1950 /* 1951 * Service SD card interrupts. 1952 */ 1953 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1954 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1955 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1956 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1957 sdmmc_card_intr(hp->sdmmc); 1958 } 1959 mutex_exit(&hp->intr_mtx); 1960 } 1961 1962 return done; 1963 } 1964 1965 #ifdef SDHC_DEBUG 1966 void 1967 sdhc_dump_regs(struct sdhc_host *hp) 1968 { 1969 1970 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1971 HREAD4(hp, SDHC_PRESENT_STATE)); 1972 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1973 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1974 HREAD1(hp, SDHC_POWER_CTL)); 1975 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1976 HREAD2(hp, SDHC_NINTR_STATUS)); 1977 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1978 HREAD2(hp, SDHC_EINTR_STATUS)); 1979 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1980 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1981 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1982 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1983 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1984 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1985 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1986 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1987 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1988 HREAD4(hp, SDHC_CAPABILITIES)); 1989 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1990 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1991 } 1992 #endif 1993
Indexes created Fri Sep 26 08:10:20 GMT 2025