sdhc.c revision 1.70
1 /* $NetBSD: sdhc.c,v 1.70 2015/08/02 11:28:01 jmcneill Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.70 2015/08/02 11:28:01 jmcneill Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 40 #include <dev/sdmmc/sdhcreg.h> 41 #include <dev/sdmmc/sdhcvar.h> 42 #include <dev/sdmmc/sdmmcchip.h> 43 #include <dev/sdmmc/sdmmcreg.h> 44 #include <dev/sdmmc/sdmmcvar.h> 45 46 #ifdef SDHC_DEBUG 47 int sdhcdebug = 1; 48 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 49 void sdhc_dump_regs(struct sdhc_host *); 50 #else 51 #define DPRINTF(n,s) do {} while (0) 52 #endif 53 54 #define SDHC_COMMAND_TIMEOUT hz 55 #define SDHC_BUFFER_TIMEOUT hz 56 #define SDHC_TRANSFER_TIMEOUT hz 57 #define SDHC_DMA_TIMEOUT (hz*3) 58 59 struct sdhc_host { 60 struct sdhc_softc *sc; /* host controller device */ 61 62 bus_space_tag_t iot; /* host register set tag */ 63 bus_space_handle_t ioh; /* host register set handle */ 64 bus_size_t ios; /* host register space size */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 u_int clkbase; /* base clock frequency in KHz */ 70 int maxblklen; /* maximum block length */ 71 uint32_t ocr; /* OCR value from capabilities */ 72 73 uint8_t regs[14]; /* host controller state */ 74 75 uint16_t intr_status; /* soft interrupt status */ 76 uint16_t intr_error_status; /* soft error status */ 77 kmutex_t intr_lock; 78 kcondvar_t intr_cv; 79 80 int specver; /* spec. version */ 81 82 uint32_t flags; /* flags for this host */ 83 #define SHF_USE_DMA 0x0001 84 #define SHF_USE_4BIT_MODE 0x0002 85 #define SHF_USE_8BIT_MODE 0x0004 86 #define SHF_MODE_DMAEN 0x0008 /* needs SDHC_DMA_ENABLE in mode */ 87 #define SHF_USE_ADMA2_32 0x0010 88 #define SHF_USE_ADMA2_64 0x0020 89 #define SHF_USE_ADMA2_MASK 0x0030 90 91 bus_dmamap_t adma_map; 92 bus_dma_segment_t adma_segs[1]; 93 void *adma2; 94 }; 95 96 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 97 98 static uint8_t 99 hread1(struct sdhc_host *hp, bus_size_t reg) 100 { 101 102 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 103 return bus_space_read_1(hp->iot, hp->ioh, reg); 104 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 105 } 106 107 static uint16_t 108 hread2(struct sdhc_host *hp, bus_size_t reg) 109 { 110 111 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 112 return bus_space_read_2(hp->iot, hp->ioh, reg); 113 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 114 } 115 116 #define HREAD1(hp, reg) hread1(hp, reg) 117 #define HREAD2(hp, reg) hread2(hp, reg) 118 #define HREAD4(hp, reg) \ 119 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 120 121 122 static void 123 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 124 { 125 126 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 127 bus_space_write_1(hp->iot, hp->ioh, o, val); 128 } else { 129 const size_t shift = 8 * (o & 3); 130 o &= -4; 131 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 132 tmp = (val << shift) | (tmp & ~(0xff << shift)); 133 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 134 } 135 } 136 137 static void 138 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 139 { 140 141 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 142 bus_space_write_2(hp->iot, hp->ioh, o, val); 143 } else { 144 const size_t shift = 8 * (o & 2); 145 o &= -4; 146 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 147 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 148 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 149 } 150 } 151 152 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 153 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 154 #define HWRITE4(hp, reg, val) \ 155 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 156 157 #define HCLR1(hp, reg, bits) \ 158 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 159 #define HCLR2(hp, reg, bits) \ 160 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 161 #define HCLR4(hp, reg, bits) \ 162 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 163 #define HSET1(hp, reg, bits) \ 164 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 165 #define HSET2(hp, reg, bits) \ 166 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 167 #define HSET4(hp, reg, bits) \ 168 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 169 170 static int sdhc_host_reset(sdmmc_chipset_handle_t); 171 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 172 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 173 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 174 static int sdhc_card_detect(sdmmc_chipset_handle_t); 175 static int sdhc_write_protect(sdmmc_chipset_handle_t); 176 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 177 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 178 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 179 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 180 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 181 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 182 static void sdhc_exec_command(sdmmc_chipset_handle_t, 183 struct sdmmc_command *); 184 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 185 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 186 static int sdhc_soft_reset(struct sdhc_host *, int); 187 static int sdhc_wait_intr(struct sdhc_host *, int, int); 188 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 189 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 190 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 191 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 192 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 193 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 194 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 195 196 static struct sdmmc_chip_functions sdhc_functions = { 197 /* host controller reset */ 198 .host_reset = sdhc_host_reset, 199 200 /* host controller capabilities */ 201 .host_ocr = sdhc_host_ocr, 202 .host_maxblklen = sdhc_host_maxblklen, 203 204 /* card detection */ 205 .card_detect = sdhc_card_detect, 206 207 /* write protect */ 208 .write_protect = sdhc_write_protect, 209 210 /* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */ 211 .bus_power = sdhc_bus_power, 212 .bus_clock = sdhc_bus_clock, 213 .bus_width = sdhc_bus_width, 214 .bus_rod = sdhc_bus_rod, 215 216 /* command execution */ 217 .exec_command = sdhc_exec_command, 218 219 /* card interrupt */ 220 .card_enable_intr = sdhc_card_enable_intr, 221 .card_intr_ack = sdhc_card_intr_ack 222 }; 223 224 static int 225 sdhc_cfprint(void *aux, const char *pnp) 226 { 227 const struct sdmmcbus_attach_args * const saa = aux; 228 const struct sdhc_host * const hp = saa->saa_sch; 229 230 if (pnp) { 231 aprint_normal("sdmmc at %s", pnp); 232 } 233 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 234 if (hp->sc->sc_host[host] == hp) { 235 aprint_normal(" slot %zu", host); 236 } 237 } 238 239 return UNCONF; 240 } 241 242 /* 243 * Called by attachment driver. For each SD card slot there is one SD 244 * host controller standard register set. (1.3) 245 */ 246 int 247 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 248 bus_space_handle_t ioh, bus_size_t iosize) 249 { 250 struct sdmmcbus_attach_args saa; 251 struct sdhc_host *hp; 252 uint32_t caps; 253 uint16_t sdhcver; 254 int error; 255 256 /* Allocate one more host structure. */ 257 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 258 if (hp == NULL) { 259 aprint_error_dev(sc->sc_dev, 260 "couldn't alloc memory (sdhc host)\n"); 261 goto err1; 262 } 263 sc->sc_host[sc->sc_nhosts++] = hp; 264 265 /* Fill in the new host structure. */ 266 hp->sc = sc; 267 hp->iot = iot; 268 hp->ioh = ioh; 269 hp->ios = iosize; 270 hp->dmat = sc->sc_dmat; 271 272 mutex_init(&hp->intr_lock, MUTEX_DEFAULT, IPL_SDMMC); 273 cv_init(&hp->intr_cv, "sdhcintr"); 274 275 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 276 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); 277 } else { 278 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 279 } 280 aprint_normal_dev(sc->sc_dev, "SDHC "); 281 hp->specver = SDHC_SPEC_VERSION(sdhcver); 282 switch (SDHC_SPEC_VERSION(sdhcver)) { 283 case SDHC_SPEC_VERS_100: 284 aprint_normal("1.0"); 285 break; 286 287 case SDHC_SPEC_VERS_200: 288 aprint_normal("2.0"); 289 break; 290 291 case SDHC_SPEC_VERS_300: 292 aprint_normal("3.0"); 293 break; 294 295 case SDHC_SPEC_VERS_400: 296 aprint_normal("4.0"); 297 break; 298 299 default: 300 aprint_normal("unknown version(0x%x)", 301 SDHC_SPEC_VERSION(sdhcver)); 302 break; 303 } 304 aprint_normal(", rev %u", SDHC_VENDOR_VERSION(sdhcver)); 305 306 /* 307 * Reset the host controller and enable interrupts. 308 */ 309 (void)sdhc_host_reset(hp); 310 311 /* Determine host capabilities. */ 312 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 313 caps = sc->sc_caps; 314 } else { 315 caps = HREAD4(hp, SDHC_CAPABILITIES); 316 } 317 318 /* 319 * Use DMA if the host system and the controller support it. 320 * Suports integrated or external DMA egine, with or without 321 * SDHC_DMA_ENABLE in the command. 322 */ 323 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 324 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 325 ISSET(caps, SDHC_DMA_SUPPORT)))) { 326 SET(hp->flags, SHF_USE_DMA); 327 328 if (ISSET(sc->sc_flags, SDHC_FLAG_USE_ADMA2) && 329 ISSET(caps, SDHC_ADMA2_SUPP)) { 330 SET(hp->flags, SHF_MODE_DMAEN); 331 /* 332 * 64-bit mode was present in the 2.00 spec, removed 333 * from 3.00, and re-added in 4.00 with a different 334 * descriptor layout. We only support 2.00 and 3.00 335 * descriptors for now. 336 */ 337 if (hp->specver == SDHC_SPEC_VERS_200 && 338 ISSET(caps, SDHC_64BIT_SYS_BUS)) { 339 SET(hp->flags, SHF_USE_ADMA2_64); 340 aprint_normal(", 64-bit ADMA2"); 341 } else { 342 SET(hp->flags, SHF_USE_ADMA2_32); 343 aprint_normal(", 32-bit ADMA2"); 344 } 345 } else { 346 if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) || 347 ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN)) 348 SET(hp->flags, SHF_MODE_DMAEN); 349 if (sc->sc_vendor_transfer_data_dma) { 350 aprint_normal(", platform DMA"); 351 } else { 352 aprint_normal(", SDMA"); 353 } 354 } 355 } else { 356 aprint_normal(", PIO"); 357 } 358 359 /* 360 * Determine the base clock frequency. (2.2.24) 361 */ 362 if (hp->specver >= SDHC_SPEC_VERS_300) { 363 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 364 } else { 365 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 366 } 367 if (hp->clkbase == 0 || 368 ISSET(sc->sc_flags, SDHC_FLAG_NO_CLKBASE)) { 369 if (sc->sc_clkbase == 0) { 370 /* The attachment driver must tell us. */ 371 aprint_error_dev(sc->sc_dev, 372 "unknown base clock frequency\n"); 373 goto err; 374 } 375 hp->clkbase = sc->sc_clkbase; 376 } 377 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 378 /* SDHC 1.0 supports only 10-63 MHz. */ 379 aprint_error_dev(sc->sc_dev, 380 "base clock frequency out of range: %u MHz\n", 381 hp->clkbase / 1000); 382 goto err; 383 } 384 aprint_normal(", %u kHz", hp->clkbase); 385 386 /* 387 * XXX Set the data timeout counter value according to 388 * capabilities. (2.2.15) 389 */ 390 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 391 #if 1 392 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 393 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 394 #endif 395 396 if (ISSET(caps, SDHC_EMBEDDED_SLOT)) 397 aprint_normal(", embedded slot"); 398 399 /* 400 * Determine SD bus voltage levels supported by the controller. 401 */ 402 aprint_normal(","); 403 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) { 404 SET(hp->ocr, MMC_OCR_HCS); 405 aprint_normal(" High-Speed"); 406 } 407 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V) && 408 (hp->specver < SDHC_SPEC_VERS_300 || 409 ISSET(caps, SDHC_EMBEDDED_SLOT))) { 410 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 411 aprint_normal(" 1.8V"); 412 } 413 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 414 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 415 aprint_normal(" 3.0V"); 416 } 417 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 418 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 419 aprint_normal(" 3.3V"); 420 } 421 422 /* 423 * Determine the maximum block length supported by the host 424 * controller. (2.2.24) 425 */ 426 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 427 case SDHC_MAX_BLK_LEN_512: 428 hp->maxblklen = 512; 429 break; 430 431 case SDHC_MAX_BLK_LEN_1024: 432 hp->maxblklen = 1024; 433 break; 434 435 case SDHC_MAX_BLK_LEN_2048: 436 hp->maxblklen = 2048; 437 break; 438 439 case SDHC_MAX_BLK_LEN_4096: 440 hp->maxblklen = 4096; 441 break; 442 443 default: 444 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 445 goto err; 446 } 447 aprint_normal(", %u byte blocks", hp->maxblklen); 448 aprint_normal("\n"); 449 450 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 451 int rseg; 452 453 /* Allocate ADMA2 descriptor memory */ 454 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 455 PAGE_SIZE, hp->adma_segs, 1, &rseg, BUS_DMA_WAITOK); 456 if (error) { 457 aprint_error_dev(sc->sc_dev, 458 "ADMA2 dmamem_alloc failed (%d)\n", error); 459 goto adma_done; 460 } 461 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 462 PAGE_SIZE, (void **)&hp->adma2, BUS_DMA_WAITOK); 463 if (error) { 464 aprint_error_dev(sc->sc_dev, 465 "ADMA2 dmamem_map failed (%d)\n", error); 466 goto adma_done; 467 } 468 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 469 0, BUS_DMA_WAITOK, &hp->adma_map); 470 if (error) { 471 aprint_error_dev(sc->sc_dev, 472 "ADMA2 dmamap_create failed (%d)\n", error); 473 goto adma_done; 474 } 475 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 476 hp->adma2, PAGE_SIZE, NULL, 477 BUS_DMA_WAITOK|BUS_DMA_WRITE); 478 if (error) { 479 aprint_error_dev(sc->sc_dev, 480 "ADMA2 dmamap_load failed (%d)\n", error); 481 goto adma_done; 482 } 483 484 memset(hp->adma2, 0, PAGE_SIZE); 485 486 adma_done: 487 if (error) 488 CLR(hp->flags, SHF_USE_ADMA2_MASK); 489 } 490 491 /* 492 * Attach the generic SD/MMC bus driver. (The bus driver must 493 * not invoke any chipset functions before it is attached.) 494 */ 495 memset(&saa, 0, sizeof(saa)); 496 saa.saa_busname = "sdmmc"; 497 saa.saa_sct = &sdhc_functions; 498 saa.saa_sch = hp; 499 saa.saa_dmat = hp->dmat; 500 saa.saa_clkmax = hp->clkbase; 501 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 502 saa.saa_clkmin = hp->clkbase / 256 / 2046; 503 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 504 saa.saa_clkmin = hp->clkbase / 256 / 16; 505 else if (hp->sc->sc_clkmsk != 0) 506 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 507 (ffs(hp->sc->sc_clkmsk) - 1)); 508 else if (hp->specver >= SDHC_SPEC_VERS_300) 509 saa.saa_clkmin = hp->clkbase / 0x3ff; 510 else 511 saa.saa_clkmin = hp->clkbase / 256; 512 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 513 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 514 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 515 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 516 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 517 if (ISSET(hp->flags, SHF_USE_DMA)) { 518 saa.saa_caps |= SMC_CAPS_DMA; 519 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 520 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 521 } 522 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 523 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 524 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 525 526 return 0; 527 528 err: 529 cv_destroy(&hp->intr_cv); 530 mutex_destroy(&hp->intr_lock); 531 free(hp, M_DEVBUF); 532 sc->sc_host[--sc->sc_nhosts] = NULL; 533 err1: 534 return 1; 535 } 536 537 int 538 sdhc_detach(struct sdhc_softc *sc, int flags) 539 { 540 struct sdhc_host *hp; 541 int rv = 0; 542 543 for (size_t n = 0; n < sc->sc_nhosts; n++) { 544 hp = sc->sc_host[n]; 545 if (hp == NULL) 546 continue; 547 if (hp->sdmmc != NULL) { 548 rv = config_detach(hp->sdmmc, flags); 549 if (rv) 550 break; 551 hp->sdmmc = NULL; 552 } 553 /* disable interrupts */ 554 if ((flags & DETACH_FORCE) == 0) { 555 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 556 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 557 } else { 558 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 559 } 560 sdhc_soft_reset(hp, SDHC_RESET_ALL); 561 } 562 cv_destroy(&hp->intr_cv); 563 mutex_destroy(&hp->intr_lock); 564 if (hp->ios > 0) { 565 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 566 hp->ios = 0; 567 } 568 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 569 bus_dmamap_unload(sc->sc_dmat, hp->adma_map); 570 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 571 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 572 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, 1); 573 } 574 free(hp, M_DEVBUF); 575 sc->sc_host[n] = NULL; 576 } 577 578 return rv; 579 } 580 581 bool 582 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 583 { 584 struct sdhc_softc *sc = device_private(dev); 585 struct sdhc_host *hp; 586 size_t i; 587 588 /* XXX poll for command completion or suspend command 589 * in progress */ 590 591 /* Save the host controller state. */ 592 for (size_t n = 0; n < sc->sc_nhosts; n++) { 593 hp = sc->sc_host[n]; 594 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 595 for (i = 0; i < sizeof hp->regs; i += 4) { 596 uint32_t v = HREAD4(hp, i); 597 hp->regs[i + 0] = (v >> 0); 598 hp->regs[i + 1] = (v >> 8); 599 if (i + 3 < sizeof hp->regs) { 600 hp->regs[i + 2] = (v >> 16); 601 hp->regs[i + 3] = (v >> 24); 602 } 603 } 604 } else { 605 for (i = 0; i < sizeof hp->regs; i++) { 606 hp->regs[i] = HREAD1(hp, i); 607 } 608 } 609 } 610 return true; 611 } 612 613 bool 614 sdhc_resume(device_t dev, const pmf_qual_t *qual) 615 { 616 struct sdhc_softc *sc = device_private(dev); 617 struct sdhc_host *hp; 618 size_t i; 619 620 /* Restore the host controller state. */ 621 for (size_t n = 0; n < sc->sc_nhosts; n++) { 622 hp = sc->sc_host[n]; 623 (void)sdhc_host_reset(hp); 624 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 625 for (i = 0; i < sizeof hp->regs; i += 4) { 626 if (i + 3 < sizeof hp->regs) { 627 HWRITE4(hp, i, 628 (hp->regs[i + 0] << 0) 629 | (hp->regs[i + 1] << 8) 630 | (hp->regs[i + 2] << 16) 631 | (hp->regs[i + 3] << 24)); 632 } else { 633 HWRITE4(hp, i, 634 (hp->regs[i + 0] << 0) 635 | (hp->regs[i + 1] << 8)); 636 } 637 } 638 } else { 639 for (i = 0; i < sizeof hp->regs; i++) { 640 HWRITE1(hp, i, hp->regs[i]); 641 } 642 } 643 } 644 return true; 645 } 646 647 bool 648 sdhc_shutdown(device_t dev, int flags) 649 { 650 struct sdhc_softc *sc = device_private(dev); 651 struct sdhc_host *hp; 652 653 /* XXX chip locks up if we don't disable it before reboot. */ 654 for (size_t i = 0; i < sc->sc_nhosts; i++) { 655 hp = sc->sc_host[i]; 656 (void)sdhc_host_reset(hp); 657 } 658 return true; 659 } 660 661 /* 662 * Reset the host controller. Called during initialization, when 663 * cards are removed, upon resume, and during error recovery. 664 */ 665 static int 666 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 667 { 668 struct sdhc_host *hp = (struct sdhc_host *)sch; 669 uint32_t sdhcimask; 670 int error; 671 672 KASSERT(mutex_owned(&hp->intr_lock)); 673 674 /* Disable all interrupts. */ 675 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 676 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 677 } else { 678 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 679 } 680 681 /* 682 * Reset the entire host controller and wait up to 100ms for 683 * the controller to clear the reset bit. 684 */ 685 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 686 if (error) 687 goto out; 688 689 /* Set data timeout counter value to max for now. */ 690 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 691 #if 1 692 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 693 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 694 #endif 695 696 /* Enable interrupts. */ 697 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 698 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 699 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 700 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 701 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 702 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 703 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 704 sdhcimask ^= 705 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 706 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 707 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 708 } else { 709 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 710 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 711 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 712 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 713 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 714 } 715 716 out: 717 return error; 718 } 719 720 static int 721 sdhc_host_reset(sdmmc_chipset_handle_t sch) 722 { 723 struct sdhc_host *hp = (struct sdhc_host *)sch; 724 int error; 725 726 mutex_enter(&hp->intr_lock); 727 error = sdhc_host_reset1(sch); 728 mutex_exit(&hp->intr_lock); 729 730 return error; 731 } 732 733 static uint32_t 734 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 735 { 736 struct sdhc_host *hp = (struct sdhc_host *)sch; 737 738 return hp->ocr; 739 } 740 741 static int 742 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 743 { 744 struct sdhc_host *hp = (struct sdhc_host *)sch; 745 746 return hp->maxblklen; 747 } 748 749 /* 750 * Return non-zero if the card is currently inserted. 751 */ 752 static int 753 sdhc_card_detect(sdmmc_chipset_handle_t sch) 754 { 755 struct sdhc_host *hp = (struct sdhc_host *)sch; 756 int r; 757 758 if (hp->sc->sc_vendor_card_detect) 759 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 760 761 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 762 763 return r ? 1 : 0; 764 } 765 766 /* 767 * Return non-zero if the card is currently write-protected. 768 */ 769 static int 770 sdhc_write_protect(sdmmc_chipset_handle_t sch) 771 { 772 struct sdhc_host *hp = (struct sdhc_host *)sch; 773 int r; 774 775 if (hp->sc->sc_vendor_write_protect) 776 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 777 778 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 779 780 return r ? 0 : 1; 781 } 782 783 /* 784 * Set or change SD bus voltage and enable or disable SD bus power. 785 * Return zero on success. 786 */ 787 static int 788 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 789 { 790 struct sdhc_host *hp = (struct sdhc_host *)sch; 791 uint8_t vdd; 792 int error = 0; 793 const uint32_t pcmask = 794 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 795 796 mutex_enter(&hp->intr_lock); 797 798 /* 799 * Disable bus power before voltage change. 800 */ 801 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 802 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 803 HWRITE1(hp, SDHC_POWER_CTL, 0); 804 805 /* If power is disabled, reset the host and return now. */ 806 if (ocr == 0) { 807 (void)sdhc_host_reset1(hp); 808 goto out; 809 } 810 811 /* 812 * Select the lowest voltage according to capabilities. 813 */ 814 ocr &= hp->ocr; 815 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 816 vdd = SDHC_VOLTAGE_1_8V; 817 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 818 vdd = SDHC_VOLTAGE_3_0V; 819 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 820 vdd = SDHC_VOLTAGE_3_3V; 821 } else { 822 /* Unsupported voltage level requested. */ 823 error = EINVAL; 824 goto out; 825 } 826 827 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 828 /* 829 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 830 * voltage ramp until power rises. 831 */ 832 833 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SINGLE_POWER_WRITE)) { 834 HWRITE1(hp, SDHC_POWER_CTL, 835 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 836 } else { 837 HWRITE1(hp, SDHC_POWER_CTL, 838 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 839 sdmmc_delay(1); 840 HWRITE1(hp, SDHC_POWER_CTL, 841 (vdd << SDHC_VOLTAGE_SHIFT)); 842 sdmmc_delay(1); 843 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 844 sdmmc_delay(10000); 845 } 846 847 /* 848 * The host system may not power the bus due to battery low, 849 * etc. In that case, the host controller should clear the 850 * bus power bit. 851 */ 852 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 853 error = ENXIO; 854 goto out; 855 } 856 } 857 858 out: 859 mutex_exit(&hp->intr_lock); 860 861 return error; 862 } 863 864 /* 865 * Return the smallest possible base clock frequency divisor value 866 * for the CLOCK_CTL register to produce `freq' (KHz). 867 */ 868 static bool 869 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 870 { 871 u_int div; 872 873 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 874 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 875 if ((hp->clkbase / div) <= freq) { 876 *divp = SDHC_SDCLK_CGM 877 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 878 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 879 //freq = hp->clkbase / div; 880 return true; 881 } 882 } 883 /* No divisor found. */ 884 return false; 885 } 886 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 887 u_int dvs = (hp->clkbase + freq - 1) / freq; 888 u_int roundup = dvs & 1; 889 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 890 if (dvs + roundup <= 16) { 891 dvs += roundup - 1; 892 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 893 | (dvs << SDHC_SDCLK_DVS_SHIFT); 894 DPRINTF(2, 895 ("%s: divisor for freq %u is %u * %u\n", 896 HDEVNAME(hp), freq, div * 2, dvs + 1)); 897 //freq = hp->clkbase / (div * 2) * (dvs + 1); 898 return true; 899 } 900 /* 901 * If we drop bits, we need to round up the divisor. 902 */ 903 roundup |= dvs & 1; 904 } 905 /* No divisor found. */ 906 return false; 907 } 908 if (hp->sc->sc_clkmsk != 0) { 909 div = howmany(hp->clkbase, freq); 910 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 911 return false; 912 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 913 //freq = hp->clkbase / div; 914 return true; 915 } 916 if (hp->specver >= SDHC_SPEC_VERS_300) { 917 div = howmany(hp->clkbase, freq); 918 div = div > 1 ? howmany(div, 2) : 0; 919 if (div > 0x3ff) 920 return false; 921 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 922 << SDHC_SDCLK_XDIV_SHIFT) | 923 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 924 << SDHC_SDCLK_DIV_SHIFT); 925 //freq = hp->clkbase / (div ? div * 2 : 1); 926 return true; 927 } else { 928 for (div = 1; div <= 256; div *= 2) { 929 if ((hp->clkbase / div) <= freq) { 930 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 931 //freq = hp->clkbase / div; 932 return true; 933 } 934 } 935 /* No divisor found. */ 936 return false; 937 } 938 /* No divisor found. */ 939 return false; 940 } 941 942 /* 943 * Set or change SDCLK frequency or disable the SD clock. 944 * Return zero on success. 945 */ 946 static int 947 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 948 { 949 struct sdhc_host *hp = (struct sdhc_host *)sch; 950 u_int div; 951 u_int timo; 952 int16_t reg; 953 int error = 0; 954 bool present __diagused; 955 956 mutex_enter(&hp->intr_lock); 957 958 #ifdef DIAGNOSTIC 959 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 960 961 /* Must not stop the clock if commands are in progress. */ 962 if (present && sdhc_card_detect(hp)) { 963 aprint_normal_dev(hp->sc->sc_dev, 964 "%s: command in progress\n", __func__); 965 } 966 #endif 967 968 if (hp->sc->sc_vendor_bus_clock) { 969 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 970 if (error != 0) 971 goto out; 972 } 973 974 /* 975 * Stop SD clock before changing the frequency. 976 */ 977 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 978 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 979 if (freq == SDMMC_SDCLK_OFF) { 980 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 981 goto out; 982 } 983 } else { 984 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 985 if (freq == SDMMC_SDCLK_OFF) 986 goto out; 987 } 988 989 /* 990 * Set the minimum base clock frequency divisor. 991 */ 992 if (!sdhc_clock_divisor(hp, freq, &div)) { 993 /* Invalid base clock frequency or `freq' value. */ 994 aprint_error_dev(hp->sc->sc_dev, 995 "Invalid bus clock %d kHz\n", freq); 996 error = EINVAL; 997 goto out; 998 } 999 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1000 HWRITE4(hp, SDHC_CLOCK_CTL, 1001 div | (SDHC_TIMEOUT_MAX << 16)); 1002 } else { 1003 reg = HREAD2(hp, SDHC_CLOCK_CTL); 1004 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 1005 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 1006 } 1007 1008 /* 1009 * Start internal clock. Wait 10ms for stabilization. 1010 */ 1011 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1012 sdmmc_delay(10000); 1013 HSET4(hp, SDHC_CLOCK_CTL, 1014 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 1015 } else { 1016 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 1017 for (timo = 1000; timo > 0; timo--) { 1018 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 1019 SDHC_INTCLK_STABLE)) 1020 break; 1021 sdmmc_delay(10); 1022 } 1023 if (timo == 0) { 1024 error = ETIMEDOUT; 1025 goto out; 1026 } 1027 } 1028 1029 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1030 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 1031 /* 1032 * Sending 80 clocks at 400kHz takes 200us. 1033 * So delay for that time + slop and then 1034 * check a few times for completion. 1035 */ 1036 sdmmc_delay(210); 1037 for (timo = 10; timo > 0; timo--) { 1038 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 1039 SDHC_INIT_ACTIVE)) 1040 break; 1041 sdmmc_delay(10); 1042 } 1043 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 1044 1045 /* 1046 * Enable SD clock. 1047 */ 1048 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1049 } else { 1050 /* 1051 * Enable SD clock. 1052 */ 1053 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1054 1055 if (freq > 25000 && 1056 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 1057 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1058 else 1059 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1060 } 1061 1062 out: 1063 mutex_exit(&hp->intr_lock); 1064 1065 return error; 1066 } 1067 1068 static int 1069 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 1070 { 1071 struct sdhc_host *hp = (struct sdhc_host *)sch; 1072 int reg; 1073 1074 switch (width) { 1075 case 1: 1076 case 4: 1077 break; 1078 1079 case 8: 1080 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 1081 break; 1082 /* FALLTHROUGH */ 1083 default: 1084 DPRINTF(0,("%s: unsupported bus width (%d)\n", 1085 HDEVNAME(hp), width)); 1086 return 1; 1087 } 1088 1089 mutex_enter(&hp->intr_lock); 1090 1091 reg = HREAD1(hp, SDHC_HOST_CTL); 1092 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1093 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 1094 if (width == 4) 1095 reg |= SDHC_4BIT_MODE; 1096 else if (width == 8) 1097 reg |= SDHC_ESDHC_8BIT_MODE; 1098 } else { 1099 reg &= ~SDHC_4BIT_MODE; 1100 if (hp->specver >= SDHC_SPEC_VERS_300) { 1101 reg &= ~SDHC_8BIT_MODE; 1102 } 1103 if (width == 4) { 1104 reg |= SDHC_4BIT_MODE; 1105 } else if (width == 8 && hp->specver >= SDHC_SPEC_VERS_300) { 1106 reg |= SDHC_8BIT_MODE; 1107 } 1108 } 1109 HWRITE1(hp, SDHC_HOST_CTL, reg); 1110 1111 mutex_exit(&hp->intr_lock); 1112 1113 return 0; 1114 } 1115 1116 static int 1117 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1118 { 1119 struct sdhc_host *hp = (struct sdhc_host *)sch; 1120 1121 if (hp->sc->sc_vendor_rod) 1122 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1123 1124 return 0; 1125 } 1126 1127 static void 1128 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1129 { 1130 struct sdhc_host *hp = (struct sdhc_host *)sch; 1131 1132 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1133 mutex_enter(&hp->intr_lock); 1134 if (enable) { 1135 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1136 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1137 } else { 1138 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1139 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1140 } 1141 mutex_exit(&hp->intr_lock); 1142 } 1143 } 1144 1145 static void 1146 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1147 { 1148 struct sdhc_host *hp = (struct sdhc_host *)sch; 1149 1150 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1151 mutex_enter(&hp->intr_lock); 1152 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1153 mutex_exit(&hp->intr_lock); 1154 } 1155 } 1156 1157 static int 1158 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1159 { 1160 uint32_t state; 1161 int timeout; 1162 1163 for (timeout = 10000; timeout > 0; timeout--) { 1164 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 1165 return 0; 1166 sdmmc_delay(10); 1167 } 1168 aprint_error_dev(hp->sc->sc_dev, "timeout waiting for %x (state=%x)\n", 1169 value, state); 1170 return ETIMEDOUT; 1171 } 1172 1173 static void 1174 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1175 { 1176 struct sdhc_host *hp = (struct sdhc_host *)sch; 1177 int error; 1178 1179 mutex_enter(&hp->intr_lock); 1180 1181 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1182 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1183 if (ISSET(hp->flags, SHF_USE_DMA)) { 1184 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1185 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1186 } else { 1187 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1188 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1189 } 1190 } 1191 1192 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_TIMEOUT)) { 1193 const uint16_t eintr = SDHC_CMD_TIMEOUT_ERROR; 1194 if (cmd->c_data != NULL) { 1195 HCLR2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1196 HCLR2(hp, SDHC_EINTR_STATUS_EN, eintr); 1197 } else { 1198 HSET2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1199 HSET2(hp, SDHC_EINTR_STATUS_EN, eintr); 1200 } 1201 } 1202 1203 /* 1204 * Start the MMC command, or mark `cmd' as failed and return. 1205 */ 1206 error = sdhc_start_command(hp, cmd); 1207 if (error) { 1208 cmd->c_error = error; 1209 goto out; 1210 } 1211 1212 /* 1213 * Wait until the command phase is done, or until the command 1214 * is marked done for any other reason. 1215 */ 1216 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1217 cmd->c_error = ETIMEDOUT; 1218 goto out; 1219 } 1220 1221 /* 1222 * The host controller removes bits [0:7] from the response 1223 * data (CRC) and we pass the data up unchanged to the bus 1224 * driver (without padding). 1225 */ 1226 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1227 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1228 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1229 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1230 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1231 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1232 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1233 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1234 (cmd->c_resp[1] << 24); 1235 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1236 (cmd->c_resp[2] << 24); 1237 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1238 (cmd->c_resp[3] << 24); 1239 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1240 } 1241 } 1242 } 1243 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1244 1245 /* 1246 * If the command has data to transfer in any direction, 1247 * execute the transfer now. 1248 */ 1249 if (cmd->c_error == 0 && cmd->c_data != NULL) 1250 sdhc_transfer_data(hp, cmd); 1251 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1252 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10)) { 1253 cmd->c_error = ETIMEDOUT; 1254 goto out; 1255 } 1256 } 1257 1258 out: 1259 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1260 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1261 /* Turn off the LED. */ 1262 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1263 } 1264 SET(cmd->c_flags, SCF_ITSDONE); 1265 1266 mutex_exit(&hp->intr_lock); 1267 1268 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1269 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1270 cmd->c_flags, cmd->c_error)); 1271 } 1272 1273 static int 1274 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1275 { 1276 struct sdhc_softc * const sc = hp->sc; 1277 uint16_t blksize = 0; 1278 uint16_t blkcount = 0; 1279 uint16_t mode; 1280 uint16_t command; 1281 int error; 1282 1283 KASSERT(mutex_owned(&hp->intr_lock)); 1284 1285 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1286 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1287 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1288 1289 /* 1290 * The maximum block length for commands should be the minimum 1291 * of the host buffer size and the card buffer size. (1.7.2) 1292 */ 1293 1294 /* Fragment the data into proper blocks. */ 1295 if (cmd->c_datalen > 0) { 1296 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1297 blkcount = cmd->c_datalen / blksize; 1298 if (cmd->c_datalen % blksize > 0) { 1299 /* XXX: Split this command. (1.7.4) */ 1300 aprint_error_dev(sc->sc_dev, 1301 "data not a multiple of %u bytes\n", blksize); 1302 return EINVAL; 1303 } 1304 } 1305 1306 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1307 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1308 aprint_error_dev(sc->sc_dev, "too much data\n"); 1309 return EINVAL; 1310 } 1311 1312 /* Prepare transfer mode register value. (2.2.5) */ 1313 mode = SDHC_BLOCK_COUNT_ENABLE; 1314 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1315 mode |= SDHC_READ_MODE; 1316 if (blkcount > 1) { 1317 mode |= SDHC_MULTI_BLOCK_MODE; 1318 /* XXX only for memory commands? */ 1319 mode |= SDHC_AUTO_CMD12_ENABLE; 1320 } 1321 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1322 ISSET(hp->flags, SHF_MODE_DMAEN)) { 1323 mode |= SDHC_DMA_ENABLE; 1324 } 1325 1326 /* 1327 * Prepare command register value. (2.2.6) 1328 */ 1329 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1330 1331 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1332 command |= SDHC_CRC_CHECK_ENABLE; 1333 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1334 command |= SDHC_INDEX_CHECK_ENABLE; 1335 if (cmd->c_data != NULL) 1336 command |= SDHC_DATA_PRESENT_SELECT; 1337 1338 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1339 command |= SDHC_NO_RESPONSE; 1340 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1341 command |= SDHC_RESP_LEN_136; 1342 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1343 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1344 else 1345 command |= SDHC_RESP_LEN_48; 1346 1347 /* Wait until command and data inhibit bits are clear. (1.5) */ 1348 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1349 if (error) { 1350 aprint_error_dev(sc->sc_dev, "command or data phase inhibited\n"); 1351 return error; 1352 } 1353 1354 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1355 HDEVNAME(hp), blksize, blkcount, mode, command)); 1356 1357 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1358 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1359 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1360 } 1361 1362 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1363 /* Alert the user not to remove the card. */ 1364 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1365 } 1366 1367 /* Set DMA start address. */ 1368 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK) && cmd->c_datalen > 0) { 1369 for (int seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 1370 bus_addr_t paddr = 1371 cmd->c_dmamap->dm_segs[seg].ds_addr; 1372 uint16_t len = 1373 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1374 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1375 uint16_t attr = 1376 SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1377 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 1378 attr |= SDHC_ADMA2_END; 1379 } 1380 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1381 struct sdhc_adma2_descriptor32 *desc = 1382 hp->adma2; 1383 desc[seg].attribute = htole16(attr); 1384 desc[seg].length = htole16(len); 1385 desc[seg].address = htole32(paddr); 1386 } else { 1387 struct sdhc_adma2_descriptor64 *desc = 1388 hp->adma2; 1389 desc[seg].attribute = htole16(attr); 1390 desc[seg].length = htole16(len); 1391 desc[seg].address = htole32(paddr & 0xffffffff); 1392 desc[seg].address_hi = htole32( 1393 (uint64_t)paddr >> 32); 1394 } 1395 } 1396 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1397 struct sdhc_adma2_descriptor32 *desc = hp->adma2; 1398 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1399 } else { 1400 struct sdhc_adma2_descriptor64 *desc = hp->adma2; 1401 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1402 } 1403 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1404 BUS_DMASYNC_PREWRITE); 1405 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1406 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2); 1407 1408 const bus_addr_t desc_addr = hp->adma_map->dm_segs[0].ds_addr; 1409 1410 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff); 1411 if (ISSET(hp->flags, SHF_USE_ADMA2_64)) { 1412 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4, 1413 (uint64_t)desc_addr >> 32); 1414 } 1415 } else if (ISSET(mode, SDHC_DMA_ENABLE) && 1416 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) { 1417 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1418 } 1419 1420 /* 1421 * Start a CPU data transfer. Writing to the high order byte 1422 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1423 */ 1424 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1425 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1426 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1427 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1428 } else { 1429 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1430 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1431 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1432 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1433 HWRITE2(hp, SDHC_COMMAND, command); 1434 } 1435 1436 return 0; 1437 } 1438 1439 static void 1440 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1441 { 1442 struct sdhc_softc *sc = hp->sc; 1443 int error; 1444 1445 KASSERT(mutex_owned(&hp->intr_lock)); 1446 1447 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1448 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1449 1450 #ifdef SDHC_DEBUG 1451 /* XXX I forgot why I wanted to know when this happens :-( */ 1452 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1453 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1454 aprint_error_dev(hp->sc->sc_dev, 1455 "CMD52/53 error response flags %#x\n", 1456 MMC_R1(cmd->c_resp) & 0xff00); 1457 } 1458 #endif 1459 1460 if (cmd->c_dmamap != NULL) { 1461 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1462 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd); 1463 if (error == 0 && !sdhc_wait_intr(hp, 1464 SDHC_TRANSFER_COMPLETE, SDHC_DMA_TIMEOUT)) { 1465 error = ETIMEDOUT; 1466 } 1467 } else { 1468 error = sdhc_transfer_data_dma(hp, cmd); 1469 } 1470 } else 1471 error = sdhc_transfer_data_pio(hp, cmd); 1472 if (error) 1473 cmd->c_error = error; 1474 SET(cmd->c_flags, SCF_ITSDONE); 1475 1476 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1477 HDEVNAME(hp), cmd->c_error)); 1478 } 1479 1480 static int 1481 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1482 { 1483 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1484 bus_addr_t posaddr; 1485 bus_addr_t segaddr; 1486 bus_size_t seglen; 1487 u_int seg = 0; 1488 int error = 0; 1489 int status; 1490 1491 KASSERT(mutex_owned(&hp->intr_lock)); 1492 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1493 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1494 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1495 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1496 1497 for (;;) { 1498 status = sdhc_wait_intr(hp, 1499 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1500 SDHC_DMA_TIMEOUT); 1501 1502 if (status & SDHC_TRANSFER_COMPLETE) { 1503 break; 1504 } 1505 if (!status) { 1506 error = ETIMEDOUT; 1507 break; 1508 } 1509 1510 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1511 continue; 1512 } 1513 1514 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1515 continue; 1516 } 1517 1518 /* DMA Interrupt (boundary crossing) */ 1519 1520 segaddr = dm_segs[seg].ds_addr; 1521 seglen = dm_segs[seg].ds_len; 1522 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1523 1524 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1525 continue; 1526 } 1527 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1528 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1529 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1530 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1531 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1532 } 1533 1534 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1535 bus_dmamap_sync(hp->sc->sc_dmat, hp->adma_map, 0, 1536 PAGE_SIZE, BUS_DMASYNC_POSTWRITE); 1537 } 1538 1539 return error; 1540 } 1541 1542 static int 1543 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1544 { 1545 uint8_t *data = cmd->c_data; 1546 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1547 u_int len, datalen; 1548 u_int imask; 1549 u_int pmask; 1550 int error = 0; 1551 1552 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1553 imask = SDHC_BUFFER_READ_READY; 1554 pmask = SDHC_BUFFER_READ_ENABLE; 1555 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1556 pio_func = esdhc_read_data_pio; 1557 } else { 1558 pio_func = sdhc_read_data_pio; 1559 } 1560 } else { 1561 imask = SDHC_BUFFER_WRITE_READY; 1562 pmask = SDHC_BUFFER_WRITE_ENABLE; 1563 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1564 pio_func = esdhc_write_data_pio; 1565 } else { 1566 pio_func = sdhc_write_data_pio; 1567 } 1568 } 1569 datalen = cmd->c_datalen; 1570 1571 KASSERT(mutex_owned(&hp->intr_lock)); 1572 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1573 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1574 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1575 1576 while (datalen > 0) { 1577 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1578 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1579 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1580 } else { 1581 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1582 } 1583 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1584 error = ETIMEDOUT; 1585 break; 1586 } 1587 1588 error = sdhc_wait_state(hp, pmask, pmask); 1589 if (error) 1590 break; 1591 } 1592 1593 len = MIN(datalen, cmd->c_blklen); 1594 (*pio_func)(hp, data, len); 1595 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1596 HDEVNAME(hp), len, data)); 1597 1598 data += len; 1599 datalen -= len; 1600 } 1601 1602 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1603 SDHC_TRANSFER_TIMEOUT)) 1604 error = ETIMEDOUT; 1605 1606 return error; 1607 } 1608 1609 static void 1610 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1611 { 1612 1613 if (((__uintptr_t)data & 3) == 0) { 1614 while (datalen > 3) { 1615 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1616 data += 4; 1617 datalen -= 4; 1618 } 1619 if (datalen > 1) { 1620 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1621 data += 2; 1622 datalen -= 2; 1623 } 1624 if (datalen > 0) { 1625 *data = HREAD1(hp, SDHC_DATA); 1626 data += 1; 1627 datalen -= 1; 1628 } 1629 } else if (((__uintptr_t)data & 1) == 0) { 1630 while (datalen > 1) { 1631 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1632 data += 2; 1633 datalen -= 2; 1634 } 1635 if (datalen > 0) { 1636 *data = HREAD1(hp, SDHC_DATA); 1637 data += 1; 1638 datalen -= 1; 1639 } 1640 } else { 1641 while (datalen > 0) { 1642 *data = HREAD1(hp, SDHC_DATA); 1643 data += 1; 1644 datalen -= 1; 1645 } 1646 } 1647 } 1648 1649 static void 1650 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1651 { 1652 1653 if (((__uintptr_t)data & 3) == 0) { 1654 while (datalen > 3) { 1655 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 1656 data += 4; 1657 datalen -= 4; 1658 } 1659 if (datalen > 1) { 1660 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1661 data += 2; 1662 datalen -= 2; 1663 } 1664 if (datalen > 0) { 1665 HWRITE1(hp, SDHC_DATA, *data); 1666 data += 1; 1667 datalen -= 1; 1668 } 1669 } else if (((__uintptr_t)data & 1) == 0) { 1670 while (datalen > 1) { 1671 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1672 data += 2; 1673 datalen -= 2; 1674 } 1675 if (datalen > 0) { 1676 HWRITE1(hp, SDHC_DATA, *data); 1677 data += 1; 1678 datalen -= 1; 1679 } 1680 } else { 1681 while (datalen > 0) { 1682 HWRITE1(hp, SDHC_DATA, *data); 1683 data += 1; 1684 datalen -= 1; 1685 } 1686 } 1687 } 1688 1689 static void 1690 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1691 { 1692 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1693 uint32_t v; 1694 1695 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1696 size_t count = 0; 1697 1698 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1699 if (count == 0) { 1700 /* 1701 * If we've drained "watermark" words, we need to wait 1702 * a little bit so the read FIFO can refill. 1703 */ 1704 sdmmc_delay(10); 1705 count = watermark; 1706 } 1707 v = HREAD4(hp, SDHC_DATA); 1708 v = le32toh(v); 1709 *(uint32_t *)data = v; 1710 data += 4; 1711 datalen -= 4; 1712 status = HREAD2(hp, SDHC_NINTR_STATUS); 1713 count--; 1714 } 1715 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1716 if (count == 0) { 1717 sdmmc_delay(10); 1718 } 1719 v = HREAD4(hp, SDHC_DATA); 1720 v = le32toh(v); 1721 do { 1722 *data++ = v; 1723 v >>= 8; 1724 } while (--datalen > 0); 1725 } 1726 } 1727 1728 static void 1729 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1730 { 1731 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1732 uint32_t v; 1733 1734 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1735 size_t count = watermark; 1736 1737 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1738 if (count == 0) { 1739 sdmmc_delay(10); 1740 count = watermark; 1741 } 1742 v = *(uint32_t *)data; 1743 v = htole32(v); 1744 HWRITE4(hp, SDHC_DATA, v); 1745 data += 4; 1746 datalen -= 4; 1747 status = HREAD2(hp, SDHC_NINTR_STATUS); 1748 count--; 1749 } 1750 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1751 if (count == 0) { 1752 sdmmc_delay(10); 1753 } 1754 v = *(uint32_t *)data; 1755 v = htole32(v); 1756 HWRITE4(hp, SDHC_DATA, v); 1757 } 1758 } 1759 1760 /* Prepare for another command. */ 1761 static int 1762 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1763 { 1764 int timo; 1765 1766 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1767 1768 /* Request the reset. */ 1769 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1770 1771 /* 1772 * If necessary, wait for the controller to set the bits to 1773 * acknowledge the reset. 1774 */ 1775 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 1776 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 1777 for (timo = 10000; timo > 0; timo--) { 1778 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1779 break; 1780 /* Short delay because I worry we may miss it... */ 1781 sdmmc_delay(1); 1782 } 1783 if (timo == 0) 1784 return ETIMEDOUT; 1785 } 1786 1787 /* 1788 * Wait for the controller to clear the bits to indicate that 1789 * the reset has completed. 1790 */ 1791 for (timo = 10; timo > 0; timo--) { 1792 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1793 break; 1794 sdmmc_delay(10000); 1795 } 1796 if (timo == 0) { 1797 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1798 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1799 return ETIMEDOUT; 1800 } 1801 1802 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1803 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1804 } 1805 1806 return 0; 1807 } 1808 1809 static int 1810 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1811 { 1812 int status; 1813 1814 KASSERT(mutex_owned(&hp->intr_lock)); 1815 1816 mask |= SDHC_ERROR_INTERRUPT; 1817 1818 status = hp->intr_status & mask; 1819 while (status == 0) { 1820 if (cv_timedwait(&hp->intr_cv, &hp->intr_lock, timo) 1821 == EWOULDBLOCK) { 1822 status |= SDHC_ERROR_INTERRUPT; 1823 break; 1824 } 1825 status = hp->intr_status & mask; 1826 } 1827 hp->intr_status &= ~status; 1828 1829 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1830 hp->intr_error_status)); 1831 1832 /* Command timeout has higher priority than command complete. */ 1833 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1834 hp->intr_error_status = 0; 1835 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1836 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1837 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1838 } 1839 status = 0; 1840 } 1841 1842 return status; 1843 } 1844 1845 /* 1846 * Established by attachment driver at interrupt priority IPL_SDMMC. 1847 */ 1848 int 1849 sdhc_intr(void *arg) 1850 { 1851 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1852 struct sdhc_host *hp; 1853 int done = 0; 1854 uint16_t status; 1855 uint16_t error; 1856 1857 /* We got an interrupt, but we don't know from which slot. */ 1858 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1859 hp = sc->sc_host[host]; 1860 if (hp == NULL) 1861 continue; 1862 1863 mutex_enter(&hp->intr_lock); 1864 1865 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1866 /* Find out which interrupts are pending. */ 1867 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1868 status = xstatus; 1869 error = xstatus >> 16; 1870 if (error) 1871 xstatus |= SDHC_ERROR_INTERRUPT; 1872 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1873 goto next_port; /* no interrupt for us */ 1874 /* Acknowledge the interrupts we are about to handle. */ 1875 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1876 } else { 1877 /* Find out which interrupts are pending. */ 1878 error = 0; 1879 status = HREAD2(hp, SDHC_NINTR_STATUS); 1880 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1881 goto next_port; /* no interrupt for us */ 1882 /* Acknowledge the interrupts we are about to handle. */ 1883 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1884 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1885 /* Acknowledge error interrupts. */ 1886 error = HREAD2(hp, SDHC_EINTR_STATUS); 1887 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1888 } 1889 } 1890 1891 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1892 status, error)); 1893 1894 /* Claim this interrupt. */ 1895 done = 1; 1896 1897 if (ISSET(error, SDHC_ADMA_ERROR)) { 1898 uint8_t adma_err = HREAD1(hp, SDHC_ADMA_ERROR_STATUS); 1899 printf("%s: ADMA error, status %02x\n", HDEVNAME(hp), 1900 adma_err); 1901 } 1902 1903 /* 1904 * Service error interrupts. 1905 */ 1906 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1907 SDHC_DATA_TIMEOUT_ERROR)) { 1908 hp->intr_error_status |= error; 1909 hp->intr_status |= status; 1910 cv_broadcast(&hp->intr_cv); 1911 } 1912 1913 /* 1914 * Wake up the sdmmc event thread to scan for cards. 1915 */ 1916 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1917 if (hp->sdmmc != NULL) { 1918 sdmmc_needs_discover(hp->sdmmc); 1919 } 1920 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1921 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1922 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1923 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1924 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1925 } 1926 } 1927 1928 /* 1929 * Wake up the blocking process to service command 1930 * related interrupt(s). 1931 */ 1932 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1933 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1934 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1935 hp->intr_status |= status; 1936 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1937 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1938 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1939 } 1940 cv_broadcast(&hp->intr_cv); 1941 } 1942 1943 /* 1944 * Service SD card interrupts. 1945 */ 1946 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1947 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1948 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1949 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1950 sdmmc_card_intr(hp->sdmmc); 1951 } 1952 next_port: 1953 mutex_exit(&hp->intr_lock); 1954 } 1955 1956 return done; 1957 } 1958 1959 kmutex_t * 1960 sdhc_host_lock(struct sdhc_host *hp) 1961 { 1962 return &hp->intr_lock; 1963 } 1964 1965 #ifdef SDHC_DEBUG 1966 void 1967 sdhc_dump_regs(struct sdhc_host *hp) 1968 { 1969 1970 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1971 HREAD4(hp, SDHC_PRESENT_STATE)); 1972 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1973 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1974 HREAD1(hp, SDHC_POWER_CTL)); 1975 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1976 HREAD2(hp, SDHC_NINTR_STATUS)); 1977 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1978 HREAD2(hp, SDHC_EINTR_STATUS)); 1979 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1980 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1981 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1982 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1983 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1984 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1985 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1986 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1987 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1988 HREAD4(hp, SDHC_CAPABILITIES)); 1989 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1990 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1991 } 1992 #endif 1993
Indexes created Thu Sep 25 16:09:42 GMT 2025