sdhc.c revision 1.73
1 /* $NetBSD: sdhc.c,v 1.73 2015/08/03 00:19:27 jmcneill Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.73 2015/08/03 00:19:27 jmcneill Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 40 #include <dev/sdmmc/sdhcreg.h> 41 #include <dev/sdmmc/sdhcvar.h> 42 #include <dev/sdmmc/sdmmcchip.h> 43 #include <dev/sdmmc/sdmmcreg.h> 44 #include <dev/sdmmc/sdmmcvar.h> 45 46 #ifdef SDHC_DEBUG 47 int sdhcdebug = 1; 48 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 49 void sdhc_dump_regs(struct sdhc_host *); 50 #else 51 #define DPRINTF(n,s) do {} while (0) 52 #endif 53 54 #define SDHC_COMMAND_TIMEOUT hz 55 #define SDHC_BUFFER_TIMEOUT hz 56 #define SDHC_TRANSFER_TIMEOUT hz 57 #define SDHC_DMA_TIMEOUT (hz*3) 58 59 struct sdhc_host { 60 struct sdhc_softc *sc; /* host controller device */ 61 62 bus_space_tag_t iot; /* host register set tag */ 63 bus_space_handle_t ioh; /* host register set handle */ 64 bus_size_t ios; /* host register space size */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 u_int clkbase; /* base clock frequency in KHz */ 70 int maxblklen; /* maximum block length */ 71 uint32_t ocr; /* OCR value from capabilities */ 72 73 uint8_t regs[14]; /* host controller state */ 74 75 uint16_t intr_status; /* soft interrupt status */ 76 uint16_t intr_error_status; /* soft error status */ 77 kmutex_t intr_lock; 78 kcondvar_t intr_cv; 79 80 int specver; /* spec. version */ 81 82 uint32_t flags; /* flags for this host */ 83 #define SHF_USE_DMA 0x0001 84 #define SHF_USE_4BIT_MODE 0x0002 85 #define SHF_USE_8BIT_MODE 0x0004 86 #define SHF_MODE_DMAEN 0x0008 /* needs SDHC_DMA_ENABLE in mode */ 87 #define SHF_USE_ADMA2_32 0x0010 88 #define SHF_USE_ADMA2_64 0x0020 89 #define SHF_USE_ADMA2_MASK 0x0030 90 91 bus_dmamap_t adma_map; 92 bus_dma_segment_t adma_segs[1]; 93 void *adma2; 94 }; 95 96 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 97 98 static uint8_t 99 hread1(struct sdhc_host *hp, bus_size_t reg) 100 { 101 102 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 103 return bus_space_read_1(hp->iot, hp->ioh, reg); 104 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 105 } 106 107 static uint16_t 108 hread2(struct sdhc_host *hp, bus_size_t reg) 109 { 110 111 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 112 return bus_space_read_2(hp->iot, hp->ioh, reg); 113 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 114 } 115 116 #define HREAD1(hp, reg) hread1(hp, reg) 117 #define HREAD2(hp, reg) hread2(hp, reg) 118 #define HREAD4(hp, reg) \ 119 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 120 121 122 static void 123 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 124 { 125 126 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 127 bus_space_write_1(hp->iot, hp->ioh, o, val); 128 } else { 129 const size_t shift = 8 * (o & 3); 130 o &= -4; 131 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 132 tmp = (val << shift) | (tmp & ~(0xff << shift)); 133 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 134 } 135 } 136 137 static void 138 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 139 { 140 141 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 142 bus_space_write_2(hp->iot, hp->ioh, o, val); 143 } else { 144 const size_t shift = 8 * (o & 2); 145 o &= -4; 146 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 147 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 148 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 149 } 150 } 151 152 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 153 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 154 #define HWRITE4(hp, reg, val) \ 155 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 156 157 #define HCLR1(hp, reg, bits) \ 158 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 159 #define HCLR2(hp, reg, bits) \ 160 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 161 #define HCLR4(hp, reg, bits) \ 162 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 163 #define HSET1(hp, reg, bits) \ 164 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 165 #define HSET2(hp, reg, bits) \ 166 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 167 #define HSET4(hp, reg, bits) \ 168 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 169 170 static int sdhc_host_reset(sdmmc_chipset_handle_t); 171 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 172 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 173 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 174 static int sdhc_card_detect(sdmmc_chipset_handle_t); 175 static int sdhc_write_protect(sdmmc_chipset_handle_t); 176 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 177 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 178 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 179 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 180 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 181 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 182 static void sdhc_exec_command(sdmmc_chipset_handle_t, 183 struct sdmmc_command *); 184 static int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 185 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 186 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 187 static int sdhc_soft_reset(struct sdhc_host *, int); 188 static int sdhc_wait_intr(struct sdhc_host *, int, int); 189 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 190 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 191 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 192 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 193 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 194 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 195 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 196 197 static struct sdmmc_chip_functions sdhc_functions = { 198 /* host controller reset */ 199 .host_reset = sdhc_host_reset, 200 201 /* host controller capabilities */ 202 .host_ocr = sdhc_host_ocr, 203 .host_maxblklen = sdhc_host_maxblklen, 204 205 /* card detection */ 206 .card_detect = sdhc_card_detect, 207 208 /* write protect */ 209 .write_protect = sdhc_write_protect, 210 211 /* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */ 212 .bus_power = sdhc_bus_power, 213 .bus_clock = sdhc_bus_clock, 214 .bus_width = sdhc_bus_width, 215 .bus_rod = sdhc_bus_rod, 216 217 /* command execution */ 218 .exec_command = sdhc_exec_command, 219 220 /* card interrupt */ 221 .card_enable_intr = sdhc_card_enable_intr, 222 .card_intr_ack = sdhc_card_intr_ack, 223 224 /* UHS functions */ 225 .signal_voltage = sdhc_signal_voltage, 226 }; 227 228 static int 229 sdhc_cfprint(void *aux, const char *pnp) 230 { 231 const struct sdmmcbus_attach_args * const saa = aux; 232 const struct sdhc_host * const hp = saa->saa_sch; 233 234 if (pnp) { 235 aprint_normal("sdmmc at %s", pnp); 236 } 237 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 238 if (hp->sc->sc_host[host] == hp) { 239 aprint_normal(" slot %zu", host); 240 } 241 } 242 243 return UNCONF; 244 } 245 246 /* 247 * Called by attachment driver. For each SD card slot there is one SD 248 * host controller standard register set. (1.3) 249 */ 250 int 251 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 252 bus_space_handle_t ioh, bus_size_t iosize) 253 { 254 struct sdmmcbus_attach_args saa; 255 struct sdhc_host *hp; 256 uint32_t caps, caps2; 257 uint16_t sdhcver; 258 int error; 259 260 /* Allocate one more host structure. */ 261 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 262 if (hp == NULL) { 263 aprint_error_dev(sc->sc_dev, 264 "couldn't alloc memory (sdhc host)\n"); 265 goto err1; 266 } 267 sc->sc_host[sc->sc_nhosts++] = hp; 268 269 /* Fill in the new host structure. */ 270 hp->sc = sc; 271 hp->iot = iot; 272 hp->ioh = ioh; 273 hp->ios = iosize; 274 hp->dmat = sc->sc_dmat; 275 276 mutex_init(&hp->intr_lock, MUTEX_DEFAULT, IPL_SDMMC); 277 cv_init(&hp->intr_cv, "sdhcintr"); 278 279 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 280 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); 281 } else { 282 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 283 } 284 aprint_normal_dev(sc->sc_dev, "SDHC "); 285 hp->specver = SDHC_SPEC_VERSION(sdhcver); 286 switch (SDHC_SPEC_VERSION(sdhcver)) { 287 case SDHC_SPEC_VERS_100: 288 aprint_normal("1.0"); 289 break; 290 291 case SDHC_SPEC_VERS_200: 292 aprint_normal("2.0"); 293 break; 294 295 case SDHC_SPEC_VERS_300: 296 aprint_normal("3.0"); 297 break; 298 299 case SDHC_SPEC_VERS_400: 300 aprint_normal("4.0"); 301 break; 302 303 default: 304 aprint_normal("unknown version(0x%x)", 305 SDHC_SPEC_VERSION(sdhcver)); 306 break; 307 } 308 aprint_normal(", rev %u", SDHC_VENDOR_VERSION(sdhcver)); 309 310 /* 311 * Reset the host controller and enable interrupts. 312 */ 313 (void)sdhc_host_reset(hp); 314 315 /* Determine host capabilities. */ 316 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 317 caps = sc->sc_caps; 318 caps2 = sc->sc_caps2; 319 } else { 320 caps = HREAD4(hp, SDHC_CAPABILITIES); 321 if (hp->specver >= SDHC_SPEC_VERS_300) { 322 caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 323 } else { 324 caps2 = 0; 325 } 326 } 327 328 /* 329 * Use DMA if the host system and the controller support it. 330 * Suports integrated or external DMA egine, with or without 331 * SDHC_DMA_ENABLE in the command. 332 */ 333 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 334 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 335 ISSET(caps, SDHC_DMA_SUPPORT)))) { 336 SET(hp->flags, SHF_USE_DMA); 337 338 if (ISSET(sc->sc_flags, SDHC_FLAG_USE_ADMA2) && 339 ISSET(caps, SDHC_ADMA2_SUPP)) { 340 SET(hp->flags, SHF_MODE_DMAEN); 341 /* 342 * 64-bit mode was present in the 2.00 spec, removed 343 * from 3.00, and re-added in 4.00 with a different 344 * descriptor layout. We only support 2.00 and 3.00 345 * descriptors for now. 346 */ 347 if (hp->specver == SDHC_SPEC_VERS_200 && 348 ISSET(caps, SDHC_64BIT_SYS_BUS)) { 349 SET(hp->flags, SHF_USE_ADMA2_64); 350 aprint_normal(", 64-bit ADMA2"); 351 } else { 352 SET(hp->flags, SHF_USE_ADMA2_32); 353 aprint_normal(", 32-bit ADMA2"); 354 } 355 } else { 356 if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) || 357 ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN)) 358 SET(hp->flags, SHF_MODE_DMAEN); 359 if (sc->sc_vendor_transfer_data_dma) { 360 aprint_normal(", platform DMA"); 361 } else { 362 aprint_normal(", SDMA"); 363 } 364 } 365 } else { 366 aprint_normal(", PIO"); 367 } 368 369 /* 370 * Determine the base clock frequency. (2.2.24) 371 */ 372 if (hp->specver >= SDHC_SPEC_VERS_300) { 373 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 374 } else { 375 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 376 } 377 if (hp->clkbase == 0 || 378 ISSET(sc->sc_flags, SDHC_FLAG_NO_CLKBASE)) { 379 if (sc->sc_clkbase == 0) { 380 /* The attachment driver must tell us. */ 381 aprint_error_dev(sc->sc_dev, 382 "unknown base clock frequency\n"); 383 goto err; 384 } 385 hp->clkbase = sc->sc_clkbase; 386 } 387 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 388 /* SDHC 1.0 supports only 10-63 MHz. */ 389 aprint_error_dev(sc->sc_dev, 390 "base clock frequency out of range: %u MHz\n", 391 hp->clkbase / 1000); 392 goto err; 393 } 394 aprint_normal(", %u kHz", hp->clkbase); 395 396 /* 397 * XXX Set the data timeout counter value according to 398 * capabilities. (2.2.15) 399 */ 400 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 401 #if 1 402 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 403 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 404 #endif 405 406 if (ISSET(caps, SDHC_EMBEDDED_SLOT)) 407 aprint_normal(", embedded slot"); 408 409 /* 410 * Determine SD bus voltage levels supported by the controller. 411 */ 412 aprint_normal(","); 413 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) { 414 SET(hp->ocr, MMC_OCR_HCS); 415 aprint_normal(" HS"); 416 } 417 if (ISSET(caps2, SDHC_SDR50_SUPP)) { 418 SET(hp->ocr, MMC_OCR_S18A); 419 aprint_normal(" SDR50"); 420 } 421 if (ISSET(caps2, SDHC_SDR104_SUPP)) { 422 SET(hp->ocr, MMC_OCR_S18A); 423 aprint_normal(" SDR104"); 424 } 425 if (ISSET(caps2, SDHC_DDR50_SUPP)) { 426 SET(hp->ocr, MMC_OCR_S18A); 427 aprint_normal(" DDR50"); 428 } 429 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 430 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 431 aprint_normal(" 1.8V"); 432 } 433 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 434 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 435 aprint_normal(" 3.0V"); 436 } 437 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 438 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 439 aprint_normal(" 3.3V"); 440 } 441 442 /* 443 * Determine the maximum block length supported by the host 444 * controller. (2.2.24) 445 */ 446 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 447 case SDHC_MAX_BLK_LEN_512: 448 hp->maxblklen = 512; 449 break; 450 451 case SDHC_MAX_BLK_LEN_1024: 452 hp->maxblklen = 1024; 453 break; 454 455 case SDHC_MAX_BLK_LEN_2048: 456 hp->maxblklen = 2048; 457 break; 458 459 case SDHC_MAX_BLK_LEN_4096: 460 hp->maxblklen = 4096; 461 break; 462 463 default: 464 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 465 goto err; 466 } 467 aprint_normal(", %u byte blocks", hp->maxblklen); 468 aprint_normal("\n"); 469 470 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 471 int rseg; 472 473 /* Allocate ADMA2 descriptor memory */ 474 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 475 PAGE_SIZE, hp->adma_segs, 1, &rseg, BUS_DMA_WAITOK); 476 if (error) { 477 aprint_error_dev(sc->sc_dev, 478 "ADMA2 dmamem_alloc failed (%d)\n", error); 479 goto adma_done; 480 } 481 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 482 PAGE_SIZE, (void **)&hp->adma2, BUS_DMA_WAITOK); 483 if (error) { 484 aprint_error_dev(sc->sc_dev, 485 "ADMA2 dmamem_map failed (%d)\n", error); 486 goto adma_done; 487 } 488 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 489 0, BUS_DMA_WAITOK, &hp->adma_map); 490 if (error) { 491 aprint_error_dev(sc->sc_dev, 492 "ADMA2 dmamap_create failed (%d)\n", error); 493 goto adma_done; 494 } 495 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 496 hp->adma2, PAGE_SIZE, NULL, 497 BUS_DMA_WAITOK|BUS_DMA_WRITE); 498 if (error) { 499 aprint_error_dev(sc->sc_dev, 500 "ADMA2 dmamap_load failed (%d)\n", error); 501 goto adma_done; 502 } 503 504 memset(hp->adma2, 0, PAGE_SIZE); 505 506 adma_done: 507 if (error) 508 CLR(hp->flags, SHF_USE_ADMA2_MASK); 509 } 510 511 /* 512 * Attach the generic SD/MMC bus driver. (The bus driver must 513 * not invoke any chipset functions before it is attached.) 514 */ 515 memset(&saa, 0, sizeof(saa)); 516 saa.saa_busname = "sdmmc"; 517 saa.saa_sct = &sdhc_functions; 518 saa.saa_sch = hp; 519 saa.saa_dmat = hp->dmat; 520 saa.saa_clkmax = hp->clkbase; 521 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 522 saa.saa_clkmin = hp->clkbase / 256 / 2046; 523 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 524 saa.saa_clkmin = hp->clkbase / 256 / 16; 525 else if (hp->sc->sc_clkmsk != 0) 526 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 527 (ffs(hp->sc->sc_clkmsk) - 1)); 528 else if (hp->specver >= SDHC_SPEC_VERS_300) 529 saa.saa_clkmin = hp->clkbase / 0x3ff; 530 else 531 saa.saa_clkmin = hp->clkbase / 256; 532 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 533 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 534 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 535 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 536 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 537 if (ISSET(hp->flags, SHF_USE_DMA)) { 538 saa.saa_caps |= SMC_CAPS_DMA; 539 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 540 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 541 } 542 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 543 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 544 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 545 546 return 0; 547 548 err: 549 cv_destroy(&hp->intr_cv); 550 mutex_destroy(&hp->intr_lock); 551 free(hp, M_DEVBUF); 552 sc->sc_host[--sc->sc_nhosts] = NULL; 553 err1: 554 return 1; 555 } 556 557 int 558 sdhc_detach(struct sdhc_softc *sc, int flags) 559 { 560 struct sdhc_host *hp; 561 int rv = 0; 562 563 for (size_t n = 0; n < sc->sc_nhosts; n++) { 564 hp = sc->sc_host[n]; 565 if (hp == NULL) 566 continue; 567 if (hp->sdmmc != NULL) { 568 rv = config_detach(hp->sdmmc, flags); 569 if (rv) 570 break; 571 hp->sdmmc = NULL; 572 } 573 /* disable interrupts */ 574 if ((flags & DETACH_FORCE) == 0) { 575 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 576 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 577 } else { 578 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 579 } 580 sdhc_soft_reset(hp, SDHC_RESET_ALL); 581 } 582 cv_destroy(&hp->intr_cv); 583 mutex_destroy(&hp->intr_lock); 584 if (hp->ios > 0) { 585 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 586 hp->ios = 0; 587 } 588 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 589 bus_dmamap_unload(sc->sc_dmat, hp->adma_map); 590 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 591 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 592 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, 1); 593 } 594 free(hp, M_DEVBUF); 595 sc->sc_host[n] = NULL; 596 } 597 598 return rv; 599 } 600 601 bool 602 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 603 { 604 struct sdhc_softc *sc = device_private(dev); 605 struct sdhc_host *hp; 606 size_t i; 607 608 /* XXX poll for command completion or suspend command 609 * in progress */ 610 611 /* Save the host controller state. */ 612 for (size_t n = 0; n < sc->sc_nhosts; n++) { 613 hp = sc->sc_host[n]; 614 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 615 for (i = 0; i < sizeof hp->regs; i += 4) { 616 uint32_t v = HREAD4(hp, i); 617 hp->regs[i + 0] = (v >> 0); 618 hp->regs[i + 1] = (v >> 8); 619 if (i + 3 < sizeof hp->regs) { 620 hp->regs[i + 2] = (v >> 16); 621 hp->regs[i + 3] = (v >> 24); 622 } 623 } 624 } else { 625 for (i = 0; i < sizeof hp->regs; i++) { 626 hp->regs[i] = HREAD1(hp, i); 627 } 628 } 629 } 630 return true; 631 } 632 633 bool 634 sdhc_resume(device_t dev, const pmf_qual_t *qual) 635 { 636 struct sdhc_softc *sc = device_private(dev); 637 struct sdhc_host *hp; 638 size_t i; 639 640 /* Restore the host controller state. */ 641 for (size_t n = 0; n < sc->sc_nhosts; n++) { 642 hp = sc->sc_host[n]; 643 (void)sdhc_host_reset(hp); 644 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 645 for (i = 0; i < sizeof hp->regs; i += 4) { 646 if (i + 3 < sizeof hp->regs) { 647 HWRITE4(hp, i, 648 (hp->regs[i + 0] << 0) 649 | (hp->regs[i + 1] << 8) 650 | (hp->regs[i + 2] << 16) 651 | (hp->regs[i + 3] << 24)); 652 } else { 653 HWRITE4(hp, i, 654 (hp->regs[i + 0] << 0) 655 | (hp->regs[i + 1] << 8)); 656 } 657 } 658 } else { 659 for (i = 0; i < sizeof hp->regs; i++) { 660 HWRITE1(hp, i, hp->regs[i]); 661 } 662 } 663 } 664 return true; 665 } 666 667 bool 668 sdhc_shutdown(device_t dev, int flags) 669 { 670 struct sdhc_softc *sc = device_private(dev); 671 struct sdhc_host *hp; 672 673 /* XXX chip locks up if we don't disable it before reboot. */ 674 for (size_t i = 0; i < sc->sc_nhosts; i++) { 675 hp = sc->sc_host[i]; 676 (void)sdhc_host_reset(hp); 677 } 678 return true; 679 } 680 681 /* 682 * Reset the host controller. Called during initialization, when 683 * cards are removed, upon resume, and during error recovery. 684 */ 685 static int 686 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 687 { 688 struct sdhc_host *hp = (struct sdhc_host *)sch; 689 uint32_t sdhcimask; 690 int error; 691 692 KASSERT(mutex_owned(&hp->intr_lock)); 693 694 /* Disable all interrupts. */ 695 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 696 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 697 } else { 698 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 699 } 700 701 /* 702 * Reset the entire host controller and wait up to 100ms for 703 * the controller to clear the reset bit. 704 */ 705 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 706 if (error) 707 goto out; 708 709 /* Set data timeout counter value to max for now. */ 710 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 711 #if 1 712 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 713 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 714 #endif 715 716 /* Enable interrupts. */ 717 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 718 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 719 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 720 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 721 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 722 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 723 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 724 sdhcimask ^= 725 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 726 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 727 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 728 } else { 729 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 730 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 731 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 732 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 733 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 734 } 735 736 out: 737 return error; 738 } 739 740 static int 741 sdhc_host_reset(sdmmc_chipset_handle_t sch) 742 { 743 struct sdhc_host *hp = (struct sdhc_host *)sch; 744 int error; 745 746 mutex_enter(&hp->intr_lock); 747 error = sdhc_host_reset1(sch); 748 mutex_exit(&hp->intr_lock); 749 750 return error; 751 } 752 753 static uint32_t 754 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 755 { 756 struct sdhc_host *hp = (struct sdhc_host *)sch; 757 758 return hp->ocr; 759 } 760 761 static int 762 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 763 { 764 struct sdhc_host *hp = (struct sdhc_host *)sch; 765 766 return hp->maxblklen; 767 } 768 769 /* 770 * Return non-zero if the card is currently inserted. 771 */ 772 static int 773 sdhc_card_detect(sdmmc_chipset_handle_t sch) 774 { 775 struct sdhc_host *hp = (struct sdhc_host *)sch; 776 int r; 777 778 if (hp->sc->sc_vendor_card_detect) 779 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 780 781 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 782 783 return r ? 1 : 0; 784 } 785 786 /* 787 * Return non-zero if the card is currently write-protected. 788 */ 789 static int 790 sdhc_write_protect(sdmmc_chipset_handle_t sch) 791 { 792 struct sdhc_host *hp = (struct sdhc_host *)sch; 793 int r; 794 795 if (hp->sc->sc_vendor_write_protect) 796 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 797 798 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 799 800 return r ? 0 : 1; 801 } 802 803 /* 804 * Set or change SD bus voltage and enable or disable SD bus power. 805 * Return zero on success. 806 */ 807 static int 808 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 809 { 810 struct sdhc_host *hp = (struct sdhc_host *)sch; 811 uint8_t vdd; 812 int error = 0; 813 const uint32_t pcmask = 814 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 815 816 mutex_enter(&hp->intr_lock); 817 818 /* 819 * Disable bus power before voltage change. 820 */ 821 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 822 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 823 HWRITE1(hp, SDHC_POWER_CTL, 0); 824 825 /* If power is disabled, reset the host and return now. */ 826 if (ocr == 0) { 827 (void)sdhc_host_reset1(hp); 828 goto out; 829 } 830 831 /* 832 * Select the lowest voltage according to capabilities. 833 */ 834 ocr &= hp->ocr; 835 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 836 vdd = SDHC_VOLTAGE_1_8V; 837 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 838 vdd = SDHC_VOLTAGE_3_0V; 839 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 840 vdd = SDHC_VOLTAGE_3_3V; 841 } else { 842 /* Unsupported voltage level requested. */ 843 error = EINVAL; 844 goto out; 845 } 846 847 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 848 /* 849 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 850 * voltage ramp until power rises. 851 */ 852 853 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SINGLE_POWER_WRITE)) { 854 HWRITE1(hp, SDHC_POWER_CTL, 855 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 856 } else { 857 HWRITE1(hp, SDHC_POWER_CTL, 858 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 859 sdmmc_delay(1); 860 HWRITE1(hp, SDHC_POWER_CTL, 861 (vdd << SDHC_VOLTAGE_SHIFT)); 862 sdmmc_delay(1); 863 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 864 sdmmc_delay(10000); 865 } 866 867 /* 868 * The host system may not power the bus due to battery low, 869 * etc. In that case, the host controller should clear the 870 * bus power bit. 871 */ 872 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 873 error = ENXIO; 874 goto out; 875 } 876 } 877 878 out: 879 mutex_exit(&hp->intr_lock); 880 881 return error; 882 } 883 884 /* 885 * Return the smallest possible base clock frequency divisor value 886 * for the CLOCK_CTL register to produce `freq' (KHz). 887 */ 888 static bool 889 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 890 { 891 u_int div; 892 893 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 894 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 895 if ((hp->clkbase / div) <= freq) { 896 *divp = SDHC_SDCLK_CGM 897 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 898 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 899 //freq = hp->clkbase / div; 900 return true; 901 } 902 } 903 /* No divisor found. */ 904 return false; 905 } 906 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 907 u_int dvs = (hp->clkbase + freq - 1) / freq; 908 u_int roundup = dvs & 1; 909 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 910 if (dvs + roundup <= 16) { 911 dvs += roundup - 1; 912 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 913 | (dvs << SDHC_SDCLK_DVS_SHIFT); 914 DPRINTF(2, 915 ("%s: divisor for freq %u is %u * %u\n", 916 HDEVNAME(hp), freq, div * 2, dvs + 1)); 917 //freq = hp->clkbase / (div * 2) * (dvs + 1); 918 return true; 919 } 920 /* 921 * If we drop bits, we need to round up the divisor. 922 */ 923 roundup |= dvs & 1; 924 } 925 /* No divisor found. */ 926 return false; 927 } 928 if (hp->sc->sc_clkmsk != 0) { 929 div = howmany(hp->clkbase, freq); 930 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 931 return false; 932 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 933 //freq = hp->clkbase / div; 934 return true; 935 } 936 if (hp->specver >= SDHC_SPEC_VERS_300) { 937 div = howmany(hp->clkbase, freq); 938 div = div > 1 ? howmany(div, 2) : 0; 939 if (div > 0x3ff) 940 return false; 941 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 942 << SDHC_SDCLK_XDIV_SHIFT) | 943 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 944 << SDHC_SDCLK_DIV_SHIFT); 945 //freq = hp->clkbase / (div ? div * 2 : 1); 946 return true; 947 } else { 948 for (div = 1; div <= 256; div *= 2) { 949 if ((hp->clkbase / div) <= freq) { 950 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 951 //freq = hp->clkbase / div; 952 return true; 953 } 954 } 955 /* No divisor found. */ 956 return false; 957 } 958 /* No divisor found. */ 959 return false; 960 } 961 962 /* 963 * Set or change SDCLK frequency or disable the SD clock. 964 * Return zero on success. 965 */ 966 static int 967 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 968 { 969 struct sdhc_host *hp = (struct sdhc_host *)sch; 970 u_int div; 971 u_int timo; 972 int16_t reg; 973 int error = 0; 974 bool present __diagused; 975 976 mutex_enter(&hp->intr_lock); 977 978 #ifdef DIAGNOSTIC 979 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 980 981 /* Must not stop the clock if commands are in progress. */ 982 if (present && sdhc_card_detect(hp)) { 983 aprint_normal_dev(hp->sc->sc_dev, 984 "%s: command in progress\n", __func__); 985 } 986 #endif 987 988 if (hp->sc->sc_vendor_bus_clock) { 989 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 990 if (error != 0) 991 goto out; 992 } 993 994 /* 995 * Stop SD clock before changing the frequency. 996 */ 997 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 998 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 999 if (freq == SDMMC_SDCLK_OFF) { 1000 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 1001 goto out; 1002 } 1003 } else { 1004 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1005 if (freq == SDMMC_SDCLK_OFF) 1006 goto out; 1007 } 1008 1009 if (hp->specver >= SDHC_SPEC_VERS_300) { 1010 /* XXX DDR */ 1011 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 1012 if (freq > 100000) { 1013 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR104); 1014 } else if (freq > 50000) { 1015 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR50); 1016 } else if (freq > 25000) { 1017 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR25); 1018 } else { 1019 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR12); 1020 } 1021 } 1022 1023 /* 1024 * Set the minimum base clock frequency divisor. 1025 */ 1026 if (!sdhc_clock_divisor(hp, freq, &div)) { 1027 /* Invalid base clock frequency or `freq' value. */ 1028 aprint_error_dev(hp->sc->sc_dev, 1029 "Invalid bus clock %d kHz\n", freq); 1030 error = EINVAL; 1031 goto out; 1032 } 1033 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1034 HWRITE4(hp, SDHC_CLOCK_CTL, 1035 div | (SDHC_TIMEOUT_MAX << 16)); 1036 } else { 1037 reg = HREAD2(hp, SDHC_CLOCK_CTL); 1038 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 1039 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 1040 } 1041 1042 /* 1043 * Start internal clock. Wait 10ms for stabilization. 1044 */ 1045 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1046 sdmmc_delay(10000); 1047 HSET4(hp, SDHC_CLOCK_CTL, 1048 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 1049 } else { 1050 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 1051 for (timo = 1000; timo > 0; timo--) { 1052 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 1053 SDHC_INTCLK_STABLE)) 1054 break; 1055 sdmmc_delay(10); 1056 } 1057 if (timo == 0) { 1058 error = ETIMEDOUT; 1059 goto out; 1060 } 1061 } 1062 1063 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1064 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 1065 /* 1066 * Sending 80 clocks at 400kHz takes 200us. 1067 * So delay for that time + slop and then 1068 * check a few times for completion. 1069 */ 1070 sdmmc_delay(210); 1071 for (timo = 10; timo > 0; timo--) { 1072 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 1073 SDHC_INIT_ACTIVE)) 1074 break; 1075 sdmmc_delay(10); 1076 } 1077 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 1078 1079 /* 1080 * Enable SD clock. 1081 */ 1082 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1083 } else { 1084 /* 1085 * Enable SD clock. 1086 */ 1087 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1088 1089 if (freq > 25000 && 1090 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 1091 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1092 else 1093 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1094 } 1095 1096 out: 1097 mutex_exit(&hp->intr_lock); 1098 1099 return error; 1100 } 1101 1102 static int 1103 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 1104 { 1105 struct sdhc_host *hp = (struct sdhc_host *)sch; 1106 int reg; 1107 1108 switch (width) { 1109 case 1: 1110 case 4: 1111 break; 1112 1113 case 8: 1114 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 1115 break; 1116 /* FALLTHROUGH */ 1117 default: 1118 DPRINTF(0,("%s: unsupported bus width (%d)\n", 1119 HDEVNAME(hp), width)); 1120 return 1; 1121 } 1122 1123 mutex_enter(&hp->intr_lock); 1124 1125 reg = HREAD1(hp, SDHC_HOST_CTL); 1126 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1127 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 1128 if (width == 4) 1129 reg |= SDHC_4BIT_MODE; 1130 else if (width == 8) 1131 reg |= SDHC_ESDHC_8BIT_MODE; 1132 } else { 1133 reg &= ~SDHC_4BIT_MODE; 1134 if (hp->specver >= SDHC_SPEC_VERS_300) { 1135 reg &= ~SDHC_8BIT_MODE; 1136 } 1137 if (width == 4) { 1138 reg |= SDHC_4BIT_MODE; 1139 } else if (width == 8 && hp->specver >= SDHC_SPEC_VERS_300) { 1140 reg |= SDHC_8BIT_MODE; 1141 } 1142 } 1143 HWRITE1(hp, SDHC_HOST_CTL, reg); 1144 1145 mutex_exit(&hp->intr_lock); 1146 1147 return 0; 1148 } 1149 1150 static int 1151 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1152 { 1153 struct sdhc_host *hp = (struct sdhc_host *)sch; 1154 1155 if (hp->sc->sc_vendor_rod) 1156 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1157 1158 return 0; 1159 } 1160 1161 static void 1162 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1163 { 1164 struct sdhc_host *hp = (struct sdhc_host *)sch; 1165 1166 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1167 mutex_enter(&hp->intr_lock); 1168 if (enable) { 1169 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1170 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1171 } else { 1172 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1173 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1174 } 1175 mutex_exit(&hp->intr_lock); 1176 } 1177 } 1178 1179 static void 1180 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1181 { 1182 struct sdhc_host *hp = (struct sdhc_host *)sch; 1183 1184 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1185 mutex_enter(&hp->intr_lock); 1186 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1187 mutex_exit(&hp->intr_lock); 1188 } 1189 } 1190 1191 static int 1192 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 1193 { 1194 struct sdhc_host *hp = (struct sdhc_host *)sch; 1195 1196 switch (signal_voltage) { 1197 case SDMMC_SIGNAL_VOLTAGE_180: 1198 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1199 break; 1200 case SDMMC_SIGNAL_VOLTAGE_330: 1201 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1202 break; 1203 default: 1204 return EINVAL; 1205 } 1206 1207 return 0; 1208 } 1209 1210 static int 1211 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1212 { 1213 uint32_t state; 1214 int timeout; 1215 1216 for (timeout = 10000; timeout > 0; timeout--) { 1217 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 1218 return 0; 1219 sdmmc_delay(10); 1220 } 1221 aprint_error_dev(hp->sc->sc_dev, "timeout waiting for %x (state=%x)\n", 1222 value, state); 1223 return ETIMEDOUT; 1224 } 1225 1226 static void 1227 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1228 { 1229 struct sdhc_host *hp = (struct sdhc_host *)sch; 1230 int error; 1231 1232 mutex_enter(&hp->intr_lock); 1233 1234 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1235 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1236 if (ISSET(hp->flags, SHF_USE_DMA)) { 1237 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1238 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1239 } else { 1240 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1241 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1242 } 1243 } 1244 1245 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_TIMEOUT)) { 1246 const uint16_t eintr = SDHC_CMD_TIMEOUT_ERROR; 1247 if (cmd->c_data != NULL) { 1248 HCLR2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1249 HCLR2(hp, SDHC_EINTR_STATUS_EN, eintr); 1250 } else { 1251 HSET2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1252 HSET2(hp, SDHC_EINTR_STATUS_EN, eintr); 1253 } 1254 } 1255 1256 /* 1257 * Start the MMC command, or mark `cmd' as failed and return. 1258 */ 1259 error = sdhc_start_command(hp, cmd); 1260 if (error) { 1261 cmd->c_error = error; 1262 goto out; 1263 } 1264 1265 /* 1266 * Wait until the command phase is done, or until the command 1267 * is marked done for any other reason. 1268 */ 1269 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1270 cmd->c_error = ETIMEDOUT; 1271 goto out; 1272 } 1273 1274 /* 1275 * The host controller removes bits [0:7] from the response 1276 * data (CRC) and we pass the data up unchanged to the bus 1277 * driver (without padding). 1278 */ 1279 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1280 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1281 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1282 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1283 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1284 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1285 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1286 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1287 (cmd->c_resp[1] << 24); 1288 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1289 (cmd->c_resp[2] << 24); 1290 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1291 (cmd->c_resp[3] << 24); 1292 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1293 } 1294 } 1295 } 1296 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1297 1298 /* 1299 * If the command has data to transfer in any direction, 1300 * execute the transfer now. 1301 */ 1302 if (cmd->c_error == 0 && cmd->c_data != NULL) 1303 sdhc_transfer_data(hp, cmd); 1304 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1305 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10)) { 1306 cmd->c_error = ETIMEDOUT; 1307 goto out; 1308 } 1309 } 1310 1311 out: 1312 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1313 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1314 /* Turn off the LED. */ 1315 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1316 } 1317 SET(cmd->c_flags, SCF_ITSDONE); 1318 1319 mutex_exit(&hp->intr_lock); 1320 1321 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1322 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1323 cmd->c_flags, cmd->c_error)); 1324 } 1325 1326 static int 1327 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1328 { 1329 struct sdhc_softc * const sc = hp->sc; 1330 uint16_t blksize = 0; 1331 uint16_t blkcount = 0; 1332 uint16_t mode; 1333 uint16_t command; 1334 int error; 1335 1336 KASSERT(mutex_owned(&hp->intr_lock)); 1337 1338 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1339 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1340 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1341 1342 /* 1343 * The maximum block length for commands should be the minimum 1344 * of the host buffer size and the card buffer size. (1.7.2) 1345 */ 1346 1347 /* Fragment the data into proper blocks. */ 1348 if (cmd->c_datalen > 0) { 1349 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1350 blkcount = cmd->c_datalen / blksize; 1351 if (cmd->c_datalen % blksize > 0) { 1352 /* XXX: Split this command. (1.7.4) */ 1353 aprint_error_dev(sc->sc_dev, 1354 "data not a multiple of %u bytes\n", blksize); 1355 return EINVAL; 1356 } 1357 } 1358 1359 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1360 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1361 aprint_error_dev(sc->sc_dev, "too much data\n"); 1362 return EINVAL; 1363 } 1364 1365 /* Prepare transfer mode register value. (2.2.5) */ 1366 mode = SDHC_BLOCK_COUNT_ENABLE; 1367 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1368 mode |= SDHC_READ_MODE; 1369 if (blkcount > 1) { 1370 mode |= SDHC_MULTI_BLOCK_MODE; 1371 /* XXX only for memory commands? */ 1372 mode |= SDHC_AUTO_CMD12_ENABLE; 1373 } 1374 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1375 ISSET(hp->flags, SHF_MODE_DMAEN)) { 1376 mode |= SDHC_DMA_ENABLE; 1377 } 1378 1379 /* 1380 * Prepare command register value. (2.2.6) 1381 */ 1382 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1383 1384 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1385 command |= SDHC_CRC_CHECK_ENABLE; 1386 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1387 command |= SDHC_INDEX_CHECK_ENABLE; 1388 if (cmd->c_data != NULL) 1389 command |= SDHC_DATA_PRESENT_SELECT; 1390 1391 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1392 command |= SDHC_NO_RESPONSE; 1393 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1394 command |= SDHC_RESP_LEN_136; 1395 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1396 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1397 else 1398 command |= SDHC_RESP_LEN_48; 1399 1400 /* Wait until command and data inhibit bits are clear. (1.5) */ 1401 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1402 if (error) { 1403 aprint_error_dev(sc->sc_dev, "command or data phase inhibited\n"); 1404 return error; 1405 } 1406 1407 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1408 HDEVNAME(hp), blksize, blkcount, mode, command)); 1409 1410 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1411 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1412 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1413 } 1414 1415 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1416 /* Alert the user not to remove the card. */ 1417 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1418 } 1419 1420 /* Set DMA start address. */ 1421 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK) && cmd->c_datalen > 0) { 1422 for (int seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 1423 bus_addr_t paddr = 1424 cmd->c_dmamap->dm_segs[seg].ds_addr; 1425 uint16_t len = 1426 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1427 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1428 uint16_t attr = 1429 SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1430 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 1431 attr |= SDHC_ADMA2_END; 1432 } 1433 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1434 struct sdhc_adma2_descriptor32 *desc = 1435 hp->adma2; 1436 desc[seg].attribute = htole16(attr); 1437 desc[seg].length = htole16(len); 1438 desc[seg].address = htole32(paddr); 1439 } else { 1440 struct sdhc_adma2_descriptor64 *desc = 1441 hp->adma2; 1442 desc[seg].attribute = htole16(attr); 1443 desc[seg].length = htole16(len); 1444 desc[seg].address = htole32(paddr & 0xffffffff); 1445 desc[seg].address_hi = htole32( 1446 (uint64_t)paddr >> 32); 1447 } 1448 } 1449 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1450 struct sdhc_adma2_descriptor32 *desc = hp->adma2; 1451 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1452 } else { 1453 struct sdhc_adma2_descriptor64 *desc = hp->adma2; 1454 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1455 } 1456 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1457 BUS_DMASYNC_PREWRITE); 1458 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1459 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2); 1460 1461 const bus_addr_t desc_addr = hp->adma_map->dm_segs[0].ds_addr; 1462 1463 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff); 1464 if (ISSET(hp->flags, SHF_USE_ADMA2_64)) { 1465 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4, 1466 (uint64_t)desc_addr >> 32); 1467 } 1468 } else if (ISSET(mode, SDHC_DMA_ENABLE) && 1469 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) { 1470 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1471 } 1472 1473 /* 1474 * Start a CPU data transfer. Writing to the high order byte 1475 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1476 */ 1477 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1478 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1479 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1480 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1481 } else { 1482 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1483 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1484 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1485 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1486 HWRITE2(hp, SDHC_COMMAND, command); 1487 } 1488 1489 return 0; 1490 } 1491 1492 static void 1493 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1494 { 1495 struct sdhc_softc *sc = hp->sc; 1496 int error; 1497 1498 KASSERT(mutex_owned(&hp->intr_lock)); 1499 1500 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1501 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1502 1503 #ifdef SDHC_DEBUG 1504 /* XXX I forgot why I wanted to know when this happens :-( */ 1505 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1506 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1507 aprint_error_dev(hp->sc->sc_dev, 1508 "CMD52/53 error response flags %#x\n", 1509 MMC_R1(cmd->c_resp) & 0xff00); 1510 } 1511 #endif 1512 1513 if (cmd->c_dmamap != NULL) { 1514 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1515 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd); 1516 if (error == 0 && !sdhc_wait_intr(hp, 1517 SDHC_TRANSFER_COMPLETE, SDHC_DMA_TIMEOUT)) { 1518 error = ETIMEDOUT; 1519 } 1520 } else { 1521 error = sdhc_transfer_data_dma(hp, cmd); 1522 } 1523 } else 1524 error = sdhc_transfer_data_pio(hp, cmd); 1525 if (error) 1526 cmd->c_error = error; 1527 SET(cmd->c_flags, SCF_ITSDONE); 1528 1529 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1530 HDEVNAME(hp), cmd->c_error)); 1531 } 1532 1533 static int 1534 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1535 { 1536 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1537 bus_addr_t posaddr; 1538 bus_addr_t segaddr; 1539 bus_size_t seglen; 1540 u_int seg = 0; 1541 int error = 0; 1542 int status; 1543 1544 KASSERT(mutex_owned(&hp->intr_lock)); 1545 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1546 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1547 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1548 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1549 1550 for (;;) { 1551 status = sdhc_wait_intr(hp, 1552 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1553 SDHC_DMA_TIMEOUT); 1554 1555 if (status & SDHC_TRANSFER_COMPLETE) { 1556 break; 1557 } 1558 if (!status) { 1559 error = ETIMEDOUT; 1560 break; 1561 } 1562 1563 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1564 continue; 1565 } 1566 1567 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1568 continue; 1569 } 1570 1571 /* DMA Interrupt (boundary crossing) */ 1572 1573 segaddr = dm_segs[seg].ds_addr; 1574 seglen = dm_segs[seg].ds_len; 1575 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1576 1577 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1578 continue; 1579 } 1580 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1581 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1582 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1583 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1584 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1585 } 1586 1587 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1588 bus_dmamap_sync(hp->sc->sc_dmat, hp->adma_map, 0, 1589 PAGE_SIZE, BUS_DMASYNC_POSTWRITE); 1590 } 1591 1592 return error; 1593 } 1594 1595 static int 1596 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1597 { 1598 uint8_t *data = cmd->c_data; 1599 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1600 u_int len, datalen; 1601 u_int imask; 1602 u_int pmask; 1603 int error = 0; 1604 1605 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1606 imask = SDHC_BUFFER_READ_READY; 1607 pmask = SDHC_BUFFER_READ_ENABLE; 1608 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1609 pio_func = esdhc_read_data_pio; 1610 } else { 1611 pio_func = sdhc_read_data_pio; 1612 } 1613 } else { 1614 imask = SDHC_BUFFER_WRITE_READY; 1615 pmask = SDHC_BUFFER_WRITE_ENABLE; 1616 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1617 pio_func = esdhc_write_data_pio; 1618 } else { 1619 pio_func = sdhc_write_data_pio; 1620 } 1621 } 1622 datalen = cmd->c_datalen; 1623 1624 KASSERT(mutex_owned(&hp->intr_lock)); 1625 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1626 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1627 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1628 1629 while (datalen > 0) { 1630 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1631 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1632 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1633 } else { 1634 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1635 } 1636 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1637 error = ETIMEDOUT; 1638 break; 1639 } 1640 1641 error = sdhc_wait_state(hp, pmask, pmask); 1642 if (error) 1643 break; 1644 } 1645 1646 len = MIN(datalen, cmd->c_blklen); 1647 (*pio_func)(hp, data, len); 1648 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1649 HDEVNAME(hp), len, data)); 1650 1651 data += len; 1652 datalen -= len; 1653 } 1654 1655 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1656 SDHC_TRANSFER_TIMEOUT)) 1657 error = ETIMEDOUT; 1658 1659 return error; 1660 } 1661 1662 static void 1663 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1664 { 1665 1666 if (((__uintptr_t)data & 3) == 0) { 1667 while (datalen > 3) { 1668 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1669 data += 4; 1670 datalen -= 4; 1671 } 1672 if (datalen > 1) { 1673 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1674 data += 2; 1675 datalen -= 2; 1676 } 1677 if (datalen > 0) { 1678 *data = HREAD1(hp, SDHC_DATA); 1679 data += 1; 1680 datalen -= 1; 1681 } 1682 } else if (((__uintptr_t)data & 1) == 0) { 1683 while (datalen > 1) { 1684 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1685 data += 2; 1686 datalen -= 2; 1687 } 1688 if (datalen > 0) { 1689 *data = HREAD1(hp, SDHC_DATA); 1690 data += 1; 1691 datalen -= 1; 1692 } 1693 } else { 1694 while (datalen > 0) { 1695 *data = HREAD1(hp, SDHC_DATA); 1696 data += 1; 1697 datalen -= 1; 1698 } 1699 } 1700 } 1701 1702 static void 1703 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1704 { 1705 1706 if (((__uintptr_t)data & 3) == 0) { 1707 while (datalen > 3) { 1708 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 1709 data += 4; 1710 datalen -= 4; 1711 } 1712 if (datalen > 1) { 1713 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1714 data += 2; 1715 datalen -= 2; 1716 } 1717 if (datalen > 0) { 1718 HWRITE1(hp, SDHC_DATA, *data); 1719 data += 1; 1720 datalen -= 1; 1721 } 1722 } else if (((__uintptr_t)data & 1) == 0) { 1723 while (datalen > 1) { 1724 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1725 data += 2; 1726 datalen -= 2; 1727 } 1728 if (datalen > 0) { 1729 HWRITE1(hp, SDHC_DATA, *data); 1730 data += 1; 1731 datalen -= 1; 1732 } 1733 } else { 1734 while (datalen > 0) { 1735 HWRITE1(hp, SDHC_DATA, *data); 1736 data += 1; 1737 datalen -= 1; 1738 } 1739 } 1740 } 1741 1742 static void 1743 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1744 { 1745 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1746 uint32_t v; 1747 1748 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1749 size_t count = 0; 1750 1751 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1752 if (count == 0) { 1753 /* 1754 * If we've drained "watermark" words, we need to wait 1755 * a little bit so the read FIFO can refill. 1756 */ 1757 sdmmc_delay(10); 1758 count = watermark; 1759 } 1760 v = HREAD4(hp, SDHC_DATA); 1761 v = le32toh(v); 1762 *(uint32_t *)data = v; 1763 data += 4; 1764 datalen -= 4; 1765 status = HREAD2(hp, SDHC_NINTR_STATUS); 1766 count--; 1767 } 1768 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1769 if (count == 0) { 1770 sdmmc_delay(10); 1771 } 1772 v = HREAD4(hp, SDHC_DATA); 1773 v = le32toh(v); 1774 do { 1775 *data++ = v; 1776 v >>= 8; 1777 } while (--datalen > 0); 1778 } 1779 } 1780 1781 static void 1782 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1783 { 1784 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1785 uint32_t v; 1786 1787 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1788 size_t count = watermark; 1789 1790 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1791 if (count == 0) { 1792 sdmmc_delay(10); 1793 count = watermark; 1794 } 1795 v = *(uint32_t *)data; 1796 v = htole32(v); 1797 HWRITE4(hp, SDHC_DATA, v); 1798 data += 4; 1799 datalen -= 4; 1800 status = HREAD2(hp, SDHC_NINTR_STATUS); 1801 count--; 1802 } 1803 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1804 if (count == 0) { 1805 sdmmc_delay(10); 1806 } 1807 v = *(uint32_t *)data; 1808 v = htole32(v); 1809 HWRITE4(hp, SDHC_DATA, v); 1810 } 1811 } 1812 1813 /* Prepare for another command. */ 1814 static int 1815 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1816 { 1817 int timo; 1818 1819 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1820 1821 /* Request the reset. */ 1822 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1823 1824 /* 1825 * If necessary, wait for the controller to set the bits to 1826 * acknowledge the reset. 1827 */ 1828 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 1829 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 1830 for (timo = 10000; timo > 0; timo--) { 1831 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1832 break; 1833 /* Short delay because I worry we may miss it... */ 1834 sdmmc_delay(1); 1835 } 1836 if (timo == 0) 1837 return ETIMEDOUT; 1838 } 1839 1840 /* 1841 * Wait for the controller to clear the bits to indicate that 1842 * the reset has completed. 1843 */ 1844 for (timo = 10; timo > 0; timo--) { 1845 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1846 break; 1847 sdmmc_delay(10000); 1848 } 1849 if (timo == 0) { 1850 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1851 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1852 return ETIMEDOUT; 1853 } 1854 1855 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1856 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1857 } 1858 1859 return 0; 1860 } 1861 1862 static int 1863 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1864 { 1865 int status; 1866 1867 KASSERT(mutex_owned(&hp->intr_lock)); 1868 1869 mask |= SDHC_ERROR_INTERRUPT; 1870 1871 status = hp->intr_status & mask; 1872 while (status == 0) { 1873 if (cv_timedwait(&hp->intr_cv, &hp->intr_lock, timo) 1874 == EWOULDBLOCK) { 1875 status |= SDHC_ERROR_INTERRUPT; 1876 break; 1877 } 1878 status = hp->intr_status & mask; 1879 } 1880 hp->intr_status &= ~status; 1881 1882 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1883 hp->intr_error_status)); 1884 1885 /* Command timeout has higher priority than command complete. */ 1886 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1887 hp->intr_error_status = 0; 1888 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1889 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1890 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1891 } 1892 status = 0; 1893 } 1894 1895 return status; 1896 } 1897 1898 /* 1899 * Established by attachment driver at interrupt priority IPL_SDMMC. 1900 */ 1901 int 1902 sdhc_intr(void *arg) 1903 { 1904 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1905 struct sdhc_host *hp; 1906 int done = 0; 1907 uint16_t status; 1908 uint16_t error; 1909 1910 /* We got an interrupt, but we don't know from which slot. */ 1911 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1912 hp = sc->sc_host[host]; 1913 if (hp == NULL) 1914 continue; 1915 1916 mutex_enter(&hp->intr_lock); 1917 1918 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1919 /* Find out which interrupts are pending. */ 1920 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1921 status = xstatus; 1922 error = xstatus >> 16; 1923 if (error) 1924 xstatus |= SDHC_ERROR_INTERRUPT; 1925 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1926 goto next_port; /* no interrupt for us */ 1927 /* Acknowledge the interrupts we are about to handle. */ 1928 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1929 } else { 1930 /* Find out which interrupts are pending. */ 1931 error = 0; 1932 status = HREAD2(hp, SDHC_NINTR_STATUS); 1933 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1934 goto next_port; /* no interrupt for us */ 1935 /* Acknowledge the interrupts we are about to handle. */ 1936 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1937 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1938 /* Acknowledge error interrupts. */ 1939 error = HREAD2(hp, SDHC_EINTR_STATUS); 1940 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1941 } 1942 } 1943 1944 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1945 status, error)); 1946 1947 /* Claim this interrupt. */ 1948 done = 1; 1949 1950 if (ISSET(error, SDHC_ADMA_ERROR)) { 1951 uint8_t adma_err = HREAD1(hp, SDHC_ADMA_ERROR_STATUS); 1952 printf("%s: ADMA error, status %02x\n", HDEVNAME(hp), 1953 adma_err); 1954 } 1955 1956 /* 1957 * Service error interrupts. 1958 */ 1959 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1960 SDHC_DATA_TIMEOUT_ERROR)) { 1961 hp->intr_error_status |= error; 1962 hp->intr_status |= status; 1963 cv_broadcast(&hp->intr_cv); 1964 } 1965 1966 /* 1967 * Wake up the sdmmc event thread to scan for cards. 1968 */ 1969 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1970 if (hp->sdmmc != NULL) { 1971 sdmmc_needs_discover(hp->sdmmc); 1972 } 1973 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1974 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1975 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1976 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1977 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1978 } 1979 } 1980 1981 /* 1982 * Wake up the blocking process to service command 1983 * related interrupt(s). 1984 */ 1985 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1986 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1987 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1988 hp->intr_status |= status; 1989 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1990 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1991 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1992 } 1993 cv_broadcast(&hp->intr_cv); 1994 } 1995 1996 /* 1997 * Service SD card interrupts. 1998 */ 1999 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 2000 && ISSET(status, SDHC_CARD_INTERRUPT)) { 2001 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 2002 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 2003 sdmmc_card_intr(hp->sdmmc); 2004 } 2005 next_port: 2006 mutex_exit(&hp->intr_lock); 2007 } 2008 2009 return done; 2010 } 2011 2012 kmutex_t * 2013 sdhc_host_lock(struct sdhc_host *hp) 2014 { 2015 return &hp->intr_lock; 2016 } 2017 2018 #ifdef SDHC_DEBUG 2019 void 2020 sdhc_dump_regs(struct sdhc_host *hp) 2021 { 2022 2023 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 2024 HREAD4(hp, SDHC_PRESENT_STATE)); 2025 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 2026 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 2027 HREAD1(hp, SDHC_POWER_CTL)); 2028 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 2029 HREAD2(hp, SDHC_NINTR_STATUS)); 2030 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 2031 HREAD2(hp, SDHC_EINTR_STATUS)); 2032 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 2033 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 2034 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 2035 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 2036 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 2037 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 2038 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 2039 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 2040 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 2041 HREAD4(hp, SDHC_CAPABILITIES)); 2042 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 2043 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 2044 } 2045 #endif 2046
Indexes created Tue Sep 23 21:09:50 GMT 2025