sdhc.c revision 1.76
1 /* $NetBSD: sdhc.c,v 1.76 2015/08/03 10:08:51 jmcneill Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.76 2015/08/03 10:08:51 jmcneill Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 40 #include <dev/sdmmc/sdhcreg.h> 41 #include <dev/sdmmc/sdhcvar.h> 42 #include <dev/sdmmc/sdmmcchip.h> 43 #include <dev/sdmmc/sdmmcreg.h> 44 #include <dev/sdmmc/sdmmcvar.h> 45 46 #ifdef SDHC_DEBUG 47 int sdhcdebug = 1; 48 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 49 void sdhc_dump_regs(struct sdhc_host *); 50 #else 51 #define DPRINTF(n,s) do {} while (0) 52 #endif 53 54 #define SDHC_COMMAND_TIMEOUT hz 55 #define SDHC_BUFFER_TIMEOUT hz 56 #define SDHC_TRANSFER_TIMEOUT hz 57 #define SDHC_DMA_TIMEOUT (hz*3) 58 59 struct sdhc_host { 60 struct sdhc_softc *sc; /* host controller device */ 61 62 bus_space_tag_t iot; /* host register set tag */ 63 bus_space_handle_t ioh; /* host register set handle */ 64 bus_size_t ios; /* host register space size */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 u_int clkbase; /* base clock frequency in KHz */ 70 int maxblklen; /* maximum block length */ 71 uint32_t ocr; /* OCR value from capabilities */ 72 73 uint8_t regs[14]; /* host controller state */ 74 75 uint16_t intr_status; /* soft interrupt status */ 76 uint16_t intr_error_status; /* soft error status */ 77 kmutex_t intr_lock; 78 kcondvar_t intr_cv; 79 80 int specver; /* spec. version */ 81 82 uint32_t flags; /* flags for this host */ 83 #define SHF_USE_DMA 0x0001 84 #define SHF_USE_4BIT_MODE 0x0002 85 #define SHF_USE_8BIT_MODE 0x0004 86 #define SHF_MODE_DMAEN 0x0008 /* needs SDHC_DMA_ENABLE in mode */ 87 #define SHF_USE_ADMA2_32 0x0010 88 #define SHF_USE_ADMA2_64 0x0020 89 #define SHF_USE_ADMA2_MASK 0x0030 90 91 bus_dmamap_t adma_map; 92 bus_dma_segment_t adma_segs[1]; 93 void *adma2; 94 }; 95 96 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 97 98 static uint8_t 99 hread1(struct sdhc_host *hp, bus_size_t reg) 100 { 101 102 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 103 return bus_space_read_1(hp->iot, hp->ioh, reg); 104 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 105 } 106 107 static uint16_t 108 hread2(struct sdhc_host *hp, bus_size_t reg) 109 { 110 111 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 112 return bus_space_read_2(hp->iot, hp->ioh, reg); 113 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 114 } 115 116 #define HREAD1(hp, reg) hread1(hp, reg) 117 #define HREAD2(hp, reg) hread2(hp, reg) 118 #define HREAD4(hp, reg) \ 119 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 120 121 122 static void 123 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 124 { 125 126 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 127 bus_space_write_1(hp->iot, hp->ioh, o, val); 128 } else { 129 const size_t shift = 8 * (o & 3); 130 o &= -4; 131 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 132 tmp = (val << shift) | (tmp & ~(0xff << shift)); 133 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 134 } 135 } 136 137 static void 138 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 139 { 140 141 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 142 bus_space_write_2(hp->iot, hp->ioh, o, val); 143 } else { 144 const size_t shift = 8 * (o & 2); 145 o &= -4; 146 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 147 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 148 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 149 } 150 } 151 152 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 153 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 154 #define HWRITE4(hp, reg, val) \ 155 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 156 157 #define HCLR1(hp, reg, bits) \ 158 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 159 #define HCLR2(hp, reg, bits) \ 160 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 161 #define HCLR4(hp, reg, bits) \ 162 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 163 #define HSET1(hp, reg, bits) \ 164 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 165 #define HSET2(hp, reg, bits) \ 166 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 167 #define HSET4(hp, reg, bits) \ 168 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 169 170 static int sdhc_host_reset(sdmmc_chipset_handle_t); 171 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 172 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 173 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 174 static int sdhc_card_detect(sdmmc_chipset_handle_t); 175 static int sdhc_write_protect(sdmmc_chipset_handle_t); 176 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 177 static int sdhc_bus_clock_ddr(sdmmc_chipset_handle_t, int, bool); 178 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 179 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 180 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 181 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 182 static void sdhc_exec_command(sdmmc_chipset_handle_t, 183 struct sdmmc_command *); 184 static int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 185 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 186 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 187 static int sdhc_soft_reset(struct sdhc_host *, int); 188 static int sdhc_wait_intr(struct sdhc_host *, int, int); 189 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 190 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 191 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 192 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 193 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 194 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 195 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 196 197 static struct sdmmc_chip_functions sdhc_functions = { 198 /* host controller reset */ 199 .host_reset = sdhc_host_reset, 200 201 /* host controller capabilities */ 202 .host_ocr = sdhc_host_ocr, 203 .host_maxblklen = sdhc_host_maxblklen, 204 205 /* card detection */ 206 .card_detect = sdhc_card_detect, 207 208 /* write protect */ 209 .write_protect = sdhc_write_protect, 210 211 /* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */ 212 .bus_power = sdhc_bus_power, 213 .bus_clock = NULL, /* see sdhc_bus_clock_ddr */ 214 .bus_width = sdhc_bus_width, 215 .bus_rod = sdhc_bus_rod, 216 217 /* command execution */ 218 .exec_command = sdhc_exec_command, 219 220 /* card interrupt */ 221 .card_enable_intr = sdhc_card_enable_intr, 222 .card_intr_ack = sdhc_card_intr_ack, 223 224 /* UHS functions */ 225 .signal_voltage = sdhc_signal_voltage, 226 .bus_clock_ddr = sdhc_bus_clock_ddr, 227 }; 228 229 static int 230 sdhc_cfprint(void *aux, const char *pnp) 231 { 232 const struct sdmmcbus_attach_args * const saa = aux; 233 const struct sdhc_host * const hp = saa->saa_sch; 234 235 if (pnp) { 236 aprint_normal("sdmmc at %s", pnp); 237 } 238 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 239 if (hp->sc->sc_host[host] == hp) { 240 aprint_normal(" slot %zu", host); 241 } 242 } 243 244 return UNCONF; 245 } 246 247 /* 248 * Called by attachment driver. For each SD card slot there is one SD 249 * host controller standard register set. (1.3) 250 */ 251 int 252 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 253 bus_space_handle_t ioh, bus_size_t iosize) 254 { 255 struct sdmmcbus_attach_args saa; 256 struct sdhc_host *hp; 257 uint32_t caps, caps2; 258 uint16_t sdhcver; 259 int error; 260 261 /* Allocate one more host structure. */ 262 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 263 if (hp == NULL) { 264 aprint_error_dev(sc->sc_dev, 265 "couldn't alloc memory (sdhc host)\n"); 266 goto err1; 267 } 268 sc->sc_host[sc->sc_nhosts++] = hp; 269 270 /* Fill in the new host structure. */ 271 hp->sc = sc; 272 hp->iot = iot; 273 hp->ioh = ioh; 274 hp->ios = iosize; 275 hp->dmat = sc->sc_dmat; 276 277 mutex_init(&hp->intr_lock, MUTEX_DEFAULT, IPL_SDMMC); 278 cv_init(&hp->intr_cv, "sdhcintr"); 279 280 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 281 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); 282 } else { 283 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 284 } 285 aprint_normal_dev(sc->sc_dev, "SDHC "); 286 hp->specver = SDHC_SPEC_VERSION(sdhcver); 287 switch (SDHC_SPEC_VERSION(sdhcver)) { 288 case SDHC_SPEC_VERS_100: 289 aprint_normal("1.0"); 290 break; 291 292 case SDHC_SPEC_VERS_200: 293 aprint_normal("2.0"); 294 break; 295 296 case SDHC_SPEC_VERS_300: 297 aprint_normal("3.0"); 298 break; 299 300 case SDHC_SPEC_VERS_400: 301 aprint_normal("4.0"); 302 break; 303 304 default: 305 aprint_normal("unknown version(0x%x)", 306 SDHC_SPEC_VERSION(sdhcver)); 307 break; 308 } 309 aprint_normal(", rev %u", SDHC_VENDOR_VERSION(sdhcver)); 310 311 /* 312 * Reset the host controller and enable interrupts. 313 */ 314 (void)sdhc_host_reset(hp); 315 316 /* Determine host capabilities. */ 317 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 318 caps = sc->sc_caps; 319 caps2 = sc->sc_caps2; 320 } else { 321 caps = HREAD4(hp, SDHC_CAPABILITIES); 322 if (hp->specver >= SDHC_SPEC_VERS_300) { 323 caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 324 } else { 325 caps2 = 0; 326 } 327 } 328 329 /* 330 * Use DMA if the host system and the controller support it. 331 * Suports integrated or external DMA egine, with or without 332 * SDHC_DMA_ENABLE in the command. 333 */ 334 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 335 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 336 ISSET(caps, SDHC_DMA_SUPPORT)))) { 337 SET(hp->flags, SHF_USE_DMA); 338 339 if (ISSET(sc->sc_flags, SDHC_FLAG_USE_ADMA2) && 340 ISSET(caps, SDHC_ADMA2_SUPP)) { 341 SET(hp->flags, SHF_MODE_DMAEN); 342 /* 343 * 64-bit mode was present in the 2.00 spec, removed 344 * from 3.00, and re-added in 4.00 with a different 345 * descriptor layout. We only support 2.00 and 3.00 346 * descriptors for now. 347 */ 348 if (hp->specver == SDHC_SPEC_VERS_200 && 349 ISSET(caps, SDHC_64BIT_SYS_BUS)) { 350 SET(hp->flags, SHF_USE_ADMA2_64); 351 aprint_normal(", 64-bit ADMA2"); 352 } else { 353 SET(hp->flags, SHF_USE_ADMA2_32); 354 aprint_normal(", 32-bit ADMA2"); 355 } 356 } else { 357 if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) || 358 ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN)) 359 SET(hp->flags, SHF_MODE_DMAEN); 360 if (sc->sc_vendor_transfer_data_dma) { 361 aprint_normal(", platform DMA"); 362 } else { 363 aprint_normal(", SDMA"); 364 } 365 } 366 } else { 367 aprint_normal(", PIO"); 368 } 369 370 /* 371 * Determine the base clock frequency. (2.2.24) 372 */ 373 if (hp->specver >= SDHC_SPEC_VERS_300) { 374 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 375 } else { 376 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 377 } 378 if (hp->clkbase == 0 || 379 ISSET(sc->sc_flags, SDHC_FLAG_NO_CLKBASE)) { 380 if (sc->sc_clkbase == 0) { 381 /* The attachment driver must tell us. */ 382 aprint_error_dev(sc->sc_dev, 383 "unknown base clock frequency\n"); 384 goto err; 385 } 386 hp->clkbase = sc->sc_clkbase; 387 } 388 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 389 /* SDHC 1.0 supports only 10-63 MHz. */ 390 aprint_error_dev(sc->sc_dev, 391 "base clock frequency out of range: %u MHz\n", 392 hp->clkbase / 1000); 393 goto err; 394 } 395 aprint_normal(", %u kHz", hp->clkbase); 396 397 /* 398 * XXX Set the data timeout counter value according to 399 * capabilities. (2.2.15) 400 */ 401 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 402 #if 1 403 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 404 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 405 #endif 406 407 if (ISSET(caps, SDHC_EMBEDDED_SLOT)) 408 aprint_normal(", embedded slot"); 409 410 /* 411 * Determine SD bus voltage levels supported by the controller. 412 */ 413 aprint_normal(","); 414 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) { 415 SET(hp->ocr, MMC_OCR_HCS); 416 aprint_normal(" HS"); 417 } 418 if (ISSET(caps2, SDHC_SDR50_SUPP)) { 419 SET(hp->ocr, MMC_OCR_S18A); 420 aprint_normal(" SDR50"); 421 } 422 if (ISSET(caps2, SDHC_DDR50_SUPP)) { 423 SET(hp->ocr, MMC_OCR_S18A); 424 aprint_normal(" DDR50"); 425 } 426 if (ISSET(caps2, SDHC_SDR104_SUPP)) { 427 SET(hp->ocr, MMC_OCR_S18A); 428 aprint_normal(" SDR104 HS200"); 429 } 430 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 431 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 432 aprint_normal(" 1.8V"); 433 } 434 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 435 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 436 aprint_normal(" 3.0V"); 437 } 438 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 439 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 440 aprint_normal(" 3.3V"); 441 } 442 443 /* 444 * Determine the maximum block length supported by the host 445 * controller. (2.2.24) 446 */ 447 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 448 case SDHC_MAX_BLK_LEN_512: 449 hp->maxblklen = 512; 450 break; 451 452 case SDHC_MAX_BLK_LEN_1024: 453 hp->maxblklen = 1024; 454 break; 455 456 case SDHC_MAX_BLK_LEN_2048: 457 hp->maxblklen = 2048; 458 break; 459 460 case SDHC_MAX_BLK_LEN_4096: 461 hp->maxblklen = 4096; 462 break; 463 464 default: 465 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 466 goto err; 467 } 468 aprint_normal(", %u byte blocks", hp->maxblklen); 469 aprint_normal("\n"); 470 471 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 472 int rseg; 473 474 /* Allocate ADMA2 descriptor memory */ 475 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 476 PAGE_SIZE, hp->adma_segs, 1, &rseg, BUS_DMA_WAITOK); 477 if (error) { 478 aprint_error_dev(sc->sc_dev, 479 "ADMA2 dmamem_alloc failed (%d)\n", error); 480 goto adma_done; 481 } 482 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 483 PAGE_SIZE, (void **)&hp->adma2, BUS_DMA_WAITOK); 484 if (error) { 485 aprint_error_dev(sc->sc_dev, 486 "ADMA2 dmamem_map failed (%d)\n", error); 487 goto adma_done; 488 } 489 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 490 0, BUS_DMA_WAITOK, &hp->adma_map); 491 if (error) { 492 aprint_error_dev(sc->sc_dev, 493 "ADMA2 dmamap_create failed (%d)\n", error); 494 goto adma_done; 495 } 496 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 497 hp->adma2, PAGE_SIZE, NULL, 498 BUS_DMA_WAITOK|BUS_DMA_WRITE); 499 if (error) { 500 aprint_error_dev(sc->sc_dev, 501 "ADMA2 dmamap_load failed (%d)\n", error); 502 goto adma_done; 503 } 504 505 memset(hp->adma2, 0, PAGE_SIZE); 506 507 adma_done: 508 if (error) 509 CLR(hp->flags, SHF_USE_ADMA2_MASK); 510 } 511 512 /* 513 * Attach the generic SD/MMC bus driver. (The bus driver must 514 * not invoke any chipset functions before it is attached.) 515 */ 516 memset(&saa, 0, sizeof(saa)); 517 saa.saa_busname = "sdmmc"; 518 saa.saa_sct = &sdhc_functions; 519 saa.saa_sch = hp; 520 saa.saa_dmat = hp->dmat; 521 saa.saa_clkmax = hp->clkbase; 522 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 523 saa.saa_clkmin = hp->clkbase / 256 / 2046; 524 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 525 saa.saa_clkmin = hp->clkbase / 256 / 16; 526 else if (hp->sc->sc_clkmsk != 0) 527 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 528 (ffs(hp->sc->sc_clkmsk) - 1)); 529 else if (hp->specver >= SDHC_SPEC_VERS_300) 530 saa.saa_clkmin = hp->clkbase / 0x3ff; 531 else 532 saa.saa_clkmin = hp->clkbase / 256; 533 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 534 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 535 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 536 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 537 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 538 if (ISSET(caps2, SDHC_SDR104_SUPP)) 539 saa.saa_caps |= SMC_CAPS_UHS_SDR104 | 540 SMC_CAPS_UHS_SDR50 | 541 SMC_CAPS_MMC_HS200; 542 if (ISSET(caps2, SDHC_SDR50_SUPP)) 543 saa.saa_caps |= SMC_CAPS_UHS_SDR50; 544 if (ISSET(caps2, SDHC_DDR50_SUPP)) 545 saa.saa_caps |= SMC_CAPS_UHS_DDR50; 546 if (ISSET(hp->flags, SHF_USE_DMA)) { 547 saa.saa_caps |= SMC_CAPS_DMA; 548 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 549 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 550 } 551 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 552 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 553 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 554 555 return 0; 556 557 err: 558 cv_destroy(&hp->intr_cv); 559 mutex_destroy(&hp->intr_lock); 560 free(hp, M_DEVBUF); 561 sc->sc_host[--sc->sc_nhosts] = NULL; 562 err1: 563 return 1; 564 } 565 566 int 567 sdhc_detach(struct sdhc_softc *sc, int flags) 568 { 569 struct sdhc_host *hp; 570 int rv = 0; 571 572 for (size_t n = 0; n < sc->sc_nhosts; n++) { 573 hp = sc->sc_host[n]; 574 if (hp == NULL) 575 continue; 576 if (hp->sdmmc != NULL) { 577 rv = config_detach(hp->sdmmc, flags); 578 if (rv) 579 break; 580 hp->sdmmc = NULL; 581 } 582 /* disable interrupts */ 583 if ((flags & DETACH_FORCE) == 0) { 584 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 585 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 586 } else { 587 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 588 } 589 sdhc_soft_reset(hp, SDHC_RESET_ALL); 590 } 591 cv_destroy(&hp->intr_cv); 592 mutex_destroy(&hp->intr_lock); 593 if (hp->ios > 0) { 594 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 595 hp->ios = 0; 596 } 597 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 598 bus_dmamap_unload(sc->sc_dmat, hp->adma_map); 599 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 600 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 601 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, 1); 602 } 603 free(hp, M_DEVBUF); 604 sc->sc_host[n] = NULL; 605 } 606 607 return rv; 608 } 609 610 bool 611 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 612 { 613 struct sdhc_softc *sc = device_private(dev); 614 struct sdhc_host *hp; 615 size_t i; 616 617 /* XXX poll for command completion or suspend command 618 * in progress */ 619 620 /* Save the host controller state. */ 621 for (size_t n = 0; n < sc->sc_nhosts; n++) { 622 hp = sc->sc_host[n]; 623 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 624 for (i = 0; i < sizeof hp->regs; i += 4) { 625 uint32_t v = HREAD4(hp, i); 626 hp->regs[i + 0] = (v >> 0); 627 hp->regs[i + 1] = (v >> 8); 628 if (i + 3 < sizeof hp->regs) { 629 hp->regs[i + 2] = (v >> 16); 630 hp->regs[i + 3] = (v >> 24); 631 } 632 } 633 } else { 634 for (i = 0; i < sizeof hp->regs; i++) { 635 hp->regs[i] = HREAD1(hp, i); 636 } 637 } 638 } 639 return true; 640 } 641 642 bool 643 sdhc_resume(device_t dev, const pmf_qual_t *qual) 644 { 645 struct sdhc_softc *sc = device_private(dev); 646 struct sdhc_host *hp; 647 size_t i; 648 649 /* Restore the host controller state. */ 650 for (size_t n = 0; n < sc->sc_nhosts; n++) { 651 hp = sc->sc_host[n]; 652 (void)sdhc_host_reset(hp); 653 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 654 for (i = 0; i < sizeof hp->regs; i += 4) { 655 if (i + 3 < sizeof hp->regs) { 656 HWRITE4(hp, i, 657 (hp->regs[i + 0] << 0) 658 | (hp->regs[i + 1] << 8) 659 | (hp->regs[i + 2] << 16) 660 | (hp->regs[i + 3] << 24)); 661 } else { 662 HWRITE4(hp, i, 663 (hp->regs[i + 0] << 0) 664 | (hp->regs[i + 1] << 8)); 665 } 666 } 667 } else { 668 for (i = 0; i < sizeof hp->regs; i++) { 669 HWRITE1(hp, i, hp->regs[i]); 670 } 671 } 672 } 673 return true; 674 } 675 676 bool 677 sdhc_shutdown(device_t dev, int flags) 678 { 679 struct sdhc_softc *sc = device_private(dev); 680 struct sdhc_host *hp; 681 682 /* XXX chip locks up if we don't disable it before reboot. */ 683 for (size_t i = 0; i < sc->sc_nhosts; i++) { 684 hp = sc->sc_host[i]; 685 (void)sdhc_host_reset(hp); 686 } 687 return true; 688 } 689 690 /* 691 * Reset the host controller. Called during initialization, when 692 * cards are removed, upon resume, and during error recovery. 693 */ 694 static int 695 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 696 { 697 struct sdhc_host *hp = (struct sdhc_host *)sch; 698 uint32_t sdhcimask; 699 int error; 700 701 KASSERT(mutex_owned(&hp->intr_lock)); 702 703 /* Disable all interrupts. */ 704 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 705 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 706 } else { 707 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 708 } 709 710 /* 711 * Reset the entire host controller and wait up to 100ms for 712 * the controller to clear the reset bit. 713 */ 714 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 715 if (error) 716 goto out; 717 718 /* Set data timeout counter value to max for now. */ 719 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 720 #if 1 721 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 722 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 723 #endif 724 725 /* Enable interrupts. */ 726 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 727 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 728 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 729 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 730 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 731 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 732 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 733 sdhcimask ^= 734 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 735 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 736 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 737 } else { 738 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 739 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 740 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 741 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 742 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 743 } 744 745 out: 746 return error; 747 } 748 749 static int 750 sdhc_host_reset(sdmmc_chipset_handle_t sch) 751 { 752 struct sdhc_host *hp = (struct sdhc_host *)sch; 753 int error; 754 755 mutex_enter(&hp->intr_lock); 756 error = sdhc_host_reset1(sch); 757 mutex_exit(&hp->intr_lock); 758 759 return error; 760 } 761 762 static uint32_t 763 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 764 { 765 struct sdhc_host *hp = (struct sdhc_host *)sch; 766 767 return hp->ocr; 768 } 769 770 static int 771 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 772 { 773 struct sdhc_host *hp = (struct sdhc_host *)sch; 774 775 return hp->maxblklen; 776 } 777 778 /* 779 * Return non-zero if the card is currently inserted. 780 */ 781 static int 782 sdhc_card_detect(sdmmc_chipset_handle_t sch) 783 { 784 struct sdhc_host *hp = (struct sdhc_host *)sch; 785 int r; 786 787 if (hp->sc->sc_vendor_card_detect) 788 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 789 790 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 791 792 return r ? 1 : 0; 793 } 794 795 /* 796 * Return non-zero if the card is currently write-protected. 797 */ 798 static int 799 sdhc_write_protect(sdmmc_chipset_handle_t sch) 800 { 801 struct sdhc_host *hp = (struct sdhc_host *)sch; 802 int r; 803 804 if (hp->sc->sc_vendor_write_protect) 805 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 806 807 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 808 809 return r ? 0 : 1; 810 } 811 812 /* 813 * Set or change SD bus voltage and enable or disable SD bus power. 814 * Return zero on success. 815 */ 816 static int 817 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 818 { 819 struct sdhc_host *hp = (struct sdhc_host *)sch; 820 uint8_t vdd; 821 int error = 0; 822 const uint32_t pcmask = 823 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 824 825 mutex_enter(&hp->intr_lock); 826 827 /* 828 * Disable bus power before voltage change. 829 */ 830 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 831 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 832 HWRITE1(hp, SDHC_POWER_CTL, 0); 833 834 /* If power is disabled, reset the host and return now. */ 835 if (ocr == 0) { 836 (void)sdhc_host_reset1(hp); 837 goto out; 838 } 839 840 /* 841 * Select the lowest voltage according to capabilities. 842 */ 843 ocr &= hp->ocr; 844 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 845 vdd = SDHC_VOLTAGE_1_8V; 846 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 847 vdd = SDHC_VOLTAGE_3_0V; 848 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 849 vdd = SDHC_VOLTAGE_3_3V; 850 } else { 851 /* Unsupported voltage level requested. */ 852 error = EINVAL; 853 goto out; 854 } 855 856 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 857 /* 858 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 859 * voltage ramp until power rises. 860 */ 861 862 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SINGLE_POWER_WRITE)) { 863 HWRITE1(hp, SDHC_POWER_CTL, 864 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 865 } else { 866 HWRITE1(hp, SDHC_POWER_CTL, 867 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 868 sdmmc_delay(1); 869 HWRITE1(hp, SDHC_POWER_CTL, 870 (vdd << SDHC_VOLTAGE_SHIFT)); 871 sdmmc_delay(1); 872 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 873 sdmmc_delay(10000); 874 } 875 876 /* 877 * The host system may not power the bus due to battery low, 878 * etc. In that case, the host controller should clear the 879 * bus power bit. 880 */ 881 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 882 error = ENXIO; 883 goto out; 884 } 885 } 886 887 out: 888 mutex_exit(&hp->intr_lock); 889 890 return error; 891 } 892 893 /* 894 * Return the smallest possible base clock frequency divisor value 895 * for the CLOCK_CTL register to produce `freq' (KHz). 896 */ 897 static bool 898 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 899 { 900 u_int div; 901 902 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 903 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 904 if ((hp->clkbase / div) <= freq) { 905 *divp = SDHC_SDCLK_CGM 906 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 907 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 908 //freq = hp->clkbase / div; 909 return true; 910 } 911 } 912 /* No divisor found. */ 913 return false; 914 } 915 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 916 u_int dvs = (hp->clkbase + freq - 1) / freq; 917 u_int roundup = dvs & 1; 918 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 919 if (dvs + roundup <= 16) { 920 dvs += roundup - 1; 921 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 922 | (dvs << SDHC_SDCLK_DVS_SHIFT); 923 DPRINTF(2, 924 ("%s: divisor for freq %u is %u * %u\n", 925 HDEVNAME(hp), freq, div * 2, dvs + 1)); 926 //freq = hp->clkbase / (div * 2) * (dvs + 1); 927 return true; 928 } 929 /* 930 * If we drop bits, we need to round up the divisor. 931 */ 932 roundup |= dvs & 1; 933 } 934 /* No divisor found. */ 935 return false; 936 } 937 if (hp->sc->sc_clkmsk != 0) { 938 div = howmany(hp->clkbase, freq); 939 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 940 return false; 941 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 942 //freq = hp->clkbase / div; 943 return true; 944 } 945 if (hp->specver >= SDHC_SPEC_VERS_300) { 946 div = howmany(hp->clkbase, freq); 947 div = div > 1 ? howmany(div, 2) : 0; 948 if (div > 0x3ff) 949 return false; 950 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 951 << SDHC_SDCLK_XDIV_SHIFT) | 952 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 953 << SDHC_SDCLK_DIV_SHIFT); 954 //freq = hp->clkbase / (div ? div * 2 : 1); 955 return true; 956 } else { 957 for (div = 1; div <= 256; div *= 2) { 958 if ((hp->clkbase / div) <= freq) { 959 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 960 //freq = hp->clkbase / div; 961 return true; 962 } 963 } 964 /* No divisor found. */ 965 return false; 966 } 967 /* No divisor found. */ 968 return false; 969 } 970 971 /* 972 * Set or change SDCLK frequency or disable the SD clock. 973 * Return zero on success. 974 */ 975 static int 976 sdhc_bus_clock_ddr(sdmmc_chipset_handle_t sch, int freq, bool ddr) 977 { 978 struct sdhc_host *hp = (struct sdhc_host *)sch; 979 u_int div; 980 u_int timo; 981 int16_t reg; 982 int error = 0; 983 bool present __diagused; 984 985 mutex_enter(&hp->intr_lock); 986 987 #ifdef DIAGNOSTIC 988 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 989 990 /* Must not stop the clock if commands are in progress. */ 991 if (present && sdhc_card_detect(hp)) { 992 aprint_normal_dev(hp->sc->sc_dev, 993 "%s: command in progress\n", __func__); 994 } 995 #endif 996 997 if (hp->sc->sc_vendor_bus_clock) { 998 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 999 if (error != 0) 1000 goto out; 1001 } 1002 1003 /* 1004 * Stop SD clock before changing the frequency. 1005 */ 1006 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1007 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 1008 if (freq == SDMMC_SDCLK_OFF) { 1009 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 1010 goto out; 1011 } 1012 } else { 1013 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1014 if (freq == SDMMC_SDCLK_OFF) 1015 goto out; 1016 } 1017 1018 if (hp->specver >= SDHC_SPEC_VERS_300) { 1019 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 1020 if (freq > 100000) { 1021 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR104); 1022 } else if (freq > 50000) { 1023 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR50); 1024 } else if (freq > 25000) { 1025 if (ddr) { 1026 HSET2(hp, SDHC_HOST_CTL2, 1027 SDHC_UHS_MODE_SELECT_DDR50); 1028 } else { 1029 HSET2(hp, SDHC_HOST_CTL2, 1030 SDHC_UHS_MODE_SELECT_SDR25); 1031 } 1032 } else if (freq > 400) { 1033 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR12); 1034 } 1035 } 1036 1037 /* 1038 * Set the minimum base clock frequency divisor. 1039 */ 1040 if (!sdhc_clock_divisor(hp, freq, &div)) { 1041 /* Invalid base clock frequency or `freq' value. */ 1042 aprint_error_dev(hp->sc->sc_dev, 1043 "Invalid bus clock %d kHz\n", freq); 1044 error = EINVAL; 1045 goto out; 1046 } 1047 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1048 HWRITE4(hp, SDHC_CLOCK_CTL, 1049 div | (SDHC_TIMEOUT_MAX << 16)); 1050 } else { 1051 reg = HREAD2(hp, SDHC_CLOCK_CTL); 1052 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 1053 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 1054 } 1055 1056 /* 1057 * Start internal clock. Wait 10ms for stabilization. 1058 */ 1059 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1060 sdmmc_delay(10000); 1061 HSET4(hp, SDHC_CLOCK_CTL, 1062 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 1063 } else { 1064 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 1065 for (timo = 1000; timo > 0; timo--) { 1066 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 1067 SDHC_INTCLK_STABLE)) 1068 break; 1069 sdmmc_delay(10); 1070 } 1071 if (timo == 0) { 1072 error = ETIMEDOUT; 1073 goto out; 1074 } 1075 } 1076 1077 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1078 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 1079 /* 1080 * Sending 80 clocks at 400kHz takes 200us. 1081 * So delay for that time + slop and then 1082 * check a few times for completion. 1083 */ 1084 sdmmc_delay(210); 1085 for (timo = 10; timo > 0; timo--) { 1086 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 1087 SDHC_INIT_ACTIVE)) 1088 break; 1089 sdmmc_delay(10); 1090 } 1091 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 1092 1093 /* 1094 * Enable SD clock. 1095 */ 1096 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1097 } else { 1098 /* 1099 * Enable SD clock. 1100 */ 1101 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1102 1103 if (freq > 25000 && 1104 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 1105 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1106 else 1107 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1108 } 1109 1110 out: 1111 mutex_exit(&hp->intr_lock); 1112 1113 return error; 1114 } 1115 1116 static int 1117 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 1118 { 1119 struct sdhc_host *hp = (struct sdhc_host *)sch; 1120 int reg; 1121 1122 switch (width) { 1123 case 1: 1124 case 4: 1125 break; 1126 1127 case 8: 1128 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 1129 break; 1130 /* FALLTHROUGH */ 1131 default: 1132 DPRINTF(0,("%s: unsupported bus width (%d)\n", 1133 HDEVNAME(hp), width)); 1134 return 1; 1135 } 1136 1137 mutex_enter(&hp->intr_lock); 1138 1139 reg = HREAD1(hp, SDHC_HOST_CTL); 1140 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1141 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 1142 if (width == 4) 1143 reg |= SDHC_4BIT_MODE; 1144 else if (width == 8) 1145 reg |= SDHC_ESDHC_8BIT_MODE; 1146 } else { 1147 reg &= ~SDHC_4BIT_MODE; 1148 if (hp->specver >= SDHC_SPEC_VERS_300) { 1149 reg &= ~SDHC_8BIT_MODE; 1150 } 1151 if (width == 4) { 1152 reg |= SDHC_4BIT_MODE; 1153 } else if (width == 8 && hp->specver >= SDHC_SPEC_VERS_300) { 1154 reg |= SDHC_8BIT_MODE; 1155 } 1156 } 1157 HWRITE1(hp, SDHC_HOST_CTL, reg); 1158 1159 mutex_exit(&hp->intr_lock); 1160 1161 return 0; 1162 } 1163 1164 static int 1165 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1166 { 1167 struct sdhc_host *hp = (struct sdhc_host *)sch; 1168 1169 if (hp->sc->sc_vendor_rod) 1170 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1171 1172 return 0; 1173 } 1174 1175 static void 1176 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1177 { 1178 struct sdhc_host *hp = (struct sdhc_host *)sch; 1179 1180 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1181 mutex_enter(&hp->intr_lock); 1182 if (enable) { 1183 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1184 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1185 } else { 1186 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1187 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1188 } 1189 mutex_exit(&hp->intr_lock); 1190 } 1191 } 1192 1193 static void 1194 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1195 { 1196 struct sdhc_host *hp = (struct sdhc_host *)sch; 1197 1198 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1199 mutex_enter(&hp->intr_lock); 1200 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1201 mutex_exit(&hp->intr_lock); 1202 } 1203 } 1204 1205 static int 1206 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 1207 { 1208 struct sdhc_host *hp = (struct sdhc_host *)sch; 1209 1210 switch (signal_voltage) { 1211 case SDMMC_SIGNAL_VOLTAGE_180: 1212 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1213 break; 1214 case SDMMC_SIGNAL_VOLTAGE_330: 1215 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1216 break; 1217 default: 1218 return EINVAL; 1219 } 1220 1221 return 0; 1222 } 1223 1224 static int 1225 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1226 { 1227 uint32_t state; 1228 int timeout; 1229 1230 for (timeout = 10000; timeout > 0; timeout--) { 1231 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 1232 return 0; 1233 sdmmc_delay(10); 1234 } 1235 aprint_error_dev(hp->sc->sc_dev, "timeout waiting for mask %#x value %#x (state=%#x)\n", 1236 mask, value, state); 1237 return ETIMEDOUT; 1238 } 1239 1240 static void 1241 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1242 { 1243 struct sdhc_host *hp = (struct sdhc_host *)sch; 1244 int error; 1245 1246 mutex_enter(&hp->intr_lock); 1247 1248 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1249 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1250 if (ISSET(hp->flags, SHF_USE_DMA)) { 1251 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1252 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1253 } else { 1254 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1255 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1256 } 1257 } 1258 1259 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_TIMEOUT)) { 1260 const uint16_t eintr = SDHC_CMD_TIMEOUT_ERROR; 1261 if (cmd->c_data != NULL) { 1262 HCLR2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1263 HCLR2(hp, SDHC_EINTR_STATUS_EN, eintr); 1264 } else { 1265 HSET2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1266 HSET2(hp, SDHC_EINTR_STATUS_EN, eintr); 1267 } 1268 } 1269 1270 /* 1271 * Start the MMC command, or mark `cmd' as failed and return. 1272 */ 1273 error = sdhc_start_command(hp, cmd); 1274 if (error) { 1275 cmd->c_error = error; 1276 goto out; 1277 } 1278 1279 /* 1280 * Wait until the command phase is done, or until the command 1281 * is marked done for any other reason. 1282 */ 1283 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1284 cmd->c_error = ETIMEDOUT; 1285 goto out; 1286 } 1287 1288 /* 1289 * The host controller removes bits [0:7] from the response 1290 * data (CRC) and we pass the data up unchanged to the bus 1291 * driver (without padding). 1292 */ 1293 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1294 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1295 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1296 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1297 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1298 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1299 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1300 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1301 (cmd->c_resp[1] << 24); 1302 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1303 (cmd->c_resp[2] << 24); 1304 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1305 (cmd->c_resp[3] << 24); 1306 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1307 } 1308 } 1309 } 1310 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1311 1312 /* 1313 * If the command has data to transfer in any direction, 1314 * execute the transfer now. 1315 */ 1316 if (cmd->c_error == 0 && cmd->c_data != NULL) 1317 sdhc_transfer_data(hp, cmd); 1318 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1319 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10)) { 1320 cmd->c_error = ETIMEDOUT; 1321 goto out; 1322 } 1323 } 1324 1325 out: 1326 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1327 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1328 /* Turn off the LED. */ 1329 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1330 } 1331 SET(cmd->c_flags, SCF_ITSDONE); 1332 1333 mutex_exit(&hp->intr_lock); 1334 1335 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1336 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1337 cmd->c_flags, cmd->c_error)); 1338 } 1339 1340 static int 1341 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1342 { 1343 struct sdhc_softc * const sc = hp->sc; 1344 uint16_t blksize = 0; 1345 uint16_t blkcount = 0; 1346 uint16_t mode; 1347 uint16_t command; 1348 int error; 1349 1350 KASSERT(mutex_owned(&hp->intr_lock)); 1351 1352 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1353 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1354 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1355 1356 /* 1357 * The maximum block length for commands should be the minimum 1358 * of the host buffer size and the card buffer size. (1.7.2) 1359 */ 1360 1361 /* Fragment the data into proper blocks. */ 1362 if (cmd->c_datalen > 0) { 1363 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1364 blkcount = cmd->c_datalen / blksize; 1365 if (cmd->c_datalen % blksize > 0) { 1366 /* XXX: Split this command. (1.7.4) */ 1367 aprint_error_dev(sc->sc_dev, 1368 "data not a multiple of %u bytes\n", blksize); 1369 return EINVAL; 1370 } 1371 } 1372 1373 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1374 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1375 aprint_error_dev(sc->sc_dev, "too much data\n"); 1376 return EINVAL; 1377 } 1378 1379 /* Prepare transfer mode register value. (2.2.5) */ 1380 mode = SDHC_BLOCK_COUNT_ENABLE; 1381 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1382 mode |= SDHC_READ_MODE; 1383 if (blkcount > 1) { 1384 mode |= SDHC_MULTI_BLOCK_MODE; 1385 /* XXX only for memory commands? */ 1386 mode |= SDHC_AUTO_CMD12_ENABLE; 1387 } 1388 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1389 ISSET(hp->flags, SHF_MODE_DMAEN)) { 1390 mode |= SDHC_DMA_ENABLE; 1391 } 1392 1393 /* 1394 * Prepare command register value. (2.2.6) 1395 */ 1396 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1397 1398 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1399 command |= SDHC_CRC_CHECK_ENABLE; 1400 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1401 command |= SDHC_INDEX_CHECK_ENABLE; 1402 if (cmd->c_data != NULL) 1403 command |= SDHC_DATA_PRESENT_SELECT; 1404 1405 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1406 command |= SDHC_NO_RESPONSE; 1407 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1408 command |= SDHC_RESP_LEN_136; 1409 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1410 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1411 else 1412 command |= SDHC_RESP_LEN_48; 1413 1414 /* Wait until command and data inhibit bits are clear. (1.5) */ 1415 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1416 if (error) { 1417 aprint_error_dev(sc->sc_dev, "command or data phase inhibited\n"); 1418 return error; 1419 } 1420 1421 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1422 HDEVNAME(hp), blksize, blkcount, mode, command)); 1423 1424 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1425 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1426 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1427 } 1428 1429 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1430 /* Alert the user not to remove the card. */ 1431 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1432 } 1433 1434 /* Set DMA start address. */ 1435 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK) && cmd->c_datalen > 0) { 1436 for (int seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 1437 bus_addr_t paddr = 1438 cmd->c_dmamap->dm_segs[seg].ds_addr; 1439 uint16_t len = 1440 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1441 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1442 uint16_t attr = 1443 SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1444 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 1445 attr |= SDHC_ADMA2_END; 1446 } 1447 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1448 struct sdhc_adma2_descriptor32 *desc = 1449 hp->adma2; 1450 desc[seg].attribute = htole16(attr); 1451 desc[seg].length = htole16(len); 1452 desc[seg].address = htole32(paddr); 1453 } else { 1454 struct sdhc_adma2_descriptor64 *desc = 1455 hp->adma2; 1456 desc[seg].attribute = htole16(attr); 1457 desc[seg].length = htole16(len); 1458 desc[seg].address = htole32(paddr & 0xffffffff); 1459 desc[seg].address_hi = htole32( 1460 (uint64_t)paddr >> 32); 1461 } 1462 } 1463 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1464 struct sdhc_adma2_descriptor32 *desc = hp->adma2; 1465 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1466 } else { 1467 struct sdhc_adma2_descriptor64 *desc = hp->adma2; 1468 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1469 } 1470 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1471 BUS_DMASYNC_PREWRITE); 1472 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1473 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2); 1474 1475 const bus_addr_t desc_addr = hp->adma_map->dm_segs[0].ds_addr; 1476 1477 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff); 1478 if (ISSET(hp->flags, SHF_USE_ADMA2_64)) { 1479 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4, 1480 (uint64_t)desc_addr >> 32); 1481 } 1482 } else if (ISSET(mode, SDHC_DMA_ENABLE) && 1483 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) { 1484 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1485 } 1486 1487 /* 1488 * Start a CPU data transfer. Writing to the high order byte 1489 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1490 */ 1491 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1492 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1493 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1494 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1495 } else { 1496 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1497 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1498 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1499 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1500 HWRITE2(hp, SDHC_COMMAND, command); 1501 } 1502 1503 return 0; 1504 } 1505 1506 static void 1507 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1508 { 1509 struct sdhc_softc *sc = hp->sc; 1510 int error; 1511 1512 KASSERT(mutex_owned(&hp->intr_lock)); 1513 1514 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1515 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1516 1517 #ifdef SDHC_DEBUG 1518 /* XXX I forgot why I wanted to know when this happens :-( */ 1519 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1520 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1521 aprint_error_dev(hp->sc->sc_dev, 1522 "CMD52/53 error response flags %#x\n", 1523 MMC_R1(cmd->c_resp) & 0xff00); 1524 } 1525 #endif 1526 1527 if (cmd->c_dmamap != NULL) { 1528 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1529 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd); 1530 if (error == 0 && !sdhc_wait_intr(hp, 1531 SDHC_TRANSFER_COMPLETE, SDHC_DMA_TIMEOUT)) { 1532 error = ETIMEDOUT; 1533 } 1534 } else { 1535 error = sdhc_transfer_data_dma(hp, cmd); 1536 } 1537 } else 1538 error = sdhc_transfer_data_pio(hp, cmd); 1539 if (error) 1540 cmd->c_error = error; 1541 SET(cmd->c_flags, SCF_ITSDONE); 1542 1543 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1544 HDEVNAME(hp), cmd->c_error)); 1545 } 1546 1547 static int 1548 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1549 { 1550 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1551 bus_addr_t posaddr; 1552 bus_addr_t segaddr; 1553 bus_size_t seglen; 1554 u_int seg = 0; 1555 int error = 0; 1556 int status; 1557 1558 KASSERT(mutex_owned(&hp->intr_lock)); 1559 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1560 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1561 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1562 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1563 1564 for (;;) { 1565 status = sdhc_wait_intr(hp, 1566 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1567 SDHC_DMA_TIMEOUT); 1568 1569 if (status & SDHC_TRANSFER_COMPLETE) { 1570 break; 1571 } 1572 if (!status) { 1573 error = ETIMEDOUT; 1574 break; 1575 } 1576 1577 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1578 continue; 1579 } 1580 1581 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1582 continue; 1583 } 1584 1585 /* DMA Interrupt (boundary crossing) */ 1586 1587 segaddr = dm_segs[seg].ds_addr; 1588 seglen = dm_segs[seg].ds_len; 1589 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1590 1591 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1592 continue; 1593 } 1594 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1595 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1596 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1597 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1598 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1599 } 1600 1601 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1602 bus_dmamap_sync(hp->sc->sc_dmat, hp->adma_map, 0, 1603 PAGE_SIZE, BUS_DMASYNC_POSTWRITE); 1604 } 1605 1606 return error; 1607 } 1608 1609 static int 1610 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1611 { 1612 uint8_t *data = cmd->c_data; 1613 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1614 u_int len, datalen; 1615 u_int imask; 1616 u_int pmask; 1617 int error = 0; 1618 1619 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1620 imask = SDHC_BUFFER_READ_READY; 1621 pmask = SDHC_BUFFER_READ_ENABLE; 1622 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1623 pio_func = esdhc_read_data_pio; 1624 } else { 1625 pio_func = sdhc_read_data_pio; 1626 } 1627 } else { 1628 imask = SDHC_BUFFER_WRITE_READY; 1629 pmask = SDHC_BUFFER_WRITE_ENABLE; 1630 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1631 pio_func = esdhc_write_data_pio; 1632 } else { 1633 pio_func = sdhc_write_data_pio; 1634 } 1635 } 1636 datalen = cmd->c_datalen; 1637 1638 KASSERT(mutex_owned(&hp->intr_lock)); 1639 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1640 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1641 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1642 1643 while (datalen > 0) { 1644 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1645 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1646 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1647 } else { 1648 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1649 } 1650 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1651 error = ETIMEDOUT; 1652 break; 1653 } 1654 1655 error = sdhc_wait_state(hp, pmask, pmask); 1656 if (error) 1657 break; 1658 } 1659 1660 len = MIN(datalen, cmd->c_blklen); 1661 (*pio_func)(hp, data, len); 1662 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1663 HDEVNAME(hp), len, data)); 1664 1665 data += len; 1666 datalen -= len; 1667 } 1668 1669 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1670 SDHC_TRANSFER_TIMEOUT)) 1671 error = ETIMEDOUT; 1672 1673 return error; 1674 } 1675 1676 static void 1677 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1678 { 1679 1680 if (((__uintptr_t)data & 3) == 0) { 1681 while (datalen > 3) { 1682 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1683 data += 4; 1684 datalen -= 4; 1685 } 1686 if (datalen > 1) { 1687 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1688 data += 2; 1689 datalen -= 2; 1690 } 1691 if (datalen > 0) { 1692 *data = HREAD1(hp, SDHC_DATA); 1693 data += 1; 1694 datalen -= 1; 1695 } 1696 } else if (((__uintptr_t)data & 1) == 0) { 1697 while (datalen > 1) { 1698 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1699 data += 2; 1700 datalen -= 2; 1701 } 1702 if (datalen > 0) { 1703 *data = HREAD1(hp, SDHC_DATA); 1704 data += 1; 1705 datalen -= 1; 1706 } 1707 } else { 1708 while (datalen > 0) { 1709 *data = HREAD1(hp, SDHC_DATA); 1710 data += 1; 1711 datalen -= 1; 1712 } 1713 } 1714 } 1715 1716 static void 1717 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1718 { 1719 1720 if (((__uintptr_t)data & 3) == 0) { 1721 while (datalen > 3) { 1722 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 1723 data += 4; 1724 datalen -= 4; 1725 } 1726 if (datalen > 1) { 1727 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1728 data += 2; 1729 datalen -= 2; 1730 } 1731 if (datalen > 0) { 1732 HWRITE1(hp, SDHC_DATA, *data); 1733 data += 1; 1734 datalen -= 1; 1735 } 1736 } else if (((__uintptr_t)data & 1) == 0) { 1737 while (datalen > 1) { 1738 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1739 data += 2; 1740 datalen -= 2; 1741 } 1742 if (datalen > 0) { 1743 HWRITE1(hp, SDHC_DATA, *data); 1744 data += 1; 1745 datalen -= 1; 1746 } 1747 } else { 1748 while (datalen > 0) { 1749 HWRITE1(hp, SDHC_DATA, *data); 1750 data += 1; 1751 datalen -= 1; 1752 } 1753 } 1754 } 1755 1756 static void 1757 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1758 { 1759 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1760 uint32_t v; 1761 1762 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1763 size_t count = 0; 1764 1765 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1766 if (count == 0) { 1767 /* 1768 * If we've drained "watermark" words, we need to wait 1769 * a little bit so the read FIFO can refill. 1770 */ 1771 sdmmc_delay(10); 1772 count = watermark; 1773 } 1774 v = HREAD4(hp, SDHC_DATA); 1775 v = le32toh(v); 1776 *(uint32_t *)data = v; 1777 data += 4; 1778 datalen -= 4; 1779 status = HREAD2(hp, SDHC_NINTR_STATUS); 1780 count--; 1781 } 1782 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1783 if (count == 0) { 1784 sdmmc_delay(10); 1785 } 1786 v = HREAD4(hp, SDHC_DATA); 1787 v = le32toh(v); 1788 do { 1789 *data++ = v; 1790 v >>= 8; 1791 } while (--datalen > 0); 1792 } 1793 } 1794 1795 static void 1796 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1797 { 1798 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1799 uint32_t v; 1800 1801 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1802 size_t count = watermark; 1803 1804 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1805 if (count == 0) { 1806 sdmmc_delay(10); 1807 count = watermark; 1808 } 1809 v = *(uint32_t *)data; 1810 v = htole32(v); 1811 HWRITE4(hp, SDHC_DATA, v); 1812 data += 4; 1813 datalen -= 4; 1814 status = HREAD2(hp, SDHC_NINTR_STATUS); 1815 count--; 1816 } 1817 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1818 if (count == 0) { 1819 sdmmc_delay(10); 1820 } 1821 v = *(uint32_t *)data; 1822 v = htole32(v); 1823 HWRITE4(hp, SDHC_DATA, v); 1824 } 1825 } 1826 1827 /* Prepare for another command. */ 1828 static int 1829 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1830 { 1831 int timo; 1832 1833 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1834 1835 /* Request the reset. */ 1836 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1837 1838 /* 1839 * If necessary, wait for the controller to set the bits to 1840 * acknowledge the reset. 1841 */ 1842 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 1843 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 1844 for (timo = 10000; timo > 0; timo--) { 1845 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1846 break; 1847 /* Short delay because I worry we may miss it... */ 1848 sdmmc_delay(1); 1849 } 1850 if (timo == 0) 1851 return ETIMEDOUT; 1852 } 1853 1854 /* 1855 * Wait for the controller to clear the bits to indicate that 1856 * the reset has completed. 1857 */ 1858 for (timo = 10; timo > 0; timo--) { 1859 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1860 break; 1861 sdmmc_delay(10000); 1862 } 1863 if (timo == 0) { 1864 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1865 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1866 return ETIMEDOUT; 1867 } 1868 1869 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1870 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1871 } 1872 1873 return 0; 1874 } 1875 1876 static int 1877 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1878 { 1879 int status; 1880 1881 KASSERT(mutex_owned(&hp->intr_lock)); 1882 1883 mask |= SDHC_ERROR_INTERRUPT; 1884 1885 status = hp->intr_status & mask; 1886 while (status == 0) { 1887 if (cv_timedwait(&hp->intr_cv, &hp->intr_lock, timo) 1888 == EWOULDBLOCK) { 1889 status |= SDHC_ERROR_INTERRUPT; 1890 break; 1891 } 1892 status = hp->intr_status & mask; 1893 } 1894 hp->intr_status &= ~status; 1895 1896 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1897 hp->intr_error_status)); 1898 1899 /* Command timeout has higher priority than command complete. */ 1900 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1901 hp->intr_error_status = 0; 1902 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1903 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1904 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1905 } 1906 status = 0; 1907 } 1908 1909 return status; 1910 } 1911 1912 /* 1913 * Established by attachment driver at interrupt priority IPL_SDMMC. 1914 */ 1915 int 1916 sdhc_intr(void *arg) 1917 { 1918 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1919 struct sdhc_host *hp; 1920 int done = 0; 1921 uint16_t status; 1922 uint16_t error; 1923 1924 /* We got an interrupt, but we don't know from which slot. */ 1925 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1926 hp = sc->sc_host[host]; 1927 if (hp == NULL) 1928 continue; 1929 1930 mutex_enter(&hp->intr_lock); 1931 1932 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1933 /* Find out which interrupts are pending. */ 1934 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1935 status = xstatus; 1936 error = xstatus >> 16; 1937 if (error) 1938 xstatus |= SDHC_ERROR_INTERRUPT; 1939 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1940 goto next_port; /* no interrupt for us */ 1941 /* Acknowledge the interrupts we are about to handle. */ 1942 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1943 } else { 1944 /* Find out which interrupts are pending. */ 1945 error = 0; 1946 status = HREAD2(hp, SDHC_NINTR_STATUS); 1947 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1948 goto next_port; /* no interrupt for us */ 1949 /* Acknowledge the interrupts we are about to handle. */ 1950 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1951 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1952 /* Acknowledge error interrupts. */ 1953 error = HREAD2(hp, SDHC_EINTR_STATUS); 1954 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1955 } 1956 } 1957 1958 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1959 status, error)); 1960 1961 /* Claim this interrupt. */ 1962 done = 1; 1963 1964 if (ISSET(error, SDHC_ADMA_ERROR)) { 1965 uint8_t adma_err = HREAD1(hp, SDHC_ADMA_ERROR_STATUS); 1966 printf("%s: ADMA error, status %02x\n", HDEVNAME(hp), 1967 adma_err); 1968 } 1969 1970 /* 1971 * Service error interrupts. 1972 */ 1973 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1974 SDHC_DATA_TIMEOUT_ERROR)) { 1975 hp->intr_error_status |= error; 1976 hp->intr_status |= status; 1977 cv_broadcast(&hp->intr_cv); 1978 } 1979 1980 /* 1981 * Wake up the sdmmc event thread to scan for cards. 1982 */ 1983 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1984 if (hp->sdmmc != NULL) { 1985 sdmmc_needs_discover(hp->sdmmc); 1986 } 1987 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1988 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1989 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1990 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1991 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1992 } 1993 } 1994 1995 /* 1996 * Wake up the blocking process to service command 1997 * related interrupt(s). 1998 */ 1999 if (ISSET(status, SDHC_COMMAND_COMPLETE| 2000 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 2001 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 2002 hp->intr_status |= status; 2003 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 2004 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 2005 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 2006 } 2007 cv_broadcast(&hp->intr_cv); 2008 } 2009 2010 /* 2011 * Service SD card interrupts. 2012 */ 2013 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 2014 && ISSET(status, SDHC_CARD_INTERRUPT)) { 2015 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 2016 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 2017 sdmmc_card_intr(hp->sdmmc); 2018 } 2019 next_port: 2020 mutex_exit(&hp->intr_lock); 2021 } 2022 2023 return done; 2024 } 2025 2026 kmutex_t * 2027 sdhc_host_lock(struct sdhc_host *hp) 2028 { 2029 return &hp->intr_lock; 2030 } 2031 2032 #ifdef SDHC_DEBUG 2033 void 2034 sdhc_dump_regs(struct sdhc_host *hp) 2035 { 2036 2037 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 2038 HREAD4(hp, SDHC_PRESENT_STATE)); 2039 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 2040 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 2041 HREAD1(hp, SDHC_POWER_CTL)); 2042 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 2043 HREAD2(hp, SDHC_NINTR_STATUS)); 2044 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 2045 HREAD2(hp, SDHC_EINTR_STATUS)); 2046 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 2047 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 2048 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 2049 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 2050 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 2051 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 2052 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 2053 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 2054 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 2055 HREAD4(hp, SDHC_CAPABILITIES)); 2056 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 2057 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 2058 } 2059 #endif 2060
Indexes created Thu Sep 25 08:09:54 GMT 2025