sdhc.c revision 1.78
1 /* $NetBSD: sdhc.c,v 1.78 2015/08/05 07:31:52 mlelstv Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.78 2015/08/05 07:31:52 mlelstv Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 40 #include <dev/sdmmc/sdhcreg.h> 41 #include <dev/sdmmc/sdhcvar.h> 42 #include <dev/sdmmc/sdmmcchip.h> 43 #include <dev/sdmmc/sdmmcreg.h> 44 #include <dev/sdmmc/sdmmcvar.h> 45 46 #ifdef SDHC_DEBUG 47 int sdhcdebug = 1; 48 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 49 void sdhc_dump_regs(struct sdhc_host *); 50 #else 51 #define DPRINTF(n,s) do {} while (0) 52 #endif 53 54 #define SDHC_COMMAND_TIMEOUT hz 55 #define SDHC_BUFFER_TIMEOUT hz 56 #define SDHC_TRANSFER_TIMEOUT hz 57 #define SDHC_DMA_TIMEOUT (hz*3) 58 59 struct sdhc_host { 60 struct sdhc_softc *sc; /* host controller device */ 61 62 bus_space_tag_t iot; /* host register set tag */ 63 bus_space_handle_t ioh; /* host register set handle */ 64 bus_size_t ios; /* host register space size */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 u_int clkbase; /* base clock frequency in KHz */ 70 int maxblklen; /* maximum block length */ 71 uint32_t ocr; /* OCR value from capabilities */ 72 73 uint8_t regs[14]; /* host controller state */ 74 75 uint16_t intr_status; /* soft interrupt status */ 76 uint16_t intr_error_status; /* soft error status */ 77 kmutex_t intr_lock; 78 kcondvar_t intr_cv; 79 80 int specver; /* spec. version */ 81 82 uint32_t flags; /* flags for this host */ 83 #define SHF_USE_DMA 0x0001 84 #define SHF_USE_4BIT_MODE 0x0002 85 #define SHF_USE_8BIT_MODE 0x0004 86 #define SHF_MODE_DMAEN 0x0008 /* needs SDHC_DMA_ENABLE in mode */ 87 #define SHF_USE_ADMA2_32 0x0010 88 #define SHF_USE_ADMA2_64 0x0020 89 #define SHF_USE_ADMA2_MASK 0x0030 90 91 bus_dmamap_t adma_map; 92 bus_dma_segment_t adma_segs[1]; 93 void *adma2; 94 }; 95 96 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 97 98 static uint8_t 99 hread1(struct sdhc_host *hp, bus_size_t reg) 100 { 101 102 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 103 return bus_space_read_1(hp->iot, hp->ioh, reg); 104 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 105 } 106 107 static uint16_t 108 hread2(struct sdhc_host *hp, bus_size_t reg) 109 { 110 111 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 112 return bus_space_read_2(hp->iot, hp->ioh, reg); 113 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 114 } 115 116 #define HREAD1(hp, reg) hread1(hp, reg) 117 #define HREAD2(hp, reg) hread2(hp, reg) 118 #define HREAD4(hp, reg) \ 119 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 120 121 122 static void 123 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 124 { 125 126 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 127 bus_space_write_1(hp->iot, hp->ioh, o, val); 128 } else { 129 const size_t shift = 8 * (o & 3); 130 o &= -4; 131 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 132 tmp = (val << shift) | (tmp & ~(0xff << shift)); 133 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 134 } 135 } 136 137 static void 138 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 139 { 140 141 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 142 bus_space_write_2(hp->iot, hp->ioh, o, val); 143 } else { 144 const size_t shift = 8 * (o & 2); 145 o &= -4; 146 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 147 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 148 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 149 } 150 } 151 152 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 153 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 154 #define HWRITE4(hp, reg, val) \ 155 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 156 157 #define HCLR1(hp, reg, bits) \ 158 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 159 #define HCLR2(hp, reg, bits) \ 160 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 161 #define HCLR4(hp, reg, bits) \ 162 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 163 #define HSET1(hp, reg, bits) \ 164 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 165 #define HSET2(hp, reg, bits) \ 166 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 167 #define HSET4(hp, reg, bits) \ 168 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 169 170 static int sdhc_host_reset(sdmmc_chipset_handle_t); 171 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 172 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 173 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 174 static int sdhc_card_detect(sdmmc_chipset_handle_t); 175 static int sdhc_write_protect(sdmmc_chipset_handle_t); 176 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 177 static int sdhc_bus_clock_ddr(sdmmc_chipset_handle_t, int, bool); 178 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 179 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 180 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 181 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 182 static void sdhc_exec_command(sdmmc_chipset_handle_t, 183 struct sdmmc_command *); 184 static int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 185 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 186 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 187 static int sdhc_soft_reset(struct sdhc_host *, int); 188 static int sdhc_wait_intr(struct sdhc_host *, int, int); 189 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 190 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 191 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 192 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 193 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 194 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 195 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 196 197 static struct sdmmc_chip_functions sdhc_functions = { 198 /* host controller reset */ 199 .host_reset = sdhc_host_reset, 200 201 /* host controller capabilities */ 202 .host_ocr = sdhc_host_ocr, 203 .host_maxblklen = sdhc_host_maxblklen, 204 205 /* card detection */ 206 .card_detect = sdhc_card_detect, 207 208 /* write protect */ 209 .write_protect = sdhc_write_protect, 210 211 /* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */ 212 .bus_power = sdhc_bus_power, 213 .bus_clock = NULL, /* see sdhc_bus_clock_ddr */ 214 .bus_width = sdhc_bus_width, 215 .bus_rod = sdhc_bus_rod, 216 217 /* command execution */ 218 .exec_command = sdhc_exec_command, 219 220 /* card interrupt */ 221 .card_enable_intr = sdhc_card_enable_intr, 222 .card_intr_ack = sdhc_card_intr_ack, 223 224 /* UHS functions */ 225 .signal_voltage = sdhc_signal_voltage, 226 .bus_clock_ddr = sdhc_bus_clock_ddr, 227 }; 228 229 static int 230 sdhc_cfprint(void *aux, const char *pnp) 231 { 232 const struct sdmmcbus_attach_args * const saa = aux; 233 const struct sdhc_host * const hp = saa->saa_sch; 234 235 if (pnp) { 236 aprint_normal("sdmmc at %s", pnp); 237 } 238 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 239 if (hp->sc->sc_host[host] == hp) { 240 aprint_normal(" slot %zu", host); 241 } 242 } 243 244 return UNCONF; 245 } 246 247 /* 248 * Called by attachment driver. For each SD card slot there is one SD 249 * host controller standard register set. (1.3) 250 */ 251 int 252 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 253 bus_space_handle_t ioh, bus_size_t iosize) 254 { 255 struct sdmmcbus_attach_args saa; 256 struct sdhc_host *hp; 257 uint32_t caps, caps2; 258 uint16_t sdhcver; 259 int error; 260 261 /* Allocate one more host structure. */ 262 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 263 if (hp == NULL) { 264 aprint_error_dev(sc->sc_dev, 265 "couldn't alloc memory (sdhc host)\n"); 266 goto err1; 267 } 268 sc->sc_host[sc->sc_nhosts++] = hp; 269 270 /* Fill in the new host structure. */ 271 hp->sc = sc; 272 hp->iot = iot; 273 hp->ioh = ioh; 274 hp->ios = iosize; 275 hp->dmat = sc->sc_dmat; 276 277 mutex_init(&hp->intr_lock, MUTEX_DEFAULT, IPL_SDMMC); 278 cv_init(&hp->intr_cv, "sdhcintr"); 279 280 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 281 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); 282 } else { 283 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 284 } 285 aprint_normal_dev(sc->sc_dev, "SDHC "); 286 hp->specver = SDHC_SPEC_VERSION(sdhcver); 287 switch (SDHC_SPEC_VERSION(sdhcver)) { 288 case SDHC_SPEC_VERS_100: 289 aprint_normal("1.0"); 290 break; 291 292 case SDHC_SPEC_VERS_200: 293 aprint_normal("2.0"); 294 break; 295 296 case SDHC_SPEC_VERS_300: 297 aprint_normal("3.0"); 298 break; 299 300 case SDHC_SPEC_VERS_400: 301 aprint_normal("4.0"); 302 break; 303 304 default: 305 aprint_normal("unknown version(0x%x)", 306 SDHC_SPEC_VERSION(sdhcver)); 307 break; 308 } 309 aprint_normal(", rev %u", SDHC_VENDOR_VERSION(sdhcver)); 310 311 /* 312 * Reset the host controller and enable interrupts. 313 */ 314 (void)sdhc_host_reset(hp); 315 316 /* Determine host capabilities. */ 317 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 318 caps = sc->sc_caps; 319 caps2 = sc->sc_caps2; 320 } else { 321 caps = HREAD4(hp, SDHC_CAPABILITIES); 322 if (hp->specver >= SDHC_SPEC_VERS_300) { 323 caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 324 } else { 325 caps2 = 0; 326 } 327 } 328 329 /* 330 * Use DMA if the host system and the controller support it. 331 * Suports integrated or external DMA egine, with or without 332 * SDHC_DMA_ENABLE in the command. 333 */ 334 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 335 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 336 ISSET(caps, SDHC_DMA_SUPPORT)))) { 337 SET(hp->flags, SHF_USE_DMA); 338 339 if (ISSET(sc->sc_flags, SDHC_FLAG_USE_ADMA2) && 340 ISSET(caps, SDHC_ADMA2_SUPP)) { 341 SET(hp->flags, SHF_MODE_DMAEN); 342 /* 343 * 64-bit mode was present in the 2.00 spec, removed 344 * from 3.00, and re-added in 4.00 with a different 345 * descriptor layout. We only support 2.00 and 3.00 346 * descriptors for now. 347 */ 348 if (hp->specver == SDHC_SPEC_VERS_200 && 349 ISSET(caps, SDHC_64BIT_SYS_BUS)) { 350 SET(hp->flags, SHF_USE_ADMA2_64); 351 aprint_normal(", 64-bit ADMA2"); 352 } else { 353 SET(hp->flags, SHF_USE_ADMA2_32); 354 aprint_normal(", 32-bit ADMA2"); 355 } 356 } else { 357 if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) || 358 ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN)) 359 SET(hp->flags, SHF_MODE_DMAEN); 360 if (sc->sc_vendor_transfer_data_dma) { 361 aprint_normal(", platform DMA"); 362 } else { 363 aprint_normal(", SDMA"); 364 } 365 } 366 } else { 367 aprint_normal(", PIO"); 368 } 369 370 /* 371 * Determine the base clock frequency. (2.2.24) 372 */ 373 if (hp->specver >= SDHC_SPEC_VERS_300) { 374 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 375 } else { 376 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 377 } 378 if (hp->clkbase == 0 || 379 ISSET(sc->sc_flags, SDHC_FLAG_NO_CLKBASE)) { 380 if (sc->sc_clkbase == 0) { 381 /* The attachment driver must tell us. */ 382 aprint_error_dev(sc->sc_dev, 383 "unknown base clock frequency\n"); 384 goto err; 385 } 386 hp->clkbase = sc->sc_clkbase; 387 } 388 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 389 /* SDHC 1.0 supports only 10-63 MHz. */ 390 aprint_error_dev(sc->sc_dev, 391 "base clock frequency out of range: %u MHz\n", 392 hp->clkbase / 1000); 393 goto err; 394 } 395 aprint_normal(", %u kHz", hp->clkbase); 396 397 /* 398 * XXX Set the data timeout counter value according to 399 * capabilities. (2.2.15) 400 */ 401 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 402 #if 1 403 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 404 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 405 #endif 406 407 if (ISSET(caps, SDHC_EMBEDDED_SLOT)) 408 aprint_normal(", embedded slot"); 409 410 /* 411 * Determine SD bus voltage levels supported by the controller. 412 */ 413 aprint_normal(","); 414 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) { 415 SET(hp->ocr, MMC_OCR_HCS); 416 aprint_normal(" HS"); 417 } 418 if (ISSET(caps2, SDHC_SDR50_SUPP)) { 419 SET(hp->ocr, MMC_OCR_S18A); 420 aprint_normal(" SDR50"); 421 } 422 if (ISSET(caps2, SDHC_DDR50_SUPP)) { 423 SET(hp->ocr, MMC_OCR_S18A); 424 aprint_normal(" DDR50"); 425 } 426 if (ISSET(caps2, SDHC_SDR104_SUPP)) { 427 SET(hp->ocr, MMC_OCR_S18A); 428 aprint_normal(" SDR104 HS200"); 429 } 430 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 431 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 432 aprint_normal(" 1.8V"); 433 } 434 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 435 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 436 aprint_normal(" 3.0V"); 437 } 438 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 439 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 440 aprint_normal(" 3.3V"); 441 } 442 443 /* 444 * Determine the maximum block length supported by the host 445 * controller. (2.2.24) 446 */ 447 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 448 case SDHC_MAX_BLK_LEN_512: 449 hp->maxblklen = 512; 450 break; 451 452 case SDHC_MAX_BLK_LEN_1024: 453 hp->maxblklen = 1024; 454 break; 455 456 case SDHC_MAX_BLK_LEN_2048: 457 hp->maxblklen = 2048; 458 break; 459 460 case SDHC_MAX_BLK_LEN_4096: 461 hp->maxblklen = 4096; 462 break; 463 464 default: 465 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 466 goto err; 467 } 468 aprint_normal(", %u byte blocks", hp->maxblklen); 469 aprint_normal("\n"); 470 471 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 472 int rseg; 473 474 /* Allocate ADMA2 descriptor memory */ 475 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 476 PAGE_SIZE, hp->adma_segs, 1, &rseg, BUS_DMA_WAITOK); 477 if (error) { 478 aprint_error_dev(sc->sc_dev, 479 "ADMA2 dmamem_alloc failed (%d)\n", error); 480 goto adma_done; 481 } 482 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 483 PAGE_SIZE, (void **)&hp->adma2, BUS_DMA_WAITOK); 484 if (error) { 485 aprint_error_dev(sc->sc_dev, 486 "ADMA2 dmamem_map failed (%d)\n", error); 487 goto adma_done; 488 } 489 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 490 0, BUS_DMA_WAITOK, &hp->adma_map); 491 if (error) { 492 aprint_error_dev(sc->sc_dev, 493 "ADMA2 dmamap_create failed (%d)\n", error); 494 goto adma_done; 495 } 496 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 497 hp->adma2, PAGE_SIZE, NULL, 498 BUS_DMA_WAITOK|BUS_DMA_WRITE); 499 if (error) { 500 aprint_error_dev(sc->sc_dev, 501 "ADMA2 dmamap_load failed (%d)\n", error); 502 goto adma_done; 503 } 504 505 memset(hp->adma2, 0, PAGE_SIZE); 506 507 adma_done: 508 if (error) 509 CLR(hp->flags, SHF_USE_ADMA2_MASK); 510 } 511 512 /* 513 * Attach the generic SD/MMC bus driver. (The bus driver must 514 * not invoke any chipset functions before it is attached.) 515 */ 516 memset(&saa, 0, sizeof(saa)); 517 saa.saa_busname = "sdmmc"; 518 saa.saa_sct = &sdhc_functions; 519 saa.saa_sch = hp; 520 saa.saa_dmat = hp->dmat; 521 saa.saa_clkmax = hp->clkbase; 522 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 523 saa.saa_clkmin = hp->clkbase / 256 / 2046; 524 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 525 saa.saa_clkmin = hp->clkbase / 256 / 16; 526 else if (hp->sc->sc_clkmsk != 0) 527 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 528 (ffs(hp->sc->sc_clkmsk) - 1)); 529 else if (hp->specver >= SDHC_SPEC_VERS_300) 530 saa.saa_clkmin = hp->clkbase / 0x3ff; 531 else 532 saa.saa_clkmin = hp->clkbase / 256; 533 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 534 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 535 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 536 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 537 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 538 if (ISSET(caps2, SDHC_SDR104_SUPP)) 539 saa.saa_caps |= SMC_CAPS_UHS_SDR104 | 540 SMC_CAPS_UHS_SDR50 | 541 SMC_CAPS_MMC_HS200; 542 if (ISSET(caps2, SDHC_SDR50_SUPP)) 543 saa.saa_caps |= SMC_CAPS_UHS_SDR50; 544 if (ISSET(caps2, SDHC_DDR50_SUPP)) 545 saa.saa_caps |= SMC_CAPS_UHS_DDR50; 546 if (ISSET(hp->flags, SHF_USE_DMA)) { 547 saa.saa_caps |= SMC_CAPS_DMA; 548 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 549 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 550 } 551 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 552 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 553 if (ISSET(sc->sc_flags, SDHC_FLAG_POLL_CARD_DET)) 554 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 555 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 556 557 return 0; 558 559 err: 560 cv_destroy(&hp->intr_cv); 561 mutex_destroy(&hp->intr_lock); 562 free(hp, M_DEVBUF); 563 sc->sc_host[--sc->sc_nhosts] = NULL; 564 err1: 565 return 1; 566 } 567 568 int 569 sdhc_detach(struct sdhc_softc *sc, int flags) 570 { 571 struct sdhc_host *hp; 572 int rv = 0; 573 574 for (size_t n = 0; n < sc->sc_nhosts; n++) { 575 hp = sc->sc_host[n]; 576 if (hp == NULL) 577 continue; 578 if (hp->sdmmc != NULL) { 579 rv = config_detach(hp->sdmmc, flags); 580 if (rv) 581 break; 582 hp->sdmmc = NULL; 583 } 584 /* disable interrupts */ 585 if ((flags & DETACH_FORCE) == 0) { 586 mutex_enter(&hp->intr_lock); 587 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 588 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 589 } else { 590 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 591 } 592 sdhc_soft_reset(hp, SDHC_RESET_ALL); 593 mutex_exit(&hp->intr_lock); 594 } 595 cv_destroy(&hp->intr_cv); 596 mutex_destroy(&hp->intr_lock); 597 if (hp->ios > 0) { 598 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 599 hp->ios = 0; 600 } 601 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 602 bus_dmamap_unload(sc->sc_dmat, hp->adma_map); 603 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 604 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 605 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, 1); 606 } 607 free(hp, M_DEVBUF); 608 sc->sc_host[n] = NULL; 609 } 610 611 return rv; 612 } 613 614 bool 615 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 616 { 617 struct sdhc_softc *sc = device_private(dev); 618 struct sdhc_host *hp; 619 size_t i; 620 621 /* XXX poll for command completion or suspend command 622 * in progress */ 623 624 /* Save the host controller state. */ 625 for (size_t n = 0; n < sc->sc_nhosts; n++) { 626 hp = sc->sc_host[n]; 627 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 628 for (i = 0; i < sizeof hp->regs; i += 4) { 629 uint32_t v = HREAD4(hp, i); 630 hp->regs[i + 0] = (v >> 0); 631 hp->regs[i + 1] = (v >> 8); 632 if (i + 3 < sizeof hp->regs) { 633 hp->regs[i + 2] = (v >> 16); 634 hp->regs[i + 3] = (v >> 24); 635 } 636 } 637 } else { 638 for (i = 0; i < sizeof hp->regs; i++) { 639 hp->regs[i] = HREAD1(hp, i); 640 } 641 } 642 } 643 return true; 644 } 645 646 bool 647 sdhc_resume(device_t dev, const pmf_qual_t *qual) 648 { 649 struct sdhc_softc *sc = device_private(dev); 650 struct sdhc_host *hp; 651 size_t i; 652 653 /* Restore the host controller state. */ 654 for (size_t n = 0; n < sc->sc_nhosts; n++) { 655 hp = sc->sc_host[n]; 656 (void)sdhc_host_reset(hp); 657 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 658 for (i = 0; i < sizeof hp->regs; i += 4) { 659 if (i + 3 < sizeof hp->regs) { 660 HWRITE4(hp, i, 661 (hp->regs[i + 0] << 0) 662 | (hp->regs[i + 1] << 8) 663 | (hp->regs[i + 2] << 16) 664 | (hp->regs[i + 3] << 24)); 665 } else { 666 HWRITE4(hp, i, 667 (hp->regs[i + 0] << 0) 668 | (hp->regs[i + 1] << 8)); 669 } 670 } 671 } else { 672 for (i = 0; i < sizeof hp->regs; i++) { 673 HWRITE1(hp, i, hp->regs[i]); 674 } 675 } 676 } 677 return true; 678 } 679 680 bool 681 sdhc_shutdown(device_t dev, int flags) 682 { 683 struct sdhc_softc *sc = device_private(dev); 684 struct sdhc_host *hp; 685 686 /* XXX chip locks up if we don't disable it before reboot. */ 687 for (size_t i = 0; i < sc->sc_nhosts; i++) { 688 hp = sc->sc_host[i]; 689 (void)sdhc_host_reset(hp); 690 } 691 return true; 692 } 693 694 /* 695 * Reset the host controller. Called during initialization, when 696 * cards are removed, upon resume, and during error recovery. 697 */ 698 static int 699 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 700 { 701 struct sdhc_host *hp = (struct sdhc_host *)sch; 702 uint32_t sdhcimask; 703 int error; 704 705 KASSERT(mutex_owned(&hp->intr_lock)); 706 707 /* Disable all interrupts. */ 708 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 709 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 710 } else { 711 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 712 } 713 714 /* 715 * Reset the entire host controller and wait up to 100ms for 716 * the controller to clear the reset bit. 717 */ 718 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 719 if (error) 720 goto out; 721 722 /* Set data timeout counter value to max for now. */ 723 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 724 #if 1 725 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 726 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 727 #endif 728 729 /* Enable interrupts. */ 730 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 731 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 732 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 733 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 734 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 735 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 736 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 737 sdhcimask ^= 738 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 739 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 740 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 741 } else { 742 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 743 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 744 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 745 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 746 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 747 } 748 749 out: 750 return error; 751 } 752 753 static int 754 sdhc_host_reset(sdmmc_chipset_handle_t sch) 755 { 756 struct sdhc_host *hp = (struct sdhc_host *)sch; 757 int error; 758 759 mutex_enter(&hp->intr_lock); 760 error = sdhc_host_reset1(sch); 761 mutex_exit(&hp->intr_lock); 762 763 return error; 764 } 765 766 static uint32_t 767 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 768 { 769 struct sdhc_host *hp = (struct sdhc_host *)sch; 770 771 return hp->ocr; 772 } 773 774 static int 775 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 776 { 777 struct sdhc_host *hp = (struct sdhc_host *)sch; 778 779 return hp->maxblklen; 780 } 781 782 /* 783 * Return non-zero if the card is currently inserted. 784 */ 785 static int 786 sdhc_card_detect(sdmmc_chipset_handle_t sch) 787 { 788 struct sdhc_host *hp = (struct sdhc_host *)sch; 789 int r; 790 791 if (hp->sc->sc_vendor_card_detect) 792 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 793 794 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 795 796 return r ? 1 : 0; 797 } 798 799 /* 800 * Return non-zero if the card is currently write-protected. 801 */ 802 static int 803 sdhc_write_protect(sdmmc_chipset_handle_t sch) 804 { 805 struct sdhc_host *hp = (struct sdhc_host *)sch; 806 int r; 807 808 if (hp->sc->sc_vendor_write_protect) 809 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 810 811 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 812 813 return r ? 0 : 1; 814 } 815 816 /* 817 * Set or change SD bus voltage and enable or disable SD bus power. 818 * Return zero on success. 819 */ 820 static int 821 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 822 { 823 struct sdhc_host *hp = (struct sdhc_host *)sch; 824 uint8_t vdd; 825 int error = 0; 826 const uint32_t pcmask = 827 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 828 829 mutex_enter(&hp->intr_lock); 830 831 /* 832 * Disable bus power before voltage change. 833 */ 834 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 835 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 836 HWRITE1(hp, SDHC_POWER_CTL, 0); 837 838 /* If power is disabled, reset the host and return now. */ 839 if (ocr == 0) { 840 (void)sdhc_host_reset1(hp); 841 goto out; 842 } 843 844 /* 845 * Select the lowest voltage according to capabilities. 846 */ 847 ocr &= hp->ocr; 848 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 849 vdd = SDHC_VOLTAGE_1_8V; 850 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 851 vdd = SDHC_VOLTAGE_3_0V; 852 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 853 vdd = SDHC_VOLTAGE_3_3V; 854 } else { 855 /* Unsupported voltage level requested. */ 856 error = EINVAL; 857 goto out; 858 } 859 860 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 861 /* 862 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 863 * voltage ramp until power rises. 864 */ 865 866 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SINGLE_POWER_WRITE)) { 867 HWRITE1(hp, SDHC_POWER_CTL, 868 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 869 } else { 870 HWRITE1(hp, SDHC_POWER_CTL, 871 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 872 sdmmc_delay(1); 873 HWRITE1(hp, SDHC_POWER_CTL, 874 (vdd << SDHC_VOLTAGE_SHIFT)); 875 sdmmc_delay(1); 876 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 877 sdmmc_delay(10000); 878 } 879 880 /* 881 * The host system may not power the bus due to battery low, 882 * etc. In that case, the host controller should clear the 883 * bus power bit. 884 */ 885 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 886 error = ENXIO; 887 goto out; 888 } 889 } 890 891 out: 892 mutex_exit(&hp->intr_lock); 893 894 return error; 895 } 896 897 /* 898 * Return the smallest possible base clock frequency divisor value 899 * for the CLOCK_CTL register to produce `freq' (KHz). 900 */ 901 static bool 902 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 903 { 904 u_int div; 905 906 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 907 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 908 if ((hp->clkbase / div) <= freq) { 909 *divp = SDHC_SDCLK_CGM 910 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 911 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 912 //freq = hp->clkbase / div; 913 return true; 914 } 915 } 916 /* No divisor found. */ 917 return false; 918 } 919 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 920 u_int dvs = (hp->clkbase + freq - 1) / freq; 921 u_int roundup = dvs & 1; 922 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 923 if (dvs + roundup <= 16) { 924 dvs += roundup - 1; 925 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 926 | (dvs << SDHC_SDCLK_DVS_SHIFT); 927 DPRINTF(2, 928 ("%s: divisor for freq %u is %u * %u\n", 929 HDEVNAME(hp), freq, div * 2, dvs + 1)); 930 //freq = hp->clkbase / (div * 2) * (dvs + 1); 931 return true; 932 } 933 /* 934 * If we drop bits, we need to round up the divisor. 935 */ 936 roundup |= dvs & 1; 937 } 938 /* No divisor found. */ 939 return false; 940 } 941 if (hp->sc->sc_clkmsk != 0) { 942 div = howmany(hp->clkbase, freq); 943 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 944 return false; 945 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 946 //freq = hp->clkbase / div; 947 return true; 948 } 949 if (hp->specver >= SDHC_SPEC_VERS_300) { 950 div = howmany(hp->clkbase, freq); 951 div = div > 1 ? howmany(div, 2) : 0; 952 if (div > 0x3ff) 953 return false; 954 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 955 << SDHC_SDCLK_XDIV_SHIFT) | 956 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 957 << SDHC_SDCLK_DIV_SHIFT); 958 //freq = hp->clkbase / (div ? div * 2 : 1); 959 return true; 960 } else { 961 for (div = 1; div <= 256; div *= 2) { 962 if ((hp->clkbase / div) <= freq) { 963 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 964 //freq = hp->clkbase / div; 965 return true; 966 } 967 } 968 /* No divisor found. */ 969 return false; 970 } 971 /* No divisor found. */ 972 return false; 973 } 974 975 /* 976 * Set or change SDCLK frequency or disable the SD clock. 977 * Return zero on success. 978 */ 979 static int 980 sdhc_bus_clock_ddr(sdmmc_chipset_handle_t sch, int freq, bool ddr) 981 { 982 struct sdhc_host *hp = (struct sdhc_host *)sch; 983 u_int div; 984 u_int timo; 985 int16_t reg; 986 int error = 0; 987 bool present __diagused; 988 989 mutex_enter(&hp->intr_lock); 990 991 #ifdef DIAGNOSTIC 992 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 993 994 /* Must not stop the clock if commands are in progress. */ 995 if (present && sdhc_card_detect(hp)) { 996 aprint_normal_dev(hp->sc->sc_dev, 997 "%s: command in progress\n", __func__); 998 } 999 #endif 1000 1001 if (hp->sc->sc_vendor_bus_clock) { 1002 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 1003 if (error != 0) 1004 goto out; 1005 } 1006 1007 /* 1008 * Stop SD clock before changing the frequency. 1009 */ 1010 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1011 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 1012 if (freq == SDMMC_SDCLK_OFF) { 1013 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 1014 goto out; 1015 } 1016 } else { 1017 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1018 if (freq == SDMMC_SDCLK_OFF) 1019 goto out; 1020 } 1021 1022 if (hp->specver >= SDHC_SPEC_VERS_300) { 1023 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 1024 if (freq > 100000) { 1025 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR104); 1026 } else if (freq > 50000) { 1027 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR50); 1028 } else if (freq > 25000) { 1029 if (ddr) { 1030 HSET2(hp, SDHC_HOST_CTL2, 1031 SDHC_UHS_MODE_SELECT_DDR50); 1032 } else { 1033 HSET2(hp, SDHC_HOST_CTL2, 1034 SDHC_UHS_MODE_SELECT_SDR25); 1035 } 1036 } else if (freq > 400) { 1037 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR12); 1038 } 1039 } 1040 1041 /* 1042 * Set the minimum base clock frequency divisor. 1043 */ 1044 if (!sdhc_clock_divisor(hp, freq, &div)) { 1045 /* Invalid base clock frequency or `freq' value. */ 1046 aprint_error_dev(hp->sc->sc_dev, 1047 "Invalid bus clock %d kHz\n", freq); 1048 error = EINVAL; 1049 goto out; 1050 } 1051 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1052 HWRITE4(hp, SDHC_CLOCK_CTL, 1053 div | (SDHC_TIMEOUT_MAX << 16)); 1054 } else { 1055 reg = HREAD2(hp, SDHC_CLOCK_CTL); 1056 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 1057 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 1058 } 1059 1060 /* 1061 * Start internal clock. Wait 10ms for stabilization. 1062 */ 1063 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1064 sdmmc_delay(10000); 1065 HSET4(hp, SDHC_CLOCK_CTL, 1066 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 1067 } else { 1068 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 1069 for (timo = 1000; timo > 0; timo--) { 1070 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 1071 SDHC_INTCLK_STABLE)) 1072 break; 1073 sdmmc_delay(10); 1074 } 1075 if (timo == 0) { 1076 error = ETIMEDOUT; 1077 goto out; 1078 } 1079 } 1080 1081 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1082 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 1083 /* 1084 * Sending 80 clocks at 400kHz takes 200us. 1085 * So delay for that time + slop and then 1086 * check a few times for completion. 1087 */ 1088 sdmmc_delay(210); 1089 for (timo = 10; timo > 0; timo--) { 1090 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 1091 SDHC_INIT_ACTIVE)) 1092 break; 1093 sdmmc_delay(10); 1094 } 1095 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 1096 1097 /* 1098 * Enable SD clock. 1099 */ 1100 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1101 } else { 1102 /* 1103 * Enable SD clock. 1104 */ 1105 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1106 1107 if (freq > 25000 && 1108 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 1109 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1110 else 1111 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1112 } 1113 1114 out: 1115 mutex_exit(&hp->intr_lock); 1116 1117 return error; 1118 } 1119 1120 static int 1121 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 1122 { 1123 struct sdhc_host *hp = (struct sdhc_host *)sch; 1124 int reg; 1125 1126 switch (width) { 1127 case 1: 1128 case 4: 1129 break; 1130 1131 case 8: 1132 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 1133 break; 1134 /* FALLTHROUGH */ 1135 default: 1136 DPRINTF(0,("%s: unsupported bus width (%d)\n", 1137 HDEVNAME(hp), width)); 1138 return 1; 1139 } 1140 1141 mutex_enter(&hp->intr_lock); 1142 1143 reg = HREAD1(hp, SDHC_HOST_CTL); 1144 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1145 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 1146 if (width == 4) 1147 reg |= SDHC_4BIT_MODE; 1148 else if (width == 8) 1149 reg |= SDHC_ESDHC_8BIT_MODE; 1150 } else { 1151 reg &= ~SDHC_4BIT_MODE; 1152 if (hp->specver >= SDHC_SPEC_VERS_300) { 1153 reg &= ~SDHC_8BIT_MODE; 1154 } 1155 if (width == 4) { 1156 reg |= SDHC_4BIT_MODE; 1157 } else if (width == 8 && hp->specver >= SDHC_SPEC_VERS_300) { 1158 reg |= SDHC_8BIT_MODE; 1159 } 1160 } 1161 HWRITE1(hp, SDHC_HOST_CTL, reg); 1162 1163 mutex_exit(&hp->intr_lock); 1164 1165 return 0; 1166 } 1167 1168 static int 1169 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1170 { 1171 struct sdhc_host *hp = (struct sdhc_host *)sch; 1172 1173 if (hp->sc->sc_vendor_rod) 1174 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1175 1176 return 0; 1177 } 1178 1179 static void 1180 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1181 { 1182 struct sdhc_host *hp = (struct sdhc_host *)sch; 1183 1184 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1185 mutex_enter(&hp->intr_lock); 1186 if (enable) { 1187 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1188 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1189 } else { 1190 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1191 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1192 } 1193 mutex_exit(&hp->intr_lock); 1194 } 1195 } 1196 1197 static void 1198 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1199 { 1200 struct sdhc_host *hp = (struct sdhc_host *)sch; 1201 1202 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1203 mutex_enter(&hp->intr_lock); 1204 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1205 mutex_exit(&hp->intr_lock); 1206 } 1207 } 1208 1209 static int 1210 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 1211 { 1212 struct sdhc_host *hp = (struct sdhc_host *)sch; 1213 1214 mutex_enter(&hp->intr_lock); 1215 switch (signal_voltage) { 1216 case SDMMC_SIGNAL_VOLTAGE_180: 1217 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1218 break; 1219 case SDMMC_SIGNAL_VOLTAGE_330: 1220 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1221 break; 1222 default: 1223 return EINVAL; 1224 } 1225 mutex_exit(&hp->intr_lock); 1226 1227 return 0; 1228 } 1229 1230 static int 1231 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1232 { 1233 uint32_t state; 1234 int timeout; 1235 1236 for (timeout = 10000; timeout > 0; timeout--) { 1237 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 1238 return 0; 1239 sdmmc_delay(10); 1240 } 1241 aprint_error_dev(hp->sc->sc_dev, "timeout waiting for mask %#x value %#x (state=%#x)\n", 1242 mask, value, state); 1243 return ETIMEDOUT; 1244 } 1245 1246 static void 1247 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1248 { 1249 struct sdhc_host *hp = (struct sdhc_host *)sch; 1250 int error; 1251 1252 mutex_enter(&hp->intr_lock); 1253 1254 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1255 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1256 if (ISSET(hp->flags, SHF_USE_DMA)) { 1257 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1258 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1259 } else { 1260 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1261 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1262 } 1263 } 1264 1265 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_TIMEOUT)) { 1266 const uint16_t eintr = SDHC_CMD_TIMEOUT_ERROR; 1267 if (cmd->c_data != NULL) { 1268 HCLR2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1269 HCLR2(hp, SDHC_EINTR_STATUS_EN, eintr); 1270 } else { 1271 HSET2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1272 HSET2(hp, SDHC_EINTR_STATUS_EN, eintr); 1273 } 1274 } 1275 1276 /* 1277 * Start the MMC command, or mark `cmd' as failed and return. 1278 */ 1279 error = sdhc_start_command(hp, cmd); 1280 if (error) { 1281 cmd->c_error = error; 1282 goto out; 1283 } 1284 1285 /* 1286 * Wait until the command phase is done, or until the command 1287 * is marked done for any other reason. 1288 */ 1289 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1290 cmd->c_error = ETIMEDOUT; 1291 goto out; 1292 } 1293 1294 /* 1295 * The host controller removes bits [0:7] from the response 1296 * data (CRC) and we pass the data up unchanged to the bus 1297 * driver (without padding). 1298 */ 1299 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1300 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1301 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1302 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1303 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1304 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1305 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1306 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1307 (cmd->c_resp[1] << 24); 1308 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1309 (cmd->c_resp[2] << 24); 1310 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1311 (cmd->c_resp[3] << 24); 1312 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1313 } 1314 } 1315 } 1316 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1317 1318 /* 1319 * If the command has data to transfer in any direction, 1320 * execute the transfer now. 1321 */ 1322 if (cmd->c_error == 0 && cmd->c_data != NULL) 1323 sdhc_transfer_data(hp, cmd); 1324 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1325 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10)) { 1326 cmd->c_error = ETIMEDOUT; 1327 goto out; 1328 } 1329 } 1330 1331 out: 1332 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1333 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1334 /* Turn off the LED. */ 1335 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1336 } 1337 SET(cmd->c_flags, SCF_ITSDONE); 1338 1339 mutex_exit(&hp->intr_lock); 1340 1341 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1342 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1343 cmd->c_flags, cmd->c_error)); 1344 } 1345 1346 static int 1347 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1348 { 1349 struct sdhc_softc * const sc = hp->sc; 1350 uint16_t blksize = 0; 1351 uint16_t blkcount = 0; 1352 uint16_t mode; 1353 uint16_t command; 1354 int error; 1355 1356 KASSERT(mutex_owned(&hp->intr_lock)); 1357 1358 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1359 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1360 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1361 1362 /* 1363 * The maximum block length for commands should be the minimum 1364 * of the host buffer size and the card buffer size. (1.7.2) 1365 */ 1366 1367 /* Fragment the data into proper blocks. */ 1368 if (cmd->c_datalen > 0) { 1369 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1370 blkcount = cmd->c_datalen / blksize; 1371 if (cmd->c_datalen % blksize > 0) { 1372 /* XXX: Split this command. (1.7.4) */ 1373 aprint_error_dev(sc->sc_dev, 1374 "data not a multiple of %u bytes\n", blksize); 1375 return EINVAL; 1376 } 1377 } 1378 1379 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1380 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1381 aprint_error_dev(sc->sc_dev, "too much data\n"); 1382 return EINVAL; 1383 } 1384 1385 /* Prepare transfer mode register value. (2.2.5) */ 1386 mode = SDHC_BLOCK_COUNT_ENABLE; 1387 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1388 mode |= SDHC_READ_MODE; 1389 if (blkcount > 1) { 1390 mode |= SDHC_MULTI_BLOCK_MODE; 1391 /* XXX only for memory commands? */ 1392 mode |= SDHC_AUTO_CMD12_ENABLE; 1393 } 1394 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1395 ISSET(hp->flags, SHF_MODE_DMAEN)) { 1396 mode |= SDHC_DMA_ENABLE; 1397 } 1398 1399 /* 1400 * Prepare command register value. (2.2.6) 1401 */ 1402 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1403 1404 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1405 command |= SDHC_CRC_CHECK_ENABLE; 1406 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1407 command |= SDHC_INDEX_CHECK_ENABLE; 1408 if (cmd->c_data != NULL) 1409 command |= SDHC_DATA_PRESENT_SELECT; 1410 1411 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1412 command |= SDHC_NO_RESPONSE; 1413 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1414 command |= SDHC_RESP_LEN_136; 1415 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1416 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1417 else 1418 command |= SDHC_RESP_LEN_48; 1419 1420 /* Wait until command and data inhibit bits are clear. (1.5) */ 1421 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1422 if (error) { 1423 aprint_error_dev(sc->sc_dev, "command or data phase inhibited\n"); 1424 return error; 1425 } 1426 1427 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1428 HDEVNAME(hp), blksize, blkcount, mode, command)); 1429 1430 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1431 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1432 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1433 } 1434 1435 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1436 /* Alert the user not to remove the card. */ 1437 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1438 } 1439 1440 /* Set DMA start address. */ 1441 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK) && cmd->c_datalen > 0) { 1442 for (int seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 1443 bus_addr_t paddr = 1444 cmd->c_dmamap->dm_segs[seg].ds_addr; 1445 uint16_t len = 1446 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1447 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1448 uint16_t attr = 1449 SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1450 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 1451 attr |= SDHC_ADMA2_END; 1452 } 1453 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1454 struct sdhc_adma2_descriptor32 *desc = 1455 hp->adma2; 1456 desc[seg].attribute = htole16(attr); 1457 desc[seg].length = htole16(len); 1458 desc[seg].address = htole32(paddr); 1459 } else { 1460 struct sdhc_adma2_descriptor64 *desc = 1461 hp->adma2; 1462 desc[seg].attribute = htole16(attr); 1463 desc[seg].length = htole16(len); 1464 desc[seg].address = htole32(paddr & 0xffffffff); 1465 desc[seg].address_hi = htole32( 1466 (uint64_t)paddr >> 32); 1467 } 1468 } 1469 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1470 struct sdhc_adma2_descriptor32 *desc = hp->adma2; 1471 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1472 } else { 1473 struct sdhc_adma2_descriptor64 *desc = hp->adma2; 1474 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1475 } 1476 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1477 BUS_DMASYNC_PREWRITE); 1478 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1479 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2); 1480 1481 const bus_addr_t desc_addr = hp->adma_map->dm_segs[0].ds_addr; 1482 1483 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff); 1484 if (ISSET(hp->flags, SHF_USE_ADMA2_64)) { 1485 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4, 1486 (uint64_t)desc_addr >> 32); 1487 } 1488 } else if (ISSET(mode, SDHC_DMA_ENABLE) && 1489 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) { 1490 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1491 } 1492 1493 /* 1494 * Start a CPU data transfer. Writing to the high order byte 1495 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1496 */ 1497 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1498 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1499 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1500 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1501 } else { 1502 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1503 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1504 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1505 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1506 HWRITE2(hp, SDHC_COMMAND, command); 1507 } 1508 1509 return 0; 1510 } 1511 1512 static void 1513 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1514 { 1515 struct sdhc_softc *sc = hp->sc; 1516 int error; 1517 1518 KASSERT(mutex_owned(&hp->intr_lock)); 1519 1520 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1521 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1522 1523 #ifdef SDHC_DEBUG 1524 /* XXX I forgot why I wanted to know when this happens :-( */ 1525 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1526 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1527 aprint_error_dev(hp->sc->sc_dev, 1528 "CMD52/53 error response flags %#x\n", 1529 MMC_R1(cmd->c_resp) & 0xff00); 1530 } 1531 #endif 1532 1533 if (cmd->c_dmamap != NULL) { 1534 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1535 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd); 1536 if (error == 0 && !sdhc_wait_intr(hp, 1537 SDHC_TRANSFER_COMPLETE, SDHC_DMA_TIMEOUT)) { 1538 error = ETIMEDOUT; 1539 } 1540 } else { 1541 error = sdhc_transfer_data_dma(hp, cmd); 1542 } 1543 } else 1544 error = sdhc_transfer_data_pio(hp, cmd); 1545 if (error) 1546 cmd->c_error = error; 1547 SET(cmd->c_flags, SCF_ITSDONE); 1548 1549 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1550 HDEVNAME(hp), cmd->c_error)); 1551 } 1552 1553 static int 1554 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1555 { 1556 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1557 bus_addr_t posaddr; 1558 bus_addr_t segaddr; 1559 bus_size_t seglen; 1560 u_int seg = 0; 1561 int error = 0; 1562 int status; 1563 1564 KASSERT(mutex_owned(&hp->intr_lock)); 1565 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1566 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1567 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1568 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1569 1570 for (;;) { 1571 status = sdhc_wait_intr(hp, 1572 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1573 SDHC_DMA_TIMEOUT); 1574 1575 if (status & SDHC_TRANSFER_COMPLETE) { 1576 break; 1577 } 1578 if (!status) { 1579 error = ETIMEDOUT; 1580 break; 1581 } 1582 1583 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1584 continue; 1585 } 1586 1587 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1588 continue; 1589 } 1590 1591 /* DMA Interrupt (boundary crossing) */ 1592 1593 segaddr = dm_segs[seg].ds_addr; 1594 seglen = dm_segs[seg].ds_len; 1595 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1596 1597 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1598 continue; 1599 } 1600 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1601 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1602 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1603 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1604 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1605 } 1606 1607 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1608 bus_dmamap_sync(hp->sc->sc_dmat, hp->adma_map, 0, 1609 PAGE_SIZE, BUS_DMASYNC_POSTWRITE); 1610 } 1611 1612 return error; 1613 } 1614 1615 static int 1616 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1617 { 1618 uint8_t *data = cmd->c_data; 1619 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1620 u_int len, datalen; 1621 u_int imask; 1622 u_int pmask; 1623 int error = 0; 1624 1625 KASSERT(mutex_owned(&hp->intr_lock)); 1626 1627 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1628 imask = SDHC_BUFFER_READ_READY; 1629 pmask = SDHC_BUFFER_READ_ENABLE; 1630 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1631 pio_func = esdhc_read_data_pio; 1632 } else { 1633 pio_func = sdhc_read_data_pio; 1634 } 1635 } else { 1636 imask = SDHC_BUFFER_WRITE_READY; 1637 pmask = SDHC_BUFFER_WRITE_ENABLE; 1638 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1639 pio_func = esdhc_write_data_pio; 1640 } else { 1641 pio_func = sdhc_write_data_pio; 1642 } 1643 } 1644 datalen = cmd->c_datalen; 1645 1646 KASSERT(mutex_owned(&hp->intr_lock)); 1647 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1648 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1649 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1650 1651 while (datalen > 0) { 1652 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1653 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1654 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1655 } else { 1656 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1657 } 1658 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1659 error = ETIMEDOUT; 1660 break; 1661 } 1662 1663 error = sdhc_wait_state(hp, pmask, pmask); 1664 if (error) 1665 break; 1666 } 1667 1668 len = MIN(datalen, cmd->c_blklen); 1669 (*pio_func)(hp, data, len); 1670 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1671 HDEVNAME(hp), len, data)); 1672 1673 data += len; 1674 datalen -= len; 1675 } 1676 1677 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1678 SDHC_TRANSFER_TIMEOUT)) 1679 error = ETIMEDOUT; 1680 1681 return error; 1682 } 1683 1684 static void 1685 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1686 { 1687 1688 if (((__uintptr_t)data & 3) == 0) { 1689 while (datalen > 3) { 1690 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1691 data += 4; 1692 datalen -= 4; 1693 } 1694 if (datalen > 1) { 1695 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1696 data += 2; 1697 datalen -= 2; 1698 } 1699 if (datalen > 0) { 1700 *data = HREAD1(hp, SDHC_DATA); 1701 data += 1; 1702 datalen -= 1; 1703 } 1704 } else if (((__uintptr_t)data & 1) == 0) { 1705 while (datalen > 1) { 1706 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1707 data += 2; 1708 datalen -= 2; 1709 } 1710 if (datalen > 0) { 1711 *data = HREAD1(hp, SDHC_DATA); 1712 data += 1; 1713 datalen -= 1; 1714 } 1715 } else { 1716 while (datalen > 0) { 1717 *data = HREAD1(hp, SDHC_DATA); 1718 data += 1; 1719 datalen -= 1; 1720 } 1721 } 1722 } 1723 1724 static void 1725 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1726 { 1727 1728 if (((__uintptr_t)data & 3) == 0) { 1729 while (datalen > 3) { 1730 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 1731 data += 4; 1732 datalen -= 4; 1733 } 1734 if (datalen > 1) { 1735 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1736 data += 2; 1737 datalen -= 2; 1738 } 1739 if (datalen > 0) { 1740 HWRITE1(hp, SDHC_DATA, *data); 1741 data += 1; 1742 datalen -= 1; 1743 } 1744 } else if (((__uintptr_t)data & 1) == 0) { 1745 while (datalen > 1) { 1746 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1747 data += 2; 1748 datalen -= 2; 1749 } 1750 if (datalen > 0) { 1751 HWRITE1(hp, SDHC_DATA, *data); 1752 data += 1; 1753 datalen -= 1; 1754 } 1755 } else { 1756 while (datalen > 0) { 1757 HWRITE1(hp, SDHC_DATA, *data); 1758 data += 1; 1759 datalen -= 1; 1760 } 1761 } 1762 } 1763 1764 static void 1765 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1766 { 1767 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1768 uint32_t v; 1769 1770 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1771 size_t count = 0; 1772 1773 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1774 if (count == 0) { 1775 /* 1776 * If we've drained "watermark" words, we need to wait 1777 * a little bit so the read FIFO can refill. 1778 */ 1779 sdmmc_delay(10); 1780 count = watermark; 1781 } 1782 v = HREAD4(hp, SDHC_DATA); 1783 v = le32toh(v); 1784 *(uint32_t *)data = v; 1785 data += 4; 1786 datalen -= 4; 1787 status = HREAD2(hp, SDHC_NINTR_STATUS); 1788 count--; 1789 } 1790 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1791 if (count == 0) { 1792 sdmmc_delay(10); 1793 } 1794 v = HREAD4(hp, SDHC_DATA); 1795 v = le32toh(v); 1796 do { 1797 *data++ = v; 1798 v >>= 8; 1799 } while (--datalen > 0); 1800 } 1801 } 1802 1803 static void 1804 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1805 { 1806 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1807 uint32_t v; 1808 1809 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1810 size_t count = watermark; 1811 1812 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1813 if (count == 0) { 1814 sdmmc_delay(10); 1815 count = watermark; 1816 } 1817 v = *(uint32_t *)data; 1818 v = htole32(v); 1819 HWRITE4(hp, SDHC_DATA, v); 1820 data += 4; 1821 datalen -= 4; 1822 status = HREAD2(hp, SDHC_NINTR_STATUS); 1823 count--; 1824 } 1825 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1826 if (count == 0) { 1827 sdmmc_delay(10); 1828 } 1829 v = *(uint32_t *)data; 1830 v = htole32(v); 1831 HWRITE4(hp, SDHC_DATA, v); 1832 } 1833 } 1834 1835 /* Prepare for another command. */ 1836 static int 1837 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1838 { 1839 int timo; 1840 1841 KASSERT(mutex_owned(&hp->intr_lock)); 1842 1843 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1844 1845 /* Request the reset. */ 1846 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1847 1848 /* 1849 * If necessary, wait for the controller to set the bits to 1850 * acknowledge the reset. 1851 */ 1852 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 1853 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 1854 for (timo = 10000; timo > 0; timo--) { 1855 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1856 break; 1857 /* Short delay because I worry we may miss it... */ 1858 sdmmc_delay(1); 1859 } 1860 if (timo == 0) 1861 return ETIMEDOUT; 1862 } 1863 1864 /* 1865 * Wait for the controller to clear the bits to indicate that 1866 * the reset has completed. 1867 */ 1868 for (timo = 10; timo > 0; timo--) { 1869 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1870 break; 1871 sdmmc_delay(10000); 1872 } 1873 if (timo == 0) { 1874 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1875 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1876 return ETIMEDOUT; 1877 } 1878 1879 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1880 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1881 } 1882 1883 return 0; 1884 } 1885 1886 static int 1887 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1888 { 1889 int status; 1890 1891 KASSERT(mutex_owned(&hp->intr_lock)); 1892 1893 mask |= SDHC_ERROR_INTERRUPT; 1894 1895 status = hp->intr_status & mask; 1896 while (status == 0) { 1897 if (cv_timedwait(&hp->intr_cv, &hp->intr_lock, timo) 1898 == EWOULDBLOCK) { 1899 status |= SDHC_ERROR_INTERRUPT; 1900 break; 1901 } 1902 status = hp->intr_status & mask; 1903 } 1904 hp->intr_status &= ~status; 1905 1906 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1907 hp->intr_error_status)); 1908 1909 /* Command timeout has higher priority than command complete. */ 1910 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1911 hp->intr_error_status = 0; 1912 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1913 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1914 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1915 } 1916 status = 0; 1917 } 1918 1919 return status; 1920 } 1921 1922 /* 1923 * Established by attachment driver at interrupt priority IPL_SDMMC. 1924 */ 1925 int 1926 sdhc_intr(void *arg) 1927 { 1928 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1929 struct sdhc_host *hp; 1930 int done = 0; 1931 uint16_t status; 1932 uint16_t error; 1933 1934 /* We got an interrupt, but we don't know from which slot. */ 1935 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1936 hp = sc->sc_host[host]; 1937 if (hp == NULL) 1938 continue; 1939 1940 mutex_enter(&hp->intr_lock); 1941 1942 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1943 /* Find out which interrupts are pending. */ 1944 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1945 status = xstatus; 1946 error = xstatus >> 16; 1947 if (error) 1948 xstatus |= SDHC_ERROR_INTERRUPT; 1949 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1950 goto next_port; /* no interrupt for us */ 1951 /* Acknowledge the interrupts we are about to handle. */ 1952 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1953 } else { 1954 /* Find out which interrupts are pending. */ 1955 error = 0; 1956 status = HREAD2(hp, SDHC_NINTR_STATUS); 1957 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1958 goto next_port; /* no interrupt for us */ 1959 /* Acknowledge the interrupts we are about to handle. */ 1960 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1961 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1962 /* Acknowledge error interrupts. */ 1963 error = HREAD2(hp, SDHC_EINTR_STATUS); 1964 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1965 } 1966 } 1967 1968 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1969 status, error)); 1970 1971 /* Claim this interrupt. */ 1972 done = 1; 1973 1974 if (ISSET(error, SDHC_ADMA_ERROR)) { 1975 uint8_t adma_err = HREAD1(hp, SDHC_ADMA_ERROR_STATUS); 1976 printf("%s: ADMA error, status %02x\n", HDEVNAME(hp), 1977 adma_err); 1978 } 1979 1980 /* 1981 * Service error interrupts. 1982 */ 1983 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1984 SDHC_DATA_TIMEOUT_ERROR)) { 1985 hp->intr_error_status |= error; 1986 hp->intr_status |= status; 1987 cv_broadcast(&hp->intr_cv); 1988 } 1989 1990 /* 1991 * Wake up the sdmmc event thread to scan for cards. 1992 */ 1993 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1994 if (hp->sdmmc != NULL) { 1995 sdmmc_needs_discover(hp->sdmmc); 1996 } 1997 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1998 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1999 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 2000 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 2001 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 2002 } 2003 } 2004 2005 /* 2006 * Wake up the blocking process to service command 2007 * related interrupt(s). 2008 */ 2009 if (ISSET(status, SDHC_COMMAND_COMPLETE| 2010 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 2011 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 2012 hp->intr_status |= status; 2013 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 2014 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 2015 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 2016 } 2017 cv_broadcast(&hp->intr_cv); 2018 } 2019 2020 /* 2021 * Service SD card interrupts. 2022 */ 2023 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 2024 && ISSET(status, SDHC_CARD_INTERRUPT)) { 2025 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 2026 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 2027 sdmmc_card_intr(hp->sdmmc); 2028 } 2029 next_port: 2030 mutex_exit(&hp->intr_lock); 2031 } 2032 2033 return done; 2034 } 2035 2036 kmutex_t * 2037 sdhc_host_lock(struct sdhc_host *hp) 2038 { 2039 return &hp->intr_lock; 2040 } 2041 2042 #ifdef SDHC_DEBUG 2043 void 2044 sdhc_dump_regs(struct sdhc_host *hp) 2045 { 2046 2047 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 2048 HREAD4(hp, SDHC_PRESENT_STATE)); 2049 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 2050 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 2051 HREAD1(hp, SDHC_POWER_CTL)); 2052 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 2053 HREAD2(hp, SDHC_NINTR_STATUS)); 2054 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 2055 HREAD2(hp, SDHC_EINTR_STATUS)); 2056 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 2057 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 2058 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 2059 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 2060 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 2061 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 2062 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 2063 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 2064 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 2065 HREAD4(hp, SDHC_CAPABILITIES)); 2066 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 2067 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 2068 } 2069 #endif 2070
Indexes created Mon Sep 22 13:09:51 GMT 2025