sdhc.c revision 1.79
1 /* $NetBSD: sdhc.c,v 1.79 2015/08/05 10:30:25 jmcneill Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.79 2015/08/05 10:30:25 jmcneill Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 40 #include <dev/sdmmc/sdhcreg.h> 41 #include <dev/sdmmc/sdhcvar.h> 42 #include <dev/sdmmc/sdmmcchip.h> 43 #include <dev/sdmmc/sdmmcreg.h> 44 #include <dev/sdmmc/sdmmcvar.h> 45 46 #ifdef SDHC_DEBUG 47 int sdhcdebug = 1; 48 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 49 void sdhc_dump_regs(struct sdhc_host *); 50 #else 51 #define DPRINTF(n,s) do {} while (0) 52 #endif 53 54 #define SDHC_COMMAND_TIMEOUT hz 55 #define SDHC_BUFFER_TIMEOUT hz 56 #define SDHC_TRANSFER_TIMEOUT hz 57 #define SDHC_DMA_TIMEOUT (hz*3) 58 #define SDHC_TUNING_TIMEOUT hz 59 60 struct sdhc_host { 61 struct sdhc_softc *sc; /* host controller device */ 62 63 bus_space_tag_t iot; /* host register set tag */ 64 bus_space_handle_t ioh; /* host register set handle */ 65 bus_size_t ios; /* host register space size */ 66 bus_dma_tag_t dmat; /* host DMA tag */ 67 68 device_t sdmmc; /* generic SD/MMC device */ 69 70 u_int clkbase; /* base clock frequency in KHz */ 71 int maxblklen; /* maximum block length */ 72 uint32_t ocr; /* OCR value from capabilities */ 73 74 uint8_t regs[14]; /* host controller state */ 75 76 uint16_t intr_status; /* soft interrupt status */ 77 uint16_t intr_error_status; /* soft error status */ 78 kmutex_t intr_lock; 79 kcondvar_t intr_cv; 80 81 int specver; /* spec. version */ 82 83 uint32_t flags; /* flags for this host */ 84 #define SHF_USE_DMA 0x0001 85 #define SHF_USE_4BIT_MODE 0x0002 86 #define SHF_USE_8BIT_MODE 0x0004 87 #define SHF_MODE_DMAEN 0x0008 /* needs SDHC_DMA_ENABLE in mode */ 88 #define SHF_USE_ADMA2_32 0x0010 89 #define SHF_USE_ADMA2_64 0x0020 90 #define SHF_USE_ADMA2_MASK 0x0030 91 92 bus_dmamap_t adma_map; 93 bus_dma_segment_t adma_segs[1]; 94 void *adma2; 95 }; 96 97 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 98 99 static uint8_t 100 hread1(struct sdhc_host *hp, bus_size_t reg) 101 { 102 103 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 104 return bus_space_read_1(hp->iot, hp->ioh, reg); 105 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 106 } 107 108 static uint16_t 109 hread2(struct sdhc_host *hp, bus_size_t reg) 110 { 111 112 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 113 return bus_space_read_2(hp->iot, hp->ioh, reg); 114 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 115 } 116 117 #define HREAD1(hp, reg) hread1(hp, reg) 118 #define HREAD2(hp, reg) hread2(hp, reg) 119 #define HREAD4(hp, reg) \ 120 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 121 122 123 static void 124 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 125 { 126 127 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 128 bus_space_write_1(hp->iot, hp->ioh, o, val); 129 } else { 130 const size_t shift = 8 * (o & 3); 131 o &= -4; 132 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 133 tmp = (val << shift) | (tmp & ~(0xff << shift)); 134 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 135 } 136 } 137 138 static void 139 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 140 { 141 142 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 143 bus_space_write_2(hp->iot, hp->ioh, o, val); 144 } else { 145 const size_t shift = 8 * (o & 2); 146 o &= -4; 147 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 148 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 149 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 150 } 151 } 152 153 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 154 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 155 #define HWRITE4(hp, reg, val) \ 156 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 157 158 #define HCLR1(hp, reg, bits) \ 159 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 160 #define HCLR2(hp, reg, bits) \ 161 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 162 #define HCLR4(hp, reg, bits) \ 163 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 164 #define HSET1(hp, reg, bits) \ 165 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 166 #define HSET2(hp, reg, bits) \ 167 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 168 #define HSET4(hp, reg, bits) \ 169 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 170 171 static int sdhc_host_reset(sdmmc_chipset_handle_t); 172 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 173 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 174 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 175 static int sdhc_card_detect(sdmmc_chipset_handle_t); 176 static int sdhc_write_protect(sdmmc_chipset_handle_t); 177 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 178 static int sdhc_bus_clock_ddr(sdmmc_chipset_handle_t, int, bool); 179 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 180 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 181 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 182 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 183 static void sdhc_exec_command(sdmmc_chipset_handle_t, 184 struct sdmmc_command *); 185 static int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 186 static int sdhc_execute_tuning(sdmmc_chipset_handle_t, int); 187 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 188 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 189 static int sdhc_soft_reset(struct sdhc_host *, int); 190 static int sdhc_wait_intr(struct sdhc_host *, int, int); 191 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 192 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 193 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 194 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 195 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 196 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 197 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 198 199 static struct sdmmc_chip_functions sdhc_functions = { 200 /* host controller reset */ 201 .host_reset = sdhc_host_reset, 202 203 /* host controller capabilities */ 204 .host_ocr = sdhc_host_ocr, 205 .host_maxblklen = sdhc_host_maxblklen, 206 207 /* card detection */ 208 .card_detect = sdhc_card_detect, 209 210 /* write protect */ 211 .write_protect = sdhc_write_protect, 212 213 /* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */ 214 .bus_power = sdhc_bus_power, 215 .bus_clock = NULL, /* see sdhc_bus_clock_ddr */ 216 .bus_width = sdhc_bus_width, 217 .bus_rod = sdhc_bus_rod, 218 219 /* command execution */ 220 .exec_command = sdhc_exec_command, 221 222 /* card interrupt */ 223 .card_enable_intr = sdhc_card_enable_intr, 224 .card_intr_ack = sdhc_card_intr_ack, 225 226 /* UHS functions */ 227 .signal_voltage = sdhc_signal_voltage, 228 .bus_clock_ddr = sdhc_bus_clock_ddr, 229 .execute_tuning = sdhc_execute_tuning, 230 }; 231 232 static int 233 sdhc_cfprint(void *aux, const char *pnp) 234 { 235 const struct sdmmcbus_attach_args * const saa = aux; 236 const struct sdhc_host * const hp = saa->saa_sch; 237 238 if (pnp) { 239 aprint_normal("sdmmc at %s", pnp); 240 } 241 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 242 if (hp->sc->sc_host[host] == hp) { 243 aprint_normal(" slot %zu", host); 244 } 245 } 246 247 return UNCONF; 248 } 249 250 /* 251 * Called by attachment driver. For each SD card slot there is one SD 252 * host controller standard register set. (1.3) 253 */ 254 int 255 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 256 bus_space_handle_t ioh, bus_size_t iosize) 257 { 258 struct sdmmcbus_attach_args saa; 259 struct sdhc_host *hp; 260 uint32_t caps, caps2; 261 uint16_t sdhcver; 262 int error; 263 264 /* Allocate one more host structure. */ 265 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 266 if (hp == NULL) { 267 aprint_error_dev(sc->sc_dev, 268 "couldn't alloc memory (sdhc host)\n"); 269 goto err1; 270 } 271 sc->sc_host[sc->sc_nhosts++] = hp; 272 273 /* Fill in the new host structure. */ 274 hp->sc = sc; 275 hp->iot = iot; 276 hp->ioh = ioh; 277 hp->ios = iosize; 278 hp->dmat = sc->sc_dmat; 279 280 mutex_init(&hp->intr_lock, MUTEX_DEFAULT, IPL_SDMMC); 281 cv_init(&hp->intr_cv, "sdhcintr"); 282 283 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 284 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); 285 } else { 286 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 287 } 288 aprint_normal_dev(sc->sc_dev, "SDHC "); 289 hp->specver = SDHC_SPEC_VERSION(sdhcver); 290 switch (SDHC_SPEC_VERSION(sdhcver)) { 291 case SDHC_SPEC_VERS_100: 292 aprint_normal("1.0"); 293 break; 294 295 case SDHC_SPEC_VERS_200: 296 aprint_normal("2.0"); 297 break; 298 299 case SDHC_SPEC_VERS_300: 300 aprint_normal("3.0"); 301 break; 302 303 case SDHC_SPEC_VERS_400: 304 aprint_normal("4.0"); 305 break; 306 307 default: 308 aprint_normal("unknown version(0x%x)", 309 SDHC_SPEC_VERSION(sdhcver)); 310 break; 311 } 312 aprint_normal(", rev %u", SDHC_VENDOR_VERSION(sdhcver)); 313 314 /* 315 * Reset the host controller and enable interrupts. 316 */ 317 (void)sdhc_host_reset(hp); 318 319 /* Determine host capabilities. */ 320 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 321 caps = sc->sc_caps; 322 caps2 = sc->sc_caps2; 323 } else { 324 caps = sc->sc_caps = HREAD4(hp, SDHC_CAPABILITIES); 325 if (hp->specver >= SDHC_SPEC_VERS_300) { 326 caps2 = sc->sc_caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 327 } else { 328 caps2 = sc->sc_caps2 = 0; 329 } 330 } 331 332 /* 333 * Use DMA if the host system and the controller support it. 334 * Suports integrated or external DMA egine, with or without 335 * SDHC_DMA_ENABLE in the command. 336 */ 337 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 338 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 339 ISSET(caps, SDHC_DMA_SUPPORT)))) { 340 SET(hp->flags, SHF_USE_DMA); 341 342 if (ISSET(sc->sc_flags, SDHC_FLAG_USE_ADMA2) && 343 ISSET(caps, SDHC_ADMA2_SUPP)) { 344 SET(hp->flags, SHF_MODE_DMAEN); 345 /* 346 * 64-bit mode was present in the 2.00 spec, removed 347 * from 3.00, and re-added in 4.00 with a different 348 * descriptor layout. We only support 2.00 and 3.00 349 * descriptors for now. 350 */ 351 if (hp->specver == SDHC_SPEC_VERS_200 && 352 ISSET(caps, SDHC_64BIT_SYS_BUS)) { 353 SET(hp->flags, SHF_USE_ADMA2_64); 354 aprint_normal(", 64-bit ADMA2"); 355 } else { 356 SET(hp->flags, SHF_USE_ADMA2_32); 357 aprint_normal(", 32-bit ADMA2"); 358 } 359 } else { 360 if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) || 361 ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN)) 362 SET(hp->flags, SHF_MODE_DMAEN); 363 if (sc->sc_vendor_transfer_data_dma) { 364 aprint_normal(", platform DMA"); 365 } else { 366 aprint_normal(", SDMA"); 367 } 368 } 369 } else { 370 aprint_normal(", PIO"); 371 } 372 373 /* 374 * Determine the base clock frequency. (2.2.24) 375 */ 376 if (hp->specver >= SDHC_SPEC_VERS_300) { 377 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 378 } else { 379 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 380 } 381 if (hp->clkbase == 0 || 382 ISSET(sc->sc_flags, SDHC_FLAG_NO_CLKBASE)) { 383 if (sc->sc_clkbase == 0) { 384 /* The attachment driver must tell us. */ 385 aprint_error_dev(sc->sc_dev, 386 "unknown base clock frequency\n"); 387 goto err; 388 } 389 hp->clkbase = sc->sc_clkbase; 390 } 391 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 392 /* SDHC 1.0 supports only 10-63 MHz. */ 393 aprint_error_dev(sc->sc_dev, 394 "base clock frequency out of range: %u MHz\n", 395 hp->clkbase / 1000); 396 goto err; 397 } 398 aprint_normal(", %u kHz", hp->clkbase); 399 400 /* 401 * XXX Set the data timeout counter value according to 402 * capabilities. (2.2.15) 403 */ 404 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 405 #if 1 406 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 407 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 408 #endif 409 410 if (ISSET(caps, SDHC_EMBEDDED_SLOT)) 411 aprint_normal(", embedded slot"); 412 413 /* 414 * Determine SD bus voltage levels supported by the controller. 415 */ 416 aprint_normal(","); 417 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) { 418 SET(hp->ocr, MMC_OCR_HCS); 419 aprint_normal(" HS"); 420 } 421 if (ISSET(caps2, SDHC_SDR50_SUPP)) { 422 SET(hp->ocr, MMC_OCR_S18A); 423 aprint_normal(" SDR50"); 424 } 425 if (ISSET(caps2, SDHC_DDR50_SUPP)) { 426 SET(hp->ocr, MMC_OCR_S18A); 427 aprint_normal(" DDR50"); 428 } 429 if (ISSET(caps2, SDHC_SDR104_SUPP)) { 430 SET(hp->ocr, MMC_OCR_S18A); 431 aprint_normal(" SDR104 HS200"); 432 } 433 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 434 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 435 aprint_normal(" 1.8V"); 436 } 437 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 438 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 439 aprint_normal(" 3.0V"); 440 } 441 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 442 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 443 aprint_normal(" 3.3V"); 444 } 445 446 /* 447 * Determine the maximum block length supported by the host 448 * controller. (2.2.24) 449 */ 450 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 451 case SDHC_MAX_BLK_LEN_512: 452 hp->maxblklen = 512; 453 break; 454 455 case SDHC_MAX_BLK_LEN_1024: 456 hp->maxblklen = 1024; 457 break; 458 459 case SDHC_MAX_BLK_LEN_2048: 460 hp->maxblklen = 2048; 461 break; 462 463 case SDHC_MAX_BLK_LEN_4096: 464 hp->maxblklen = 4096; 465 break; 466 467 default: 468 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 469 goto err; 470 } 471 aprint_normal(", %u byte blocks", hp->maxblklen); 472 aprint_normal("\n"); 473 474 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 475 int rseg; 476 477 /* Allocate ADMA2 descriptor memory */ 478 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 479 PAGE_SIZE, hp->adma_segs, 1, &rseg, BUS_DMA_WAITOK); 480 if (error) { 481 aprint_error_dev(sc->sc_dev, 482 "ADMA2 dmamem_alloc failed (%d)\n", error); 483 goto adma_done; 484 } 485 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 486 PAGE_SIZE, (void **)&hp->adma2, BUS_DMA_WAITOK); 487 if (error) { 488 aprint_error_dev(sc->sc_dev, 489 "ADMA2 dmamem_map failed (%d)\n", error); 490 goto adma_done; 491 } 492 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 493 0, BUS_DMA_WAITOK, &hp->adma_map); 494 if (error) { 495 aprint_error_dev(sc->sc_dev, 496 "ADMA2 dmamap_create failed (%d)\n", error); 497 goto adma_done; 498 } 499 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 500 hp->adma2, PAGE_SIZE, NULL, 501 BUS_DMA_WAITOK|BUS_DMA_WRITE); 502 if (error) { 503 aprint_error_dev(sc->sc_dev, 504 "ADMA2 dmamap_load failed (%d)\n", error); 505 goto adma_done; 506 } 507 508 memset(hp->adma2, 0, PAGE_SIZE); 509 510 adma_done: 511 if (error) 512 CLR(hp->flags, SHF_USE_ADMA2_MASK); 513 } 514 515 /* 516 * Attach the generic SD/MMC bus driver. (The bus driver must 517 * not invoke any chipset functions before it is attached.) 518 */ 519 memset(&saa, 0, sizeof(saa)); 520 saa.saa_busname = "sdmmc"; 521 saa.saa_sct = &sdhc_functions; 522 saa.saa_sch = hp; 523 saa.saa_dmat = hp->dmat; 524 saa.saa_clkmax = hp->clkbase; 525 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 526 saa.saa_clkmin = hp->clkbase / 256 / 2046; 527 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 528 saa.saa_clkmin = hp->clkbase / 256 / 16; 529 else if (hp->sc->sc_clkmsk != 0) 530 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 531 (ffs(hp->sc->sc_clkmsk) - 1)); 532 else if (hp->specver >= SDHC_SPEC_VERS_300) 533 saa.saa_clkmin = hp->clkbase / 0x3ff; 534 else 535 saa.saa_clkmin = hp->clkbase / 256; 536 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 537 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 538 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 539 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 540 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 541 if (ISSET(caps2, SDHC_SDR104_SUPP)) 542 saa.saa_caps |= SMC_CAPS_UHS_SDR104 | 543 SMC_CAPS_UHS_SDR50 | 544 SMC_CAPS_MMC_HS200; 545 if (ISSET(caps2, SDHC_SDR50_SUPP)) 546 saa.saa_caps |= SMC_CAPS_UHS_SDR50; 547 if (ISSET(caps2, SDHC_DDR50_SUPP)) 548 saa.saa_caps |= SMC_CAPS_UHS_DDR50; 549 if (ISSET(hp->flags, SHF_USE_DMA)) { 550 saa.saa_caps |= SMC_CAPS_DMA; 551 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 552 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 553 } 554 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 555 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 556 if (ISSET(sc->sc_flags, SDHC_FLAG_POLL_CARD_DET)) 557 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 558 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 559 560 return 0; 561 562 err: 563 cv_destroy(&hp->intr_cv); 564 mutex_destroy(&hp->intr_lock); 565 free(hp, M_DEVBUF); 566 sc->sc_host[--sc->sc_nhosts] = NULL; 567 err1: 568 return 1; 569 } 570 571 int 572 sdhc_detach(struct sdhc_softc *sc, int flags) 573 { 574 struct sdhc_host *hp; 575 int rv = 0; 576 577 for (size_t n = 0; n < sc->sc_nhosts; n++) { 578 hp = sc->sc_host[n]; 579 if (hp == NULL) 580 continue; 581 if (hp->sdmmc != NULL) { 582 rv = config_detach(hp->sdmmc, flags); 583 if (rv) 584 break; 585 hp->sdmmc = NULL; 586 } 587 /* disable interrupts */ 588 if ((flags & DETACH_FORCE) == 0) { 589 mutex_enter(&hp->intr_lock); 590 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 591 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 592 } else { 593 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 594 } 595 sdhc_soft_reset(hp, SDHC_RESET_ALL); 596 mutex_exit(&hp->intr_lock); 597 } 598 cv_destroy(&hp->intr_cv); 599 mutex_destroy(&hp->intr_lock); 600 if (hp->ios > 0) { 601 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 602 hp->ios = 0; 603 } 604 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 605 bus_dmamap_unload(sc->sc_dmat, hp->adma_map); 606 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 607 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 608 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, 1); 609 } 610 free(hp, M_DEVBUF); 611 sc->sc_host[n] = NULL; 612 } 613 614 return rv; 615 } 616 617 bool 618 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 619 { 620 struct sdhc_softc *sc = device_private(dev); 621 struct sdhc_host *hp; 622 size_t i; 623 624 /* XXX poll for command completion or suspend command 625 * in progress */ 626 627 /* Save the host controller state. */ 628 for (size_t n = 0; n < sc->sc_nhosts; n++) { 629 hp = sc->sc_host[n]; 630 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 631 for (i = 0; i < sizeof hp->regs; i += 4) { 632 uint32_t v = HREAD4(hp, i); 633 hp->regs[i + 0] = (v >> 0); 634 hp->regs[i + 1] = (v >> 8); 635 if (i + 3 < sizeof hp->regs) { 636 hp->regs[i + 2] = (v >> 16); 637 hp->regs[i + 3] = (v >> 24); 638 } 639 } 640 } else { 641 for (i = 0; i < sizeof hp->regs; i++) { 642 hp->regs[i] = HREAD1(hp, i); 643 } 644 } 645 } 646 return true; 647 } 648 649 bool 650 sdhc_resume(device_t dev, const pmf_qual_t *qual) 651 { 652 struct sdhc_softc *sc = device_private(dev); 653 struct sdhc_host *hp; 654 size_t i; 655 656 /* Restore the host controller state. */ 657 for (size_t n = 0; n < sc->sc_nhosts; n++) { 658 hp = sc->sc_host[n]; 659 (void)sdhc_host_reset(hp); 660 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 661 for (i = 0; i < sizeof hp->regs; i += 4) { 662 if (i + 3 < sizeof hp->regs) { 663 HWRITE4(hp, i, 664 (hp->regs[i + 0] << 0) 665 | (hp->regs[i + 1] << 8) 666 | (hp->regs[i + 2] << 16) 667 | (hp->regs[i + 3] << 24)); 668 } else { 669 HWRITE4(hp, i, 670 (hp->regs[i + 0] << 0) 671 | (hp->regs[i + 1] << 8)); 672 } 673 } 674 } else { 675 for (i = 0; i < sizeof hp->regs; i++) { 676 HWRITE1(hp, i, hp->regs[i]); 677 } 678 } 679 } 680 return true; 681 } 682 683 bool 684 sdhc_shutdown(device_t dev, int flags) 685 { 686 struct sdhc_softc *sc = device_private(dev); 687 struct sdhc_host *hp; 688 689 /* XXX chip locks up if we don't disable it before reboot. */ 690 for (size_t i = 0; i < sc->sc_nhosts; i++) { 691 hp = sc->sc_host[i]; 692 (void)sdhc_host_reset(hp); 693 } 694 return true; 695 } 696 697 /* 698 * Reset the host controller. Called during initialization, when 699 * cards are removed, upon resume, and during error recovery. 700 */ 701 static int 702 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 703 { 704 struct sdhc_host *hp = (struct sdhc_host *)sch; 705 uint32_t sdhcimask; 706 int error; 707 708 KASSERT(mutex_owned(&hp->intr_lock)); 709 710 /* Disable all interrupts. */ 711 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 712 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 713 } else { 714 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 715 } 716 717 /* 718 * Reset the entire host controller and wait up to 100ms for 719 * the controller to clear the reset bit. 720 */ 721 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 722 if (error) 723 goto out; 724 725 /* Set data timeout counter value to max for now. */ 726 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 727 #if 1 728 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 729 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 730 #endif 731 732 /* Enable interrupts. */ 733 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 734 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 735 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 736 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 737 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 738 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 739 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 740 sdhcimask ^= 741 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 742 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 743 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 744 } else { 745 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 746 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 747 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 748 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 749 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 750 } 751 752 out: 753 return error; 754 } 755 756 static int 757 sdhc_host_reset(sdmmc_chipset_handle_t sch) 758 { 759 struct sdhc_host *hp = (struct sdhc_host *)sch; 760 int error; 761 762 mutex_enter(&hp->intr_lock); 763 error = sdhc_host_reset1(sch); 764 mutex_exit(&hp->intr_lock); 765 766 return error; 767 } 768 769 static uint32_t 770 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 771 { 772 struct sdhc_host *hp = (struct sdhc_host *)sch; 773 774 return hp->ocr; 775 } 776 777 static int 778 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 779 { 780 struct sdhc_host *hp = (struct sdhc_host *)sch; 781 782 return hp->maxblklen; 783 } 784 785 /* 786 * Return non-zero if the card is currently inserted. 787 */ 788 static int 789 sdhc_card_detect(sdmmc_chipset_handle_t sch) 790 { 791 struct sdhc_host *hp = (struct sdhc_host *)sch; 792 int r; 793 794 if (hp->sc->sc_vendor_card_detect) 795 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 796 797 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 798 799 return r ? 1 : 0; 800 } 801 802 /* 803 * Return non-zero if the card is currently write-protected. 804 */ 805 static int 806 sdhc_write_protect(sdmmc_chipset_handle_t sch) 807 { 808 struct sdhc_host *hp = (struct sdhc_host *)sch; 809 int r; 810 811 if (hp->sc->sc_vendor_write_protect) 812 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 813 814 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 815 816 return r ? 0 : 1; 817 } 818 819 /* 820 * Set or change SD bus voltage and enable or disable SD bus power. 821 * Return zero on success. 822 */ 823 static int 824 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 825 { 826 struct sdhc_host *hp = (struct sdhc_host *)sch; 827 uint8_t vdd; 828 int error = 0; 829 const uint32_t pcmask = 830 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 831 832 mutex_enter(&hp->intr_lock); 833 834 /* 835 * Disable bus power before voltage change. 836 */ 837 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 838 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 839 HWRITE1(hp, SDHC_POWER_CTL, 0); 840 841 /* If power is disabled, reset the host and return now. */ 842 if (ocr == 0) { 843 (void)sdhc_host_reset1(hp); 844 goto out; 845 } 846 847 /* 848 * Select the lowest voltage according to capabilities. 849 */ 850 ocr &= hp->ocr; 851 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 852 vdd = SDHC_VOLTAGE_1_8V; 853 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 854 vdd = SDHC_VOLTAGE_3_0V; 855 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 856 vdd = SDHC_VOLTAGE_3_3V; 857 } else { 858 /* Unsupported voltage level requested. */ 859 error = EINVAL; 860 goto out; 861 } 862 863 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 864 /* 865 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 866 * voltage ramp until power rises. 867 */ 868 869 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SINGLE_POWER_WRITE)) { 870 HWRITE1(hp, SDHC_POWER_CTL, 871 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 872 } else { 873 HWRITE1(hp, SDHC_POWER_CTL, 874 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 875 sdmmc_delay(1); 876 HWRITE1(hp, SDHC_POWER_CTL, 877 (vdd << SDHC_VOLTAGE_SHIFT)); 878 sdmmc_delay(1); 879 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 880 sdmmc_delay(10000); 881 } 882 883 /* 884 * The host system may not power the bus due to battery low, 885 * etc. In that case, the host controller should clear the 886 * bus power bit. 887 */ 888 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 889 error = ENXIO; 890 goto out; 891 } 892 } 893 894 out: 895 mutex_exit(&hp->intr_lock); 896 897 return error; 898 } 899 900 /* 901 * Return the smallest possible base clock frequency divisor value 902 * for the CLOCK_CTL register to produce `freq' (KHz). 903 */ 904 static bool 905 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 906 { 907 u_int div; 908 909 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 910 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 911 if ((hp->clkbase / div) <= freq) { 912 *divp = SDHC_SDCLK_CGM 913 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 914 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 915 //freq = hp->clkbase / div; 916 return true; 917 } 918 } 919 /* No divisor found. */ 920 return false; 921 } 922 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 923 u_int dvs = (hp->clkbase + freq - 1) / freq; 924 u_int roundup = dvs & 1; 925 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 926 if (dvs + roundup <= 16) { 927 dvs += roundup - 1; 928 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 929 | (dvs << SDHC_SDCLK_DVS_SHIFT); 930 DPRINTF(2, 931 ("%s: divisor for freq %u is %u * %u\n", 932 HDEVNAME(hp), freq, div * 2, dvs + 1)); 933 //freq = hp->clkbase / (div * 2) * (dvs + 1); 934 return true; 935 } 936 /* 937 * If we drop bits, we need to round up the divisor. 938 */ 939 roundup |= dvs & 1; 940 } 941 /* No divisor found. */ 942 return false; 943 } 944 if (hp->sc->sc_clkmsk != 0) { 945 div = howmany(hp->clkbase, freq); 946 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 947 return false; 948 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 949 //freq = hp->clkbase / div; 950 return true; 951 } 952 if (hp->specver >= SDHC_SPEC_VERS_300) { 953 div = howmany(hp->clkbase, freq); 954 div = div > 1 ? howmany(div, 2) : 0; 955 if (div > 0x3ff) 956 return false; 957 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 958 << SDHC_SDCLK_XDIV_SHIFT) | 959 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 960 << SDHC_SDCLK_DIV_SHIFT); 961 //freq = hp->clkbase / (div ? div * 2 : 1); 962 return true; 963 } else { 964 for (div = 1; div <= 256; div *= 2) { 965 if ((hp->clkbase / div) <= freq) { 966 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 967 //freq = hp->clkbase / div; 968 return true; 969 } 970 } 971 /* No divisor found. */ 972 return false; 973 } 974 /* No divisor found. */ 975 return false; 976 } 977 978 /* 979 * Set or change SDCLK frequency or disable the SD clock. 980 * Return zero on success. 981 */ 982 static int 983 sdhc_bus_clock_ddr(sdmmc_chipset_handle_t sch, int freq, bool ddr) 984 { 985 struct sdhc_host *hp = (struct sdhc_host *)sch; 986 u_int div; 987 u_int timo; 988 int16_t reg; 989 int error = 0; 990 bool present __diagused; 991 992 mutex_enter(&hp->intr_lock); 993 994 #ifdef DIAGNOSTIC 995 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 996 997 /* Must not stop the clock if commands are in progress. */ 998 if (present && sdhc_card_detect(hp)) { 999 aprint_normal_dev(hp->sc->sc_dev, 1000 "%s: command in progress\n", __func__); 1001 } 1002 #endif 1003 1004 if (hp->sc->sc_vendor_bus_clock) { 1005 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 1006 if (error != 0) 1007 goto out; 1008 } 1009 1010 /* 1011 * Stop SD clock before changing the frequency. 1012 */ 1013 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1014 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 1015 if (freq == SDMMC_SDCLK_OFF) { 1016 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 1017 goto out; 1018 } 1019 } else { 1020 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1021 if (freq == SDMMC_SDCLK_OFF) 1022 goto out; 1023 } 1024 1025 if (hp->specver >= SDHC_SPEC_VERS_300) { 1026 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 1027 if (freq > 100000) { 1028 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR104); 1029 } else if (freq > 50000) { 1030 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR50); 1031 } else if (freq > 25000) { 1032 if (ddr) { 1033 HSET2(hp, SDHC_HOST_CTL2, 1034 SDHC_UHS_MODE_SELECT_DDR50); 1035 } else { 1036 HSET2(hp, SDHC_HOST_CTL2, 1037 SDHC_UHS_MODE_SELECT_SDR25); 1038 } 1039 } else if (freq > 400) { 1040 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR12); 1041 } 1042 } 1043 1044 /* 1045 * Set the minimum base clock frequency divisor. 1046 */ 1047 if (!sdhc_clock_divisor(hp, freq, &div)) { 1048 /* Invalid base clock frequency or `freq' value. */ 1049 aprint_error_dev(hp->sc->sc_dev, 1050 "Invalid bus clock %d kHz\n", freq); 1051 error = EINVAL; 1052 goto out; 1053 } 1054 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1055 HWRITE4(hp, SDHC_CLOCK_CTL, 1056 div | (SDHC_TIMEOUT_MAX << 16)); 1057 } else { 1058 reg = HREAD2(hp, SDHC_CLOCK_CTL); 1059 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 1060 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 1061 } 1062 1063 /* 1064 * Start internal clock. Wait 10ms for stabilization. 1065 */ 1066 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1067 sdmmc_delay(10000); 1068 HSET4(hp, SDHC_CLOCK_CTL, 1069 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 1070 } else { 1071 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 1072 for (timo = 1000; timo > 0; timo--) { 1073 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 1074 SDHC_INTCLK_STABLE)) 1075 break; 1076 sdmmc_delay(10); 1077 } 1078 if (timo == 0) { 1079 error = ETIMEDOUT; 1080 goto out; 1081 } 1082 } 1083 1084 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1085 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 1086 /* 1087 * Sending 80 clocks at 400kHz takes 200us. 1088 * So delay for that time + slop and then 1089 * check a few times for completion. 1090 */ 1091 sdmmc_delay(210); 1092 for (timo = 10; timo > 0; timo--) { 1093 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 1094 SDHC_INIT_ACTIVE)) 1095 break; 1096 sdmmc_delay(10); 1097 } 1098 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 1099 1100 /* 1101 * Enable SD clock. 1102 */ 1103 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1104 } else { 1105 /* 1106 * Enable SD clock. 1107 */ 1108 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1109 1110 if (freq > 25000 && 1111 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 1112 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1113 else 1114 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1115 } 1116 1117 out: 1118 mutex_exit(&hp->intr_lock); 1119 1120 return error; 1121 } 1122 1123 static int 1124 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 1125 { 1126 struct sdhc_host *hp = (struct sdhc_host *)sch; 1127 int reg; 1128 1129 switch (width) { 1130 case 1: 1131 case 4: 1132 break; 1133 1134 case 8: 1135 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 1136 break; 1137 /* FALLTHROUGH */ 1138 default: 1139 DPRINTF(0,("%s: unsupported bus width (%d)\n", 1140 HDEVNAME(hp), width)); 1141 return 1; 1142 } 1143 1144 mutex_enter(&hp->intr_lock); 1145 1146 reg = HREAD1(hp, SDHC_HOST_CTL); 1147 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1148 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 1149 if (width == 4) 1150 reg |= SDHC_4BIT_MODE; 1151 else if (width == 8) 1152 reg |= SDHC_ESDHC_8BIT_MODE; 1153 } else { 1154 reg &= ~SDHC_4BIT_MODE; 1155 if (hp->specver >= SDHC_SPEC_VERS_300) { 1156 reg &= ~SDHC_8BIT_MODE; 1157 } 1158 if (width == 4) { 1159 reg |= SDHC_4BIT_MODE; 1160 } else if (width == 8 && hp->specver >= SDHC_SPEC_VERS_300) { 1161 reg |= SDHC_8BIT_MODE; 1162 } 1163 } 1164 HWRITE1(hp, SDHC_HOST_CTL, reg); 1165 1166 mutex_exit(&hp->intr_lock); 1167 1168 return 0; 1169 } 1170 1171 static int 1172 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1173 { 1174 struct sdhc_host *hp = (struct sdhc_host *)sch; 1175 1176 if (hp->sc->sc_vendor_rod) 1177 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1178 1179 return 0; 1180 } 1181 1182 static void 1183 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1184 { 1185 struct sdhc_host *hp = (struct sdhc_host *)sch; 1186 1187 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1188 mutex_enter(&hp->intr_lock); 1189 if (enable) { 1190 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1191 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1192 } else { 1193 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1194 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1195 } 1196 mutex_exit(&hp->intr_lock); 1197 } 1198 } 1199 1200 static void 1201 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1202 { 1203 struct sdhc_host *hp = (struct sdhc_host *)sch; 1204 1205 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1206 mutex_enter(&hp->intr_lock); 1207 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1208 mutex_exit(&hp->intr_lock); 1209 } 1210 } 1211 1212 static int 1213 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 1214 { 1215 struct sdhc_host *hp = (struct sdhc_host *)sch; 1216 1217 mutex_enter(&hp->intr_lock); 1218 switch (signal_voltage) { 1219 case SDMMC_SIGNAL_VOLTAGE_180: 1220 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1221 break; 1222 case SDMMC_SIGNAL_VOLTAGE_330: 1223 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1224 break; 1225 default: 1226 return EINVAL; 1227 } 1228 mutex_exit(&hp->intr_lock); 1229 1230 return 0; 1231 } 1232 1233 /* 1234 * Sampling clock tuning procedure (UHS) 1235 */ 1236 static int 1237 sdhc_execute_tuning(sdmmc_chipset_handle_t sch, int timing) 1238 { 1239 struct sdhc_host *hp = (struct sdhc_host *)sch; 1240 struct sdmmc_command cmd; 1241 uint8_t hostctl; 1242 int opcode, error, retry = 40; 1243 1244 switch (timing) { 1245 case SDMMC_TIMING_MMC_HS200: 1246 opcode = MMC_SEND_TUNING_BLOCK_HS200; 1247 break; 1248 case SDMMC_TIMING_UHS_SDR50: 1249 if (!ISSET(hp->sc->sc_caps2, SDHC_TUNING_SDR50)) 1250 return 0; 1251 /* FALLTHROUGH */ 1252 case SDMMC_TIMING_UHS_SDR104: 1253 opcode = MMC_SEND_TUNING_BLOCK; 1254 break; 1255 default: 1256 return EINVAL; 1257 } 1258 1259 hostctl = HREAD1(hp, SDHC_HOST_CTL); 1260 1261 /* enable buffer read ready interrupt */ 1262 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_BUFFER_READ_READY); 1263 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_BUFFER_READ_READY); 1264 1265 /* disable DMA */ 1266 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1267 1268 /* reset tuning circuit */ 1269 HCLR2(hp, SDHC_HOST_CTL2, SDHC_SAMPLING_CLOCK_SEL); 1270 1271 /* start of tuning */ 1272 HWRITE2(hp, SDHC_HOST_CTL2, SDHC_EXECUTE_TUNING); 1273 1274 mutex_enter(&hp->intr_lock); 1275 do { 1276 memset(&cmd, 0, sizeof(cmd)); 1277 cmd.c_opcode = opcode; 1278 cmd.c_arg = 0; 1279 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1; 1280 if (ISSET(hostctl, SDHC_8BIT_MODE)) { 1281 cmd.c_blklen = cmd.c_datalen = 128; 1282 } else { 1283 cmd.c_blklen = cmd.c_datalen = 64; 1284 } 1285 1286 error = sdhc_start_command(hp, &cmd); 1287 if (error) 1288 break; 1289 1290 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY, 1291 SDHC_TUNING_TIMEOUT)) { 1292 break; 1293 } 1294 1295 delay(1000); 1296 } while (HREAD2(hp, SDHC_HOST_CTL2) & SDHC_EXECUTE_TUNING && --retry); 1297 mutex_exit(&hp->intr_lock); 1298 1299 /* disable buffer read ready interrupt */ 1300 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_BUFFER_READ_READY); 1301 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_BUFFER_READ_READY); 1302 1303 if (HREAD2(hp, SDHC_HOST_CTL2) & SDHC_EXECUTE_TUNING) { 1304 HCLR2(hp, SDHC_HOST_CTL2, 1305 SDHC_SAMPLING_CLOCK_SEL|SDHC_EXECUTE_TUNING); 1306 sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1307 aprint_error_dev(hp->sc->sc_dev, 1308 "tuning did not complete, using fixed sampling clock\n"); 1309 return EIO; /* tuning did not complete */ 1310 } 1311 1312 if ((HREAD2(hp, SDHC_HOST_CTL2) & SDHC_SAMPLING_CLOCK_SEL) == 0) { 1313 HCLR2(hp, SDHC_HOST_CTL2, 1314 SDHC_SAMPLING_CLOCK_SEL|SDHC_EXECUTE_TUNING); 1315 sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1316 aprint_error_dev(hp->sc->sc_dev, 1317 "tuning failed, using fixed sampling clock\n"); 1318 return EIO; /* tuning failed */ 1319 } 1320 1321 return 0; /* tuning completed */ 1322 } 1323 1324 static int 1325 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1326 { 1327 uint32_t state; 1328 int timeout; 1329 1330 for (timeout = 10000; timeout > 0; timeout--) { 1331 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 1332 return 0; 1333 sdmmc_delay(10); 1334 } 1335 aprint_error_dev(hp->sc->sc_dev, "timeout waiting for mask %#x value %#x (state=%#x)\n", 1336 mask, value, state); 1337 return ETIMEDOUT; 1338 } 1339 1340 static void 1341 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1342 { 1343 struct sdhc_host *hp = (struct sdhc_host *)sch; 1344 int error; 1345 1346 mutex_enter(&hp->intr_lock); 1347 1348 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1349 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1350 if (ISSET(hp->flags, SHF_USE_DMA)) { 1351 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1352 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1353 } else { 1354 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1355 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1356 } 1357 } 1358 1359 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_TIMEOUT)) { 1360 const uint16_t eintr = SDHC_CMD_TIMEOUT_ERROR; 1361 if (cmd->c_data != NULL) { 1362 HCLR2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1363 HCLR2(hp, SDHC_EINTR_STATUS_EN, eintr); 1364 } else { 1365 HSET2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1366 HSET2(hp, SDHC_EINTR_STATUS_EN, eintr); 1367 } 1368 } 1369 1370 /* 1371 * Start the MMC command, or mark `cmd' as failed and return. 1372 */ 1373 error = sdhc_start_command(hp, cmd); 1374 if (error) { 1375 cmd->c_error = error; 1376 goto out; 1377 } 1378 1379 /* 1380 * Wait until the command phase is done, or until the command 1381 * is marked done for any other reason. 1382 */ 1383 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1384 cmd->c_error = ETIMEDOUT; 1385 goto out; 1386 } 1387 1388 /* 1389 * The host controller removes bits [0:7] from the response 1390 * data (CRC) and we pass the data up unchanged to the bus 1391 * driver (without padding). 1392 */ 1393 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1394 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1395 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1396 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1397 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1398 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1399 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1400 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1401 (cmd->c_resp[1] << 24); 1402 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1403 (cmd->c_resp[2] << 24); 1404 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1405 (cmd->c_resp[3] << 24); 1406 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1407 } 1408 } 1409 } 1410 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1411 1412 /* 1413 * If the command has data to transfer in any direction, 1414 * execute the transfer now. 1415 */ 1416 if (cmd->c_error == 0 && cmd->c_data != NULL) 1417 sdhc_transfer_data(hp, cmd); 1418 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1419 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10)) { 1420 cmd->c_error = ETIMEDOUT; 1421 goto out; 1422 } 1423 } 1424 1425 out: 1426 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1427 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1428 /* Turn off the LED. */ 1429 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1430 } 1431 SET(cmd->c_flags, SCF_ITSDONE); 1432 1433 mutex_exit(&hp->intr_lock); 1434 1435 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1436 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1437 cmd->c_flags, cmd->c_error)); 1438 } 1439 1440 static int 1441 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1442 { 1443 struct sdhc_softc * const sc = hp->sc; 1444 uint16_t blksize = 0; 1445 uint16_t blkcount = 0; 1446 uint16_t mode; 1447 uint16_t command; 1448 int error; 1449 1450 KASSERT(mutex_owned(&hp->intr_lock)); 1451 1452 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1453 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1454 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1455 1456 /* 1457 * The maximum block length for commands should be the minimum 1458 * of the host buffer size and the card buffer size. (1.7.2) 1459 */ 1460 1461 /* Fragment the data into proper blocks. */ 1462 if (cmd->c_datalen > 0) { 1463 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1464 blkcount = cmd->c_datalen / blksize; 1465 if (cmd->c_datalen % blksize > 0) { 1466 /* XXX: Split this command. (1.7.4) */ 1467 aprint_error_dev(sc->sc_dev, 1468 "data not a multiple of %u bytes\n", blksize); 1469 return EINVAL; 1470 } 1471 } 1472 1473 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1474 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1475 aprint_error_dev(sc->sc_dev, "too much data\n"); 1476 return EINVAL; 1477 } 1478 1479 /* Prepare transfer mode register value. (2.2.5) */ 1480 mode = SDHC_BLOCK_COUNT_ENABLE; 1481 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1482 mode |= SDHC_READ_MODE; 1483 if (blkcount > 1) { 1484 mode |= SDHC_MULTI_BLOCK_MODE; 1485 /* XXX only for memory commands? */ 1486 mode |= SDHC_AUTO_CMD12_ENABLE; 1487 } 1488 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1489 ISSET(hp->flags, SHF_MODE_DMAEN)) { 1490 mode |= SDHC_DMA_ENABLE; 1491 } 1492 1493 /* 1494 * Prepare command register value. (2.2.6) 1495 */ 1496 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1497 1498 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1499 command |= SDHC_CRC_CHECK_ENABLE; 1500 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1501 command |= SDHC_INDEX_CHECK_ENABLE; 1502 if (cmd->c_datalen > 0) 1503 command |= SDHC_DATA_PRESENT_SELECT; 1504 1505 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1506 command |= SDHC_NO_RESPONSE; 1507 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1508 command |= SDHC_RESP_LEN_136; 1509 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1510 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1511 else 1512 command |= SDHC_RESP_LEN_48; 1513 1514 /* Wait until command and data inhibit bits are clear. (1.5) */ 1515 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1516 if (error) { 1517 aprint_error_dev(sc->sc_dev, "command or data phase inhibited\n"); 1518 return error; 1519 } 1520 1521 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1522 HDEVNAME(hp), blksize, blkcount, mode, command)); 1523 1524 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1525 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1526 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1527 } 1528 1529 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1530 /* Alert the user not to remove the card. */ 1531 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1532 } 1533 1534 /* Set DMA start address. */ 1535 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK) && cmd->c_data != NULL) { 1536 for (int seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 1537 bus_addr_t paddr = 1538 cmd->c_dmamap->dm_segs[seg].ds_addr; 1539 uint16_t len = 1540 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1541 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1542 uint16_t attr = 1543 SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1544 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 1545 attr |= SDHC_ADMA2_END; 1546 } 1547 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1548 struct sdhc_adma2_descriptor32 *desc = 1549 hp->adma2; 1550 desc[seg].attribute = htole16(attr); 1551 desc[seg].length = htole16(len); 1552 desc[seg].address = htole32(paddr); 1553 } else { 1554 struct sdhc_adma2_descriptor64 *desc = 1555 hp->adma2; 1556 desc[seg].attribute = htole16(attr); 1557 desc[seg].length = htole16(len); 1558 desc[seg].address = htole32(paddr & 0xffffffff); 1559 desc[seg].address_hi = htole32( 1560 (uint64_t)paddr >> 32); 1561 } 1562 } 1563 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1564 struct sdhc_adma2_descriptor32 *desc = hp->adma2; 1565 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1566 } else { 1567 struct sdhc_adma2_descriptor64 *desc = hp->adma2; 1568 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1569 } 1570 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1571 BUS_DMASYNC_PREWRITE); 1572 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1573 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2); 1574 1575 const bus_addr_t desc_addr = hp->adma_map->dm_segs[0].ds_addr; 1576 1577 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff); 1578 if (ISSET(hp->flags, SHF_USE_ADMA2_64)) { 1579 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4, 1580 (uint64_t)desc_addr >> 32); 1581 } 1582 } else if (ISSET(mode, SDHC_DMA_ENABLE) && 1583 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) { 1584 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1585 } 1586 1587 /* 1588 * Start a CPU data transfer. Writing to the high order byte 1589 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1590 */ 1591 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1592 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1593 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1594 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1595 } else { 1596 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1597 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1598 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1599 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1600 HWRITE2(hp, SDHC_COMMAND, command); 1601 } 1602 1603 return 0; 1604 } 1605 1606 static void 1607 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1608 { 1609 struct sdhc_softc *sc = hp->sc; 1610 int error; 1611 1612 KASSERT(mutex_owned(&hp->intr_lock)); 1613 1614 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1615 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1616 1617 #ifdef SDHC_DEBUG 1618 /* XXX I forgot why I wanted to know when this happens :-( */ 1619 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1620 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1621 aprint_error_dev(hp->sc->sc_dev, 1622 "CMD52/53 error response flags %#x\n", 1623 MMC_R1(cmd->c_resp) & 0xff00); 1624 } 1625 #endif 1626 1627 if (cmd->c_dmamap != NULL) { 1628 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1629 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd); 1630 if (error == 0 && !sdhc_wait_intr(hp, 1631 SDHC_TRANSFER_COMPLETE, SDHC_DMA_TIMEOUT)) { 1632 error = ETIMEDOUT; 1633 } 1634 } else { 1635 error = sdhc_transfer_data_dma(hp, cmd); 1636 } 1637 } else 1638 error = sdhc_transfer_data_pio(hp, cmd); 1639 if (error) 1640 cmd->c_error = error; 1641 SET(cmd->c_flags, SCF_ITSDONE); 1642 1643 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1644 HDEVNAME(hp), cmd->c_error)); 1645 } 1646 1647 static int 1648 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1649 { 1650 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1651 bus_addr_t posaddr; 1652 bus_addr_t segaddr; 1653 bus_size_t seglen; 1654 u_int seg = 0; 1655 int error = 0; 1656 int status; 1657 1658 KASSERT(mutex_owned(&hp->intr_lock)); 1659 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1660 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1661 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1662 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1663 1664 for (;;) { 1665 status = sdhc_wait_intr(hp, 1666 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1667 SDHC_DMA_TIMEOUT); 1668 1669 if (status & SDHC_TRANSFER_COMPLETE) { 1670 break; 1671 } 1672 if (!status) { 1673 error = ETIMEDOUT; 1674 break; 1675 } 1676 1677 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1678 continue; 1679 } 1680 1681 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1682 continue; 1683 } 1684 1685 /* DMA Interrupt (boundary crossing) */ 1686 1687 segaddr = dm_segs[seg].ds_addr; 1688 seglen = dm_segs[seg].ds_len; 1689 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1690 1691 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1692 continue; 1693 } 1694 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1695 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1696 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1697 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1698 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1699 } 1700 1701 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1702 bus_dmamap_sync(hp->sc->sc_dmat, hp->adma_map, 0, 1703 PAGE_SIZE, BUS_DMASYNC_POSTWRITE); 1704 } 1705 1706 return error; 1707 } 1708 1709 static int 1710 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1711 { 1712 uint8_t *data = cmd->c_data; 1713 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1714 u_int len, datalen; 1715 u_int imask; 1716 u_int pmask; 1717 int error = 0; 1718 1719 KASSERT(mutex_owned(&hp->intr_lock)); 1720 1721 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1722 imask = SDHC_BUFFER_READ_READY; 1723 pmask = SDHC_BUFFER_READ_ENABLE; 1724 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1725 pio_func = esdhc_read_data_pio; 1726 } else { 1727 pio_func = sdhc_read_data_pio; 1728 } 1729 } else { 1730 imask = SDHC_BUFFER_WRITE_READY; 1731 pmask = SDHC_BUFFER_WRITE_ENABLE; 1732 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1733 pio_func = esdhc_write_data_pio; 1734 } else { 1735 pio_func = sdhc_write_data_pio; 1736 } 1737 } 1738 datalen = cmd->c_datalen; 1739 1740 KASSERT(mutex_owned(&hp->intr_lock)); 1741 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1742 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1743 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1744 1745 while (datalen > 0) { 1746 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1747 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1748 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1749 } else { 1750 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1751 } 1752 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1753 error = ETIMEDOUT; 1754 break; 1755 } 1756 1757 error = sdhc_wait_state(hp, pmask, pmask); 1758 if (error) 1759 break; 1760 } 1761 1762 len = MIN(datalen, cmd->c_blklen); 1763 (*pio_func)(hp, data, len); 1764 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1765 HDEVNAME(hp), len, data)); 1766 1767 data += len; 1768 datalen -= len; 1769 } 1770 1771 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1772 SDHC_TRANSFER_TIMEOUT)) 1773 error = ETIMEDOUT; 1774 1775 return error; 1776 } 1777 1778 static void 1779 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1780 { 1781 1782 if (((__uintptr_t)data & 3) == 0) { 1783 while (datalen > 3) { 1784 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1785 data += 4; 1786 datalen -= 4; 1787 } 1788 if (datalen > 1) { 1789 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1790 data += 2; 1791 datalen -= 2; 1792 } 1793 if (datalen > 0) { 1794 *data = HREAD1(hp, SDHC_DATA); 1795 data += 1; 1796 datalen -= 1; 1797 } 1798 } else if (((__uintptr_t)data & 1) == 0) { 1799 while (datalen > 1) { 1800 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1801 data += 2; 1802 datalen -= 2; 1803 } 1804 if (datalen > 0) { 1805 *data = HREAD1(hp, SDHC_DATA); 1806 data += 1; 1807 datalen -= 1; 1808 } 1809 } else { 1810 while (datalen > 0) { 1811 *data = HREAD1(hp, SDHC_DATA); 1812 data += 1; 1813 datalen -= 1; 1814 } 1815 } 1816 } 1817 1818 static void 1819 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1820 { 1821 1822 if (((__uintptr_t)data & 3) == 0) { 1823 while (datalen > 3) { 1824 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 1825 data += 4; 1826 datalen -= 4; 1827 } 1828 if (datalen > 1) { 1829 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1830 data += 2; 1831 datalen -= 2; 1832 } 1833 if (datalen > 0) { 1834 HWRITE1(hp, SDHC_DATA, *data); 1835 data += 1; 1836 datalen -= 1; 1837 } 1838 } else if (((__uintptr_t)data & 1) == 0) { 1839 while (datalen > 1) { 1840 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1841 data += 2; 1842 datalen -= 2; 1843 } 1844 if (datalen > 0) { 1845 HWRITE1(hp, SDHC_DATA, *data); 1846 data += 1; 1847 datalen -= 1; 1848 } 1849 } else { 1850 while (datalen > 0) { 1851 HWRITE1(hp, SDHC_DATA, *data); 1852 data += 1; 1853 datalen -= 1; 1854 } 1855 } 1856 } 1857 1858 static void 1859 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1860 { 1861 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1862 uint32_t v; 1863 1864 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1865 size_t count = 0; 1866 1867 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1868 if (count == 0) { 1869 /* 1870 * If we've drained "watermark" words, we need to wait 1871 * a little bit so the read FIFO can refill. 1872 */ 1873 sdmmc_delay(10); 1874 count = watermark; 1875 } 1876 v = HREAD4(hp, SDHC_DATA); 1877 v = le32toh(v); 1878 *(uint32_t *)data = v; 1879 data += 4; 1880 datalen -= 4; 1881 status = HREAD2(hp, SDHC_NINTR_STATUS); 1882 count--; 1883 } 1884 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1885 if (count == 0) { 1886 sdmmc_delay(10); 1887 } 1888 v = HREAD4(hp, SDHC_DATA); 1889 v = le32toh(v); 1890 do { 1891 *data++ = v; 1892 v >>= 8; 1893 } while (--datalen > 0); 1894 } 1895 } 1896 1897 static void 1898 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1899 { 1900 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1901 uint32_t v; 1902 1903 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1904 size_t count = watermark; 1905 1906 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1907 if (count == 0) { 1908 sdmmc_delay(10); 1909 count = watermark; 1910 } 1911 v = *(uint32_t *)data; 1912 v = htole32(v); 1913 HWRITE4(hp, SDHC_DATA, v); 1914 data += 4; 1915 datalen -= 4; 1916 status = HREAD2(hp, SDHC_NINTR_STATUS); 1917 count--; 1918 } 1919 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1920 if (count == 0) { 1921 sdmmc_delay(10); 1922 } 1923 v = *(uint32_t *)data; 1924 v = htole32(v); 1925 HWRITE4(hp, SDHC_DATA, v); 1926 } 1927 } 1928 1929 /* Prepare for another command. */ 1930 static int 1931 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1932 { 1933 int timo; 1934 1935 KASSERT(mutex_owned(&hp->intr_lock)); 1936 1937 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1938 1939 /* Request the reset. */ 1940 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1941 1942 /* 1943 * If necessary, wait for the controller to set the bits to 1944 * acknowledge the reset. 1945 */ 1946 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 1947 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 1948 for (timo = 10000; timo > 0; timo--) { 1949 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1950 break; 1951 /* Short delay because I worry we may miss it... */ 1952 sdmmc_delay(1); 1953 } 1954 if (timo == 0) 1955 return ETIMEDOUT; 1956 } 1957 1958 /* 1959 * Wait for the controller to clear the bits to indicate that 1960 * the reset has completed. 1961 */ 1962 for (timo = 10; timo > 0; timo--) { 1963 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1964 break; 1965 sdmmc_delay(10000); 1966 } 1967 if (timo == 0) { 1968 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1969 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1970 return ETIMEDOUT; 1971 } 1972 1973 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1974 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1975 } 1976 1977 return 0; 1978 } 1979 1980 static int 1981 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1982 { 1983 int status; 1984 1985 KASSERT(mutex_owned(&hp->intr_lock)); 1986 1987 mask |= SDHC_ERROR_INTERRUPT; 1988 1989 status = hp->intr_status & mask; 1990 while (status == 0) { 1991 if (cv_timedwait(&hp->intr_cv, &hp->intr_lock, timo) 1992 == EWOULDBLOCK) { 1993 status |= SDHC_ERROR_INTERRUPT; 1994 break; 1995 } 1996 status = hp->intr_status & mask; 1997 } 1998 hp->intr_status &= ~status; 1999 2000 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 2001 hp->intr_error_status)); 2002 2003 /* Command timeout has higher priority than command complete. */ 2004 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 2005 hp->intr_error_status = 0; 2006 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 2007 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 2008 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 2009 } 2010 status = 0; 2011 } 2012 2013 return status; 2014 } 2015 2016 /* 2017 * Established by attachment driver at interrupt priority IPL_SDMMC. 2018 */ 2019 int 2020 sdhc_intr(void *arg) 2021 { 2022 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 2023 struct sdhc_host *hp; 2024 int done = 0; 2025 uint16_t status; 2026 uint16_t error; 2027 2028 /* We got an interrupt, but we don't know from which slot. */ 2029 for (size_t host = 0; host < sc->sc_nhosts; host++) { 2030 hp = sc->sc_host[host]; 2031 if (hp == NULL) 2032 continue; 2033 2034 mutex_enter(&hp->intr_lock); 2035 2036 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 2037 /* Find out which interrupts are pending. */ 2038 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 2039 status = xstatus; 2040 error = xstatus >> 16; 2041 if (error) 2042 xstatus |= SDHC_ERROR_INTERRUPT; 2043 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 2044 goto next_port; /* no interrupt for us */ 2045 /* Acknowledge the interrupts we are about to handle. */ 2046 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 2047 } else { 2048 /* Find out which interrupts are pending. */ 2049 error = 0; 2050 status = HREAD2(hp, SDHC_NINTR_STATUS); 2051 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 2052 goto next_port; /* no interrupt for us */ 2053 /* Acknowledge the interrupts we are about to handle. */ 2054 HWRITE2(hp, SDHC_NINTR_STATUS, status); 2055 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 2056 /* Acknowledge error interrupts. */ 2057 error = HREAD2(hp, SDHC_EINTR_STATUS); 2058 HWRITE2(hp, SDHC_EINTR_STATUS, error); 2059 } 2060 } 2061 2062 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 2063 status, error)); 2064 2065 /* Claim this interrupt. */ 2066 done = 1; 2067 2068 if (ISSET(error, SDHC_ADMA_ERROR)) { 2069 uint8_t adma_err = HREAD1(hp, SDHC_ADMA_ERROR_STATUS); 2070 printf("%s: ADMA error, status %02x\n", HDEVNAME(hp), 2071 adma_err); 2072 } 2073 2074 /* 2075 * Service error interrupts. 2076 */ 2077 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 2078 SDHC_DATA_TIMEOUT_ERROR)) { 2079 hp->intr_error_status |= error; 2080 hp->intr_status |= status; 2081 cv_broadcast(&hp->intr_cv); 2082 } 2083 2084 /* 2085 * Wake up the sdmmc event thread to scan for cards. 2086 */ 2087 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 2088 if (hp->sdmmc != NULL) { 2089 sdmmc_needs_discover(hp->sdmmc); 2090 } 2091 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 2092 HCLR4(hp, SDHC_NINTR_STATUS_EN, 2093 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 2094 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 2095 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 2096 } 2097 } 2098 2099 /* 2100 * Wake up the blocking process to service command 2101 * related interrupt(s). 2102 */ 2103 if (ISSET(status, SDHC_COMMAND_COMPLETE| 2104 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 2105 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 2106 hp->intr_status |= status; 2107 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 2108 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 2109 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 2110 } 2111 cv_broadcast(&hp->intr_cv); 2112 } 2113 2114 /* 2115 * Service SD card interrupts. 2116 */ 2117 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 2118 && ISSET(status, SDHC_CARD_INTERRUPT)) { 2119 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 2120 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 2121 sdmmc_card_intr(hp->sdmmc); 2122 } 2123 next_port: 2124 mutex_exit(&hp->intr_lock); 2125 } 2126 2127 return done; 2128 } 2129 2130 kmutex_t * 2131 sdhc_host_lock(struct sdhc_host *hp) 2132 { 2133 return &hp->intr_lock; 2134 } 2135 2136 #ifdef SDHC_DEBUG 2137 void 2138 sdhc_dump_regs(struct sdhc_host *hp) 2139 { 2140 2141 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 2142 HREAD4(hp, SDHC_PRESENT_STATE)); 2143 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 2144 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 2145 HREAD1(hp, SDHC_POWER_CTL)); 2146 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 2147 HREAD2(hp, SDHC_NINTR_STATUS)); 2148 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 2149 HREAD2(hp, SDHC_EINTR_STATUS)); 2150 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 2151 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 2152 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 2153 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 2154 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 2155 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 2156 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 2157 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 2158 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 2159 HREAD4(hp, SDHC_CAPABILITIES)); 2160 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 2161 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 2162 } 2163 #endif 2164
Indexes created Tue Sep 23 14:10:03 GMT 2025