sdhc.c revision 1.9.6.3
1 /* $NetBSD: sdhc.c,v 1.9.6.3 2012/03/04 00:46:27 mrg Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.9.6.3 2012/03/04 00:46:27 mrg Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/kthread.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/sdmmc/sdhcreg.h> 42 #include <dev/sdmmc/sdhcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #ifdef SDHC_DEBUG 48 int sdhcdebug = 1; 49 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50 void sdhc_dump_regs(struct sdhc_host *); 51 #else 52 #define DPRINTF(n,s) do {} while (0) 53 #endif 54 55 #define SDHC_COMMAND_TIMEOUT hz 56 #define SDHC_BUFFER_TIMEOUT hz 57 #define SDHC_TRANSFER_TIMEOUT hz 58 #define SDHC_DMA_TIMEOUT hz 59 60 struct sdhc_host { 61 struct sdhc_softc *sc; /* host controller device */ 62 63 bus_space_tag_t iot; /* host register set tag */ 64 bus_space_handle_t ioh; /* host register set handle */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 struct kmutex host_mtx; 70 71 u_int clkbase; /* base clock frequency in KHz */ 72 int maxblklen; /* maximum block length */ 73 uint32_t ocr; /* OCR value from capabilities */ 74 75 uint8_t regs[14]; /* host controller state */ 76 77 uint16_t intr_status; /* soft interrupt status */ 78 uint16_t intr_error_status; /* soft error status */ 79 struct kmutex intr_mtx; 80 struct kcondvar intr_cv; 81 82 int specver; /* spec. version */ 83 84 uint32_t flags; /* flags for this host */ 85 #define SHF_USE_DMA 0x0001 86 #define SHF_USE_4BIT_MODE 0x0002 87 #define SHF_USE_8BIT_MODE 0x0004 88 }; 89 90 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 91 92 static uint8_t 93 hread1(struct sdhc_host *hp, bus_size_t reg) 94 { 95 96 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 97 return bus_space_read_1(hp->iot, hp->ioh, reg); 98 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 99 } 100 101 static uint16_t 102 hread2(struct sdhc_host *hp, bus_size_t reg) 103 { 104 105 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 106 return bus_space_read_2(hp->iot, hp->ioh, reg); 107 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 108 } 109 110 #define HREAD1(hp, reg) hread1(hp, reg) 111 #define HREAD2(hp, reg) hread2(hp, reg) 112 #define HREAD4(hp, reg) \ 113 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 114 115 116 static void 117 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 118 { 119 120 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 121 bus_space_write_1(hp->iot, hp->ioh, o, val); 122 } else { 123 const size_t shift = 8 * (o & 3); 124 o &= -4; 125 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 126 tmp = (val << shift) | (tmp & ~(0xff << shift)); 127 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 128 } 129 } 130 131 static void 132 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 133 { 134 135 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 136 bus_space_write_2(hp->iot, hp->ioh, o, val); 137 } else { 138 const size_t shift = 8 * (o & 2); 139 o &= -4; 140 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 141 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 142 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 143 } 144 } 145 146 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 147 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 148 #define HWRITE4(hp, reg, val) \ 149 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 150 151 #define HCLR1(hp, reg, bits) \ 152 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 153 #define HCLR2(hp, reg, bits) \ 154 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 155 #define HCLR4(hp, reg, bits) \ 156 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 157 #define HSET1(hp, reg, bits) \ 158 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 159 #define HSET2(hp, reg, bits) \ 160 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 161 #define HSET4(hp, reg, bits) \ 162 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 163 164 static int sdhc_host_reset(sdmmc_chipset_handle_t); 165 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 166 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 167 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 168 static int sdhc_card_detect(sdmmc_chipset_handle_t); 169 static int sdhc_write_protect(sdmmc_chipset_handle_t); 170 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 171 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 172 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 173 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 174 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 175 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 176 static void sdhc_exec_command(sdmmc_chipset_handle_t, 177 struct sdmmc_command *); 178 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 179 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 180 static int sdhc_soft_reset(struct sdhc_host *, int); 181 static int sdhc_wait_intr(struct sdhc_host *, int, int); 182 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 183 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 184 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 185 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 186 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 187 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 188 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 189 190 191 static struct sdmmc_chip_functions sdhc_functions = { 192 /* host controller reset */ 193 sdhc_host_reset, 194 195 /* host controller capabilities */ 196 sdhc_host_ocr, 197 sdhc_host_maxblklen, 198 199 /* card detection */ 200 sdhc_card_detect, 201 202 /* write protect */ 203 sdhc_write_protect, 204 205 /* bus power, clock frequency and width */ 206 sdhc_bus_power, 207 sdhc_bus_clock, 208 sdhc_bus_width, 209 sdhc_bus_rod, 210 211 /* command execution */ 212 sdhc_exec_command, 213 214 /* card interrupt */ 215 sdhc_card_enable_intr, 216 sdhc_card_intr_ack 217 }; 218 219 /* 220 * Called by attachment driver. For each SD card slot there is one SD 221 * host controller standard register set. (1.3) 222 */ 223 int 224 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 225 bus_space_handle_t ioh, bus_size_t iosize) 226 { 227 struct sdmmcbus_attach_args saa; 228 struct sdhc_host *hp; 229 uint32_t caps; 230 uint16_t sdhcver; 231 232 sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 233 aprint_normal_dev(sc->sc_dev, "SD Host Specification "); 234 switch (SDHC_SPEC_VERSION(sdhcver)) { 235 case SDHC_SPEC_VERS_100: 236 aprint_normal("1.0"); 237 break; 238 239 case SDHC_SPEC_VERS_200: 240 aprint_normal("2.0"); 241 break; 242 243 case SDHC_SPEC_VERS_300: 244 aprint_normal("3.0"); 245 break; 246 247 default: 248 aprint_normal("unknown version(0x%x)", 249 SDHC_SPEC_VERSION(sdhcver)); 250 break; 251 } 252 aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver)); 253 254 /* Allocate one more host structure. */ 255 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 256 if (hp == NULL) { 257 aprint_error_dev(sc->sc_dev, 258 "couldn't alloc memory (sdhc host)\n"); 259 goto err1; 260 } 261 sc->sc_host[sc->sc_nhosts++] = hp; 262 263 /* Fill in the new host structure. */ 264 hp->sc = sc; 265 hp->iot = iot; 266 hp->ioh = ioh; 267 hp->dmat = sc->sc_dmat; 268 hp->specver = SDHC_SPEC_VERSION(sdhcver); 269 270 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 271 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 272 cv_init(&hp->intr_cv, "sdhcintr"); 273 274 /* 275 * Reset the host controller and enable interrupts. 276 */ 277 (void)sdhc_host_reset(hp); 278 279 /* Determine host capabilities. */ 280 mutex_enter(&hp->host_mtx); 281 caps = HREAD4(hp, SDHC_CAPABILITIES); 282 mutex_exit(&hp->host_mtx); 283 284 #if notyet 285 /* Use DMA if the host system and the controller support it. */ 286 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) 287 || ((ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA) 288 && ISSET(caps, SDHC_DMA_SUPPORT)))) { 289 SET(hp->flags, SHF_USE_DMA); 290 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 291 } 292 #endif 293 294 /* 295 * Determine the base clock frequency. (2.2.24) 296 */ 297 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 298 if (hp->clkbase == 0) { 299 if (sc->sc_clkbase == 0) { 300 /* The attachment driver must tell us. */ 301 aprint_error_dev(sc->sc_dev, 302 "unknown base clock frequency\n"); 303 goto err; 304 } 305 hp->clkbase = sc->sc_clkbase; 306 } 307 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 308 /* SDHC 1.0 supports only 10-63 MHz. */ 309 aprint_error_dev(sc->sc_dev, 310 "base clock frequency out of range: %u MHz\n", 311 hp->clkbase / 1000); 312 goto err; 313 } 314 DPRINTF(1,("%s: base clock frequency %u MHz\n", 315 device_xname(sc->sc_dev), hp->clkbase / 1000)); 316 317 /* 318 * XXX Set the data timeout counter value according to 319 * capabilities. (2.2.15) 320 */ 321 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 322 #if 0 323 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 324 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 325 #endif 326 327 /* 328 * Determine SD bus voltage levels supported by the controller. 329 */ 330 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 331 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 332 } 333 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 334 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 335 } 336 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 337 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 338 } 339 340 /* 341 * Determine the maximum block length supported by the host 342 * controller. (2.2.24) 343 */ 344 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 345 case SDHC_MAX_BLK_LEN_512: 346 hp->maxblklen = 512; 347 break; 348 349 case SDHC_MAX_BLK_LEN_1024: 350 hp->maxblklen = 1024; 351 break; 352 353 case SDHC_MAX_BLK_LEN_2048: 354 hp->maxblklen = 2048; 355 break; 356 357 case SDHC_MAX_BLK_LEN_4096: 358 hp->maxblklen = 4096; 359 break; 360 361 default: 362 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 363 goto err; 364 } 365 DPRINTF(1, ("%s: max block length %u byte%s\n", 366 device_xname(sc->sc_dev), hp->maxblklen, 367 hp->maxblklen > 1 ? "s" : "")); 368 369 /* 370 * Attach the generic SD/MMC bus driver. (The bus driver must 371 * not invoke any chipset functions before it is attached.) 372 */ 373 memset(&saa, 0, sizeof(saa)); 374 saa.saa_busname = "sdmmc"; 375 saa.saa_sct = &sdhc_functions; 376 saa.saa_sch = hp; 377 saa.saa_dmat = hp->dmat; 378 saa.saa_clkmin = hp->clkbase / 256; 379 saa.saa_clkmax = hp->clkbase; 380 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 381 saa.saa_clkmin /= 2046; 382 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 383 saa.saa_clkmin /= 16; 384 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 385 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 386 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 387 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 388 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 389 #if notyet 390 if (ISSET(hp->flags, SHF_USE_DMA)) 391 saa.saa_caps |= SMC_CAPS_DMA; 392 #endif 393 hp->sdmmc = config_found(sc->sc_dev, &saa, NULL); 394 395 return 0; 396 397 err: 398 cv_destroy(&hp->intr_cv); 399 mutex_destroy(&hp->intr_mtx); 400 mutex_destroy(&hp->host_mtx); 401 free(hp, M_DEVBUF); 402 sc->sc_host[--sc->sc_nhosts] = NULL; 403 err1: 404 return 1; 405 } 406 407 int 408 sdhc_detach(device_t dev, int flags) 409 { 410 struct sdhc_host *hp = (struct sdhc_host *)dev; 411 struct sdhc_softc *sc = hp->sc; 412 int rv = 0; 413 414 if (hp->sdmmc) 415 rv = config_detach(hp->sdmmc, flags); 416 417 cv_destroy(&hp->intr_cv); 418 mutex_destroy(&hp->intr_mtx); 419 mutex_destroy(&hp->host_mtx); 420 free(hp, M_DEVBUF); 421 sc->sc_host[--sc->sc_nhosts] = NULL; 422 423 return rv; 424 } 425 426 bool 427 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 428 { 429 struct sdhc_softc *sc = device_private(dev); 430 struct sdhc_host *hp; 431 size_t i; 432 433 /* XXX poll for command completion or suspend command 434 * in progress */ 435 436 /* Save the host controller state. */ 437 for (size_t n = 0; n < sc->sc_nhosts; n++) { 438 hp = sc->sc_host[n]; 439 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 440 for (i = 0; i < sizeof hp->regs; i += 4) { 441 uint32_t v = HREAD4(hp, i); 442 hp->regs[i + 0] = (v >> 0); 443 hp->regs[i + 1] = (v >> 8); 444 hp->regs[i + 2] = (v >> 16); 445 hp->regs[i + 3] = (v >> 24); 446 } 447 } else { 448 for (i = 0; i < sizeof hp->regs; i++) { 449 hp->regs[i] = HREAD1(hp, i); 450 } 451 } 452 } 453 return true; 454 } 455 456 bool 457 sdhc_resume(device_t dev, const pmf_qual_t *qual) 458 { 459 struct sdhc_softc *sc = device_private(dev); 460 struct sdhc_host *hp; 461 size_t i; 462 463 /* Restore the host controller state. */ 464 for (size_t n = 0; n < sc->sc_nhosts; n++) { 465 hp = sc->sc_host[n]; 466 (void)sdhc_host_reset(hp); 467 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 468 for (i = 0; i < sizeof hp->regs; i += 4) { 469 HWRITE4(hp, i, 470 (hp->regs[i + 0] << 0) 471 | (hp->regs[i + 1] << 8) 472 | (hp->regs[i + 2] << 16) 473 | (hp->regs[i + 3] << 24)); 474 } 475 } else { 476 for (i = 0; i < sizeof hp->regs; i++) { 477 HWRITE1(hp, i, hp->regs[i]); 478 } 479 } 480 } 481 return true; 482 } 483 484 bool 485 sdhc_shutdown(device_t dev, int flags) 486 { 487 struct sdhc_softc *sc = device_private(dev); 488 struct sdhc_host *hp; 489 490 /* XXX chip locks up if we don't disable it before reboot. */ 491 for (size_t i = 0; i < sc->sc_nhosts; i++) { 492 hp = sc->sc_host[i]; 493 (void)sdhc_host_reset(hp); 494 } 495 return true; 496 } 497 498 /* 499 * Reset the host controller. Called during initialization, when 500 * cards are removed, upon resume, and during error recovery. 501 */ 502 static int 503 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 504 { 505 struct sdhc_host *hp = (struct sdhc_host *)sch; 506 uint32_t sdhcimask; 507 int error; 508 509 /* Don't lock. */ 510 511 /* Disable all interrupts. */ 512 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 513 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 514 } else { 515 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 516 } 517 518 /* 519 * Reset the entire host controller and wait up to 100ms for 520 * the controller to clear the reset bit. 521 */ 522 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 523 if (error) 524 goto out; 525 526 /* Set data timeout counter value to max for now. */ 527 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 528 #if 0 529 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 530 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 531 #endif 532 533 /* Enable interrupts. */ 534 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 535 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 536 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 537 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 538 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 539 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 540 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 541 sdhcimask ^= 542 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 543 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 544 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 545 } else { 546 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 547 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 548 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 549 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 550 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 551 } 552 553 out: 554 return error; 555 } 556 557 static int 558 sdhc_host_reset(sdmmc_chipset_handle_t sch) 559 { 560 struct sdhc_host *hp = (struct sdhc_host *)sch; 561 int error; 562 563 mutex_enter(&hp->host_mtx); 564 error = sdhc_host_reset1(sch); 565 mutex_exit(&hp->host_mtx); 566 567 return error; 568 } 569 570 static uint32_t 571 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 572 { 573 struct sdhc_host *hp = (struct sdhc_host *)sch; 574 575 return hp->ocr; 576 } 577 578 static int 579 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 580 { 581 struct sdhc_host *hp = (struct sdhc_host *)sch; 582 583 return hp->maxblklen; 584 } 585 586 /* 587 * Return non-zero if the card is currently inserted. 588 */ 589 static int 590 sdhc_card_detect(sdmmc_chipset_handle_t sch) 591 { 592 struct sdhc_host *hp = (struct sdhc_host *)sch; 593 int r; 594 595 mutex_enter(&hp->host_mtx); 596 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 597 mutex_exit(&hp->host_mtx); 598 599 return r ? 1 : 0; 600 } 601 602 /* 603 * Return non-zero if the card is currently write-protected. 604 */ 605 static int 606 sdhc_write_protect(sdmmc_chipset_handle_t sch) 607 { 608 struct sdhc_host *hp = (struct sdhc_host *)sch; 609 int r; 610 611 mutex_enter(&hp->host_mtx); 612 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 613 mutex_exit(&hp->host_mtx); 614 615 return r ? 0 : 1; 616 } 617 618 /* 619 * Set or change SD bus voltage and enable or disable SD bus power. 620 * Return zero on success. 621 */ 622 static int 623 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 624 { 625 struct sdhc_host *hp = (struct sdhc_host *)sch; 626 uint8_t vdd; 627 int error = 0; 628 629 mutex_enter(&hp->host_mtx); 630 631 /* 632 * Disable bus power before voltage change. 633 */ 634 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 635 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 636 HWRITE1(hp, SDHC_POWER_CTL, 0); 637 638 /* If power is disabled, reset the host and return now. */ 639 if (ocr == 0) { 640 (void)sdhc_host_reset1(hp); 641 goto out; 642 } 643 644 /* 645 * Select the lowest voltage according to capabilities. 646 */ 647 ocr &= hp->ocr; 648 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 649 vdd = SDHC_VOLTAGE_1_8V; 650 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 651 vdd = SDHC_VOLTAGE_3_0V; 652 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 653 vdd = SDHC_VOLTAGE_3_3V; 654 } else { 655 /* Unsupported voltage level requested. */ 656 error = EINVAL; 657 goto out; 658 } 659 660 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 661 /* 662 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 663 * voltage ramp until power rises. 664 */ 665 HWRITE1(hp, SDHC_POWER_CTL, 666 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 667 sdmmc_delay(10000); 668 669 /* 670 * The host system may not power the bus due to battery low, 671 * etc. In that case, the host controller should clear the 672 * bus power bit. 673 */ 674 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 675 error = ENXIO; 676 goto out; 677 } 678 } 679 680 out: 681 mutex_exit(&hp->host_mtx); 682 683 return error; 684 } 685 686 /* 687 * Return the smallest possible base clock frequency divisor value 688 * for the CLOCK_CTL register to produce `freq' (KHz). 689 */ 690 static bool 691 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 692 { 693 u_int div; 694 695 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 696 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 697 if ((hp->clkbase / div) <= freq) { 698 *divp = SDHC_SDCLK_CGM 699 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 700 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 701 return true; 702 } 703 } 704 /* No divisor found. */ 705 return false; 706 } 707 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 708 u_int dvs = (hp->clkbase + freq - 1) / freq; 709 u_int roundup = dvs & 1; 710 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 711 if (dvs + roundup <= 16) { 712 dvs += roundup - 1; 713 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 714 | (dvs << SDHC_SDCLK_DVS_SHIFT); 715 DPRINTF(2, 716 ("%s: divisor for freq %u is %u * %u\n", 717 HDEVNAME(hp), freq, div * 2, dvs + 1)); 718 return true; 719 } 720 /* 721 * If we drop bits, we need to round up the divisor. 722 */ 723 roundup |= dvs & 1; 724 } 725 panic("%s: can't find divisor for freq %u", HDEVNAME(hp), freq); 726 } else { 727 for (div = 1; div <= 256; div *= 2) { 728 if ((hp->clkbase / div) <= freq) { 729 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 730 return true; 731 } 732 } 733 } 734 /* No divisor found. */ 735 return false; 736 } 737 738 /* 739 * Set or change SDCLK frequency or disable the SD clock. 740 * Return zero on success. 741 */ 742 static int 743 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 744 { 745 struct sdhc_host *hp = (struct sdhc_host *)sch; 746 u_int div; 747 u_int timo; 748 int error = 0; 749 #ifdef DIAGNOSTIC 750 bool present; 751 752 mutex_enter(&hp->host_mtx); 753 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 754 mutex_exit(&hp->host_mtx); 755 756 /* Must not stop the clock if commands are in progress. */ 757 if (present && sdhc_card_detect(hp)) { 758 printf("%s: sdhc_sdclk_frequency_select: command in progress\n", 759 device_xname(hp->sc->sc_dev)); 760 } 761 #endif 762 763 mutex_enter(&hp->host_mtx); 764 765 /* 766 * Stop SD clock before changing the frequency. 767 */ 768 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 769 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 770 if (freq == SDMMC_SDCLK_OFF) { 771 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 772 goto out; 773 } 774 } else { 775 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 776 if (freq == SDMMC_SDCLK_OFF) 777 goto out; 778 } 779 780 /* 781 * Set the minimum base clock frequency divisor. 782 */ 783 if (!sdhc_clock_divisor(hp, freq, &div)) { 784 /* Invalid base clock frequency or `freq' value. */ 785 error = EINVAL; 786 goto out; 787 } 788 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 789 HWRITE4(hp, SDHC_CLOCK_CTL, 790 div | (SDHC_TIMEOUT_MAX << 16)); 791 } else { 792 HWRITE2(hp, SDHC_CLOCK_CTL, div); 793 } 794 795 /* 796 * Start internal clock. Wait 10ms for stabilization. 797 */ 798 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 799 sdmmc_delay(10000); 800 HSET4(hp, SDHC_CLOCK_CTL, 801 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 802 } else { 803 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 804 for (timo = 1000; timo > 0; timo--) { 805 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 806 SDHC_INTCLK_STABLE)) 807 break; 808 sdmmc_delay(10); 809 } 810 if (timo == 0) { 811 error = ETIMEDOUT; 812 goto out; 813 } 814 } 815 816 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 817 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 818 /* 819 * Sending 80 clocks at 400kHz takes 200us. 820 * So delay for that time + slop and then 821 * check a few times for completion. 822 */ 823 sdmmc_delay(210); 824 for (timo = 10; timo > 0; timo--) { 825 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 826 SDHC_INIT_ACTIVE)) 827 break; 828 sdmmc_delay(10); 829 } 830 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 831 832 /* 833 * Enable SD clock. 834 */ 835 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 836 } else { 837 /* 838 * Enable SD clock. 839 */ 840 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 841 842 if (freq > 25000) 843 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 844 else 845 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 846 } 847 848 out: 849 mutex_exit(&hp->host_mtx); 850 851 return error; 852 } 853 854 static int 855 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 856 { 857 struct sdhc_host *hp = (struct sdhc_host *)sch; 858 int reg; 859 860 switch (width) { 861 case 1: 862 case 4: 863 break; 864 865 case 8: 866 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 867 break; 868 /* FALLTHROUGH */ 869 default: 870 DPRINTF(0,("%s: unsupported bus width (%d)\n", 871 HDEVNAME(hp), width)); 872 return 1; 873 } 874 875 mutex_enter(&hp->host_mtx); 876 reg = HREAD1(hp, SDHC_HOST_CTL); 877 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 878 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 879 if (width == 4) 880 reg |= SDHC_4BIT_MODE; 881 else if (width == 8) 882 reg |= SDHC_ESDHC_8BIT_MODE; 883 } else { 884 reg &= ~SDHC_4BIT_MODE; 885 if (width == 4) 886 reg |= SDHC_4BIT_MODE; 887 } 888 HWRITE1(hp, SDHC_HOST_CTL, reg); 889 mutex_exit(&hp->host_mtx); 890 891 return 0; 892 } 893 894 static int 895 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 896 { 897 898 /* Nothing ?? */ 899 return 0; 900 } 901 902 static void 903 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 904 { 905 struct sdhc_host *hp = (struct sdhc_host *)sch; 906 907 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 908 mutex_enter(&hp->host_mtx); 909 if (enable) { 910 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 911 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 912 } else { 913 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 914 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 915 } 916 mutex_exit(&hp->host_mtx); 917 } 918 } 919 920 static void 921 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 922 { 923 struct sdhc_host *hp = (struct sdhc_host *)sch; 924 925 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 926 mutex_enter(&hp->host_mtx); 927 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 928 mutex_exit(&hp->host_mtx); 929 } 930 } 931 932 static int 933 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 934 { 935 uint32_t state; 936 int timeout; 937 938 for (timeout = 10; timeout > 0; timeout--) { 939 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 940 return 0; 941 sdmmc_delay(10000); 942 } 943 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 944 value, state)); 945 return ETIMEDOUT; 946 } 947 948 static void 949 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 950 { 951 struct sdhc_host *hp = (struct sdhc_host *)sch; 952 int error; 953 954 #if 0 955 if (cmd->c_data) { 956 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 957 if (ISSET(hp->flags, SHF_USE_DMA)) { 958 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 959 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 960 } else { 961 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 962 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 963 } 964 } 965 #endif 966 967 /* 968 * Start the MMC command, or mark `cmd' as failed and return. 969 */ 970 error = sdhc_start_command(hp, cmd); 971 if (error) { 972 cmd->c_error = error; 973 goto out; 974 } 975 976 /* 977 * Wait until the command phase is done, or until the command 978 * is marked done for any other reason. 979 */ 980 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 981 cmd->c_error = ETIMEDOUT; 982 goto out; 983 } 984 985 /* 986 * The host controller removes bits [0:7] from the response 987 * data (CRC) and we pass the data up unchanged to the bus 988 * driver (without padding). 989 */ 990 mutex_enter(&hp->host_mtx); 991 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 992 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 993 uint8_t *p = (uint8_t *)cmd->c_resp; 994 int i; 995 996 for (i = 0; i < 15; i++) 997 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 998 } else { 999 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 1000 } 1001 } 1002 mutex_exit(&hp->host_mtx); 1003 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1004 1005 /* 1006 * If the command has data to transfer in any direction, 1007 * execute the transfer now. 1008 */ 1009 if (cmd->c_error == 0 && cmd->c_data != NULL) 1010 sdhc_transfer_data(hp, cmd); 1011 1012 out: 1013 #if 0 1014 if (cmd->c_dmamap != NULL && cmd->c_error == 0 1015 && ISSET(hp->flags, SHF_USE_DMA) 1016 && ISSET(cmd->c_flags, SCF_CMD_READ) { 1017 if (((uintptr_t)cmd->c_data & PAGE_MASK) + cmd->c_datalen > PAGE_SIZE) { 1018 memcpy(cmd->c_data, 1019 (void *)hp->sc->dma_map->dm_segs[0].ds_addr, 1020 cmd->c_datalen); 1021 } 1022 bus_dmamap_unload(hp->sc->dt, hp->sc->dma_map); 1023 } 1024 #endif 1025 1026 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1027 mutex_enter(&hp->host_mtx); 1028 /* Turn off the LED. */ 1029 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1030 mutex_exit(&hp->host_mtx); 1031 } 1032 SET(cmd->c_flags, SCF_ITSDONE); 1033 1034 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1035 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1036 cmd->c_flags, cmd->c_error)); 1037 } 1038 1039 static int 1040 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1041 { 1042 struct sdhc_softc * const sc = hp->sc; 1043 uint16_t blksize = 0; 1044 uint16_t blkcount = 0; 1045 uint16_t mode; 1046 uint16_t command; 1047 int error; 1048 1049 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1050 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1051 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1052 1053 /* 1054 * The maximum block length for commands should be the minimum 1055 * of the host buffer size and the card buffer size. (1.7.2) 1056 */ 1057 1058 /* Fragment the data into proper blocks. */ 1059 if (cmd->c_datalen > 0) { 1060 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1061 blkcount = cmd->c_datalen / blksize; 1062 if (cmd->c_datalen % blksize > 0) { 1063 /* XXX: Split this command. (1.7.4) */ 1064 aprint_error_dev(sc->sc_dev, 1065 "data not a multiple of %u bytes\n", blksize); 1066 return EINVAL; 1067 } 1068 } 1069 1070 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1071 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1072 aprint_error_dev(sc->sc_dev, "too much data\n"); 1073 return EINVAL; 1074 } 1075 1076 /* Prepare transfer mode register value. (2.2.5) */ 1077 mode = 0; 1078 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1079 mode |= SDHC_READ_MODE; 1080 if (blkcount > 0) { 1081 mode |= SDHC_BLOCK_COUNT_ENABLE; 1082 if (blkcount > 1) { 1083 mode |= SDHC_MULTI_BLOCK_MODE; 1084 /* XXX only for memory commands? */ 1085 mode |= SDHC_AUTO_CMD12_ENABLE; 1086 } 1087 } 1088 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0) { 1089 if (cmd->c_dmamap->dm_nsegs == 1) { 1090 mode |= SDHC_DMA_ENABLE; 1091 } else { 1092 cmd->c_dmamap = NULL; 1093 } 1094 } 1095 1096 /* 1097 * Prepare command register value. (2.2.6) 1098 */ 1099 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1100 1101 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1102 command |= SDHC_CRC_CHECK_ENABLE; 1103 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1104 command |= SDHC_INDEX_CHECK_ENABLE; 1105 if (cmd->c_data != NULL) 1106 command |= SDHC_DATA_PRESENT_SELECT; 1107 1108 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1109 command |= SDHC_NO_RESPONSE; 1110 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1111 command |= SDHC_RESP_LEN_136; 1112 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1113 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1114 else 1115 command |= SDHC_RESP_LEN_48; 1116 1117 /* Wait until command and data inhibit bits are clear. (1.5) */ 1118 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1119 if (error) 1120 return error; 1121 1122 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1123 HDEVNAME(hp), blksize, blkcount, mode, command)); 1124 1125 mutex_enter(&hp->host_mtx); 1126 1127 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1128 /* Alert the user not to remove the card. */ 1129 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1130 } 1131 1132 /* Set DMA start address. */ 1133 if (ISSET(mode, SDHC_DMA_ENABLE)) 1134 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1135 1136 /* 1137 * Start a CPU data transfer. Writing to the high order byte 1138 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1139 */ 1140 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1141 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1142 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1143 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1144 } else { 1145 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1146 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1147 if (blkcount > 1) 1148 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1149 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1150 HWRITE2(hp, SDHC_COMMAND, command); 1151 } 1152 1153 mutex_exit(&hp->host_mtx); 1154 1155 return 0; 1156 } 1157 1158 static void 1159 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1160 { 1161 int error; 1162 1163 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1164 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1165 1166 #ifdef SDHC_DEBUG 1167 /* XXX I forgot why I wanted to know when this happens :-( */ 1168 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1169 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1170 aprint_error_dev(hp->sc->sc_dev, 1171 "CMD52/53 error response flags %#x\n", 1172 MMC_R1(cmd->c_resp) & 0xff00); 1173 } 1174 #endif 1175 1176 if (cmd->c_dmamap != NULL) 1177 error = sdhc_transfer_data_dma(hp, cmd); 1178 else 1179 error = sdhc_transfer_data_pio(hp, cmd); 1180 if (error) 1181 cmd->c_error = error; 1182 SET(cmd->c_flags, SCF_ITSDONE); 1183 1184 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1185 HDEVNAME(hp), cmd->c_error)); 1186 } 1187 1188 static int 1189 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1190 { 1191 bus_dmamap_t dmap = cmd->c_dmamap; 1192 uint16_t blklen = cmd->c_blklen; 1193 uint16_t blkcnt = cmd->c_datalen / blklen; 1194 uint16_t remain; 1195 int error = 0; 1196 1197 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1198 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1199 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1200 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1201 1202 for (;;) { 1203 if (!sdhc_wait_intr(hp, 1204 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1205 SDHC_DMA_TIMEOUT)) { 1206 error = ETIMEDOUT; 1207 break; 1208 } 1209 1210 /* single block mode */ 1211 if (blkcnt == 1) 1212 break; 1213 1214 /* multi block mode */ 1215 remain = HREAD2(hp, SDHC_BLOCK_COUNT); 1216 if (remain == 0) 1217 break; 1218 1219 HWRITE4(hp, SDHC_DMA_ADDR, 1220 dmap->dm_segs[0].ds_addr + (blkcnt - remain) * blklen); 1221 } 1222 1223 #if 0 1224 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1225 SDHC_TRANSFER_TIMEOUT)) 1226 error = ETIMEDOUT; 1227 #endif 1228 1229 return error; 1230 } 1231 1232 static int 1233 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1234 { 1235 uint8_t *data = cmd->c_data; 1236 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1237 u_int len, datalen; 1238 u_int imask; 1239 u_int pmask; 1240 int error = 0; 1241 1242 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1243 imask = SDHC_BUFFER_READ_READY; 1244 pmask = SDHC_BUFFER_READ_ENABLE; 1245 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1246 pio_func = esdhc_read_data_pio; 1247 } else { 1248 pio_func = sdhc_read_data_pio; 1249 } 1250 } else { 1251 imask = SDHC_BUFFER_WRITE_READY; 1252 pmask = SDHC_BUFFER_WRITE_ENABLE; 1253 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1254 pio_func = esdhc_write_data_pio; 1255 } else { 1256 pio_func = sdhc_write_data_pio; 1257 } 1258 } 1259 datalen = cmd->c_datalen; 1260 1261 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1262 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1263 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1264 1265 while (datalen > 0) { 1266 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1267 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1268 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1269 } else { 1270 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1271 } 1272 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1273 error = ETIMEDOUT; 1274 break; 1275 } 1276 1277 error = sdhc_wait_state(hp, pmask, pmask); 1278 if (error) 1279 break; 1280 } 1281 1282 len = MIN(datalen, cmd->c_blklen); 1283 (*pio_func)(hp, data, len); 1284 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1285 HDEVNAME(hp), len, data)); 1286 1287 data += len; 1288 datalen -= len; 1289 } 1290 1291 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1292 SDHC_TRANSFER_TIMEOUT)) 1293 error = ETIMEDOUT; 1294 1295 return error; 1296 } 1297 1298 static void 1299 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1300 { 1301 1302 if (((__uintptr_t)data & 3) == 0) { 1303 while (datalen > 3) { 1304 *(uint32_t *)data = HREAD4(hp, SDHC_DATA); 1305 data += 4; 1306 datalen -= 4; 1307 } 1308 if (datalen > 1) { 1309 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1310 data += 2; 1311 datalen -= 2; 1312 } 1313 if (datalen > 0) { 1314 *data = HREAD1(hp, SDHC_DATA); 1315 data += 1; 1316 datalen -= 1; 1317 } 1318 } else if (((__uintptr_t)data & 1) == 0) { 1319 while (datalen > 1) { 1320 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1321 data += 2; 1322 datalen -= 2; 1323 } 1324 if (datalen > 0) { 1325 *data = HREAD1(hp, SDHC_DATA); 1326 data += 1; 1327 datalen -= 1; 1328 } 1329 } else { 1330 while (datalen > 0) { 1331 *data = HREAD1(hp, SDHC_DATA); 1332 data += 1; 1333 datalen -= 1; 1334 } 1335 } 1336 } 1337 1338 static void 1339 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1340 { 1341 1342 if (((__uintptr_t)data & 3) == 0) { 1343 while (datalen > 3) { 1344 HWRITE4(hp, SDHC_DATA, *(uint32_t *)data); 1345 data += 4; 1346 datalen -= 4; 1347 } 1348 if (datalen > 1) { 1349 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1350 data += 2; 1351 datalen -= 2; 1352 } 1353 if (datalen > 0) { 1354 HWRITE1(hp, SDHC_DATA, *data); 1355 data += 1; 1356 datalen -= 1; 1357 } 1358 } else if (((__uintptr_t)data & 1) == 0) { 1359 while (datalen > 1) { 1360 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1361 data += 2; 1362 datalen -= 2; 1363 } 1364 if (datalen > 0) { 1365 HWRITE1(hp, SDHC_DATA, *data); 1366 data += 1; 1367 datalen -= 1; 1368 } 1369 } else { 1370 while (datalen > 0) { 1371 HWRITE1(hp, SDHC_DATA, *data); 1372 data += 1; 1373 datalen -= 1; 1374 } 1375 } 1376 } 1377 1378 static void 1379 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1380 { 1381 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1382 uint32_t v; 1383 1384 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1385 v = HREAD4(hp, SDHC_DATA); 1386 v = le32toh(v); 1387 *(uint32_t *)data = v; 1388 data += 4; 1389 datalen -= 4; 1390 status = HREAD2(hp, SDHC_NINTR_STATUS); 1391 } 1392 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1393 v = HREAD4(hp, SDHC_DATA); 1394 v = le32toh(v); 1395 do { 1396 *data++ = v; 1397 v >>= 8; 1398 } while (--datalen > 0); 1399 } 1400 } 1401 1402 static void 1403 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1404 { 1405 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1406 uint32_t v; 1407 1408 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1409 v = *(uint32_t *)data; 1410 v = htole32(v); 1411 HWRITE4(hp, SDHC_DATA, v); 1412 data += 4; 1413 datalen -= 4; 1414 status = HREAD2(hp, SDHC_NINTR_STATUS); 1415 } 1416 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1417 v = *(uint32_t *)data; 1418 v = htole32(v); 1419 HWRITE4(hp, SDHC_DATA, v); 1420 } 1421 } 1422 1423 /* Prepare for another command. */ 1424 static int 1425 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1426 { 1427 int timo; 1428 1429 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1430 1431 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1432 for (timo = 10; timo > 0; timo--) { 1433 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1434 break; 1435 sdmmc_delay(10000); 1436 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1437 } 1438 if (timo == 0) { 1439 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1440 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1441 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1442 return ETIMEDOUT; 1443 } 1444 1445 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1446 HWRITE4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1447 } 1448 1449 return 0; 1450 } 1451 1452 static int 1453 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1454 { 1455 int status; 1456 1457 mask |= SDHC_ERROR_INTERRUPT; 1458 1459 mutex_enter(&hp->intr_mtx); 1460 status = hp->intr_status & mask; 1461 while (status == 0) { 1462 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1463 == EWOULDBLOCK) { 1464 status |= SDHC_ERROR_INTERRUPT; 1465 break; 1466 } 1467 status = hp->intr_status & mask; 1468 } 1469 hp->intr_status &= ~status; 1470 1471 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1472 hp->intr_error_status)); 1473 1474 /* Command timeout has higher priority than command complete. */ 1475 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1476 hp->intr_error_status = 0; 1477 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1478 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1479 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1480 } 1481 status = 0; 1482 } 1483 mutex_exit(&hp->intr_mtx); 1484 1485 return status; 1486 } 1487 1488 /* 1489 * Established by attachment driver at interrupt priority IPL_SDMMC. 1490 */ 1491 int 1492 sdhc_intr(void *arg) 1493 { 1494 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1495 struct sdhc_host *hp; 1496 int done = 0; 1497 uint16_t status; 1498 uint16_t error; 1499 1500 /* We got an interrupt, but we don't know from which slot. */ 1501 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1502 hp = sc->sc_host[host]; 1503 if (hp == NULL) 1504 continue; 1505 1506 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1507 /* Find out which interrupts are pending. */ 1508 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1509 status = xstatus; 1510 error = xstatus >> 16; 1511 status |= (error ? SDHC_ERROR_INTERRUPT : 0); 1512 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1513 continue; /* no interrupt for us */ 1514 /* Acknowledge the interrupts we are about to handle. */ 1515 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1516 } else { 1517 /* Find out which interrupts are pending. */ 1518 error = 0; 1519 status = HREAD2(hp, SDHC_NINTR_STATUS); 1520 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1521 continue; /* no interrupt for us */ 1522 /* Acknowledge the interrupts we are about to handle. */ 1523 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1524 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1525 /* Acknowledge error interrupts. */ 1526 error = HREAD2(hp, SDHC_EINTR_STATUS); 1527 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1528 } 1529 } 1530 1531 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1532 status, error)); 1533 1534 /* Claim this interrupt. */ 1535 done = 1; 1536 1537 /* 1538 * Service error interrupts. 1539 */ 1540 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1541 SDHC_DATA_TIMEOUT_ERROR)) { 1542 hp->intr_error_status |= error; 1543 hp->intr_status |= status; 1544 cv_broadcast(&hp->intr_cv); 1545 } 1546 1547 /* 1548 * Wake up the sdmmc event thread to scan for cards. 1549 */ 1550 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1551 sdmmc_needs_discover(hp->sdmmc); 1552 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1553 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1554 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1555 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1556 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1557 } 1558 } 1559 1560 /* 1561 * Wake up the blocking process to service command 1562 * related interrupt(s). 1563 */ 1564 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1565 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1566 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1567 hp->intr_status |= status; 1568 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1569 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1570 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1571 } 1572 cv_broadcast(&hp->intr_cv); 1573 } 1574 1575 /* 1576 * Service SD card interrupts. 1577 */ 1578 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1579 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1580 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1581 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1582 sdmmc_card_intr(hp->sdmmc); 1583 } 1584 } 1585 1586 return done; 1587 } 1588 1589 #ifdef SDHC_DEBUG 1590 void 1591 sdhc_dump_regs(struct sdhc_host *hp) 1592 { 1593 1594 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1595 HREAD4(hp, SDHC_PRESENT_STATE)); 1596 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1597 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1598 HREAD1(hp, SDHC_POWER_CTL)); 1599 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1600 HREAD2(hp, SDHC_NINTR_STATUS)); 1601 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1602 HREAD2(hp, SDHC_EINTR_STATUS)); 1603 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1604 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1605 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1606 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1607 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1608 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1609 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1610 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1611 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1612 HREAD4(hp, SDHC_CAPABILITIES)); 1613 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1614 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1615 } 1616 #endif 1617
Indexes created Sun Oct 19 19:09:49 GMT 2025