sdhc.c revision 1.96
1 /* $NetBSD: sdhc.c,v 1.96 2017/01/07 15:00:38 kiyohara Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.96 2017/01/07 15:00:38 kiyohara Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 #include <sys/atomic.h> 40 41 #include <dev/sdmmc/sdhcreg.h> 42 #include <dev/sdmmc/sdhcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #ifdef SDHC_DEBUG 48 int sdhcdebug = 1; 49 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50 void sdhc_dump_regs(struct sdhc_host *); 51 #else 52 #define DPRINTF(n,s) do {} while (0) 53 #endif 54 55 #define SDHC_COMMAND_TIMEOUT hz 56 #define SDHC_BUFFER_TIMEOUT hz 57 #define SDHC_TRANSFER_TIMEOUT hz 58 #define SDHC_DMA_TIMEOUT (hz*3) 59 #define SDHC_TUNING_TIMEOUT hz 60 61 struct sdhc_host { 62 struct sdhc_softc *sc; /* host controller device */ 63 64 bus_space_tag_t iot; /* host register set tag */ 65 bus_space_handle_t ioh; /* host register set handle */ 66 bus_size_t ios; /* host register space size */ 67 bus_dma_tag_t dmat; /* host DMA tag */ 68 69 device_t sdmmc; /* generic SD/MMC device */ 70 71 u_int clkbase; /* base clock frequency in KHz */ 72 int maxblklen; /* maximum block length */ 73 uint32_t ocr; /* OCR value from capabilities */ 74 75 uint8_t regs[14]; /* host controller state */ 76 77 uint16_t intr_status; /* soft interrupt status */ 78 uint16_t intr_error_status; /* soft error status */ 79 kmutex_t intr_lock; 80 kcondvar_t intr_cv; 81 82 callout_t tuning_timer; 83 int tuning_timing; 84 u_int tuning_timer_count; 85 u_int tuning_timer_pending; 86 87 int specver; /* spec. version */ 88 89 uint32_t flags; /* flags for this host */ 90 #define SHF_USE_DMA 0x0001 91 #define SHF_USE_4BIT_MODE 0x0002 92 #define SHF_USE_8BIT_MODE 0x0004 93 #define SHF_MODE_DMAEN 0x0008 /* needs SDHC_DMA_ENABLE in mode */ 94 #define SHF_USE_ADMA2_32 0x0010 95 #define SHF_USE_ADMA2_64 0x0020 96 #define SHF_USE_ADMA2_MASK 0x0030 97 98 bus_dmamap_t adma_map; 99 bus_dma_segment_t adma_segs[1]; 100 void *adma2; 101 }; 102 103 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 104 105 static uint8_t 106 hread1(struct sdhc_host *hp, bus_size_t reg) 107 { 108 109 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 110 return bus_space_read_1(hp->iot, hp->ioh, reg); 111 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 112 } 113 114 static uint16_t 115 hread2(struct sdhc_host *hp, bus_size_t reg) 116 { 117 118 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 119 return bus_space_read_2(hp->iot, hp->ioh, reg); 120 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 121 } 122 123 #define HREAD1(hp, reg) hread1(hp, reg) 124 #define HREAD2(hp, reg) hread2(hp, reg) 125 #define HREAD4(hp, reg) \ 126 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 127 128 129 static void 130 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 131 { 132 133 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 134 bus_space_write_1(hp->iot, hp->ioh, o, val); 135 } else { 136 const size_t shift = 8 * (o & 3); 137 o &= -4; 138 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 139 tmp = (val << shift) | (tmp & ~(0xff << shift)); 140 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 141 } 142 } 143 144 static void 145 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 146 { 147 148 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 149 bus_space_write_2(hp->iot, hp->ioh, o, val); 150 } else { 151 const size_t shift = 8 * (o & 2); 152 o &= -4; 153 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 154 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 155 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 156 } 157 } 158 159 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 160 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 161 #define HWRITE4(hp, reg, val) \ 162 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 163 164 #define HCLR1(hp, reg, bits) \ 165 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 166 #define HCLR2(hp, reg, bits) \ 167 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 168 #define HCLR4(hp, reg, bits) \ 169 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 170 #define HSET1(hp, reg, bits) \ 171 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 172 #define HSET2(hp, reg, bits) \ 173 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 174 #define HSET4(hp, reg, bits) \ 175 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 176 177 static int sdhc_host_reset(sdmmc_chipset_handle_t); 178 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 179 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 180 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 181 static int sdhc_card_detect(sdmmc_chipset_handle_t); 182 static int sdhc_write_protect(sdmmc_chipset_handle_t); 183 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 184 static int sdhc_bus_clock_ddr(sdmmc_chipset_handle_t, int, bool); 185 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 186 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 187 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 188 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 189 static void sdhc_exec_command(sdmmc_chipset_handle_t, 190 struct sdmmc_command *); 191 static int sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 192 static int sdhc_execute_tuning1(struct sdhc_host *, int); 193 static int sdhc_execute_tuning(sdmmc_chipset_handle_t, int); 194 static void sdhc_tuning_timer(void *); 195 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 196 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 197 static int sdhc_soft_reset(struct sdhc_host *, int); 198 static int sdhc_wait_intr(struct sdhc_host *, int, int, bool); 199 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 200 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 201 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 202 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 203 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 204 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 205 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 206 207 static struct sdmmc_chip_functions sdhc_functions = { 208 /* host controller reset */ 209 .host_reset = sdhc_host_reset, 210 211 /* host controller capabilities */ 212 .host_ocr = sdhc_host_ocr, 213 .host_maxblklen = sdhc_host_maxblklen, 214 215 /* card detection */ 216 .card_detect = sdhc_card_detect, 217 218 /* write protect */ 219 .write_protect = sdhc_write_protect, 220 221 /* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */ 222 .bus_power = sdhc_bus_power, 223 .bus_clock = NULL, /* see sdhc_bus_clock_ddr */ 224 .bus_width = sdhc_bus_width, 225 .bus_rod = sdhc_bus_rod, 226 227 /* command execution */ 228 .exec_command = sdhc_exec_command, 229 230 /* card interrupt */ 231 .card_enable_intr = sdhc_card_enable_intr, 232 .card_intr_ack = sdhc_card_intr_ack, 233 234 /* UHS functions */ 235 .signal_voltage = sdhc_signal_voltage, 236 .bus_clock_ddr = sdhc_bus_clock_ddr, 237 .execute_tuning = sdhc_execute_tuning, 238 }; 239 240 static int 241 sdhc_cfprint(void *aux, const char *pnp) 242 { 243 const struct sdmmcbus_attach_args * const saa = aux; 244 const struct sdhc_host * const hp = saa->saa_sch; 245 246 if (pnp) { 247 aprint_normal("sdmmc at %s", pnp); 248 } 249 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 250 if (hp->sc->sc_host[host] == hp) { 251 aprint_normal(" slot %zu", host); 252 } 253 } 254 255 return UNCONF; 256 } 257 258 /* 259 * Called by attachment driver. For each SD card slot there is one SD 260 * host controller standard register set. (1.3) 261 */ 262 int 263 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 264 bus_space_handle_t ioh, bus_size_t iosize) 265 { 266 struct sdmmcbus_attach_args saa; 267 struct sdhc_host *hp; 268 uint32_t caps, caps2; 269 uint16_t sdhcver; 270 int error; 271 272 /* Allocate one more host structure. */ 273 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 274 if (hp == NULL) { 275 aprint_error_dev(sc->sc_dev, 276 "couldn't alloc memory (sdhc host)\n"); 277 goto err1; 278 } 279 sc->sc_host[sc->sc_nhosts++] = hp; 280 281 /* Fill in the new host structure. */ 282 hp->sc = sc; 283 hp->iot = iot; 284 hp->ioh = ioh; 285 hp->ios = iosize; 286 hp->dmat = sc->sc_dmat; 287 288 mutex_init(&hp->intr_lock, MUTEX_DEFAULT, IPL_SDMMC); 289 cv_init(&hp->intr_cv, "sdhcintr"); 290 callout_init(&hp->tuning_timer, CALLOUT_MPSAFE); 291 callout_setfunc(&hp->tuning_timer, sdhc_tuning_timer, hp); 292 293 if (iosize <= SDHC_HOST_CTL_VERSION) { 294 aprint_normal_dev(sc->sc_dev, "SDHC NO-VERS"); 295 hp->specver = -1; 296 } else { 297 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 298 sdhcver = SDHC_SPEC_VERS_300 << SDHC_SPEC_VERS_SHIFT; 299 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 300 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); 301 } else 302 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 303 aprint_normal_dev(sc->sc_dev, "SDHC "); 304 hp->specver = SDHC_SPEC_VERSION(sdhcver); 305 switch (SDHC_SPEC_VERSION(sdhcver)) { 306 case SDHC_SPEC_VERS_100: 307 aprint_normal("1.0"); 308 break; 309 310 case SDHC_SPEC_VERS_200: 311 aprint_normal("2.0"); 312 break; 313 314 case SDHC_SPEC_VERS_300: 315 aprint_normal("3.0"); 316 break; 317 318 case SDHC_SPEC_VERS_400: 319 aprint_normal("4.0"); 320 break; 321 322 default: 323 aprint_normal("unknown version(0x%x)", 324 SDHC_SPEC_VERSION(sdhcver)); 325 break; 326 } 327 aprint_normal(", rev %u", SDHC_VENDOR_VERSION(sdhcver)); 328 } 329 330 /* 331 * Reset the host controller and enable interrupts. 332 */ 333 (void)sdhc_host_reset(hp); 334 335 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 336 /* init uSDHC registers */ 337 HWRITE4(hp, SDHC_MMC_BOOT, 0); 338 HWRITE4(hp, SDHC_HOST_CTL, SDHC_USDHC_BURST_LEN_EN | 339 SDHC_USDHC_HOST_CTL_RESV23 | SDHC_USDHC_EMODE_LE); 340 HWRITE4(hp, SDHC_WATERMARK_LEVEL, 341 (0x10 << SDHC_WATERMARK_WR_BRST_SHIFT) | 342 (0x40 << SDHC_WATERMARK_WRITE_SHIFT) | 343 (0x10 << SDHC_WATERMARK_RD_BRST_SHIFT) | 344 (0x40 << SDHC_WATERMARK_READ_SHIFT)); 345 HSET4(hp, SDHC_VEND_SPEC, 346 SDHC_VEND_SPEC_MBO | 347 SDHC_VEND_SPEC_CARD_CLK_SOFT_EN | 348 SDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN | 349 SDHC_VEND_SPEC_HCLK_SOFT_EN | 350 SDHC_VEND_SPEC_IPG_CLK_SOFT_EN | 351 SDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN | 352 SDHC_VEND_SPEC_FRC_SDCLK_ON); 353 } 354 355 /* Determine host capabilities. */ 356 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 357 caps = sc->sc_caps; 358 caps2 = sc->sc_caps2; 359 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 360 /* uSDHC capability register is little bit different */ 361 caps = HREAD4(hp, SDHC_CAPABILITIES); 362 caps |= SDHC_8BIT_SUPP; 363 if (caps & SDHC_ADMA1_SUPP) 364 caps |= SDHC_ADMA2_SUPP; 365 sc->sc_caps = caps; 366 /* uSDHC has no SDHC_CAPABILITIES2 register */ 367 caps2 = sc->sc_caps2 = SDHC_SDR50_SUPP | SDHC_DDR50_SUPP; 368 } else { 369 caps = sc->sc_caps = HREAD4(hp, SDHC_CAPABILITIES); 370 if (hp->specver >= SDHC_SPEC_VERS_300) { 371 caps2 = sc->sc_caps2 = HREAD4(hp, SDHC_CAPABILITIES2); 372 } else { 373 caps2 = sc->sc_caps2 = 0; 374 } 375 } 376 377 const u_int retuning_mode = (caps2 >> SDHC_RETUNING_MODES_SHIFT) & 378 SDHC_RETUNING_MODES_MASK; 379 if (retuning_mode == SDHC_RETUNING_MODE_1) { 380 hp->tuning_timer_count = (caps2 >> SDHC_TIMER_COUNT_SHIFT) & 381 SDHC_TIMER_COUNT_MASK; 382 if (hp->tuning_timer_count == 0xf) 383 hp->tuning_timer_count = 0; 384 if (hp->tuning_timer_count) 385 hp->tuning_timer_count = 386 1 << (hp->tuning_timer_count - 1); 387 } 388 389 /* 390 * Use DMA if the host system and the controller support it. 391 * Suports integrated or external DMA egine, with or without 392 * SDHC_DMA_ENABLE in the command. 393 */ 394 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 395 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 396 ISSET(caps, SDHC_DMA_SUPPORT)))) { 397 SET(hp->flags, SHF_USE_DMA); 398 399 if (ISSET(sc->sc_flags, SDHC_FLAG_USE_ADMA2) && 400 ISSET(caps, SDHC_ADMA2_SUPP)) { 401 SET(hp->flags, SHF_MODE_DMAEN); 402 /* 403 * 64-bit mode was present in the 2.00 spec, removed 404 * from 3.00, and re-added in 4.00 with a different 405 * descriptor layout. We only support 2.00 and 3.00 406 * descriptors for now. 407 */ 408 if (hp->specver == SDHC_SPEC_VERS_200 && 409 ISSET(caps, SDHC_64BIT_SYS_BUS)) { 410 SET(hp->flags, SHF_USE_ADMA2_64); 411 aprint_normal(", 64-bit ADMA2"); 412 } else { 413 SET(hp->flags, SHF_USE_ADMA2_32); 414 aprint_normal(", 32-bit ADMA2"); 415 } 416 } else { 417 if (!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA) || 418 ISSET(sc->sc_flags, SDHC_FLAG_EXTDMA_DMAEN)) 419 SET(hp->flags, SHF_MODE_DMAEN); 420 if (sc->sc_vendor_transfer_data_dma) { 421 aprint_normal(", platform DMA"); 422 } else { 423 aprint_normal(", SDMA"); 424 } 425 } 426 } else { 427 aprint_normal(", PIO"); 428 } 429 430 /* 431 * Determine the base clock frequency. (2.2.24) 432 */ 433 if (hp->specver >= SDHC_SPEC_VERS_300) { 434 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 435 } else { 436 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 437 } 438 if (hp->clkbase == 0 || 439 ISSET(sc->sc_flags, SDHC_FLAG_NO_CLKBASE)) { 440 if (sc->sc_clkbase == 0) { 441 /* The attachment driver must tell us. */ 442 aprint_error_dev(sc->sc_dev, 443 "unknown base clock frequency\n"); 444 goto err; 445 } 446 hp->clkbase = sc->sc_clkbase; 447 } 448 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 449 /* SDHC 1.0 supports only 10-63 MHz. */ 450 aprint_error_dev(sc->sc_dev, 451 "base clock frequency out of range: %u MHz\n", 452 hp->clkbase / 1000); 453 goto err; 454 } 455 aprint_normal(", %u kHz", hp->clkbase); 456 457 /* 458 * XXX Set the data timeout counter value according to 459 * capabilities. (2.2.15) 460 */ 461 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 462 #if 1 463 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 464 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 465 #endif 466 467 if (ISSET(caps, SDHC_EMBEDDED_SLOT)) 468 aprint_normal(", embedded slot"); 469 470 /* 471 * Determine SD bus voltage levels supported by the controller. 472 */ 473 aprint_normal(","); 474 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) { 475 SET(hp->ocr, MMC_OCR_HCS); 476 aprint_normal(" HS"); 477 } 478 if (ISSET(caps2, SDHC_SDR50_SUPP)) { 479 SET(hp->ocr, MMC_OCR_S18A); 480 aprint_normal(" SDR50"); 481 } 482 if (ISSET(caps2, SDHC_DDR50_SUPP)) { 483 SET(hp->ocr, MMC_OCR_S18A); 484 aprint_normal(" DDR50"); 485 } 486 if (ISSET(caps2, SDHC_SDR104_SUPP)) { 487 SET(hp->ocr, MMC_OCR_S18A); 488 aprint_normal(" SDR104 HS200"); 489 } 490 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 491 SET(hp->ocr, MMC_OCR_1_65V_1_95V); 492 aprint_normal(" 1.8V"); 493 } 494 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 495 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 496 aprint_normal(" 3.0V"); 497 } 498 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 499 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 500 aprint_normal(" 3.3V"); 501 } 502 if (hp->specver >= SDHC_SPEC_VERS_300) { 503 aprint_normal(", re-tuning mode %d", retuning_mode + 1); 504 if (hp->tuning_timer_count) 505 aprint_normal(" (%us timer)", hp->tuning_timer_count); 506 } 507 508 /* 509 * Determine the maximum block length supported by the host 510 * controller. (2.2.24) 511 */ 512 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 513 case SDHC_MAX_BLK_LEN_512: 514 hp->maxblklen = 512; 515 break; 516 517 case SDHC_MAX_BLK_LEN_1024: 518 hp->maxblklen = 1024; 519 break; 520 521 case SDHC_MAX_BLK_LEN_2048: 522 hp->maxblklen = 2048; 523 break; 524 525 case SDHC_MAX_BLK_LEN_4096: 526 hp->maxblklen = 4096; 527 break; 528 529 default: 530 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 531 goto err; 532 } 533 aprint_normal(", %u byte blocks", hp->maxblklen); 534 aprint_normal("\n"); 535 536 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 537 int rseg; 538 539 /* Allocate ADMA2 descriptor memory */ 540 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 541 PAGE_SIZE, hp->adma_segs, 1, &rseg, BUS_DMA_WAITOK); 542 if (error) { 543 aprint_error_dev(sc->sc_dev, 544 "ADMA2 dmamem_alloc failed (%d)\n", error); 545 goto adma_done; 546 } 547 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg, 548 PAGE_SIZE, (void **)&hp->adma2, BUS_DMA_WAITOK); 549 if (error) { 550 aprint_error_dev(sc->sc_dev, 551 "ADMA2 dmamem_map failed (%d)\n", error); 552 goto adma_done; 553 } 554 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 555 0, BUS_DMA_WAITOK, &hp->adma_map); 556 if (error) { 557 aprint_error_dev(sc->sc_dev, 558 "ADMA2 dmamap_create failed (%d)\n", error); 559 goto adma_done; 560 } 561 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map, 562 hp->adma2, PAGE_SIZE, NULL, 563 BUS_DMA_WAITOK|BUS_DMA_WRITE); 564 if (error) { 565 aprint_error_dev(sc->sc_dev, 566 "ADMA2 dmamap_load failed (%d)\n", error); 567 goto adma_done; 568 } 569 570 memset(hp->adma2, 0, PAGE_SIZE); 571 572 adma_done: 573 if (error) 574 CLR(hp->flags, SHF_USE_ADMA2_MASK); 575 } 576 577 /* 578 * Attach the generic SD/MMC bus driver. (The bus driver must 579 * not invoke any chipset functions before it is attached.) 580 */ 581 memset(&saa, 0, sizeof(saa)); 582 saa.saa_busname = "sdmmc"; 583 saa.saa_sct = &sdhc_functions; 584 saa.saa_sch = hp; 585 saa.saa_dmat = hp->dmat; 586 saa.saa_clkmax = hp->clkbase; 587 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 588 saa.saa_clkmin = hp->clkbase / 256 / 2046; 589 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 590 saa.saa_clkmin = hp->clkbase / 256 / 16; 591 else if (hp->sc->sc_clkmsk != 0) 592 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 593 (ffs(hp->sc->sc_clkmsk) - 1)); 594 else if (hp->specver >= SDHC_SPEC_VERS_300) 595 saa.saa_clkmin = hp->clkbase / 0x3ff; 596 else 597 saa.saa_clkmin = hp->clkbase / 256; 598 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 599 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 600 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 601 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 602 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 603 if (ISSET(caps2, SDHC_SDR104_SUPP)) 604 saa.saa_caps |= SMC_CAPS_UHS_SDR104 | 605 SMC_CAPS_UHS_SDR50 | 606 SMC_CAPS_MMC_HS200; 607 if (ISSET(caps2, SDHC_SDR50_SUPP)) 608 saa.saa_caps |= SMC_CAPS_UHS_SDR50; 609 if (ISSET(caps2, SDHC_DDR50_SUPP)) 610 saa.saa_caps |= SMC_CAPS_UHS_DDR50; 611 if (ISSET(hp->flags, SHF_USE_DMA)) { 612 saa.saa_caps |= SMC_CAPS_DMA; 613 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 614 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 615 } 616 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 617 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 618 if (ISSET(sc->sc_flags, SDHC_FLAG_POLL_CARD_DET)) 619 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 620 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 621 622 return 0; 623 624 err: 625 callout_destroy(&hp->tuning_timer); 626 cv_destroy(&hp->intr_cv); 627 mutex_destroy(&hp->intr_lock); 628 free(hp, M_DEVBUF); 629 sc->sc_host[--sc->sc_nhosts] = NULL; 630 err1: 631 return 1; 632 } 633 634 int 635 sdhc_detach(struct sdhc_softc *sc, int flags) 636 { 637 struct sdhc_host *hp; 638 int rv = 0; 639 640 for (size_t n = 0; n < sc->sc_nhosts; n++) { 641 hp = sc->sc_host[n]; 642 if (hp == NULL) 643 continue; 644 if (hp->sdmmc != NULL) { 645 rv = config_detach(hp->sdmmc, flags); 646 if (rv) 647 break; 648 hp->sdmmc = NULL; 649 } 650 /* disable interrupts */ 651 if ((flags & DETACH_FORCE) == 0) { 652 mutex_enter(&hp->intr_lock); 653 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 654 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 655 } else { 656 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 657 } 658 sdhc_soft_reset(hp, SDHC_RESET_ALL); 659 mutex_exit(&hp->intr_lock); 660 } 661 callout_halt(&hp->tuning_timer, NULL); 662 callout_destroy(&hp->tuning_timer); 663 cv_destroy(&hp->intr_cv); 664 mutex_destroy(&hp->intr_lock); 665 if (hp->ios > 0) { 666 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 667 hp->ios = 0; 668 } 669 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 670 bus_dmamap_unload(sc->sc_dmat, hp->adma_map); 671 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map); 672 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE); 673 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, 1); 674 } 675 free(hp, M_DEVBUF); 676 sc->sc_host[n] = NULL; 677 } 678 679 return rv; 680 } 681 682 bool 683 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 684 { 685 struct sdhc_softc *sc = device_private(dev); 686 struct sdhc_host *hp; 687 size_t i; 688 689 /* XXX poll for command completion or suspend command 690 * in progress */ 691 692 /* Save the host controller state. */ 693 for (size_t n = 0; n < sc->sc_nhosts; n++) { 694 hp = sc->sc_host[n]; 695 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 696 for (i = 0; i < sizeof hp->regs; i += 4) { 697 uint32_t v = HREAD4(hp, i); 698 hp->regs[i + 0] = (v >> 0); 699 hp->regs[i + 1] = (v >> 8); 700 if (i + 3 < sizeof hp->regs) { 701 hp->regs[i + 2] = (v >> 16); 702 hp->regs[i + 3] = (v >> 24); 703 } 704 } 705 } else { 706 for (i = 0; i < sizeof hp->regs; i++) { 707 hp->regs[i] = HREAD1(hp, i); 708 } 709 } 710 } 711 return true; 712 } 713 714 bool 715 sdhc_resume(device_t dev, const pmf_qual_t *qual) 716 { 717 struct sdhc_softc *sc = device_private(dev); 718 struct sdhc_host *hp; 719 size_t i; 720 721 /* Restore the host controller state. */ 722 for (size_t n = 0; n < sc->sc_nhosts; n++) { 723 hp = sc->sc_host[n]; 724 (void)sdhc_host_reset(hp); 725 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 726 for (i = 0; i < sizeof hp->regs; i += 4) { 727 if (i + 3 < sizeof hp->regs) { 728 HWRITE4(hp, i, 729 (hp->regs[i + 0] << 0) 730 | (hp->regs[i + 1] << 8) 731 | (hp->regs[i + 2] << 16) 732 | (hp->regs[i + 3] << 24)); 733 } else { 734 HWRITE4(hp, i, 735 (hp->regs[i + 0] << 0) 736 | (hp->regs[i + 1] << 8)); 737 } 738 } 739 } else { 740 for (i = 0; i < sizeof hp->regs; i++) { 741 HWRITE1(hp, i, hp->regs[i]); 742 } 743 } 744 } 745 return true; 746 } 747 748 bool 749 sdhc_shutdown(device_t dev, int flags) 750 { 751 struct sdhc_softc *sc = device_private(dev); 752 struct sdhc_host *hp; 753 754 /* XXX chip locks up if we don't disable it before reboot. */ 755 for (size_t i = 0; i < sc->sc_nhosts; i++) { 756 hp = sc->sc_host[i]; 757 (void)sdhc_host_reset(hp); 758 } 759 return true; 760 } 761 762 /* 763 * Reset the host controller. Called during initialization, when 764 * cards are removed, upon resume, and during error recovery. 765 */ 766 static int 767 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 768 { 769 struct sdhc_host *hp = (struct sdhc_host *)sch; 770 uint32_t sdhcimask; 771 int error; 772 773 KASSERT(mutex_owned(&hp->intr_lock)); 774 775 /* Disable all interrupts. */ 776 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 777 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 778 } else { 779 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 780 } 781 782 /* 783 * Reset the entire host controller and wait up to 100ms for 784 * the controller to clear the reset bit. 785 */ 786 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 787 if (error) 788 goto out; 789 790 /* Set data timeout counter value to max for now. */ 791 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 792 #if 1 793 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 794 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 795 #endif 796 797 /* Enable interrupts. */ 798 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 799 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 800 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 801 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 802 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 803 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 804 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 805 sdhcimask ^= 806 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 807 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 808 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 809 } else { 810 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 811 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 812 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 813 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 814 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 815 } 816 817 out: 818 return error; 819 } 820 821 static int 822 sdhc_host_reset(sdmmc_chipset_handle_t sch) 823 { 824 struct sdhc_host *hp = (struct sdhc_host *)sch; 825 int error; 826 827 mutex_enter(&hp->intr_lock); 828 error = sdhc_host_reset1(sch); 829 mutex_exit(&hp->intr_lock); 830 831 return error; 832 } 833 834 static uint32_t 835 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 836 { 837 struct sdhc_host *hp = (struct sdhc_host *)sch; 838 839 return hp->ocr; 840 } 841 842 static int 843 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 844 { 845 struct sdhc_host *hp = (struct sdhc_host *)sch; 846 847 return hp->maxblklen; 848 } 849 850 /* 851 * Return non-zero if the card is currently inserted. 852 */ 853 static int 854 sdhc_card_detect(sdmmc_chipset_handle_t sch) 855 { 856 struct sdhc_host *hp = (struct sdhc_host *)sch; 857 int r; 858 859 if (hp->sc->sc_vendor_card_detect) 860 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 861 862 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 863 864 return r ? 1 : 0; 865 } 866 867 /* 868 * Return non-zero if the card is currently write-protected. 869 */ 870 static int 871 sdhc_write_protect(sdmmc_chipset_handle_t sch) 872 { 873 struct sdhc_host *hp = (struct sdhc_host *)sch; 874 int r; 875 876 if (hp->sc->sc_vendor_write_protect) 877 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 878 879 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 880 881 return r ? 0 : 1; 882 } 883 884 /* 885 * Set or change SD bus voltage and enable or disable SD bus power. 886 * Return zero on success. 887 */ 888 static int 889 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 890 { 891 struct sdhc_host *hp = (struct sdhc_host *)sch; 892 uint8_t vdd; 893 int error = 0; 894 const uint32_t pcmask = 895 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 896 897 mutex_enter(&hp->intr_lock); 898 899 /* 900 * Disable bus power before voltage change. 901 */ 902 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 903 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 904 HWRITE1(hp, SDHC_POWER_CTL, 0); 905 906 /* If power is disabled, reset the host and return now. */ 907 if (ocr == 0) { 908 (void)sdhc_host_reset1(hp); 909 callout_halt(&hp->tuning_timer, &hp->intr_lock); 910 goto out; 911 } 912 913 /* 914 * Select the lowest voltage according to capabilities. 915 */ 916 ocr &= hp->ocr; 917 if (ISSET(ocr, MMC_OCR_1_65V_1_95V)) { 918 vdd = SDHC_VOLTAGE_1_8V; 919 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 920 vdd = SDHC_VOLTAGE_3_0V; 921 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 922 vdd = SDHC_VOLTAGE_3_3V; 923 } else { 924 /* Unsupported voltage level requested. */ 925 error = EINVAL; 926 goto out; 927 } 928 929 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 930 /* 931 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 932 * voltage ramp until power rises. 933 */ 934 935 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SINGLE_POWER_WRITE)) { 936 HWRITE1(hp, SDHC_POWER_CTL, 937 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 938 } else { 939 HWRITE1(hp, SDHC_POWER_CTL, 940 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 941 sdmmc_delay(1); 942 HWRITE1(hp, SDHC_POWER_CTL, 943 (vdd << SDHC_VOLTAGE_SHIFT)); 944 sdmmc_delay(1); 945 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 946 sdmmc_delay(10000); 947 } 948 949 /* 950 * The host system may not power the bus due to battery low, 951 * etc. In that case, the host controller should clear the 952 * bus power bit. 953 */ 954 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 955 error = ENXIO; 956 goto out; 957 } 958 } 959 960 out: 961 mutex_exit(&hp->intr_lock); 962 963 return error; 964 } 965 966 /* 967 * Return the smallest possible base clock frequency divisor value 968 * for the CLOCK_CTL register to produce `freq' (KHz). 969 */ 970 static bool 971 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 972 { 973 u_int div; 974 975 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 976 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 977 if ((hp->clkbase / div) <= freq) { 978 *divp = SDHC_SDCLK_CGM 979 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 980 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 981 //freq = hp->clkbase / div; 982 return true; 983 } 984 } 985 /* No divisor found. */ 986 return false; 987 } 988 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 989 u_int dvs = (hp->clkbase + freq - 1) / freq; 990 u_int roundup = dvs & 1; 991 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 992 if (dvs + roundup <= 16) { 993 dvs += roundup - 1; 994 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 995 | (dvs << SDHC_SDCLK_DVS_SHIFT); 996 DPRINTF(2, 997 ("%s: divisor for freq %u is %u * %u\n", 998 HDEVNAME(hp), freq, div * 2, dvs + 1)); 999 //freq = hp->clkbase / (div * 2) * (dvs + 1); 1000 return true; 1001 } 1002 /* 1003 * If we drop bits, we need to round up the divisor. 1004 */ 1005 roundup |= dvs & 1; 1006 } 1007 /* No divisor found. */ 1008 return false; 1009 } 1010 if (hp->sc->sc_clkmsk != 0) { 1011 div = howmany(hp->clkbase, freq); 1012 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 1013 return false; 1014 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 1015 //freq = hp->clkbase / div; 1016 return true; 1017 } 1018 if (hp->specver >= SDHC_SPEC_VERS_300) { 1019 div = howmany(hp->clkbase, freq); 1020 div = div > 1 ? howmany(div, 2) : 0; 1021 if (div > 0x3ff) 1022 return false; 1023 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 1024 << SDHC_SDCLK_XDIV_SHIFT) | 1025 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 1026 << SDHC_SDCLK_DIV_SHIFT); 1027 //freq = hp->clkbase / (div ? div * 2 : 1); 1028 return true; 1029 } else { 1030 for (div = 1; div <= 256; div *= 2) { 1031 if ((hp->clkbase / div) <= freq) { 1032 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 1033 //freq = hp->clkbase / div; 1034 return true; 1035 } 1036 } 1037 /* No divisor found. */ 1038 return false; 1039 } 1040 /* No divisor found. */ 1041 return false; 1042 } 1043 1044 /* 1045 * Set or change SDCLK frequency or disable the SD clock. 1046 * Return zero on success. 1047 */ 1048 static int 1049 sdhc_bus_clock_ddr(sdmmc_chipset_handle_t sch, int freq, bool ddr) 1050 { 1051 struct sdhc_host *hp = (struct sdhc_host *)sch; 1052 u_int div; 1053 u_int timo; 1054 int16_t reg; 1055 int error = 0; 1056 bool present __diagused; 1057 1058 mutex_enter(&hp->intr_lock); 1059 1060 #ifdef DIAGNOSTIC 1061 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 1062 1063 /* Must not stop the clock if commands are in progress. */ 1064 if (present && sdhc_card_detect(hp)) { 1065 aprint_normal_dev(hp->sc->sc_dev, 1066 "%s: command in progress\n", __func__); 1067 } 1068 #endif 1069 1070 if (hp->sc->sc_vendor_bus_clock) { 1071 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 1072 if (error != 0) 1073 goto out; 1074 } 1075 1076 /* 1077 * Stop SD clock before changing the frequency. 1078 */ 1079 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1080 HCLR4(hp, SDHC_VEND_SPEC, 1081 SDHC_VEND_SPEC_CARD_CLK_SOFT_EN | 1082 SDHC_VEND_SPEC_FRC_SDCLK_ON); 1083 if (freq == SDMMC_SDCLK_OFF) { 1084 goto out; 1085 } 1086 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1087 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 1088 if (freq == SDMMC_SDCLK_OFF) { 1089 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 1090 goto out; 1091 } 1092 } else { 1093 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1094 if (freq == SDMMC_SDCLK_OFF) 1095 goto out; 1096 } 1097 1098 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1099 if (ddr) 1100 HSET4(hp, SDHC_MIX_CTRL, SDHC_USDHC_DDR_EN); 1101 else 1102 HCLR4(hp, SDHC_MIX_CTRL, SDHC_USDHC_DDR_EN); 1103 } else if (hp->specver >= SDHC_SPEC_VERS_300) { 1104 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK); 1105 if (freq > 100000) { 1106 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR104); 1107 } else if (freq > 50000) { 1108 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR50); 1109 } else if (freq > 25000) { 1110 if (ddr) { 1111 HSET2(hp, SDHC_HOST_CTL2, 1112 SDHC_UHS_MODE_SELECT_DDR50); 1113 } else { 1114 HSET2(hp, SDHC_HOST_CTL2, 1115 SDHC_UHS_MODE_SELECT_SDR25); 1116 } 1117 } else if (freq > 400) { 1118 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR12); 1119 } 1120 } 1121 1122 /* 1123 * Slow down Ricoh 5U823 controller that isn't reliable 1124 * at 100MHz bus clock. 1125 */ 1126 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SLOW_SDR50)) { 1127 if (freq == 100000) 1128 --freq; 1129 } 1130 1131 /* 1132 * Set the minimum base clock frequency divisor. 1133 */ 1134 if (!sdhc_clock_divisor(hp, freq, &div)) { 1135 /* Invalid base clock frequency or `freq' value. */ 1136 aprint_error_dev(hp->sc->sc_dev, 1137 "Invalid bus clock %d kHz\n", freq); 1138 error = EINVAL; 1139 goto out; 1140 } 1141 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1142 if (ddr) { 1143 /* in ddr mode, divisor >>= 1 */ 1144 div = ((div >> 1) & (SDHC_SDCLK_DIV_MASK << 1145 SDHC_SDCLK_DIV_SHIFT)) | 1146 (div & (SDHC_SDCLK_DVS_MASK << 1147 SDHC_SDCLK_DVS_SHIFT)); 1148 } 1149 for (timo = 1000; timo > 0; timo--) { 1150 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_SDSTB)) 1151 break; 1152 sdmmc_delay(10); 1153 } 1154 HWRITE4(hp, SDHC_CLOCK_CTL, 1155 div | (SDHC_TIMEOUT_MAX << 16) | 0x0f); 1156 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1157 HWRITE4(hp, SDHC_CLOCK_CTL, 1158 div | (SDHC_TIMEOUT_MAX << 16)); 1159 } else { 1160 reg = HREAD2(hp, SDHC_CLOCK_CTL); 1161 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 1162 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 1163 } 1164 1165 /* 1166 * Start internal clock. Wait 10ms for stabilization. 1167 */ 1168 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1169 HSET4(hp, SDHC_VEND_SPEC, 1170 SDHC_VEND_SPEC_CARD_CLK_SOFT_EN | 1171 SDHC_VEND_SPEC_FRC_SDCLK_ON); 1172 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1173 sdmmc_delay(10000); 1174 HSET4(hp, SDHC_CLOCK_CTL, 1175 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 1176 } else { 1177 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 1178 for (timo = 1000; timo > 0; timo--) { 1179 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 1180 SDHC_INTCLK_STABLE)) 1181 break; 1182 sdmmc_delay(10); 1183 } 1184 if (timo == 0) { 1185 error = ETIMEDOUT; 1186 DPRINTF(1,("%s: timeout\n", __func__)); 1187 goto out; 1188 } 1189 } 1190 1191 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1192 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 1193 /* 1194 * Sending 80 clocks at 400kHz takes 200us. 1195 * So delay for that time + slop and then 1196 * check a few times for completion. 1197 */ 1198 sdmmc_delay(210); 1199 for (timo = 10; timo > 0; timo--) { 1200 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 1201 SDHC_INIT_ACTIVE)) 1202 break; 1203 sdmmc_delay(10); 1204 } 1205 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 1206 1207 /* 1208 * Enable SD clock. 1209 */ 1210 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1211 HSET4(hp, SDHC_VEND_SPEC, 1212 SDHC_VEND_SPEC_CARD_CLK_SOFT_EN | 1213 SDHC_VEND_SPEC_FRC_SDCLK_ON); 1214 } else { 1215 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1216 } 1217 } else { 1218 /* 1219 * Enable SD clock. 1220 */ 1221 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 1222 1223 if (freq > 25000 && 1224 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 1225 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1226 else 1227 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 1228 } 1229 1230 out: 1231 mutex_exit(&hp->intr_lock); 1232 1233 return error; 1234 } 1235 1236 static int 1237 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 1238 { 1239 struct sdhc_host *hp = (struct sdhc_host *)sch; 1240 int reg; 1241 1242 switch (width) { 1243 case 1: 1244 case 4: 1245 break; 1246 1247 case 8: 1248 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 1249 break; 1250 /* FALLTHROUGH */ 1251 default: 1252 DPRINTF(0,("%s: unsupported bus width (%d)\n", 1253 HDEVNAME(hp), width)); 1254 return 1; 1255 } 1256 1257 if (hp->sc->sc_vendor_bus_width) { 1258 const int error = hp->sc->sc_vendor_bus_width(hp->sc, width); 1259 if (error != 0) 1260 return error; 1261 } 1262 1263 mutex_enter(&hp->intr_lock); 1264 1265 reg = HREAD1(hp, SDHC_HOST_CTL); 1266 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1267 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 1268 if (width == 4) 1269 reg |= SDHC_4BIT_MODE; 1270 else if (width == 8) 1271 reg |= SDHC_ESDHC_8BIT_MODE; 1272 } else { 1273 reg &= ~SDHC_4BIT_MODE; 1274 if (hp->specver >= SDHC_SPEC_VERS_300) { 1275 reg &= ~SDHC_8BIT_MODE; 1276 } 1277 if (width == 4) { 1278 reg |= SDHC_4BIT_MODE; 1279 } else if (width == 8 && hp->specver >= SDHC_SPEC_VERS_300) { 1280 reg |= SDHC_8BIT_MODE; 1281 } 1282 } 1283 HWRITE1(hp, SDHC_HOST_CTL, reg); 1284 1285 mutex_exit(&hp->intr_lock); 1286 1287 return 0; 1288 } 1289 1290 static int 1291 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1292 { 1293 struct sdhc_host *hp = (struct sdhc_host *)sch; 1294 1295 if (hp->sc->sc_vendor_rod) 1296 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1297 1298 return 0; 1299 } 1300 1301 static void 1302 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1303 { 1304 struct sdhc_host *hp = (struct sdhc_host *)sch; 1305 1306 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1307 mutex_enter(&hp->intr_lock); 1308 if (enable) { 1309 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1310 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1311 } else { 1312 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1313 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1314 } 1315 mutex_exit(&hp->intr_lock); 1316 } 1317 } 1318 1319 static void 1320 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1321 { 1322 struct sdhc_host *hp = (struct sdhc_host *)sch; 1323 1324 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1325 mutex_enter(&hp->intr_lock); 1326 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1327 mutex_exit(&hp->intr_lock); 1328 } 1329 } 1330 1331 static int 1332 sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 1333 { 1334 struct sdhc_host *hp = (struct sdhc_host *)sch; 1335 1336 mutex_enter(&hp->intr_lock); 1337 switch (signal_voltage) { 1338 case SDMMC_SIGNAL_VOLTAGE_180: 1339 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) 1340 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1341 break; 1342 case SDMMC_SIGNAL_VOLTAGE_330: 1343 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) 1344 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN); 1345 break; 1346 default: 1347 return EINVAL; 1348 } 1349 mutex_exit(&hp->intr_lock); 1350 1351 return 0; 1352 } 1353 1354 /* 1355 * Sampling clock tuning procedure (UHS) 1356 */ 1357 static int 1358 sdhc_execute_tuning1(struct sdhc_host *hp, int timing) 1359 { 1360 struct sdmmc_command cmd; 1361 uint8_t hostctl; 1362 int opcode, error, retry = 40; 1363 1364 KASSERT(mutex_owned(&hp->intr_lock)); 1365 1366 hp->tuning_timing = timing; 1367 1368 switch (timing) { 1369 case SDMMC_TIMING_MMC_HS200: 1370 opcode = MMC_SEND_TUNING_BLOCK_HS200; 1371 break; 1372 case SDMMC_TIMING_UHS_SDR50: 1373 if (!ISSET(hp->sc->sc_caps2, SDHC_TUNING_SDR50)) 1374 return 0; 1375 /* FALLTHROUGH */ 1376 case SDMMC_TIMING_UHS_SDR104: 1377 opcode = MMC_SEND_TUNING_BLOCK; 1378 break; 1379 default: 1380 return EINVAL; 1381 } 1382 1383 hostctl = HREAD1(hp, SDHC_HOST_CTL); 1384 1385 /* enable buffer read ready interrupt */ 1386 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_BUFFER_READ_READY); 1387 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_BUFFER_READ_READY); 1388 1389 /* disable DMA */ 1390 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1391 1392 /* reset tuning circuit */ 1393 HCLR2(hp, SDHC_HOST_CTL2, SDHC_SAMPLING_CLOCK_SEL); 1394 1395 /* start of tuning */ 1396 HWRITE2(hp, SDHC_HOST_CTL2, SDHC_EXECUTE_TUNING); 1397 1398 do { 1399 memset(&cmd, 0, sizeof(cmd)); 1400 cmd.c_opcode = opcode; 1401 cmd.c_arg = 0; 1402 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1; 1403 if (ISSET(hostctl, SDHC_8BIT_MODE)) { 1404 cmd.c_blklen = cmd.c_datalen = 128; 1405 } else { 1406 cmd.c_blklen = cmd.c_datalen = 64; 1407 } 1408 1409 error = sdhc_start_command(hp, &cmd); 1410 if (error) 1411 break; 1412 1413 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY, 1414 SDHC_TUNING_TIMEOUT, false)) { 1415 break; 1416 } 1417 1418 delay(1000); 1419 } while (HREAD2(hp, SDHC_HOST_CTL2) & SDHC_EXECUTE_TUNING && --retry); 1420 1421 /* disable buffer read ready interrupt */ 1422 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_BUFFER_READ_READY); 1423 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_BUFFER_READ_READY); 1424 1425 if (HREAD2(hp, SDHC_HOST_CTL2) & SDHC_EXECUTE_TUNING) { 1426 HCLR2(hp, SDHC_HOST_CTL2, 1427 SDHC_SAMPLING_CLOCK_SEL|SDHC_EXECUTE_TUNING); 1428 sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1429 aprint_error_dev(hp->sc->sc_dev, 1430 "tuning did not complete, using fixed sampling clock\n"); 1431 return EIO; /* tuning did not complete */ 1432 } 1433 1434 if ((HREAD2(hp, SDHC_HOST_CTL2) & SDHC_SAMPLING_CLOCK_SEL) == 0) { 1435 HCLR2(hp, SDHC_HOST_CTL2, 1436 SDHC_SAMPLING_CLOCK_SEL|SDHC_EXECUTE_TUNING); 1437 sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1438 aprint_error_dev(hp->sc->sc_dev, 1439 "tuning failed, using fixed sampling clock\n"); 1440 return EIO; /* tuning failed */ 1441 } 1442 1443 if (hp->tuning_timer_count) { 1444 callout_schedule(&hp->tuning_timer, 1445 hz * hp->tuning_timer_count); 1446 } 1447 1448 return 0; /* tuning completed */ 1449 } 1450 1451 static int 1452 sdhc_execute_tuning(sdmmc_chipset_handle_t sch, int timing) 1453 { 1454 struct sdhc_host *hp = (struct sdhc_host *)sch; 1455 int error; 1456 1457 mutex_enter(&hp->intr_lock); 1458 error = sdhc_execute_tuning1(hp, timing); 1459 mutex_exit(&hp->intr_lock); 1460 return error; 1461 } 1462 1463 static void 1464 sdhc_tuning_timer(void *arg) 1465 { 1466 struct sdhc_host *hp = arg; 1467 1468 atomic_swap_uint(&hp->tuning_timer_pending, 1); 1469 } 1470 1471 static int 1472 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1473 { 1474 uint32_t state; 1475 int timeout; 1476 1477 for (timeout = 10000; timeout > 0; timeout--) { 1478 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 1479 return 0; 1480 sdmmc_delay(10); 1481 } 1482 aprint_error_dev(hp->sc->sc_dev, "timeout waiting for mask %#x value %#x (state=%#x)\n", 1483 mask, value, state); 1484 return ETIMEDOUT; 1485 } 1486 1487 static void 1488 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1489 { 1490 struct sdhc_host *hp = (struct sdhc_host *)sch; 1491 int error; 1492 bool probing; 1493 1494 mutex_enter(&hp->intr_lock); 1495 1496 if (atomic_cas_uint(&hp->tuning_timer_pending, 1, 0) == 1) { 1497 (void)sdhc_execute_tuning1(hp, hp->tuning_timing); 1498 } 1499 1500 if (cmd->c_data && 1501 ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1502 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1503 if (ISSET(hp->flags, SHF_USE_DMA)) { 1504 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1505 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1506 } else { 1507 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1508 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1509 } 1510 } 1511 1512 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_TIMEOUT)) { 1513 const uint16_t eintr = SDHC_CMD_TIMEOUT_ERROR; 1514 if (cmd->c_data != NULL) { 1515 HCLR2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1516 HCLR2(hp, SDHC_EINTR_STATUS_EN, eintr); 1517 } else { 1518 HSET2(hp, SDHC_EINTR_SIGNAL_EN, eintr); 1519 HSET2(hp, SDHC_EINTR_STATUS_EN, eintr); 1520 } 1521 } 1522 1523 /* 1524 * Start the MMC command, or mark `cmd' as failed and return. 1525 */ 1526 error = sdhc_start_command(hp, cmd); 1527 if (error) { 1528 cmd->c_error = error; 1529 goto out; 1530 } 1531 1532 /* 1533 * Wait until the command phase is done, or until the command 1534 * is marked done for any other reason. 1535 */ 1536 probing = (cmd->c_flags & SCF_TOUT_OK) != 0; 1537 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT, probing)) { 1538 DPRINTF(1,("%s: timeout for command\n", __func__)); 1539 sdmmc_delay(50); 1540 cmd->c_error = ETIMEDOUT; 1541 goto out; 1542 } 1543 1544 /* 1545 * The host controller removes bits [0:7] from the response 1546 * data (CRC) and we pass the data up unchanged to the bus 1547 * driver (without padding). 1548 */ 1549 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1550 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1551 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1552 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1553 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1554 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1555 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1556 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1557 (cmd->c_resp[1] << 24); 1558 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1559 (cmd->c_resp[2] << 24); 1560 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1561 (cmd->c_resp[3] << 24); 1562 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1563 } 1564 } 1565 } 1566 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1567 1568 /* 1569 * If the command has data to transfer in any direction, 1570 * execute the transfer now. 1571 */ 1572 if (cmd->c_error == 0 && cmd->c_data != NULL) 1573 sdhc_transfer_data(hp, cmd); 1574 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1575 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10, false)) { 1576 DPRINTF(1,("%s: sdhc_exec_command: RSP_BSY\n", 1577 HDEVNAME(hp))); 1578 cmd->c_error = ETIMEDOUT; 1579 goto out; 1580 } 1581 } 1582 1583 out: 1584 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1585 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1586 /* Turn off the LED. */ 1587 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1588 } 1589 SET(cmd->c_flags, SCF_ITSDONE); 1590 1591 mutex_exit(&hp->intr_lock); 1592 1593 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1594 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1595 cmd->c_flags, cmd->c_error)); 1596 } 1597 1598 static int 1599 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1600 { 1601 struct sdhc_softc * const sc = hp->sc; 1602 uint16_t blksize = 0; 1603 uint16_t blkcount = 0; 1604 uint16_t mode; 1605 uint16_t command; 1606 uint32_t pmask; 1607 int error; 1608 1609 KASSERT(mutex_owned(&hp->intr_lock)); 1610 1611 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1612 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1613 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1614 1615 /* 1616 * The maximum block length for commands should be the minimum 1617 * of the host buffer size and the card buffer size. (1.7.2) 1618 */ 1619 1620 /* Fragment the data into proper blocks. */ 1621 if (cmd->c_datalen > 0) { 1622 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1623 blkcount = cmd->c_datalen / blksize; 1624 if (cmd->c_datalen % blksize > 0) { 1625 /* XXX: Split this command. (1.7.4) */ 1626 aprint_error_dev(sc->sc_dev, 1627 "data not a multiple of %u bytes\n", blksize); 1628 return EINVAL; 1629 } 1630 } 1631 1632 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1633 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1634 aprint_error_dev(sc->sc_dev, "too much data\n"); 1635 return EINVAL; 1636 } 1637 1638 /* Prepare transfer mode register value. (2.2.5) */ 1639 mode = SDHC_BLOCK_COUNT_ENABLE; 1640 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1641 mode |= SDHC_READ_MODE; 1642 if (blkcount > 1) { 1643 mode |= SDHC_MULTI_BLOCK_MODE; 1644 /* XXX only for memory commands? */ 1645 mode |= SDHC_AUTO_CMD12_ENABLE; 1646 } 1647 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1648 ISSET(hp->flags, SHF_MODE_DMAEN)) { 1649 mode |= SDHC_DMA_ENABLE; 1650 } 1651 1652 /* 1653 * Prepare command register value. (2.2.6) 1654 */ 1655 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1656 1657 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1658 command |= SDHC_CRC_CHECK_ENABLE; 1659 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1660 command |= SDHC_INDEX_CHECK_ENABLE; 1661 if (cmd->c_datalen > 0) 1662 command |= SDHC_DATA_PRESENT_SELECT; 1663 1664 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1665 command |= SDHC_NO_RESPONSE; 1666 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1667 command |= SDHC_RESP_LEN_136; 1668 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1669 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1670 else 1671 command |= SDHC_RESP_LEN_48; 1672 1673 /* Wait until command and optionally data inhibit bits are clear. (1.5) */ 1674 pmask = SDHC_CMD_INHIBIT_CMD; 1675 if (cmd->c_flags & (SCF_CMD_ADTC|SCF_RSP_BSY)) 1676 pmask |= SDHC_CMD_INHIBIT_DAT; 1677 error = sdhc_wait_state(hp, pmask, 0); 1678 if (error) { 1679 (void) sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1680 device_printf(sc->sc_dev, "command or data phase inhibited\n"); 1681 return error; 1682 } 1683 1684 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1685 HDEVNAME(hp), blksize, blkcount, mode, command)); 1686 1687 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1688 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1689 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1690 } 1691 1692 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1693 /* Alert the user not to remove the card. */ 1694 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1695 } 1696 1697 /* Set DMA start address. */ 1698 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK) && cmd->c_data != NULL) { 1699 for (int seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 1700 bus_addr_t paddr = 1701 cmd->c_dmamap->dm_segs[seg].ds_addr; 1702 uint16_t len = 1703 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 1704 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 1705 uint16_t attr = 1706 SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 1707 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 1708 attr |= SDHC_ADMA2_END; 1709 } 1710 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1711 struct sdhc_adma2_descriptor32 *desc = 1712 hp->adma2; 1713 desc[seg].attribute = htole16(attr); 1714 desc[seg].length = htole16(len); 1715 desc[seg].address = htole32(paddr); 1716 } else { 1717 struct sdhc_adma2_descriptor64 *desc = 1718 hp->adma2; 1719 desc[seg].attribute = htole16(attr); 1720 desc[seg].length = htole16(len); 1721 desc[seg].address = htole32(paddr & 0xffffffff); 1722 desc[seg].address_hi = htole32( 1723 (uint64_t)paddr >> 32); 1724 } 1725 } 1726 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) { 1727 struct sdhc_adma2_descriptor32 *desc = hp->adma2; 1728 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1729 } else { 1730 struct sdhc_adma2_descriptor64 *desc = hp->adma2; 1731 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 1732 } 1733 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE, 1734 BUS_DMASYNC_PREWRITE); 1735 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1736 HCLR4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT); 1737 HSET4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT_ADMA2); 1738 } else { 1739 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT); 1740 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2); 1741 } 1742 1743 const bus_addr_t desc_addr = hp->adma_map->dm_segs[0].ds_addr; 1744 1745 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff); 1746 if (ISSET(hp->flags, SHF_USE_ADMA2_64)) { 1747 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4, 1748 (uint64_t)desc_addr >> 32); 1749 } 1750 } else if (ISSET(mode, SDHC_DMA_ENABLE) && 1751 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) { 1752 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1753 HCLR4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT); 1754 } 1755 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1756 } 1757 1758 /* 1759 * Start a CPU data transfer. Writing to the high order byte 1760 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1761 */ 1762 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1763 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1764 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1765 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) { 1766 /* mode bits is in MIX_CTRL register on uSDHC */ 1767 HWRITE4(hp, SDHC_MIX_CTRL, mode | 1768 (HREAD4(hp, SDHC_MIX_CTRL) & 1769 ~(SDHC_MULTI_BLOCK_MODE | 1770 SDHC_READ_MODE | 1771 SDHC_AUTO_CMD12_ENABLE | 1772 SDHC_BLOCK_COUNT_ENABLE | 1773 SDHC_DMA_ENABLE))); 1774 HWRITE4(hp, SDHC_TRANSFER_MODE, command << 16); 1775 } else { 1776 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1777 } 1778 } else { 1779 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1780 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1781 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1782 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1783 HWRITE2(hp, SDHC_COMMAND, command); 1784 } 1785 1786 return 0; 1787 } 1788 1789 static void 1790 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1791 { 1792 struct sdhc_softc *sc = hp->sc; 1793 int error; 1794 1795 KASSERT(mutex_owned(&hp->intr_lock)); 1796 1797 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1798 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1799 1800 #ifdef SDHC_DEBUG 1801 /* XXX I forgot why I wanted to know when this happens :-( */ 1802 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1803 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1804 aprint_error_dev(hp->sc->sc_dev, 1805 "CMD52/53 error response flags %#x\n", 1806 MMC_R1(cmd->c_resp) & 0xff00); 1807 } 1808 #endif 1809 1810 if (cmd->c_dmamap != NULL) { 1811 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1812 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd); 1813 if (error == 0 && !sdhc_wait_intr(hp, 1814 SDHC_TRANSFER_COMPLETE, SDHC_DMA_TIMEOUT, false)) { 1815 DPRINTF(1,("%s: timeout\n", __func__)); 1816 error = ETIMEDOUT; 1817 } 1818 } else { 1819 error = sdhc_transfer_data_dma(hp, cmd); 1820 } 1821 } else 1822 error = sdhc_transfer_data_pio(hp, cmd); 1823 if (error) 1824 cmd->c_error = error; 1825 SET(cmd->c_flags, SCF_ITSDONE); 1826 1827 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1828 HDEVNAME(hp), cmd->c_error)); 1829 } 1830 1831 static int 1832 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1833 { 1834 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1835 bus_addr_t posaddr; 1836 bus_addr_t segaddr; 1837 bus_size_t seglen; 1838 u_int seg = 0; 1839 int error = 0; 1840 int status; 1841 1842 KASSERT(mutex_owned(&hp->intr_lock)); 1843 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1844 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1845 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1846 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1847 1848 for (;;) { 1849 status = sdhc_wait_intr(hp, 1850 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1851 SDHC_DMA_TIMEOUT, false); 1852 1853 if (status & SDHC_TRANSFER_COMPLETE) { 1854 break; 1855 } 1856 if (!status) { 1857 DPRINTF(1,("%s: timeout\n", __func__)); 1858 error = ETIMEDOUT; 1859 break; 1860 } 1861 1862 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1863 continue; 1864 } 1865 1866 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1867 continue; 1868 } 1869 1870 /* DMA Interrupt (boundary crossing) */ 1871 1872 segaddr = dm_segs[seg].ds_addr; 1873 seglen = dm_segs[seg].ds_len; 1874 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1875 1876 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1877 continue; 1878 } 1879 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1880 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1881 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1882 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1883 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1884 } 1885 1886 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) { 1887 bus_dmamap_sync(hp->sc->sc_dmat, hp->adma_map, 0, 1888 PAGE_SIZE, BUS_DMASYNC_POSTWRITE); 1889 } 1890 1891 return error; 1892 } 1893 1894 static int 1895 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1896 { 1897 uint8_t *data = cmd->c_data; 1898 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1899 u_int len, datalen; 1900 u_int imask; 1901 u_int pmask; 1902 int error = 0; 1903 1904 KASSERT(mutex_owned(&hp->intr_lock)); 1905 1906 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1907 imask = SDHC_BUFFER_READ_READY; 1908 pmask = SDHC_BUFFER_READ_ENABLE; 1909 if (ISSET(hp->sc->sc_flags, 1910 SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1911 pio_func = esdhc_read_data_pio; 1912 } else { 1913 pio_func = sdhc_read_data_pio; 1914 } 1915 } else { 1916 imask = SDHC_BUFFER_WRITE_READY; 1917 pmask = SDHC_BUFFER_WRITE_ENABLE; 1918 if (ISSET(hp->sc->sc_flags, 1919 SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 1920 pio_func = esdhc_write_data_pio; 1921 } else { 1922 pio_func = sdhc_write_data_pio; 1923 } 1924 } 1925 datalen = cmd->c_datalen; 1926 1927 KASSERT(mutex_owned(&hp->intr_lock)); 1928 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1929 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1930 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1931 1932 while (datalen > 0) { 1933 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), pmask)) { 1934 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1935 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1936 } else { 1937 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1938 } 1939 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT, false)) { 1940 DPRINTF(1,("%s: timeout\n", __func__)); 1941 error = ETIMEDOUT; 1942 break; 1943 } 1944 1945 error = sdhc_wait_state(hp, pmask, pmask); 1946 if (error) 1947 break; 1948 } 1949 1950 len = MIN(datalen, cmd->c_blklen); 1951 (*pio_func)(hp, data, len); 1952 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1953 HDEVNAME(hp), len, data)); 1954 1955 data += len; 1956 datalen -= len; 1957 } 1958 1959 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1960 SDHC_TRANSFER_TIMEOUT, false)) { 1961 DPRINTF(1,("%s: timeout for transfer\n", __func__)); 1962 error = ETIMEDOUT; 1963 } 1964 1965 return error; 1966 } 1967 1968 static void 1969 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1970 { 1971 1972 if (((__uintptr_t)data & 3) == 0) { 1973 while (datalen > 3) { 1974 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1975 data += 4; 1976 datalen -= 4; 1977 } 1978 if (datalen > 1) { 1979 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1980 data += 2; 1981 datalen -= 2; 1982 } 1983 if (datalen > 0) { 1984 *data = HREAD1(hp, SDHC_DATA); 1985 data += 1; 1986 datalen -= 1; 1987 } 1988 } else if (((__uintptr_t)data & 1) == 0) { 1989 while (datalen > 1) { 1990 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1991 data += 2; 1992 datalen -= 2; 1993 } 1994 if (datalen > 0) { 1995 *data = HREAD1(hp, SDHC_DATA); 1996 data += 1; 1997 datalen -= 1; 1998 } 1999 } else { 2000 while (datalen > 0) { 2001 *data = HREAD1(hp, SDHC_DATA); 2002 data += 1; 2003 datalen -= 1; 2004 } 2005 } 2006 } 2007 2008 static void 2009 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 2010 { 2011 2012 if (((__uintptr_t)data & 3) == 0) { 2013 while (datalen > 3) { 2014 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 2015 data += 4; 2016 datalen -= 4; 2017 } 2018 if (datalen > 1) { 2019 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 2020 data += 2; 2021 datalen -= 2; 2022 } 2023 if (datalen > 0) { 2024 HWRITE1(hp, SDHC_DATA, *data); 2025 data += 1; 2026 datalen -= 1; 2027 } 2028 } else if (((__uintptr_t)data & 1) == 0) { 2029 while (datalen > 1) { 2030 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 2031 data += 2; 2032 datalen -= 2; 2033 } 2034 if (datalen > 0) { 2035 HWRITE1(hp, SDHC_DATA, *data); 2036 data += 1; 2037 datalen -= 1; 2038 } 2039 } else { 2040 while (datalen > 0) { 2041 HWRITE1(hp, SDHC_DATA, *data); 2042 data += 1; 2043 datalen -= 1; 2044 } 2045 } 2046 } 2047 2048 static void 2049 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 2050 { 2051 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 2052 uint32_t v; 2053 2054 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 2055 size_t count = 0; 2056 2057 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 2058 if (count == 0) { 2059 /* 2060 * If we've drained "watermark" words, we need to wait 2061 * a little bit so the read FIFO can refill. 2062 */ 2063 sdmmc_delay(10); 2064 count = watermark; 2065 } 2066 v = HREAD4(hp, SDHC_DATA); 2067 v = le32toh(v); 2068 *(uint32_t *)data = v; 2069 data += 4; 2070 datalen -= 4; 2071 status = HREAD2(hp, SDHC_NINTR_STATUS); 2072 count--; 2073 } 2074 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 2075 if (count == 0) { 2076 sdmmc_delay(10); 2077 } 2078 v = HREAD4(hp, SDHC_DATA); 2079 v = le32toh(v); 2080 do { 2081 *data++ = v; 2082 v >>= 8; 2083 } while (--datalen > 0); 2084 } 2085 } 2086 2087 static void 2088 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 2089 { 2090 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 2091 uint32_t v; 2092 2093 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 2094 size_t count = watermark; 2095 2096 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 2097 if (count == 0) { 2098 sdmmc_delay(10); 2099 count = watermark; 2100 } 2101 v = *(uint32_t *)data; 2102 v = htole32(v); 2103 HWRITE4(hp, SDHC_DATA, v); 2104 data += 4; 2105 datalen -= 4; 2106 status = HREAD2(hp, SDHC_NINTR_STATUS); 2107 count--; 2108 } 2109 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 2110 if (count == 0) { 2111 sdmmc_delay(10); 2112 } 2113 v = *(uint32_t *)data; 2114 v = htole32(v); 2115 HWRITE4(hp, SDHC_DATA, v); 2116 } 2117 } 2118 2119 /* Prepare for another command. */ 2120 static int 2121 sdhc_soft_reset(struct sdhc_host *hp, int mask) 2122 { 2123 int timo; 2124 2125 KASSERT(mutex_owned(&hp->intr_lock)); 2126 2127 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 2128 2129 /* Request the reset. */ 2130 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 2131 2132 /* 2133 * If necessary, wait for the controller to set the bits to 2134 * acknowledge the reset. 2135 */ 2136 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 2137 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 2138 for (timo = 10000; timo > 0; timo--) { 2139 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 2140 break; 2141 /* Short delay because I worry we may miss it... */ 2142 sdmmc_delay(1); 2143 } 2144 if (timo == 0) { 2145 DPRINTF(1,("%s: timeout for reset on\n", __func__)); 2146 return ETIMEDOUT; 2147 } 2148 } 2149 2150 /* 2151 * Wait for the controller to clear the bits to indicate that 2152 * the reset has completed. 2153 */ 2154 for (timo = 10; timo > 0; timo--) { 2155 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 2156 break; 2157 sdmmc_delay(10000); 2158 } 2159 if (timo == 0) { 2160 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 2161 HREAD1(hp, SDHC_SOFTWARE_RESET))); 2162 return ETIMEDOUT; 2163 } 2164 2165 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 2166 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 2167 } 2168 2169 return 0; 2170 } 2171 2172 static int 2173 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo, bool probing) 2174 { 2175 int status, error, nointr; 2176 2177 KASSERT(mutex_owned(&hp->intr_lock)); 2178 2179 mask |= SDHC_ERROR_INTERRUPT; 2180 2181 nointr = 0; 2182 status = hp->intr_status & mask; 2183 while (status == 0) { 2184 if (cv_timedwait(&hp->intr_cv, &hp->intr_lock, timo) 2185 == EWOULDBLOCK) { 2186 nointr = 1; 2187 break; 2188 } 2189 status = hp->intr_status & mask; 2190 } 2191 error = hp->intr_error_status; 2192 2193 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 2194 error)); 2195 2196 hp->intr_status &= ~status; 2197 hp->intr_error_status &= ~error; 2198 2199 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 2200 if (ISSET(error, SDHC_DMA_ERROR)) 2201 device_printf(hp->sc->sc_dev,"dma error\n"); 2202 if (ISSET(error, SDHC_ADMA_ERROR)) 2203 device_printf(hp->sc->sc_dev,"adma error\n"); 2204 if (ISSET(error, SDHC_AUTO_CMD12_ERROR)) 2205 device_printf(hp->sc->sc_dev,"auto_cmd12 error\n"); 2206 if (ISSET(error, SDHC_CURRENT_LIMIT_ERROR)) 2207 device_printf(hp->sc->sc_dev,"current limit error\n"); 2208 if (ISSET(error, SDHC_DATA_END_BIT_ERROR)) 2209 device_printf(hp->sc->sc_dev,"data end bit error\n"); 2210 if (ISSET(error, SDHC_DATA_CRC_ERROR)) 2211 device_printf(hp->sc->sc_dev,"data crc error\n"); 2212 if (ISSET(error, SDHC_DATA_TIMEOUT_ERROR)) 2213 device_printf(hp->sc->sc_dev,"data timeout error\n"); 2214 if (ISSET(error, SDHC_CMD_INDEX_ERROR)) 2215 device_printf(hp->sc->sc_dev,"cmd index error\n"); 2216 if (ISSET(error, SDHC_CMD_END_BIT_ERROR)) 2217 device_printf(hp->sc->sc_dev,"cmd end bit error\n"); 2218 if (ISSET(error, SDHC_CMD_CRC_ERROR)) 2219 device_printf(hp->sc->sc_dev,"cmd crc error\n"); 2220 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR)) { 2221 if (!probing) 2222 device_printf(hp->sc->sc_dev,"cmd timeout error\n"); 2223 #ifdef SDHC_DEBUG 2224 else if (sdhcdebug > 0) 2225 device_printf(hp->sc->sc_dev,"cmd timeout (expected)\n"); 2226 #endif 2227 } 2228 if ((error & ~SDHC_EINTR_STATUS_MASK) != 0) 2229 device_printf(hp->sc->sc_dev,"vendor error %#x\n", 2230 (error & ~SDHC_EINTR_STATUS_MASK)); 2231 if (error == 0) 2232 device_printf(hp->sc->sc_dev,"no error\n"); 2233 2234 /* Command timeout has higher priority than command complete. */ 2235 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR)) 2236 CLR(status, SDHC_COMMAND_COMPLETE); 2237 2238 /* Transfer complete has higher priority than data timeout. */ 2239 if (ISSET(status, SDHC_TRANSFER_COMPLETE)) 2240 CLR(error, SDHC_DATA_TIMEOUT_ERROR); 2241 } 2242 2243 if (nointr || 2244 (ISSET(status, SDHC_ERROR_INTERRUPT) && error)) { 2245 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 2246 (void)sdhc_soft_reset(hp, SDHC_RESET_CMD|SDHC_RESET_DAT); 2247 hp->intr_error_status = 0; 2248 status = 0; 2249 } 2250 2251 return status; 2252 } 2253 2254 /* 2255 * Established by attachment driver at interrupt priority IPL_SDMMC. 2256 */ 2257 int 2258 sdhc_intr(void *arg) 2259 { 2260 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 2261 struct sdhc_host *hp; 2262 int done = 0; 2263 uint16_t status; 2264 uint16_t error; 2265 2266 /* We got an interrupt, but we don't know from which slot. */ 2267 for (size_t host = 0; host < sc->sc_nhosts; host++) { 2268 hp = sc->sc_host[host]; 2269 if (hp == NULL) 2270 continue; 2271 2272 mutex_enter(&hp->intr_lock); 2273 2274 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 2275 /* Find out which interrupts are pending. */ 2276 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 2277 status = xstatus; 2278 error = xstatus >> 16; 2279 if (ISSET(sc->sc_flags, SDHC_FLAG_USDHC) && 2280 (xstatus & SDHC_TRANSFER_COMPLETE) && 2281 !(xstatus & SDHC_DMA_INTERRUPT)) { 2282 /* read again due to uSDHC errata */ 2283 status = xstatus = HREAD4(hp, 2284 SDHC_NINTR_STATUS); 2285 error = xstatus >> 16; 2286 } 2287 if (ISSET(sc->sc_flags, 2288 SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 2289 if ((error & SDHC_NINTR_STATUS_MASK) != 0) 2290 SET(status, SDHC_ERROR_INTERRUPT); 2291 } 2292 if (error) 2293 xstatus |= SDHC_ERROR_INTERRUPT; 2294 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 2295 goto next_port; /* no interrupt for us */ 2296 /* Acknowledge the interrupts we are about to handle. */ 2297 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 2298 } else { 2299 /* Find out which interrupts are pending. */ 2300 error = 0; 2301 status = HREAD2(hp, SDHC_NINTR_STATUS); 2302 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 2303 goto next_port; /* no interrupt for us */ 2304 /* Acknowledge the interrupts we are about to handle. */ 2305 HWRITE2(hp, SDHC_NINTR_STATUS, status); 2306 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 2307 /* Acknowledge error interrupts. */ 2308 error = HREAD2(hp, SDHC_EINTR_STATUS); 2309 HWRITE2(hp, SDHC_EINTR_STATUS, error); 2310 } 2311 } 2312 2313 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 2314 status, error)); 2315 2316 /* Claim this interrupt. */ 2317 done = 1; 2318 2319 if (ISSET(status, SDHC_ERROR_INTERRUPT) && 2320 ISSET(error, SDHC_ADMA_ERROR)) { 2321 uint8_t adma_err = HREAD1(hp, SDHC_ADMA_ERROR_STATUS); 2322 printf("%s: ADMA error, status %02x\n", HDEVNAME(hp), 2323 adma_err); 2324 } 2325 2326 /* 2327 * Wake up the sdmmc event thread to scan for cards. 2328 */ 2329 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 2330 if (hp->sdmmc != NULL) { 2331 sdmmc_needs_discover(hp->sdmmc); 2332 } 2333 if (ISSET(sc->sc_flags, 2334 SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 2335 HCLR4(hp, SDHC_NINTR_STATUS_EN, 2336 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 2337 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 2338 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 2339 } 2340 } 2341 2342 /* 2343 * Schedule re-tuning process (UHS). 2344 */ 2345 if (ISSET(status, SDHC_RETUNING_EVENT)) { 2346 atomic_swap_uint(&hp->tuning_timer_pending, 1); 2347 } 2348 2349 /* 2350 * Wake up the blocking process to service command 2351 * related interrupt(s). 2352 */ 2353 if (ISSET(status, SDHC_COMMAND_COMPLETE|SDHC_ERROR_INTERRUPT| 2354 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 2355 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 2356 hp->intr_error_status |= error; 2357 hp->intr_status |= status; 2358 if (ISSET(sc->sc_flags, 2359 SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) { 2360 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 2361 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 2362 } 2363 cv_broadcast(&hp->intr_cv); 2364 } 2365 2366 /* 2367 * Service SD card interrupts. 2368 */ 2369 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC) 2370 && ISSET(status, SDHC_CARD_INTERRUPT)) { 2371 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 2372 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 2373 sdmmc_card_intr(hp->sdmmc); 2374 } 2375 next_port: 2376 mutex_exit(&hp->intr_lock); 2377 } 2378 2379 return done; 2380 } 2381 2382 kmutex_t * 2383 sdhc_host_lock(struct sdhc_host *hp) 2384 { 2385 return &hp->intr_lock; 2386 } 2387 2388 #ifdef SDHC_DEBUG 2389 void 2390 sdhc_dump_regs(struct sdhc_host *hp) 2391 { 2392 2393 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 2394 HREAD4(hp, SDHC_PRESENT_STATE)); 2395 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 2396 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 2397 HREAD1(hp, SDHC_POWER_CTL)); 2398 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 2399 HREAD2(hp, SDHC_NINTR_STATUS)); 2400 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 2401 HREAD2(hp, SDHC_EINTR_STATUS)); 2402 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 2403 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 2404 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 2405 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 2406 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 2407 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 2408 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 2409 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 2410 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 2411 HREAD4(hp, SDHC_CAPABILITIES)); 2412 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 2413 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 2414 } 2415 #endif 2416
Indexes created Thu Sep 25 02:09:54 GMT 2025