sdmmc_ioreg.h revision 1.4 1 1.4 mlelstv /* $NetBSD: sdmmc_ioreg.h,v 1.4 2019/09/01 05:45:42 mlelstv Exp $ */
2 1.1 nonaka /* $OpenBSD: sdmmc_ioreg.h,v 1.4 2007/06/02 01:48:37 uwe Exp $ */
3 1.1 nonaka
4 1.1 nonaka /*
5 1.1 nonaka * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org>
6 1.1 nonaka *
7 1.1 nonaka * Permission to use, copy, modify, and distribute this software for any
8 1.1 nonaka * purpose with or without fee is hereby granted, provided that the above
9 1.1 nonaka * copyright notice and this permission notice appear in all copies.
10 1.1 nonaka *
11 1.1 nonaka * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 1.1 nonaka * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 1.1 nonaka * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 1.1 nonaka * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 1.1 nonaka * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 1.1 nonaka * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 1.1 nonaka * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 1.1 nonaka */
19 1.1 nonaka
20 1.1 nonaka #ifndef _SDMMC_IOREG_H_
21 1.1 nonaka #define _SDMMC_IOREG_H_
22 1.1 nonaka
23 1.1 nonaka /* SDIO commands */ /* response type */
24 1.1 nonaka #define SD_IO_SEND_OP_COND 5 /* R4 */
25 1.1 nonaka #define SD_IO_RW_DIRECT 52 /* R5 */
26 1.1 nonaka #define SD_IO_RW_EXTENDED 53 /* R5? */
27 1.1 nonaka
28 1.1 nonaka /* CMD52 arguments */
29 1.1 nonaka #define SD_ARG_CMD52_READ (0<<31)
30 1.3 msaitoh #define SD_ARG_CMD52_WRITE (1UL<<31)
31 1.1 nonaka #define SD_ARG_CMD52_FUNC_SHIFT 28
32 1.1 nonaka #define SD_ARG_CMD52_FUNC_MASK 0x7
33 1.1 nonaka #define SD_ARG_CMD52_EXCHANGE (1<<27)
34 1.1 nonaka #define SD_ARG_CMD52_REG_SHIFT 9
35 1.1 nonaka #define SD_ARG_CMD52_REG_MASK 0x1ffff
36 1.1 nonaka #define SD_ARG_CMD52_DATA_SHIFT 0
37 1.1 nonaka #define SD_ARG_CMD52_DATA_MASK 0xff
38 1.1 nonaka #define SD_R5_DATA(resp) ((resp)[0] & 0xff)
39 1.1 nonaka
40 1.1 nonaka /* CMD53 arguments */
41 1.1 nonaka #define SD_ARG_CMD53_READ (0<<31)
42 1.1 nonaka #define SD_ARG_CMD53_WRITE (1<<31)
43 1.1 nonaka #define SD_ARG_CMD53_FUNC_SHIFT 28
44 1.1 nonaka #define SD_ARG_CMD53_FUNC_MASK 0x7
45 1.1 nonaka #define SD_ARG_CMD53_BLOCK_MODE (1<<27)
46 1.1 nonaka #define SD_ARG_CMD53_INCREMENT (1<<26)
47 1.1 nonaka #define SD_ARG_CMD53_REG_SHIFT 9
48 1.1 nonaka #define SD_ARG_CMD53_REG_MASK 0x1ffff
49 1.1 nonaka #define SD_ARG_CMD53_LENGTH_SHIFT 0
50 1.1 nonaka #define SD_ARG_CMD53_LENGTH_MASK 0x1ff
51 1.4 mlelstv #define SD_ARG_CMD53_LENGTH_MAX 64
52 1.1 nonaka
53 1.1 nonaka /* 48-bit response decoding (32 bits w/o CRC) */
54 1.1 nonaka #define MMC_R4(resp) ((resp)[0])
55 1.1 nonaka #define MMC_R5(resp) ((resp)[0])
56 1.1 nonaka
57 1.1 nonaka /* SD R4 response (IO OCR) */
58 1.1 nonaka #define SD_IO_OCR_MEM_READY (1<<31)
59 1.2 kiyohara #define SD_IO_OCR_NUM_FUNCTIONS(ocr) (((ocr) >> 28) & 0x7)
60 1.2 kiyohara #define SD_IO_OCR_MEM_PRESENT (1<<27)
61 1.1 nonaka #define SD_IO_OCR_MASK 0x00fffff0
62 1.1 nonaka
63 1.1 nonaka /* Card Common Control Registers (CCCR) */
64 1.1 nonaka #define SD_IO_CCCR_START 0x00000
65 1.1 nonaka #define SD_IO_CCCR_SIZE 0x100
66 1.1 nonaka #define SD_IO_CCCR_CCCR_SDIO_REV 0x00
67 1.1 nonaka #define SD_IO_CCCR_CCCR_REV(r) ((r) & 0xf)
68 1.1 nonaka #define CCCR_CCCR_REV_1_00 0
69 1.1 nonaka #define CCCR_CCCR_REV_1_10 1
70 1.2 kiyohara #define CCCR_CCCR_REV_1_20 2
71 1.4 mlelstv #define CCCR_CCCR_REV_3_00 3
72 1.1 nonaka #define SD_IO_CCCR_SDIO_REV(r) (((r) >> 4) & 0xf)
73 1.1 nonaka #define CCCR_SDIO_REV_1_00 0
74 1.1 nonaka #define CCCR_SDIO_REV_1_10 1
75 1.2 kiyohara #define CCCR_SDIO_REV_1_20 2 /* (unreleased) */
76 1.2 kiyohara #define CCCR_SDIO_REV_2_00 3
77 1.4 mlelstv #define CCCR_SDIO_REV_3_00 4
78 1.1 nonaka #define SD_IO_CCCR_SPEC_REV 0x01
79 1.1 nonaka #define SD_IO_CCCR_SD_PHYS_SPEC_VER(r) ((r) & 0xf)
80 1.1 nonaka #define CCCR_SD_PHYS_SPEC_VER_1_01 0
81 1.1 nonaka #define CCCR_SD_PHYS_SPEC_VER_1_10 1
82 1.2 kiyohara #define CCCR_SD_PHYS_SPEC_VER_2_00 2
83 1.4 mlelstv #define CCCR_SD_PHYS_SPEC_VER_3_00 3
84 1.1 nonaka #define SD_IO_CCCR_FN_ENABLE 0x02
85 1.1 nonaka #define SD_IO_CCCR_FN_IOREADY 0x03
86 1.1 nonaka #define SD_IO_CCCR_FN_INTEN 0x04
87 1.1 nonaka #define CCCR_INTEN_INTM (1<<0)
88 1.1 nonaka #define SD_IO_CCCR_FN_INTPENDING 0x05
89 1.1 nonaka #define SD_IO_CCCR_CTL 0x06
90 1.1 nonaka #define CCCR_CTL_RES (1<<3)
91 1.1 nonaka #define SD_IO_CCCR_BUS_WIDTH 0x07
92 1.2 kiyohara #define CCCR_BUS_WIDTH_4 (2<<0)
93 1.2 kiyohara #define CCCR_BUS_WIDTH_1 (0<<0)
94 1.4 mlelstv #define CCCR_BUS_ECSI (1<<5)
95 1.4 mlelstv #define CCCR_BUS_SCSI (1<<6)
96 1.4 mlelstv #define CCCR_BUS_NOCD (1<<7)
97 1.1 nonaka #define SD_IO_CCCR_CAPABILITY 0x08
98 1.1 nonaka #define CCCR_CAPS_SDC (1<<0)
99 1.1 nonaka #define CCCR_CAPS_SMB (1<<1) /* Multi-Block support */
100 1.1 nonaka #define CCCR_CAPS_SRB (1<<2) /* Read Wait support */
101 1.1 nonaka #define CCCR_CAPS_SBS (1<<3) /* Suspend/Resume support */
102 1.1 nonaka #define CCCR_CAPS_S4MI (1<<4) /* intr support in 4-bit mode */
103 1.1 nonaka #define CCCR_CAPS_E4MI (1<<5) /* enable intr in 4-bit mode */
104 1.1 nonaka #define CCCR_CAPS_LSC (1<<6) /* Low speed card */
105 1.1 nonaka #define CCCR_CAPS_4BLS (1<<7) /* 4-bit support for low speed */
106 1.1 nonaka #define SD_IO_CCCR_CISPTR 0x09 /* XXX 9-10, 10-11, or 9-12 */
107 1.1 nonaka #define SD_IO_CCCR_BUS_SUSPEND 0x0c
108 1.1 nonaka #define SD_IO_CCCR_FUNC_SELECT 0x0d
109 1.4 mlelstv #define SD_IO_CCCR_EXEC_FLAGS 0x0e
110 1.4 mlelstv #define SD_IO_CCCR_READY_FLAGS 0x0f
111 1.1 nonaka #define CCCR_FUNC_FS(r) ((r) & 0xf)
112 1.1 nonaka #define CCCR_FUNC_FS_FN(fn) ((fn) & 0x7)
113 1.1 nonaka #define CCCR_FUNC_FS_MEM 8
114 1.1 nonaka #define SD_IO_CCCR_FN_EXEC_FLG 0x0e
115 1.1 nonaka #define SD_IO_CCCR_FN_READY_FLG 0x0f
116 1.1 nonaka #define SD_IO_CCCR_FN0_BLKSIZ 0x10 /* 0x10-0x11 */
117 1.1 nonaka #define SD_IO_CCCR_POWER_CTL 0x12
118 1.2 kiyohara #define SD_IO_CCCR_HIGH_SPEED 0x13
119 1.2 kiyohara #define CCCR_HIGH_SPEED_SHS (1<<0) /* Support High-Speed */
120 1.2 kiyohara #define CCCR_HIGH_SPEED_EHS (1<<1) /* Enable High-Speed */
121 1.4 mlelstv #define CCCR_HIGH_SPEED_SDR50 (2<<1)
122 1.4 mlelstv #define CCCR_HIGH_SPEED_SDR104 (3<<1)
123 1.4 mlelstv #define CCCR_HIGH_SPEED_DDR50 (4<<1)
124 1.4 mlelstv #define SD_IO_CCCR_UHS 0x14
125 1.4 mlelstv #define CCCR_UHS_SDR50 (1<<0)
126 1.4 mlelstv #define CCCR_UHS_SDR104 (1<<1)
127 1.4 mlelstv #define CCCR_UHS_DDR50 (1<<2)
128 1.4 mlelstv #define SD_IO_DRIVE_STRENGTH 0x15
129 1.4 mlelstv #define CCCR_DRIVE_SDTA (1<<0)
130 1.4 mlelstv #define CCCR_DRIVE_SDTC (1<<1)
131 1.4 mlelstv #define CCCR_DRIVE_SDTD (1<<2)
132 1.1 nonaka
133 1.1 nonaka /* Function Basic Registers (FBR) */
134 1.1 nonaka #define SD_IO_FBR_START 0x00100
135 1.2 kiyohara #define SD_IO_FBR_SIZE 0x100
136 1.2 kiyohara #define SD_IO_FBR(func) ((((func) - 1) * SD_IO_FBR_SIZE) + SD_IO_FBR_START)
137 1.4 mlelstv
138 1.4 mlelstv /* FBR offsets */
139 1.4 mlelstv #define SD_IO_FBR_BASIC 0x00
140 1.2 kiyohara #define FBR_STD_FUNC_IF_CODE(v) ((v) & 0x0f)
141 1.4 mlelstv #define FBR_STD_FUNC_CSA(v) ((v) & 0x40) /* supports CSA */
142 1.4 mlelstv #define FBR_STD_FUNC_CSAE(v) ((v) & 0x80) /* enable CSA */
143 1.4 mlelstv #define SD_IO_FBR_EXT 0x01
144 1.4 mlelstv #define SD_IO_FBR_PWR 0x02
145 1.4 mlelstv #define FBR_PWR_SPS (1<<0) /* support power selection */
146 1.4 mlelstv #define FBR_PWR_EPS (1<<1) /* enable low power selection */
147 1.4 mlelstv #define SD_IO_FBR_CIS 0x09 /* 0x109-0x10b */
148 1.4 mlelstv #define SD_IO_FBR_CSA 0x0c /* 0x10c-0x10e */
149 1.4 mlelstv #define SD_IO_FBR_DATA 0x0f
150 1.4 mlelstv #define SD_IO_FBR_BLOCKLEN 0x10 /* 0x110-0x111 */
151 1.1 nonaka
152 1.1 nonaka /* Card Information Structure (CIS) */
153 1.1 nonaka #define SD_IO_CIS_START 0x01000
154 1.1 nonaka #define SD_IO_CIS_SIZE 0x17000
155 1.1 nonaka
156 1.2 kiyohara /* SDIO Standard Function Interface code */
157 1.2 kiyohara #define SD_IO_SFIC_NO_STANDARD 0x0
158 1.2 kiyohara #define SD_IO_SFIC_UART 0x1
159 1.2 kiyohara #define SD_IO_SFIC_TYPEA_BLUETOOTH 0x2 /* Type-A Bluetooth */
160 1.2 kiyohara #define SD_IO_SFIC_TYPEB_BLUETOOTH 0x3 /* Type-B Bluetooth */
161 1.2 kiyohara #define SD_IO_SFIC_GPS 0x4
162 1.2 kiyohara #define SD_IO_SFIC_CAMERA 0x5
163 1.2 kiyohara #define SD_IO_SFIC_PHS 0x6
164 1.2 kiyohara #define SD_IO_SFIC_WLAN 0x7
165 1.2 kiyohara #define SD_IO_SFIC_ATA 0x8 /* Embedded SDIO-ATA */
166 1.4 mlelstv #define SD_IO_SFIC_EXTENDED 0xf /* See next byte */
167 1.1 nonaka
168 1.1 nonaka #endif /* _SDMMC_IOREG_H_ */
169