sdmmc_mem.c revision 1.30
1 /* $NetBSD: sdmmc_mem.c,v 1.30 2013/10/25 11:35:55 martin Exp $ */ 2 /* $OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2007, 2008, 2009, 2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 /* Routines for SD/MMC memory cards. */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.30 2013/10/25 11:35:55 martin Exp $"); 49 50 #ifdef _KERNEL_OPT 51 #include "opt_sdmmc.h" 52 #endif 53 54 #include <sys/param.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 60 #include <dev/sdmmc/sdmmcchip.h> 61 #include <dev/sdmmc/sdmmcreg.h> 62 #include <dev/sdmmc/sdmmcvar.h> 63 64 #ifdef SDMMC_DEBUG 65 #define DPRINTF(s) do { printf s; } while (/*CONSTCOND*/0) 66 #else 67 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 68 #endif 69 70 typedef struct { uint32_t _bits[512/32]; } __packed __aligned(4) sdmmc_bitfield512_t; 71 72 static int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 73 static int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 74 static int sdmmc_mem_send_cid(struct sdmmc_softc *, sdmmc_response *); 75 static int sdmmc_mem_send_csd(struct sdmmc_softc *, struct sdmmc_function *, 76 sdmmc_response *); 77 static int sdmmc_mem_send_scr(struct sdmmc_softc *, struct sdmmc_function *, 78 uint32_t scr[2]); 79 static int sdmmc_mem_decode_scr(struct sdmmc_softc *, struct sdmmc_function *); 80 static int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 81 static int sdmmc_set_bus_width(struct sdmmc_function *, int); 82 static int sdmmc_mem_sd_switch(struct sdmmc_function *, int, int, int, sdmmc_bitfield512_t *); 83 static int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, 84 uint8_t); 85 static int sdmmc_mem_spi_read_ocr(struct sdmmc_softc *, uint32_t, uint32_t *); 86 static int sdmmc_mem_single_read_block(struct sdmmc_function *, uint32_t, 87 u_char *, size_t); 88 static int sdmmc_mem_single_write_block(struct sdmmc_function *, uint32_t, 89 u_char *, size_t); 90 static int sdmmc_mem_read_block_subr(struct sdmmc_function *, uint32_t, 91 u_char *, size_t); 92 static int sdmmc_mem_write_block_subr(struct sdmmc_function *, uint32_t, 93 u_char *, size_t); 94 95 /* 96 * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 97 */ 98 int 99 sdmmc_mem_enable(struct sdmmc_softc *sc) 100 { 101 uint32_t host_ocr; 102 uint32_t card_ocr; 103 uint32_t ocr = 0; 104 int error; 105 106 SDMMC_LOCK(sc); 107 108 /* Set host mode to SD "combo" card or SD memory-only. */ 109 SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 110 111 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 112 sdmmc_spi_chip_initialize(sc->sc_spi_sct, sc->sc_sch); 113 114 /* Reset memory (*must* do that before CMD55 or CMD1). */ 115 sdmmc_go_idle_state(sc); 116 117 /* Check SD Ver.2 */ 118 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 119 if (error == 0 && card_ocr == 0x1aa) 120 SET(ocr, MMC_OCR_HCS); 121 122 /* 123 * Read the SD/MMC memory OCR value by issuing CMD55 followed 124 * by ACMD41 to read the OCR value from memory-only SD cards. 125 * MMC cards will not respond to CMD55 or ACMD41 and this is 126 * how we distinguish them from SD cards. 127 */ 128 mmc_mode: 129 error = sdmmc_mem_send_op_cond(sc, 130 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr); 131 if (error) { 132 if (ISSET(sc->sc_flags, SMF_SD_MODE) && 133 !ISSET(sc->sc_flags, SMF_IO_MODE)) { 134 /* Not a SD card, switch to MMC mode. */ 135 DPRINTF(("%s: switch to MMC mode\n", SDMMCDEVNAME(sc))); 136 CLR(sc->sc_flags, SMF_SD_MODE); 137 goto mmc_mode; 138 } 139 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 140 DPRINTF(("%s: couldn't read memory OCR\n", 141 SDMMCDEVNAME(sc))); 142 goto out; 143 } else { 144 /* Not a "combo" card. */ 145 CLR(sc->sc_flags, SMF_MEM_MODE); 146 error = 0; 147 goto out; 148 } 149 } 150 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 151 /* get card OCR */ 152 error = sdmmc_mem_spi_read_ocr(sc, ocr, &card_ocr); 153 if (error) { 154 DPRINTF(("%s: couldn't read SPI memory OCR\n", 155 SDMMCDEVNAME(sc))); 156 goto out; 157 } 158 } 159 160 /* Set the lowest voltage supported by the card and host. */ 161 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 162 error = sdmmc_set_bus_power(sc, host_ocr, card_ocr); 163 if (error) { 164 DPRINTF(("%s: couldn't supply voltage requested by card\n", 165 SDMMCDEVNAME(sc))); 166 goto out; 167 } 168 host_ocr &= card_ocr; 169 host_ocr |= ocr; 170 171 /* Send the new OCR value until all cards are ready. */ 172 error = sdmmc_mem_send_op_cond(sc, host_ocr, NULL); 173 if (error) { 174 DPRINTF(("%s: couldn't send memory OCR\n", SDMMCDEVNAME(sc))); 175 goto out; 176 } 177 178 out: 179 SDMMC_UNLOCK(sc); 180 181 return error; 182 } 183 184 /* 185 * Read the CSD and CID from all cards and assign each card a unique 186 * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 187 */ 188 void 189 sdmmc_mem_scan(struct sdmmc_softc *sc) 190 { 191 sdmmc_response resp; 192 struct sdmmc_function *sf; 193 uint16_t next_rca; 194 int error; 195 int retry; 196 197 SDMMC_LOCK(sc); 198 199 /* 200 * CMD2 is a broadcast command understood by SD cards and MMC 201 * cards. All cards begin to respond to the command, but back 202 * off if another card drives the CMD line to a different level. 203 * Only one card will get its entire response through. That 204 * card remains silent once it has been assigned a RCA. 205 */ 206 for (retry = 0; retry < 100; retry++) { 207 error = sdmmc_mem_send_cid(sc, &resp); 208 if (error) { 209 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && 210 error == ETIMEDOUT) { 211 /* No more cards there. */ 212 break; 213 } 214 DPRINTF(("%s: couldn't read CID\n", SDMMCDEVNAME(sc))); 215 break; 216 } 217 218 /* In MMC mode, find the next available RCA. */ 219 next_rca = 1; 220 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 221 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) 222 next_rca++; 223 } 224 225 /* Allocate a sdmmc_function structure. */ 226 sf = sdmmc_function_alloc(sc); 227 sf->rca = next_rca; 228 229 /* 230 * Remember the CID returned in the CMD2 response for 231 * later decoding. 232 */ 233 memcpy(sf->raw_cid, resp, sizeof(sf->raw_cid)); 234 235 /* 236 * Silence the card by assigning it a unique RCA, or 237 * querying it for its RCA in the case of SD. 238 */ 239 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 240 if (sdmmc_set_relative_addr(sc, sf) != 0) { 241 aprint_error_dev(sc->sc_dev, 242 "couldn't set mem RCA\n"); 243 sdmmc_function_free(sf); 244 break; 245 } 246 } 247 248 /* 249 * If this is a memory-only card, the card responding 250 * first becomes an alias for SDIO function 0. 251 */ 252 if (sc->sc_fn0 == NULL) 253 sc->sc_fn0 = sf; 254 255 SIMPLEQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 256 257 /* only one function in SPI mode */ 258 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 259 break; 260 } 261 262 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 263 /* Go to Data Transfer Mode, if possible. */ 264 sdmmc_chip_bus_rod(sc->sc_sct, sc->sc_sch, 0); 265 266 /* 267 * All cards are either inactive or awaiting further commands. 268 * Read the CSDs and decode the raw CID for each card. 269 */ 270 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) { 271 error = sdmmc_mem_send_csd(sc, sf, &resp); 272 if (error) { 273 SET(sf->flags, SFF_ERROR); 274 continue; 275 } 276 277 if (sdmmc_decode_csd(sc, resp, sf) != 0 || 278 sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 279 SET(sf->flags, SFF_ERROR); 280 continue; 281 } 282 283 #ifdef SDMMC_DEBUG 284 printf("%s: CID: ", SDMMCDEVNAME(sc)); 285 sdmmc_print_cid(&sf->cid); 286 #endif 287 } 288 289 SDMMC_UNLOCK(sc); 290 } 291 292 int 293 sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 294 struct sdmmc_function *sf) 295 { 296 /* TRAN_SPEED(2:0): transfer rate exponent */ 297 static const int speed_exponent[8] = { 298 100 * 1, /* 100 Kbits/s */ 299 1 * 1000, /* 1 Mbits/s */ 300 10 * 1000, /* 10 Mbits/s */ 301 100 * 1000, /* 100 Mbits/s */ 302 0, 303 0, 304 0, 305 0, 306 }; 307 /* TRAN_SPEED(6:3): time mantissa */ 308 static const int speed_mantissa[16] = { 309 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 310 }; 311 struct sdmmc_csd *csd = &sf->csd; 312 int e, m; 313 314 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 315 /* 316 * CSD version 1.0 corresponds to SD system 317 * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 318 */ 319 csd->csdver = SD_CSD_CSDVER(resp); 320 switch (csd->csdver) { 321 case SD_CSD_CSDVER_2_0: 322 DPRINTF(("%s: SD Ver.2.0\n", SDMMCDEVNAME(sc))); 323 SET(sf->flags, SFF_SDHC); 324 csd->capacity = SD_CSD_V2_CAPACITY(resp); 325 csd->read_bl_len = SD_CSD_V2_BL_LEN; 326 break; 327 328 case SD_CSD_CSDVER_1_0: 329 DPRINTF(("%s: SD Ver.1.0\n", SDMMCDEVNAME(sc))); 330 csd->capacity = SD_CSD_CAPACITY(resp); 331 csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 332 break; 333 334 default: 335 aprint_error_dev(sc->sc_dev, 336 "unknown SD CSD structure version 0x%x\n", 337 csd->csdver); 338 return 1; 339 } 340 341 csd->mmcver = SD_CSD_MMCVER(resp); 342 csd->write_bl_len = SD_CSD_WRITE_BL_LEN(resp); 343 csd->r2w_factor = SD_CSD_R2W_FACTOR(resp); 344 e = SD_CSD_SPEED_EXP(resp); 345 m = SD_CSD_SPEED_MANT(resp); 346 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 347 csd->ccc = SD_CSD_CCC(resp); 348 } else { 349 csd->csdver = MMC_CSD_CSDVER(resp); 350 if (csd->csdver == MMC_CSD_CSDVER_1_0) { 351 aprint_error_dev(sc->sc_dev, 352 "unknown MMC CSD structure version 0x%x\n", 353 csd->csdver); 354 return 1; 355 } 356 357 csd->mmcver = MMC_CSD_MMCVER(resp); 358 csd->capacity = MMC_CSD_CAPACITY(resp); 359 csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 360 csd->write_bl_len = MMC_CSD_WRITE_BL_LEN(resp); 361 csd->r2w_factor = MMC_CSD_R2W_FACTOR(resp); 362 e = MMC_CSD_TRAN_SPEED_EXP(resp); 363 m = MMC_CSD_TRAN_SPEED_MANT(resp); 364 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 365 } 366 if ((1 << csd->read_bl_len) > SDMMC_SECTOR_SIZE) 367 csd->capacity *= (1 << csd->read_bl_len) / SDMMC_SECTOR_SIZE; 368 369 #ifdef SDMMC_DUMP_CSD 370 sdmmc_print_csd(resp, csd); 371 #endif 372 373 return 0; 374 } 375 376 int 377 sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 378 struct sdmmc_function *sf) 379 { 380 struct sdmmc_cid *cid = &sf->cid; 381 382 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 383 cid->mid = SD_CID_MID(resp); 384 cid->oid = SD_CID_OID(resp); 385 SD_CID_PNM_CPY(resp, cid->pnm); 386 cid->rev = SD_CID_REV(resp); 387 cid->psn = SD_CID_PSN(resp); 388 cid->mdt = SD_CID_MDT(resp); 389 } else { 390 switch(sf->csd.mmcver) { 391 case MMC_CSD_MMCVER_1_0: 392 case MMC_CSD_MMCVER_1_4: 393 cid->mid = MMC_CID_MID_V1(resp); 394 MMC_CID_PNM_V1_CPY(resp, cid->pnm); 395 cid->rev = MMC_CID_REV_V1(resp); 396 cid->psn = MMC_CID_PSN_V1(resp); 397 cid->mdt = MMC_CID_MDT_V1(resp); 398 break; 399 case MMC_CSD_MMCVER_2_0: 400 case MMC_CSD_MMCVER_3_1: 401 case MMC_CSD_MMCVER_4_0: 402 cid->mid = MMC_CID_MID_V2(resp); 403 cid->oid = MMC_CID_OID_V2(resp); 404 MMC_CID_PNM_V2_CPY(resp, cid->pnm); 405 cid->psn = MMC_CID_PSN_V2(resp); 406 break; 407 default: 408 aprint_error_dev(sc->sc_dev, "unknown MMC version %d\n", 409 sf->csd.mmcver); 410 return 1; 411 } 412 } 413 return 0; 414 } 415 416 void 417 sdmmc_print_cid(struct sdmmc_cid *cid) 418 { 419 420 printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 421 " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 422 cid->mdt); 423 } 424 425 #ifdef SDMMC_DUMP_CSD 426 void 427 sdmmc_print_csd(sdmmc_response resp, struct sdmmc_csd *csd) 428 { 429 430 printf("csdver = %d\n", csd->csdver); 431 printf("mmcver = %d\n", csd->mmcver); 432 printf("capacity = 0x%08x\n", csd->capacity); 433 printf("read_bl_len = %d\n", csd->read_bl_len); 434 printf("write_bl_len = %d\n", csd->write_bl_len); 435 printf("r2w_factor = %d\n", csd->r2w_factor); 436 printf("tran_speed = %d\n", csd->tran_speed); 437 printf("ccc = 0x%x\n", csd->ccc); 438 } 439 #endif 440 441 /* 442 * Initialize a SD/MMC memory card. 443 */ 444 int 445 sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 446 { 447 int error = 0; 448 449 SDMMC_LOCK(sc); 450 451 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 452 error = sdmmc_select_card(sc, sf); 453 if (error) 454 goto out; 455 } 456 457 if (!ISSET(sf->flags, SFF_SDHC)) { 458 error = sdmmc_mem_set_blocklen(sc, sf); 459 if (error) 460 goto out; 461 } 462 463 if (ISSET(sc->sc_flags, SMF_SD_MODE)) 464 error = sdmmc_mem_sd_init(sc, sf); 465 else 466 error = sdmmc_mem_mmc_init(sc, sf); 467 468 out: 469 SDMMC_UNLOCK(sc); 470 471 return error; 472 } 473 474 /* 475 * Get or set the card's memory OCR value (SD or MMC). 476 */ 477 int 478 sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 479 { 480 struct sdmmc_command cmd; 481 int error; 482 int retry; 483 484 /* Don't lock */ 485 486 /* 487 * If we change the OCR value, retry the command until the OCR 488 * we receive in response has the "CARD BUSY" bit set, meaning 489 * that all cards are ready for identification. 490 */ 491 for (retry = 0; retry < 100; retry++) { 492 memset(&cmd, 0, sizeof(cmd)); 493 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? 494 ocr : (ocr & MMC_OCR_HCS); 495 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3 | SCF_RSP_SPI_R1; 496 497 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 498 cmd.c_opcode = SD_APP_OP_COND; 499 error = sdmmc_app_command(sc, NULL, &cmd); 500 } else { 501 cmd.c_opcode = MMC_SEND_OP_COND; 502 error = sdmmc_mmc_command(sc, &cmd); 503 } 504 if (error) 505 break; 506 507 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 508 if (!ISSET(MMC_SPI_R1(cmd.c_resp), R1_SPI_IDLE)) 509 break; 510 } else { 511 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 512 ocr == 0) 513 break; 514 } 515 516 error = ETIMEDOUT; 517 sdmmc_delay(10000); 518 } 519 if (error == 0 && 520 ocrp != NULL && 521 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 522 *ocrp = MMC_R3(cmd.c_resp); 523 DPRINTF(("%s: sdmmc_mem_send_op_cond: error=%d, ocr=%#x\n", 524 SDMMCDEVNAME(sc), error, MMC_R3(cmd.c_resp))); 525 return error; 526 } 527 528 int 529 sdmmc_mem_send_if_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 530 { 531 struct sdmmc_command cmd; 532 int error; 533 534 /* Don't lock */ 535 536 memset(&cmd, 0, sizeof(cmd)); 537 cmd.c_arg = ocr; 538 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R7 | SCF_RSP_SPI_R7; 539 cmd.c_opcode = SD_SEND_IF_COND; 540 541 error = sdmmc_mmc_command(sc, &cmd); 542 if (error == 0 && ocrp != NULL) { 543 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 544 *ocrp = MMC_SPI_R7(cmd.c_resp); 545 } else { 546 *ocrp = MMC_R7(cmd.c_resp); 547 } 548 DPRINTF(("%s: sdmmc_mem_send_if_cond: error=%d, ocr=%#x\n", 549 SDMMCDEVNAME(sc), error, *ocrp)); 550 } 551 return error; 552 } 553 554 /* 555 * Set the read block length appropriately for this card, according to 556 * the card CSD register value. 557 */ 558 int 559 sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf) 560 { 561 struct sdmmc_command cmd; 562 int error; 563 564 /* Don't lock */ 565 566 memset(&cmd, 0, sizeof(cmd)); 567 cmd.c_opcode = MMC_SET_BLOCKLEN; 568 cmd.c_arg = SDMMC_SECTOR_SIZE; 569 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1; 570 571 error = sdmmc_mmc_command(sc, &cmd); 572 573 DPRINTF(("%s: sdmmc_mem_set_blocklen: read_bl_len=%d sector_size=%d\n", 574 SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, SDMMC_SECTOR_SIZE)); 575 576 return error; 577 } 578 579 /* make 512-bit BE quantity __bitfield()-compatible */ 580 static void 581 sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) { 582 size_t i; 583 uint32_t tmp0, tmp1; 584 const size_t bitswords = __arraycount(buf->_bits); 585 for (i = 0; i < bitswords/2; i++) { 586 tmp0 = buf->_bits[i]; 587 tmp1 = buf->_bits[bitswords - 1 - i]; 588 buf->_bits[i] = be32toh(tmp1); 589 buf->_bits[bitswords - 1 - i] = be32toh(tmp0); 590 } 591 } 592 593 static int 594 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 595 { 596 static const struct { 597 int v; 598 int freq; 599 } switch_group0_functions[] = { 600 /* Default/SDR12 */ 601 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 602 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 25000 }, 603 604 /* High-Speed/SDR25 */ 605 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 606 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 50000 }, 607 608 /* SDR50 */ 609 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 100000 }, 610 611 /* SDR104 */ 612 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 208000 }, 613 614 /* DDR50 */ 615 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 50000 }, 616 }; 617 int host_ocr, support_func, best_func, error, g, i; 618 sdmmc_bitfield512_t status; /* Switch Function Status */ 619 620 error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr); 621 if (error) { 622 aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n"); 623 return error; 624 } 625 error = sdmmc_mem_decode_scr(sc, sf); 626 if (error) 627 return error; 628 629 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 630 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 631 DPRINTF(("%s: change bus width\n", SDMMCDEVNAME(sc))); 632 error = sdmmc_set_bus_width(sf, 4); 633 if (error) { 634 aprint_error_dev(sc->sc_dev, 635 "can't change bus width (%d bit)\n", 4); 636 return error; 637 } 638 sf->width = 4; 639 } 640 641 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 642 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 643 DPRINTF(("%s: switch func mode 0\n", SDMMCDEVNAME(sc))); 644 error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status); 645 if (error) { 646 aprint_error_dev(sc->sc_dev, 647 "switch func mode 0 failed\n"); 648 return error; 649 } 650 651 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 652 support_func = SFUNC_STATUS_GROUP(&status, 1); 653 best_func = 0; 654 for (i = 0, g = 1; 655 i < __arraycount(switch_group0_functions); i++, g <<= 1) { 656 if (!(switch_group0_functions[i].v & host_ocr)) 657 continue; 658 if (g & support_func) 659 best_func = i; 660 } 661 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) && 662 best_func != 0) { 663 DPRINTF(("%s: switch func mode 1(func=%d)\n", 664 SDMMCDEVNAME(sc), best_func)); 665 error = 666 sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status); 667 if (error) { 668 aprint_error_dev(sc->sc_dev, 669 "switch func mode 1 failed:" 670 " group 1 function %d(0x%2x)\n", 671 best_func, support_func); 672 return error; 673 } 674 sf->csd.tran_speed = 675 switch_group0_functions[best_func].freq; 676 677 /* Wait 400KHz x 8 clock (2.5us * 8 + slop) */ 678 delay(25); 679 } 680 } 681 682 /* change bus clock */ 683 if (sc->sc_busclk > sf->csd.tran_speed) 684 sc->sc_busclk = sf->csd.tran_speed; 685 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk); 686 if (error) { 687 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 688 return error; 689 } 690 691 return 0; 692 } 693 694 static int 695 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 696 { 697 int width, value, hs_timing, error; 698 char ext_csd[512]; 699 700 if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 701 error = sdmmc_mem_send_cxd_data(sc, 702 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 703 if (error) { 704 aprint_error_dev(sc->sc_dev, "can't read EXT_CSD\n"); 705 return error; 706 } 707 if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) && 708 (ext_csd[EXT_CSD_STRUCTURE] > EXT_CSD_STRUCTURE_VER_1_2)) { 709 aprint_error_dev(sc->sc_dev, 710 "unrecognised future version (%d)\n", 711 ext_csd[EXT_CSD_STRUCTURE]); 712 return error; 713 } 714 hs_timing = 0; 715 switch (ext_csd[EXT_CSD_CARD_TYPE]) { 716 case EXT_CSD_CARD_TYPE_26M: 717 sf->csd.tran_speed = 26000; /* 26MHz */ 718 break; 719 720 case EXT_CSD_CARD_TYPE_52M: 721 case EXT_CSD_CARD_TYPE_52M_V18: 722 case EXT_CSD_CARD_TYPE_52M_V12: 723 case EXT_CSD_CARD_TYPE_52M_V12_18: 724 sf->csd.tran_speed = 52000; /* 52MHz */ 725 hs_timing = 1; 726 break; 727 728 default: 729 aprint_error_dev(sc->sc_dev, 730 "unknown CARD_TYPE: 0x%x\n", 731 ext_csd[EXT_CSD_CARD_TYPE]); 732 return error; 733 } 734 735 if (!ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 736 hs_timing = 0; 737 } 738 if (hs_timing) { 739 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 740 EXT_CSD_HS_TIMING, hs_timing); 741 if (error) { 742 aprint_error_dev(sc->sc_dev, 743 "can't change high speed\n"); 744 return error; 745 } 746 } 747 748 if (sc->sc_busclk > sf->csd.tran_speed) 749 sc->sc_busclk = sf->csd.tran_speed; 750 error = 751 sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk); 752 if (error) { 753 aprint_error_dev(sc->sc_dev, 754 "can't change bus clock\n"); 755 return error; 756 } 757 758 if (hs_timing) { 759 error = sdmmc_mem_send_cxd_data(sc, 760 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 761 if (error) { 762 aprint_error_dev(sc->sc_dev, 763 "can't re-read EXT_CSD\n"); 764 return error; 765 } 766 if (ext_csd[EXT_CSD_HS_TIMING] != hs_timing) { 767 aprint_error_dev(sc->sc_dev, 768 "HS_TIMING set failed\n"); 769 return EINVAL; 770 } 771 } 772 773 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 774 width = 8; 775 value = EXT_CSD_BUS_WIDTH_8; 776 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 777 width = 4; 778 value = EXT_CSD_BUS_WIDTH_4; 779 } else { 780 width = 1; 781 value = EXT_CSD_BUS_WIDTH_1; 782 } 783 784 if (width != 1) { 785 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 786 EXT_CSD_BUS_WIDTH, value); 787 if (error == 0) 788 error = sdmmc_chip_bus_width(sc->sc_sct, 789 sc->sc_sch, width); 790 else { 791 DPRINTF(("%s: can't change bus width" 792 " (%d bit)\n", SDMMCDEVNAME(sc), width)); 793 return error; 794 } 795 796 /* XXXX: need bus test? (using by CMD14 & CMD19) */ 797 } 798 sf->width = width; 799 } else { 800 if (sc->sc_busclk > sf->csd.tran_speed) 801 sc->sc_busclk = sf->csd.tran_speed; 802 error = 803 sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk); 804 if (error) { 805 aprint_error_dev(sc->sc_dev, 806 "can't change bus clock\n"); 807 return error; 808 } 809 } 810 811 return 0; 812 } 813 814 static int 815 sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp) 816 { 817 struct sdmmc_command cmd; 818 int error; 819 820 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 821 memset(&cmd, 0, sizeof cmd); 822 cmd.c_opcode = MMC_ALL_SEND_CID; 823 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 824 825 error = sdmmc_mmc_command(sc, &cmd); 826 } else { 827 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CID, &cmd.c_resp, 828 sizeof(cmd.c_resp)); 829 } 830 831 #ifdef SDMMC_DEBUG 832 sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp)); 833 #endif 834 if (error == 0 && resp != NULL) 835 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 836 return error; 837 } 838 839 static int 840 sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf, 841 sdmmc_response *resp) 842 { 843 struct sdmmc_command cmd; 844 int error; 845 846 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 847 memset(&cmd, 0, sizeof cmd); 848 cmd.c_opcode = MMC_SEND_CSD; 849 cmd.c_arg = MMC_ARG_RCA(sf->rca); 850 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 851 852 error = sdmmc_mmc_command(sc, &cmd); 853 } else { 854 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CSD, &cmd.c_resp, 855 sizeof(cmd.c_resp)); 856 } 857 858 #ifdef SDMMC_DEBUG 859 sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp)); 860 #endif 861 if (error == 0 && resp != NULL) 862 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 863 return error; 864 } 865 866 static int 867 sdmmc_mem_send_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf, 868 uint32_t scr[2]) 869 { 870 struct sdmmc_command cmd; 871 bus_dma_segment_t ds[1]; 872 void *ptr = NULL; 873 int datalen = 8; 874 int rseg; 875 int error = 0; 876 877 /* Don't lock */ 878 879 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 880 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, 881 ds, 1, &rseg, BUS_DMA_NOWAIT); 882 if (error) 883 goto out; 884 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 885 BUS_DMA_NOWAIT); 886 if (error) 887 goto dmamem_free; 888 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 889 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 890 if (error) 891 goto dmamem_unmap; 892 893 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 894 BUS_DMASYNC_PREREAD); 895 } else { 896 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 897 if (ptr == NULL) 898 goto out; 899 } 900 901 memset(&cmd, 0, sizeof(cmd)); 902 cmd.c_data = ptr; 903 cmd.c_datalen = datalen; 904 cmd.c_blklen = datalen; 905 cmd.c_arg = 0; 906 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 907 cmd.c_opcode = SD_APP_SEND_SCR; 908 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 909 cmd.c_dmamap = sc->sc_dmap; 910 911 error = sdmmc_app_command(sc, sf, &cmd); 912 if (error == 0) { 913 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 914 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 915 BUS_DMASYNC_POSTREAD); 916 } 917 memcpy(scr, ptr, datalen); 918 } 919 920 out: 921 if (ptr != NULL) { 922 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 923 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 924 dmamem_unmap: 925 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 926 dmamem_free: 927 bus_dmamem_free(sc->sc_dmat, ds, rseg); 928 } else { 929 free(ptr, M_DEVBUF); 930 } 931 } 932 DPRINTF(("%s: sdmem_mem_send_scr: error = %d\n", SDMMCDEVNAME(sc), 933 error)); 934 935 #ifdef SDMMC_DEBUG 936 if (error == 0) 937 sdmmc_dump_data("SCR", scr, 8); 938 #endif 939 return error; 940 } 941 942 static int 943 sdmmc_mem_decode_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf) 944 { 945 sdmmc_response resp; 946 int ver; 947 948 memset(resp, 0, sizeof(resp)); 949 /* 950 * Change the raw-scr received from the DMA stream to resp. 951 */ 952 resp[0] = be32toh(sf->raw_scr[1]) >> 8; // LSW 953 resp[1] = be32toh(sf->raw_scr[0]); // MSW 954 resp[0] |= (resp[1] & 0xff) << 24; 955 resp[1] >>= 8; 956 957 ver = SCR_STRUCTURE(resp); 958 sf->scr.sd_spec = SCR_SD_SPEC(resp); 959 sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 960 961 DPRINTF(("%s: sdmmc_mem_decode_scr: %08x%08x spec=%d, bus width=%d\n", 962 SDMMCDEVNAME(sc), resp[1], resp[0], 963 sf->scr.sd_spec, sf->scr.bus_width)); 964 965 if (ver != 0) { 966 DPRINTF(("%s: unknown structure version: %d\n", 967 SDMMCDEVNAME(sc), ver)); 968 return EINVAL; 969 } 970 return 0; 971 } 972 973 static int 974 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 975 size_t datalen) 976 { 977 struct sdmmc_command cmd; 978 bus_dma_segment_t ds[1]; 979 void *ptr = NULL; 980 int rseg; 981 int error = 0; 982 983 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 984 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, ds, 985 1, &rseg, BUS_DMA_NOWAIT); 986 if (error) 987 goto out; 988 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 989 BUS_DMA_NOWAIT); 990 if (error) 991 goto dmamem_free; 992 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 993 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 994 if (error) 995 goto dmamem_unmap; 996 997 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 998 BUS_DMASYNC_PREREAD); 999 } else { 1000 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1001 if (ptr == NULL) 1002 goto out; 1003 } 1004 1005 memset(&cmd, 0, sizeof(cmd)); 1006 cmd.c_data = ptr; 1007 cmd.c_datalen = datalen; 1008 cmd.c_blklen = datalen; 1009 cmd.c_opcode = opcode; 1010 cmd.c_arg = 0; 1011 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_SPI_R1; 1012 if (opcode == MMC_SEND_EXT_CSD) 1013 SET(cmd.c_flags, SCF_RSP_R1); 1014 else 1015 SET(cmd.c_flags, SCF_RSP_R2); 1016 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1017 cmd.c_dmamap = sc->sc_dmap; 1018 1019 error = sdmmc_mmc_command(sc, &cmd); 1020 if (error == 0) { 1021 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1022 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1023 BUS_DMASYNC_POSTREAD); 1024 } 1025 memcpy(data, ptr, datalen); 1026 #ifdef SDMMC_DEBUG 1027 sdmmc_dump_data("CXD", data, datalen); 1028 #endif 1029 } 1030 1031 out: 1032 if (ptr != NULL) { 1033 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1034 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1035 dmamem_unmap: 1036 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1037 dmamem_free: 1038 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1039 } else { 1040 free(ptr, M_DEVBUF); 1041 } 1042 } 1043 return error; 1044 } 1045 1046 static int 1047 sdmmc_set_bus_width(struct sdmmc_function *sf, int width) 1048 { 1049 struct sdmmc_softc *sc = sf->sc; 1050 struct sdmmc_command cmd; 1051 int error; 1052 1053 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1054 return ENODEV; 1055 1056 memset(&cmd, 0, sizeof(cmd)); 1057 cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 1058 cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 1059 1060 switch (width) { 1061 case 1: 1062 cmd.c_arg = SD_ARG_BUS_WIDTH_1; 1063 break; 1064 1065 case 4: 1066 cmd.c_arg = SD_ARG_BUS_WIDTH_4; 1067 break; 1068 1069 default: 1070 return EINVAL; 1071 } 1072 1073 error = sdmmc_app_command(sc, sf, &cmd); 1074 if (error == 0) 1075 error = sdmmc_chip_bus_width(sc->sc_sct, sc->sc_sch, width); 1076 return error; 1077 } 1078 1079 static int 1080 sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 1081 int function, sdmmc_bitfield512_t *status) 1082 { 1083 struct sdmmc_softc *sc = sf->sc; 1084 struct sdmmc_command cmd; 1085 bus_dma_segment_t ds[1]; 1086 void *ptr = NULL; 1087 int gsft, rseg, error = 0; 1088 const int statlen = 64; 1089 1090 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 1091 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 1092 return EINVAL; 1093 1094 if (group <= 0 || group > 6 || 1095 function < 0 || function > 15) 1096 return EINVAL; 1097 1098 gsft = (group - 1) << 2; 1099 1100 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1101 error = bus_dmamem_alloc(sc->sc_dmat, statlen, PAGE_SIZE, 0, ds, 1102 1, &rseg, BUS_DMA_NOWAIT); 1103 if (error) 1104 goto out; 1105 error = bus_dmamem_map(sc->sc_dmat, ds, 1, statlen, &ptr, 1106 BUS_DMA_NOWAIT); 1107 if (error) 1108 goto dmamem_free; 1109 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, statlen, 1110 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1111 if (error) 1112 goto dmamem_unmap; 1113 1114 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1115 BUS_DMASYNC_PREREAD); 1116 } else { 1117 ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 1118 if (ptr == NULL) 1119 goto out; 1120 } 1121 1122 memset(&cmd, 0, sizeof(cmd)); 1123 cmd.c_data = ptr; 1124 cmd.c_datalen = statlen; 1125 cmd.c_blklen = statlen; 1126 cmd.c_opcode = SD_SEND_SWITCH_FUNC; 1127 cmd.c_arg = 1128 (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 1129 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1130 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1131 cmd.c_dmamap = sc->sc_dmap; 1132 1133 error = sdmmc_mmc_command(sc, &cmd); 1134 if (error == 0) { 1135 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1136 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1137 BUS_DMASYNC_POSTREAD); 1138 } 1139 memcpy(status, ptr, statlen); 1140 } 1141 1142 out: 1143 if (ptr != NULL) { 1144 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1145 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1146 dmamem_unmap: 1147 bus_dmamem_unmap(sc->sc_dmat, ptr, statlen); 1148 dmamem_free: 1149 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1150 } else { 1151 free(ptr, M_DEVBUF); 1152 } 1153 } 1154 1155 if (error == 0) 1156 sdmmc_be512_to_bitfield512(status); 1157 1158 return error; 1159 } 1160 1161 static int 1162 sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 1163 uint8_t value) 1164 { 1165 struct sdmmc_softc *sc = sf->sc; 1166 struct sdmmc_command cmd; 1167 1168 memset(&cmd, 0, sizeof(cmd)); 1169 cmd.c_opcode = MMC_SWITCH; 1170 cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 1171 (index << 16) | (value << 8) | set; 1172 cmd.c_flags = SCF_RSP_SPI_R1B | SCF_RSP_R1B | SCF_CMD_AC; 1173 1174 return sdmmc_mmc_command(sc, &cmd); 1175 } 1176 1177 /* 1178 * SPI mode function 1179 */ 1180 static int 1181 sdmmc_mem_spi_read_ocr(struct sdmmc_softc *sc, uint32_t hcs, uint32_t *card_ocr) 1182 { 1183 struct sdmmc_command cmd; 1184 int error; 1185 1186 memset(&cmd, 0, sizeof(cmd)); 1187 cmd.c_opcode = MMC_READ_OCR; 1188 cmd.c_arg = hcs ? MMC_OCR_HCS : 0; 1189 cmd.c_flags = SCF_RSP_SPI_R3; 1190 1191 error = sdmmc_mmc_command(sc, &cmd); 1192 if (error == 0 && card_ocr != NULL) 1193 *card_ocr = cmd.c_resp[1]; 1194 DPRINTF(("%s: sdmmc_mem_spi_read_ocr: error=%d, ocr=%#x\n", 1195 SDMMCDEVNAME(sc), error, cmd.c_resp[1])); 1196 return error; 1197 } 1198 1199 /* 1200 * read/write function 1201 */ 1202 /* read */ 1203 static int 1204 sdmmc_mem_single_read_block(struct sdmmc_function *sf, uint32_t blkno, 1205 u_char *data, size_t datalen) 1206 { 1207 struct sdmmc_softc *sc __diagused = sf->sc; 1208 int error = 0; 1209 int i; 1210 1211 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1212 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1213 1214 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1215 error = sdmmc_mem_read_block_subr(sf, blkno + i, 1216 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1217 if (error) 1218 break; 1219 } 1220 return error; 1221 } 1222 1223 static int 1224 sdmmc_mem_read_block_subr(struct sdmmc_function *sf, uint32_t blkno, 1225 u_char *data, size_t datalen) 1226 { 1227 struct sdmmc_softc *sc = sf->sc; 1228 struct sdmmc_command cmd; 1229 int error, bbuf, seg, off, len, num; 1230 1231 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1232 error = sdmmc_select_card(sc, sf); 1233 if (error) 1234 goto out; 1235 } 1236 1237 bbuf = 0; 1238 num = 0; 1239 seg = off = len = 0; 1240 retry: 1241 memset(&cmd, 0, sizeof(cmd)); 1242 cmd.c_data = data; 1243 cmd.c_datalen = datalen; 1244 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1245 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1246 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1247 cmd.c_arg = blkno; 1248 if (!ISSET(sf->flags, SFF_SDHC)) 1249 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1250 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1251 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1252 cmd.c_dmamap = sc->sc_dmap; 1253 if (!ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1254 len = sc->sc_dmap->dm_segs[seg].ds_len - off; 1255 len &= ~(SDMMC_SECTOR_SIZE - 1); 1256 cmd.c_datalen = len; 1257 cmd.c_dmaseg = seg; 1258 cmd.c_dmaoff = off; 1259 bbuf = 0; 1260 if (len == 0) { 1261 /* Use bounce buffer */ 1262 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 1263 0, SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREREAD); 1264 cmd.c_datalen = SDMMC_SECTOR_SIZE; 1265 cmd.c_dmamap = sf->bbuf_dmap; 1266 cmd.c_dmaseg = 0; 1267 cmd.c_dmaoff = 0; 1268 bbuf = 1; 1269 len = SDMMC_SECTOR_SIZE; 1270 } 1271 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1272 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1273 } 1274 } 1275 1276 error = sdmmc_mmc_command(sc, &cmd); 1277 if (error) 1278 goto out; 1279 1280 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1281 if (cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 1282 memset(&cmd, 0, sizeof cmd); 1283 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1284 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1285 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1286 error = sdmmc_mmc_command(sc, &cmd); 1287 if (error) 1288 goto out; 1289 } 1290 } 1291 1292 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1293 do { 1294 memset(&cmd, 0, sizeof(cmd)); 1295 cmd.c_opcode = MMC_SEND_STATUS; 1296 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1297 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1298 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1299 error = sdmmc_mmc_command(sc, &cmd); 1300 if (error) 1301 break; 1302 /* XXX time out */ 1303 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1304 } 1305 1306 if (ISSET(sc->sc_caps, SMC_CAPS_DMA) && 1307 !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1308 bus_dma_segment_t *dm_segs = sc->sc_dmap->dm_segs; 1309 1310 if (bbuf) { 1311 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 1312 0, SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTREAD); 1313 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1314 SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTREAD); 1315 memcpy(data, sf->bbuf, SDMMC_SECTOR_SIZE); 1316 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1317 SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREREAD); 1318 } 1319 num += len; 1320 data += len; 1321 datalen -= len; 1322 blkno += (len / SDMMC_SECTOR_SIZE); 1323 1324 while (off + len >= dm_segs[seg].ds_len) { 1325 len -= dm_segs[seg++].ds_len; 1326 off = 0; 1327 } 1328 off += len; 1329 1330 if (seg < sc->sc_dmap->dm_nsegs) 1331 goto retry; 1332 } 1333 1334 out: 1335 return error; 1336 } 1337 1338 int 1339 sdmmc_mem_read_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1340 size_t datalen) 1341 { 1342 struct sdmmc_softc *sc = sf->sc; 1343 int error; 1344 1345 SDMMC_LOCK(sc); 1346 1347 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1348 error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 1349 goto out; 1350 } 1351 1352 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1353 error = sdmmc_mem_read_block_subr(sf, blkno, data, datalen); 1354 goto out; 1355 } 1356 1357 /* DMA transfer */ 1358 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1359 BUS_DMA_NOWAIT|BUS_DMA_READ); 1360 if (error) 1361 goto out; 1362 1363 #ifdef SDMMC_DEBUG 1364 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1365 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1366 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1367 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1368 } 1369 #endif 1370 1371 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1372 BUS_DMASYNC_PREREAD); 1373 1374 error = sdmmc_mem_read_block_subr(sf, blkno, data, datalen); 1375 if (error) 1376 goto unload; 1377 1378 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1379 BUS_DMASYNC_POSTREAD); 1380 unload: 1381 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1382 1383 out: 1384 SDMMC_UNLOCK(sc); 1385 1386 return error; 1387 } 1388 1389 /* write */ 1390 static int 1391 sdmmc_mem_single_write_block(struct sdmmc_function *sf, uint32_t blkno, 1392 u_char *data, size_t datalen) 1393 { 1394 struct sdmmc_softc *sc __diagused = sf->sc; 1395 int error = 0; 1396 int i; 1397 1398 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1399 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1400 1401 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1402 error = sdmmc_mem_write_block_subr(sf, blkno + i, 1403 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1404 if (error) 1405 break; 1406 } 1407 return error; 1408 } 1409 1410 static int 1411 sdmmc_mem_write_block_subr(struct sdmmc_function *sf, uint32_t blkno, 1412 u_char *data, size_t datalen) 1413 { 1414 struct sdmmc_softc *sc = sf->sc; 1415 struct sdmmc_command cmd; 1416 int error, bbuf, seg, off, len, num; 1417 1418 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1419 error = sdmmc_select_card(sc, sf); 1420 if (error) 1421 goto out; 1422 } 1423 1424 bbuf = 0; 1425 num = 0; 1426 seg = off = len = 0; 1427 retry: 1428 memset(&cmd, 0, sizeof(cmd)); 1429 cmd.c_data = data; 1430 cmd.c_datalen = datalen; 1431 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1432 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1433 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1434 cmd.c_arg = blkno; 1435 if (!ISSET(sf->flags, SFF_SDHC)) 1436 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1437 cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 1438 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1439 cmd.c_dmamap = sc->sc_dmap; 1440 if (!ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1441 len = sc->sc_dmap->dm_segs[seg].ds_len - off; 1442 len &= ~(SDMMC_SECTOR_SIZE - 1); 1443 cmd.c_datalen = len; 1444 cmd.c_dmaseg = seg; 1445 cmd.c_dmaoff = off; 1446 bbuf = 0; 1447 if (len == 0) { 1448 /* Use bounce buffer */ 1449 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1450 SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTWRITE); 1451 memcpy(sf->bbuf, data, SDMMC_SECTOR_SIZE); 1452 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1453 SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREWRITE); 1454 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, 1455 SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREWRITE); 1456 cmd.c_datalen = SDMMC_SECTOR_SIZE; 1457 cmd.c_dmamap = sf->bbuf_dmap; 1458 cmd.c_dmaseg = 0; 1459 cmd.c_dmaoff = 0; 1460 bbuf = 1; 1461 len = SDMMC_SECTOR_SIZE; 1462 } 1463 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1464 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1465 } 1466 } 1467 1468 error = sdmmc_mmc_command(sc, &cmd); 1469 if (error) 1470 goto out; 1471 1472 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1473 if (cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1474 memset(&cmd, 0, sizeof(cmd)); 1475 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1476 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1477 error = sdmmc_mmc_command(sc, &cmd); 1478 if (error) 1479 goto out; 1480 } 1481 } 1482 1483 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1484 do { 1485 memset(&cmd, 0, sizeof(cmd)); 1486 cmd.c_opcode = MMC_SEND_STATUS; 1487 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1488 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1489 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1490 error = sdmmc_mmc_command(sc, &cmd); 1491 if (error) 1492 break; 1493 /* XXX time out */ 1494 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1495 } 1496 1497 if (ISSET(sc->sc_caps, SMC_CAPS_DMA) && 1498 !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1499 bus_dma_segment_t *dm_segs = sc->sc_dmap->dm_segs; 1500 1501 if (bbuf) 1502 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 1503 0, SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTWRITE); 1504 num += len; 1505 data += len; 1506 datalen -= len; 1507 blkno += (len / SDMMC_SECTOR_SIZE); 1508 1509 while (off + len >= dm_segs[seg].ds_len) { 1510 len -= dm_segs[seg++].ds_len; 1511 off = 0; 1512 } 1513 off += len; 1514 1515 if (seg < sc->sc_dmap->dm_nsegs) 1516 goto retry; 1517 } 1518 1519 out: 1520 return error; 1521 } 1522 1523 int 1524 sdmmc_mem_write_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1525 size_t datalen) 1526 { 1527 struct sdmmc_softc *sc = sf->sc; 1528 int error; 1529 1530 SDMMC_LOCK(sc); 1531 1532 if (sdmmc_chip_write_protect(sc->sc_sct, sc->sc_sch)) { 1533 aprint_normal_dev(sc->sc_dev, "write-protected\n"); 1534 error = EIO; 1535 goto out; 1536 } 1537 1538 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1539 error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1540 goto out; 1541 } 1542 1543 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1544 error = sdmmc_mem_write_block_subr(sf, blkno, data, datalen); 1545 goto out; 1546 } 1547 1548 /* DMA transfer */ 1549 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1550 BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1551 if (error) 1552 goto out; 1553 1554 #ifdef SDMMC_DEBUG 1555 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1556 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1557 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1558 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1559 } 1560 #endif 1561 1562 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1563 BUS_DMASYNC_PREWRITE); 1564 1565 error = sdmmc_mem_write_block_subr(sf, blkno, data, datalen); 1566 if (error) 1567 goto unload; 1568 1569 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1570 BUS_DMASYNC_POSTWRITE); 1571 unload: 1572 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1573 1574 out: 1575 SDMMC_UNLOCK(sc); 1576 1577 return error; 1578 } 1579
Indexes created Thu Sep 25 16:09:42 GMT 2025