sdmmc_mem.c revision 1.33
1 /* $NetBSD: sdmmc_mem.c,v 1.33 2015/02/07 04:13:26 christos Exp $ */ 2 /* $OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2007, 2008, 2009, 2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 /* Routines for SD/MMC memory cards. */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.33 2015/02/07 04:13:26 christos Exp $"); 49 50 #ifdef _KERNEL_OPT 51 #include "opt_sdmmc.h" 52 #endif 53 54 #include <sys/param.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 60 #include <dev/sdmmc/sdmmcchip.h> 61 #include <dev/sdmmc/sdmmcreg.h> 62 #include <dev/sdmmc/sdmmcvar.h> 63 64 #ifdef SDMMC_DEBUG 65 #define DPRINTF(s) do { printf s; } while (/*CONSTCOND*/0) 66 #else 67 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 68 #endif 69 70 typedef struct { uint32_t _bits[512/32]; } __packed __aligned(4) sdmmc_bitfield512_t; 71 72 static int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 73 static int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 74 static int sdmmc_mem_send_cid(struct sdmmc_softc *, sdmmc_response *); 75 static int sdmmc_mem_send_csd(struct sdmmc_softc *, struct sdmmc_function *, 76 sdmmc_response *); 77 static int sdmmc_mem_send_scr(struct sdmmc_softc *, struct sdmmc_function *, 78 uint32_t *scr); 79 static int sdmmc_mem_decode_scr(struct sdmmc_softc *, struct sdmmc_function *); 80 static int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 81 static int sdmmc_set_bus_width(struct sdmmc_function *, int); 82 static int sdmmc_mem_sd_switch(struct sdmmc_function *, int, int, int, sdmmc_bitfield512_t *); 83 static int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, 84 uint8_t); 85 static int sdmmc_mem_spi_read_ocr(struct sdmmc_softc *, uint32_t, uint32_t *); 86 static int sdmmc_mem_single_read_block(struct sdmmc_function *, uint32_t, 87 u_char *, size_t); 88 static int sdmmc_mem_single_write_block(struct sdmmc_function *, uint32_t, 89 u_char *, size_t); 90 static int sdmmc_mem_read_block_subr(struct sdmmc_function *, uint32_t, 91 u_char *, size_t); 92 static int sdmmc_mem_write_block_subr(struct sdmmc_function *, uint32_t, 93 u_char *, size_t); 94 95 /* 96 * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 97 */ 98 int 99 sdmmc_mem_enable(struct sdmmc_softc *sc) 100 { 101 uint32_t host_ocr; 102 uint32_t card_ocr; 103 uint32_t ocr = 0; 104 int error; 105 106 SDMMC_LOCK(sc); 107 108 /* Set host mode to SD "combo" card or SD memory-only. */ 109 SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 110 111 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 112 sdmmc_spi_chip_initialize(sc->sc_spi_sct, sc->sc_sch); 113 114 /* Reset memory (*must* do that before CMD55 or CMD1). */ 115 sdmmc_go_idle_state(sc); 116 117 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 118 /* Check SD Ver.2 */ 119 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 120 if (error == 0 && card_ocr == 0x1aa) 121 SET(ocr, MMC_OCR_HCS); 122 } 123 124 /* 125 * Read the SD/MMC memory OCR value by issuing CMD55 followed 126 * by ACMD41 to read the OCR value from memory-only SD cards. 127 * MMC cards will not respond to CMD55 or ACMD41 and this is 128 * how we distinguish them from SD cards. 129 */ 130 mmc_mode: 131 error = sdmmc_mem_send_op_cond(sc, 132 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr); 133 if (error) { 134 if (ISSET(sc->sc_flags, SMF_SD_MODE) && 135 !ISSET(sc->sc_flags, SMF_IO_MODE)) { 136 /* Not a SD card, switch to MMC mode. */ 137 DPRINTF(("%s: switch to MMC mode\n", SDMMCDEVNAME(sc))); 138 CLR(sc->sc_flags, SMF_SD_MODE); 139 goto mmc_mode; 140 } 141 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 142 DPRINTF(("%s: couldn't read memory OCR\n", 143 SDMMCDEVNAME(sc))); 144 goto out; 145 } else { 146 /* Not a "combo" card. */ 147 CLR(sc->sc_flags, SMF_MEM_MODE); 148 error = 0; 149 goto out; 150 } 151 } 152 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 153 /* get card OCR */ 154 error = sdmmc_mem_spi_read_ocr(sc, ocr, &card_ocr); 155 if (error) { 156 DPRINTF(("%s: couldn't read SPI memory OCR\n", 157 SDMMCDEVNAME(sc))); 158 goto out; 159 } 160 } 161 162 /* Set the lowest voltage supported by the card and host. */ 163 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 164 error = sdmmc_set_bus_power(sc, host_ocr, card_ocr); 165 if (error) { 166 DPRINTF(("%s: couldn't supply voltage requested by card\n", 167 SDMMCDEVNAME(sc))); 168 goto out; 169 } 170 171 /* Tell the card(s) to enter the idle state (again). */ 172 sdmmc_go_idle_state(sc); 173 174 DPRINTF(("%s: host_ocr 0x%08x\n", SDMMCDEVNAME(sc), host_ocr)); 175 DPRINTF(("%s: card_ocr 0x%08x\n", SDMMCDEVNAME(sc), card_ocr)); 176 177 host_ocr &= card_ocr; /* only allow the common voltages */ 178 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 179 /* Check SD Ver.2 */ 180 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 181 if (error == 0 && card_ocr == 0x1aa) 182 SET(ocr, MMC_OCR_HCS); 183 } 184 host_ocr |= ocr; 185 186 /* Send the new OCR value until all cards are ready. */ 187 error = sdmmc_mem_send_op_cond(sc, host_ocr, NULL); 188 if (error) { 189 DPRINTF(("%s: couldn't send memory OCR\n", SDMMCDEVNAME(sc))); 190 goto out; 191 } 192 193 out: 194 SDMMC_UNLOCK(sc); 195 196 return error; 197 } 198 199 /* 200 * Read the CSD and CID from all cards and assign each card a unique 201 * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 202 */ 203 void 204 sdmmc_mem_scan(struct sdmmc_softc *sc) 205 { 206 sdmmc_response resp; 207 struct sdmmc_function *sf; 208 uint16_t next_rca; 209 int error; 210 int retry; 211 212 SDMMC_LOCK(sc); 213 214 /* 215 * CMD2 is a broadcast command understood by SD cards and MMC 216 * cards. All cards begin to respond to the command, but back 217 * off if another card drives the CMD line to a different level. 218 * Only one card will get its entire response through. That 219 * card remains silent once it has been assigned a RCA. 220 */ 221 for (retry = 0; retry < 100; retry++) { 222 error = sdmmc_mem_send_cid(sc, &resp); 223 if (error) { 224 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && 225 error == ETIMEDOUT) { 226 /* No more cards there. */ 227 break; 228 } 229 DPRINTF(("%s: couldn't read CID\n", SDMMCDEVNAME(sc))); 230 break; 231 } 232 233 /* In MMC mode, find the next available RCA. */ 234 next_rca = 1; 235 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 236 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) 237 next_rca++; 238 } 239 240 /* Allocate a sdmmc_function structure. */ 241 sf = sdmmc_function_alloc(sc); 242 sf->rca = next_rca; 243 244 /* 245 * Remember the CID returned in the CMD2 response for 246 * later decoding. 247 */ 248 memcpy(sf->raw_cid, resp, sizeof(sf->raw_cid)); 249 250 /* 251 * Silence the card by assigning it a unique RCA, or 252 * querying it for its RCA in the case of SD. 253 */ 254 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 255 if (sdmmc_set_relative_addr(sc, sf) != 0) { 256 aprint_error_dev(sc->sc_dev, 257 "couldn't set mem RCA\n"); 258 sdmmc_function_free(sf); 259 break; 260 } 261 } 262 263 /* 264 * If this is a memory-only card, the card responding 265 * first becomes an alias for SDIO function 0. 266 */ 267 if (sc->sc_fn0 == NULL) 268 sc->sc_fn0 = sf; 269 270 SIMPLEQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 271 272 /* only one function in SPI mode */ 273 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 274 break; 275 } 276 277 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 278 /* Go to Data Transfer Mode, if possible. */ 279 sdmmc_chip_bus_rod(sc->sc_sct, sc->sc_sch, 0); 280 281 /* 282 * All cards are either inactive or awaiting further commands. 283 * Read the CSDs and decode the raw CID for each card. 284 */ 285 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) { 286 error = sdmmc_mem_send_csd(sc, sf, &resp); 287 if (error) { 288 SET(sf->flags, SFF_ERROR); 289 continue; 290 } 291 292 if (sdmmc_decode_csd(sc, resp, sf) != 0 || 293 sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 294 SET(sf->flags, SFF_ERROR); 295 continue; 296 } 297 298 #ifdef SDMMC_DEBUG 299 printf("%s: CID: ", SDMMCDEVNAME(sc)); 300 sdmmc_print_cid(&sf->cid); 301 #endif 302 } 303 304 SDMMC_UNLOCK(sc); 305 } 306 307 int 308 sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 309 struct sdmmc_function *sf) 310 { 311 /* TRAN_SPEED(2:0): transfer rate exponent */ 312 static const int speed_exponent[8] = { 313 100 * 1, /* 100 Kbits/s */ 314 1 * 1000, /* 1 Mbits/s */ 315 10 * 1000, /* 10 Mbits/s */ 316 100 * 1000, /* 100 Mbits/s */ 317 0, 318 0, 319 0, 320 0, 321 }; 322 /* TRAN_SPEED(6:3): time mantissa */ 323 static const int speed_mantissa[16] = { 324 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 325 }; 326 struct sdmmc_csd *csd = &sf->csd; 327 int e, m; 328 329 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 330 /* 331 * CSD version 1.0 corresponds to SD system 332 * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 333 */ 334 csd->csdver = SD_CSD_CSDVER(resp); 335 switch (csd->csdver) { 336 case SD_CSD_CSDVER_2_0: 337 DPRINTF(("%s: SD Ver.2.0\n", SDMMCDEVNAME(sc))); 338 SET(sf->flags, SFF_SDHC); 339 csd->capacity = SD_CSD_V2_CAPACITY(resp); 340 csd->read_bl_len = SD_CSD_V2_BL_LEN; 341 break; 342 343 case SD_CSD_CSDVER_1_0: 344 DPRINTF(("%s: SD Ver.1.0\n", SDMMCDEVNAME(sc))); 345 csd->capacity = SD_CSD_CAPACITY(resp); 346 csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 347 break; 348 349 default: 350 aprint_error_dev(sc->sc_dev, 351 "unknown SD CSD structure version 0x%x\n", 352 csd->csdver); 353 return 1; 354 } 355 356 csd->mmcver = SD_CSD_MMCVER(resp); 357 csd->write_bl_len = SD_CSD_WRITE_BL_LEN(resp); 358 csd->r2w_factor = SD_CSD_R2W_FACTOR(resp); 359 e = SD_CSD_SPEED_EXP(resp); 360 m = SD_CSD_SPEED_MANT(resp); 361 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 362 csd->ccc = SD_CSD_CCC(resp); 363 } else { 364 csd->csdver = MMC_CSD_CSDVER(resp); 365 if (csd->csdver == MMC_CSD_CSDVER_1_0) { 366 aprint_error_dev(sc->sc_dev, 367 "unknown MMC CSD structure version 0x%x\n", 368 csd->csdver); 369 return 1; 370 } 371 372 csd->mmcver = MMC_CSD_MMCVER(resp); 373 csd->capacity = MMC_CSD_CAPACITY(resp); 374 csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 375 csd->write_bl_len = MMC_CSD_WRITE_BL_LEN(resp); 376 csd->r2w_factor = MMC_CSD_R2W_FACTOR(resp); 377 e = MMC_CSD_TRAN_SPEED_EXP(resp); 378 m = MMC_CSD_TRAN_SPEED_MANT(resp); 379 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 380 } 381 if ((1 << csd->read_bl_len) > SDMMC_SECTOR_SIZE) 382 csd->capacity *= (1 << csd->read_bl_len) / SDMMC_SECTOR_SIZE; 383 384 #ifdef SDMMC_DUMP_CSD 385 sdmmc_print_csd(resp, csd); 386 #endif 387 388 return 0; 389 } 390 391 int 392 sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 393 struct sdmmc_function *sf) 394 { 395 struct sdmmc_cid *cid = &sf->cid; 396 397 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 398 cid->mid = SD_CID_MID(resp); 399 cid->oid = SD_CID_OID(resp); 400 SD_CID_PNM_CPY(resp, cid->pnm); 401 cid->rev = SD_CID_REV(resp); 402 cid->psn = SD_CID_PSN(resp); 403 cid->mdt = SD_CID_MDT(resp); 404 } else { 405 switch(sf->csd.mmcver) { 406 case MMC_CSD_MMCVER_1_0: 407 case MMC_CSD_MMCVER_1_4: 408 cid->mid = MMC_CID_MID_V1(resp); 409 MMC_CID_PNM_V1_CPY(resp, cid->pnm); 410 cid->rev = MMC_CID_REV_V1(resp); 411 cid->psn = MMC_CID_PSN_V1(resp); 412 cid->mdt = MMC_CID_MDT_V1(resp); 413 break; 414 case MMC_CSD_MMCVER_2_0: 415 case MMC_CSD_MMCVER_3_1: 416 case MMC_CSD_MMCVER_4_0: 417 cid->mid = MMC_CID_MID_V2(resp); 418 cid->oid = MMC_CID_OID_V2(resp); 419 MMC_CID_PNM_V2_CPY(resp, cid->pnm); 420 cid->psn = MMC_CID_PSN_V2(resp); 421 break; 422 default: 423 aprint_error_dev(sc->sc_dev, "unknown MMC version %d\n", 424 sf->csd.mmcver); 425 return 1; 426 } 427 } 428 return 0; 429 } 430 431 void 432 sdmmc_print_cid(struct sdmmc_cid *cid) 433 { 434 435 printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 436 " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 437 cid->mdt); 438 } 439 440 #ifdef SDMMC_DUMP_CSD 441 void 442 sdmmc_print_csd(sdmmc_response resp, struct sdmmc_csd *csd) 443 { 444 445 printf("csdver = %d\n", csd->csdver); 446 printf("mmcver = %d\n", csd->mmcver); 447 printf("capacity = 0x%08x\n", csd->capacity); 448 printf("read_bl_len = %d\n", csd->read_bl_len); 449 printf("write_bl_len = %d\n", csd->write_bl_len); 450 printf("r2w_factor = %d\n", csd->r2w_factor); 451 printf("tran_speed = %d\n", csd->tran_speed); 452 printf("ccc = 0x%x\n", csd->ccc); 453 } 454 #endif 455 456 /* 457 * Initialize a SD/MMC memory card. 458 */ 459 int 460 sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 461 { 462 int error = 0; 463 464 SDMMC_LOCK(sc); 465 466 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 467 error = sdmmc_select_card(sc, sf); 468 if (error) 469 goto out; 470 } 471 472 error = sdmmc_mem_set_blocklen(sc, sf, SDMMC_SECTOR_SIZE); 473 if (error) 474 goto out; 475 476 if (ISSET(sc->sc_flags, SMF_SD_MODE)) 477 error = sdmmc_mem_sd_init(sc, sf); 478 else 479 error = sdmmc_mem_mmc_init(sc, sf); 480 481 out: 482 SDMMC_UNLOCK(sc); 483 484 return error; 485 } 486 487 /* 488 * Get or set the card's memory OCR value (SD or MMC). 489 */ 490 int 491 sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 492 { 493 struct sdmmc_command cmd; 494 int error; 495 int retry; 496 497 /* Don't lock */ 498 499 DPRINTF(("%s: sdmmc_mem_send_op_cond: ocr=%#x\n", 500 SDMMCDEVNAME(sc), ocr)); 501 502 /* 503 * If we change the OCR value, retry the command until the OCR 504 * we receive in response has the "CARD BUSY" bit set, meaning 505 * that all cards are ready for identification. 506 */ 507 for (retry = 0; retry < 100; retry++) { 508 memset(&cmd, 0, sizeof(cmd)); 509 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? 510 ocr : (ocr & MMC_OCR_HCS); 511 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3 | SCF_RSP_SPI_R1; 512 513 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 514 cmd.c_opcode = SD_APP_OP_COND; 515 error = sdmmc_app_command(sc, NULL, &cmd); 516 } else { 517 cmd.c_opcode = MMC_SEND_OP_COND; 518 error = sdmmc_mmc_command(sc, &cmd); 519 } 520 if (error) 521 break; 522 523 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 524 if (!ISSET(MMC_SPI_R1(cmd.c_resp), R1_SPI_IDLE)) 525 break; 526 } else { 527 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 528 ocr == 0) 529 break; 530 } 531 532 error = ETIMEDOUT; 533 sdmmc_delay(10000); 534 } 535 if (error == 0 && 536 ocrp != NULL && 537 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 538 *ocrp = MMC_R3(cmd.c_resp); 539 DPRINTF(("%s: sdmmc_mem_send_op_cond: error=%d, ocr=%#x\n", 540 SDMMCDEVNAME(sc), error, MMC_R3(cmd.c_resp))); 541 return error; 542 } 543 544 int 545 sdmmc_mem_send_if_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 546 { 547 struct sdmmc_command cmd; 548 int error; 549 550 /* Don't lock */ 551 552 memset(&cmd, 0, sizeof(cmd)); 553 cmd.c_arg = ocr; 554 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R7 | SCF_RSP_SPI_R7; 555 cmd.c_opcode = SD_SEND_IF_COND; 556 557 error = sdmmc_mmc_command(sc, &cmd); 558 if (error == 0 && ocrp != NULL) { 559 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 560 *ocrp = MMC_SPI_R7(cmd.c_resp); 561 } else { 562 *ocrp = MMC_R7(cmd.c_resp); 563 } 564 DPRINTF(("%s: sdmmc_mem_send_if_cond: error=%d, ocr=%#x\n", 565 SDMMCDEVNAME(sc), error, *ocrp)); 566 } 567 return error; 568 } 569 570 /* 571 * Set the read block length appropriately for this card, according to 572 * the card CSD register value. 573 */ 574 int 575 sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf, 576 int block_len) 577 { 578 struct sdmmc_command cmd; 579 int error; 580 581 /* Don't lock */ 582 583 memset(&cmd, 0, sizeof(cmd)); 584 cmd.c_opcode = MMC_SET_BLOCKLEN; 585 cmd.c_arg = block_len; 586 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1; 587 588 error = sdmmc_mmc_command(sc, &cmd); 589 590 DPRINTF(("%s: sdmmc_mem_set_blocklen: read_bl_len=%d sector_size=%d\n", 591 SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, block_len)); 592 593 return error; 594 } 595 596 /* make 512-bit BE quantity __bitfield()-compatible */ 597 static void 598 sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) { 599 size_t i; 600 uint32_t tmp0, tmp1; 601 const size_t bitswords = __arraycount(buf->_bits); 602 for (i = 0; i < bitswords/2; i++) { 603 tmp0 = buf->_bits[i]; 604 tmp1 = buf->_bits[bitswords - 1 - i]; 605 buf->_bits[i] = be32toh(tmp1); 606 buf->_bits[bitswords - 1 - i] = be32toh(tmp0); 607 } 608 } 609 610 static int 611 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 612 { 613 static const struct { 614 int v; 615 int freq; 616 } switch_group0_functions[] = { 617 /* Default/SDR12 */ 618 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 619 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 25000 }, 620 621 /* High-Speed/SDR25 */ 622 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 623 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 50000 }, 624 625 /* SDR50 */ 626 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 100000 }, 627 628 /* SDR104 */ 629 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 208000 }, 630 631 /* DDR50 */ 632 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 50000 }, 633 }; 634 int host_ocr, support_func, best_func, bus_clock, error, g, i; 635 sdmmc_bitfield512_t status; /* Switch Function Status */ 636 637 /* change bus clock */ 638 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 639 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock); 640 if (error) { 641 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 642 return error; 643 } 644 645 error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr); 646 if (error) { 647 aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n"); 648 return error; 649 } 650 error = sdmmc_mem_decode_scr(sc, sf); 651 if (error) 652 return error; 653 654 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 655 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 656 DPRINTF(("%s: change bus width\n", SDMMCDEVNAME(sc))); 657 error = sdmmc_set_bus_width(sf, 4); 658 if (error) { 659 aprint_error_dev(sc->sc_dev, 660 "can't change bus width (%d bit)\n", 4); 661 return error; 662 } 663 sf->width = 4; 664 } 665 666 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 667 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 668 DPRINTF(("%s: switch func mode 0\n", SDMMCDEVNAME(sc))); 669 error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status); 670 if (error) { 671 aprint_error_dev(sc->sc_dev, 672 "switch func mode 0 failed\n"); 673 return error; 674 } 675 676 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 677 support_func = SFUNC_STATUS_GROUP(&status, 1); 678 best_func = 0; 679 for (i = 0, g = 1; 680 i < __arraycount(switch_group0_functions); i++, g <<= 1) { 681 if (!(switch_group0_functions[i].v & host_ocr)) 682 continue; 683 if (g & support_func) 684 best_func = i; 685 } 686 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) && 687 best_func != 0) { 688 DPRINTF(("%s: switch func mode 1(func=%d)\n", 689 SDMMCDEVNAME(sc), best_func)); 690 error = 691 sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status); 692 if (error) { 693 aprint_error_dev(sc->sc_dev, 694 "switch func mode 1 failed:" 695 " group 1 function %d(0x%2x)\n", 696 best_func, support_func); 697 return error; 698 } 699 sf->csd.tran_speed = 700 switch_group0_functions[best_func].freq; 701 702 /* Wait 400KHz x 8 clock (2.5us * 8 + slop) */ 703 delay(25); 704 } 705 } 706 707 /* update bus clock */ 708 if (sc->sc_busclk > sf->csd.tran_speed) 709 sc->sc_busclk = sf->csd.tran_speed; 710 if (sc->sc_busclk == bus_clock) 711 return 0; 712 713 /* change bus clock */ 714 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk); 715 if (error) { 716 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 717 return error; 718 } 719 720 return 0; 721 } 722 723 static int 724 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 725 { 726 int width, value, hs_timing, bus_clock, error; 727 char ext_csd[512]; 728 uint32_t sectors = 0; 729 730 /* change bus clock */ 731 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 732 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock); 733 if (error) { 734 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 735 return error; 736 } 737 738 if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 739 error = sdmmc_mem_send_cxd_data(sc, 740 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 741 if (error) { 742 aprint_error_dev(sc->sc_dev, 743 "can't read EXT_CSD (error=%d)\n", error); 744 return error; 745 } 746 if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) && 747 (ext_csd[EXT_CSD_STRUCTURE] > EXT_CSD_STRUCTURE_VER_1_2)) { 748 aprint_error_dev(sc->sc_dev, 749 "unrecognised future version (%d)\n", 750 ext_csd[EXT_CSD_STRUCTURE]); 751 return ENOTSUP; 752 } 753 754 if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_52M) { 755 sf->csd.tran_speed = 52000; /* 52MHz */ 756 hs_timing = 1; 757 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_26M) { 758 sf->csd.tran_speed = 26000; /* 26MHz */ 759 hs_timing = 0; 760 } else { 761 aprint_error_dev(sc->sc_dev, 762 "unknown CARD_TYPE: 0x%x\n", 763 ext_csd[EXT_CSD_CARD_TYPE]); 764 return ENOTSUP; 765 } 766 767 if (!ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 768 hs_timing = 0; 769 } 770 if (hs_timing) { 771 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 772 EXT_CSD_HS_TIMING, hs_timing); 773 if (error) { 774 aprint_error_dev(sc->sc_dev, 775 "can't change high speed\n"); 776 return error; 777 } 778 } 779 780 if (sc->sc_busclk > sf->csd.tran_speed) 781 sc->sc_busclk = sf->csd.tran_speed; 782 if (sc->sc_busclk != bus_clock) { 783 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 784 sc->sc_busclk); 785 if (error) { 786 aprint_error_dev(sc->sc_dev, 787 "can't change bus clock\n"); 788 return error; 789 } 790 } 791 792 if (hs_timing) { 793 error = sdmmc_mem_send_cxd_data(sc, 794 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 795 if (error) { 796 aprint_error_dev(sc->sc_dev, 797 "can't re-read EXT_CSD\n"); 798 return error; 799 } 800 if (ext_csd[EXT_CSD_HS_TIMING] != hs_timing) { 801 aprint_error_dev(sc->sc_dev, 802 "HS_TIMING set failed\n"); 803 return EINVAL; 804 } 805 } 806 807 sectors = ext_csd[EXT_CSD_SEC_COUNT + 0] << 0 | 808 ext_csd[EXT_CSD_SEC_COUNT + 1] << 8 | 809 ext_csd[EXT_CSD_SEC_COUNT + 2] << 16 | 810 ext_csd[EXT_CSD_SEC_COUNT + 3] << 24; 811 if (sectors > (2u * 1024 * 1024 * 1024) / 512) { 812 SET(sf->flags, SFF_SDHC); 813 sf->csd.capacity = sectors; 814 } 815 816 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 817 width = 8; 818 value = EXT_CSD_BUS_WIDTH_8; 819 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 820 width = 4; 821 value = EXT_CSD_BUS_WIDTH_4; 822 } else { 823 width = 1; 824 value = EXT_CSD_BUS_WIDTH_1; 825 } 826 827 if (width != 1) { 828 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 829 EXT_CSD_BUS_WIDTH, value); 830 if (error == 0) 831 error = sdmmc_chip_bus_width(sc->sc_sct, 832 sc->sc_sch, width); 833 else { 834 DPRINTF(("%s: can't change bus width" 835 " (%d bit)\n", SDMMCDEVNAME(sc), width)); 836 return error; 837 } 838 839 /* XXXX: need bus test? (using by CMD14 & CMD19) */ 840 } 841 sf->width = width; 842 } else { 843 if (sc->sc_busclk > sf->csd.tran_speed) 844 sc->sc_busclk = sf->csd.tran_speed; 845 if (sc->sc_busclk != bus_clock) { 846 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 847 sc->sc_busclk); 848 if (error) { 849 aprint_error_dev(sc->sc_dev, 850 "can't change bus clock\n"); 851 return error; 852 } 853 } 854 } 855 856 return 0; 857 } 858 859 static int 860 sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp) 861 { 862 struct sdmmc_command cmd; 863 int error; 864 865 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 866 memset(&cmd, 0, sizeof cmd); 867 cmd.c_opcode = MMC_ALL_SEND_CID; 868 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 869 870 error = sdmmc_mmc_command(sc, &cmd); 871 } else { 872 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CID, &cmd.c_resp, 873 sizeof(cmd.c_resp)); 874 } 875 876 #ifdef SDMMC_DEBUG 877 if (error == 0) 878 sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp)); 879 #endif 880 if (error == 0 && resp != NULL) 881 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 882 return error; 883 } 884 885 static int 886 sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf, 887 sdmmc_response *resp) 888 { 889 struct sdmmc_command cmd; 890 int error; 891 892 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 893 memset(&cmd, 0, sizeof cmd); 894 cmd.c_opcode = MMC_SEND_CSD; 895 cmd.c_arg = MMC_ARG_RCA(sf->rca); 896 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 897 898 error = sdmmc_mmc_command(sc, &cmd); 899 } else { 900 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CSD, &cmd.c_resp, 901 sizeof(cmd.c_resp)); 902 } 903 904 #ifdef SDMMC_DEBUG 905 if (error == 0) 906 sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp)); 907 #endif 908 if (error == 0 && resp != NULL) 909 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 910 return error; 911 } 912 913 static int 914 sdmmc_mem_send_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf, 915 uint32_t *scr) 916 { 917 struct sdmmc_command cmd; 918 bus_dma_segment_t ds[1]; 919 void *ptr = NULL; 920 int datalen = 8; 921 int rseg; 922 int error = 0; 923 924 /* Don't lock */ 925 926 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 927 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, 928 ds, 1, &rseg, BUS_DMA_NOWAIT); 929 if (error) 930 goto out; 931 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 932 BUS_DMA_NOWAIT); 933 if (error) 934 goto dmamem_free; 935 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 936 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 937 if (error) 938 goto dmamem_unmap; 939 940 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 941 BUS_DMASYNC_PREREAD); 942 } else { 943 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 944 if (ptr == NULL) 945 goto out; 946 } 947 948 memset(&cmd, 0, sizeof(cmd)); 949 cmd.c_data = ptr; 950 cmd.c_datalen = datalen; 951 cmd.c_blklen = datalen; 952 cmd.c_arg = 0; 953 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 954 cmd.c_opcode = SD_APP_SEND_SCR; 955 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 956 cmd.c_dmamap = sc->sc_dmap; 957 958 error = sdmmc_app_command(sc, sf, &cmd); 959 if (error == 0) { 960 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 961 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 962 BUS_DMASYNC_POSTREAD); 963 } 964 memcpy(scr, ptr, datalen); 965 } 966 967 out: 968 if (ptr != NULL) { 969 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 970 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 971 dmamem_unmap: 972 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 973 dmamem_free: 974 bus_dmamem_free(sc->sc_dmat, ds, rseg); 975 } else { 976 free(ptr, M_DEVBUF); 977 } 978 } 979 DPRINTF(("%s: sdmem_mem_send_scr: error = %d\n", SDMMCDEVNAME(sc), 980 error)); 981 982 #ifdef SDMMC_DEBUG 983 if (error == 0) 984 sdmmc_dump_data("SCR", scr, datalen); 985 #endif 986 return error; 987 } 988 989 static int 990 sdmmc_mem_decode_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf) 991 { 992 sdmmc_response resp; 993 int ver; 994 995 memset(resp, 0, sizeof(resp)); 996 /* 997 * Change the raw-scr received from the DMA stream to resp. 998 */ 999 resp[0] = be32toh(sf->raw_scr[1]) >> 8; // LSW 1000 resp[1] = be32toh(sf->raw_scr[0]); // MSW 1001 resp[0] |= (resp[1] & 0xff) << 24; 1002 resp[1] >>= 8; 1003 1004 ver = SCR_STRUCTURE(resp); 1005 sf->scr.sd_spec = SCR_SD_SPEC(resp); 1006 sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 1007 1008 DPRINTF(("%s: sdmmc_mem_decode_scr: %08x%08x spec=%d, bus width=%d\n", 1009 SDMMCDEVNAME(sc), resp[1], resp[0], 1010 sf->scr.sd_spec, sf->scr.bus_width)); 1011 1012 if (ver != 0) { 1013 DPRINTF(("%s: unknown structure version: %d\n", 1014 SDMMCDEVNAME(sc), ver)); 1015 return EINVAL; 1016 } 1017 return 0; 1018 } 1019 1020 static int 1021 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 1022 size_t datalen) 1023 { 1024 struct sdmmc_command cmd; 1025 bus_dma_segment_t ds[1]; 1026 void *ptr = NULL; 1027 int rseg; 1028 int error = 0; 1029 1030 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1031 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, ds, 1032 1, &rseg, BUS_DMA_NOWAIT); 1033 if (error) 1034 goto out; 1035 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1036 BUS_DMA_NOWAIT); 1037 if (error) 1038 goto dmamem_free; 1039 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1040 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1041 if (error) 1042 goto dmamem_unmap; 1043 1044 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1045 BUS_DMASYNC_PREREAD); 1046 } else { 1047 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1048 if (ptr == NULL) 1049 goto out; 1050 } 1051 1052 memset(&cmd, 0, sizeof(cmd)); 1053 cmd.c_data = ptr; 1054 cmd.c_datalen = datalen; 1055 cmd.c_blklen = datalen; 1056 cmd.c_opcode = opcode; 1057 cmd.c_arg = 0; 1058 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_SPI_R1; 1059 if (opcode == MMC_SEND_EXT_CSD) 1060 SET(cmd.c_flags, SCF_RSP_R1); 1061 else 1062 SET(cmd.c_flags, SCF_RSP_R2); 1063 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1064 cmd.c_dmamap = sc->sc_dmap; 1065 1066 error = sdmmc_mmc_command(sc, &cmd); 1067 if (error == 0) { 1068 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1069 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1070 BUS_DMASYNC_POSTREAD); 1071 } 1072 memcpy(data, ptr, datalen); 1073 #ifdef SDMMC_DEBUG 1074 sdmmc_dump_data("CXD", data, datalen); 1075 #endif 1076 } 1077 1078 out: 1079 if (ptr != NULL) { 1080 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1081 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1082 dmamem_unmap: 1083 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1084 dmamem_free: 1085 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1086 } else { 1087 free(ptr, M_DEVBUF); 1088 } 1089 } 1090 return error; 1091 } 1092 1093 static int 1094 sdmmc_set_bus_width(struct sdmmc_function *sf, int width) 1095 { 1096 struct sdmmc_softc *sc = sf->sc; 1097 struct sdmmc_command cmd; 1098 int error; 1099 1100 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1101 return ENODEV; 1102 1103 memset(&cmd, 0, sizeof(cmd)); 1104 cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 1105 cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 1106 1107 switch (width) { 1108 case 1: 1109 cmd.c_arg = SD_ARG_BUS_WIDTH_1; 1110 break; 1111 1112 case 4: 1113 cmd.c_arg = SD_ARG_BUS_WIDTH_4; 1114 break; 1115 1116 default: 1117 return EINVAL; 1118 } 1119 1120 error = sdmmc_app_command(sc, sf, &cmd); 1121 if (error == 0) 1122 error = sdmmc_chip_bus_width(sc->sc_sct, sc->sc_sch, width); 1123 return error; 1124 } 1125 1126 static int 1127 sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 1128 int function, sdmmc_bitfield512_t *status) 1129 { 1130 struct sdmmc_softc *sc = sf->sc; 1131 struct sdmmc_command cmd; 1132 bus_dma_segment_t ds[1]; 1133 void *ptr = NULL; 1134 int gsft, rseg, error = 0; 1135 const int statlen = 64; 1136 1137 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 1138 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 1139 return EINVAL; 1140 1141 if (group <= 0 || group > 6 || 1142 function < 0 || function > 15) 1143 return EINVAL; 1144 1145 gsft = (group - 1) << 2; 1146 1147 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1148 error = bus_dmamem_alloc(sc->sc_dmat, statlen, PAGE_SIZE, 0, ds, 1149 1, &rseg, BUS_DMA_NOWAIT); 1150 if (error) 1151 goto out; 1152 error = bus_dmamem_map(sc->sc_dmat, ds, 1, statlen, &ptr, 1153 BUS_DMA_NOWAIT); 1154 if (error) 1155 goto dmamem_free; 1156 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, statlen, 1157 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1158 if (error) 1159 goto dmamem_unmap; 1160 1161 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1162 BUS_DMASYNC_PREREAD); 1163 } else { 1164 ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 1165 if (ptr == NULL) 1166 goto out; 1167 } 1168 1169 memset(&cmd, 0, sizeof(cmd)); 1170 cmd.c_data = ptr; 1171 cmd.c_datalen = statlen; 1172 cmd.c_blklen = statlen; 1173 cmd.c_opcode = SD_SEND_SWITCH_FUNC; 1174 cmd.c_arg = 1175 (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 1176 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1177 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1178 cmd.c_dmamap = sc->sc_dmap; 1179 1180 error = sdmmc_mmc_command(sc, &cmd); 1181 if (error == 0) { 1182 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1183 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1184 BUS_DMASYNC_POSTREAD); 1185 } 1186 memcpy(status, ptr, statlen); 1187 } 1188 1189 out: 1190 if (ptr != NULL) { 1191 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1192 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1193 dmamem_unmap: 1194 bus_dmamem_unmap(sc->sc_dmat, ptr, statlen); 1195 dmamem_free: 1196 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1197 } else { 1198 free(ptr, M_DEVBUF); 1199 } 1200 } 1201 1202 if (error == 0) 1203 sdmmc_be512_to_bitfield512(status); 1204 1205 return error; 1206 } 1207 1208 static int 1209 sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 1210 uint8_t value) 1211 { 1212 struct sdmmc_softc *sc = sf->sc; 1213 struct sdmmc_command cmd; 1214 1215 memset(&cmd, 0, sizeof(cmd)); 1216 cmd.c_opcode = MMC_SWITCH; 1217 cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 1218 (index << 16) | (value << 8) | set; 1219 cmd.c_flags = SCF_RSP_SPI_R1B | SCF_RSP_R1B | SCF_CMD_AC; 1220 1221 return sdmmc_mmc_command(sc, &cmd); 1222 } 1223 1224 /* 1225 * SPI mode function 1226 */ 1227 static int 1228 sdmmc_mem_spi_read_ocr(struct sdmmc_softc *sc, uint32_t hcs, uint32_t *card_ocr) 1229 { 1230 struct sdmmc_command cmd; 1231 int error; 1232 1233 memset(&cmd, 0, sizeof(cmd)); 1234 cmd.c_opcode = MMC_READ_OCR; 1235 cmd.c_arg = hcs ? MMC_OCR_HCS : 0; 1236 cmd.c_flags = SCF_RSP_SPI_R3; 1237 1238 error = sdmmc_mmc_command(sc, &cmd); 1239 if (error == 0 && card_ocr != NULL) 1240 *card_ocr = cmd.c_resp[1]; 1241 DPRINTF(("%s: sdmmc_mem_spi_read_ocr: error=%d, ocr=%#x\n", 1242 SDMMCDEVNAME(sc), error, cmd.c_resp[1])); 1243 return error; 1244 } 1245 1246 /* 1247 * read/write function 1248 */ 1249 /* read */ 1250 static int 1251 sdmmc_mem_single_read_block(struct sdmmc_function *sf, uint32_t blkno, 1252 u_char *data, size_t datalen) 1253 { 1254 struct sdmmc_softc *sc __diagused = sf->sc; 1255 int error = 0; 1256 int i; 1257 1258 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1259 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1260 1261 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1262 error = sdmmc_mem_read_block_subr(sf, blkno + i, 1263 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1264 if (error) 1265 break; 1266 } 1267 return error; 1268 } 1269 1270 static int 1271 sdmmc_mem_read_block_subr(struct sdmmc_function *sf, uint32_t blkno, 1272 u_char *data, size_t datalen) 1273 { 1274 struct sdmmc_softc *sc = sf->sc; 1275 struct sdmmc_command cmd; 1276 int error, bbuf, seg, off, len, num; 1277 1278 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1279 error = sdmmc_select_card(sc, sf); 1280 if (error) 1281 goto out; 1282 } 1283 1284 bbuf = 0; 1285 num = 0; 1286 seg = off = len = 0; 1287 retry: 1288 memset(&cmd, 0, sizeof(cmd)); 1289 cmd.c_data = data; 1290 cmd.c_datalen = datalen; 1291 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1292 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1293 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1294 cmd.c_arg = blkno; 1295 if (!ISSET(sf->flags, SFF_SDHC)) 1296 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1297 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1298 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1299 cmd.c_dmamap = sc->sc_dmap; 1300 if (!ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1301 len = sc->sc_dmap->dm_segs[seg].ds_len - off; 1302 len &= ~(SDMMC_SECTOR_SIZE - 1); 1303 cmd.c_datalen = len; 1304 cmd.c_dmaseg = seg; 1305 cmd.c_dmaoff = off; 1306 bbuf = 0; 1307 if (len == 0) { 1308 /* Use bounce buffer */ 1309 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 1310 0, SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREREAD); 1311 cmd.c_datalen = SDMMC_SECTOR_SIZE; 1312 cmd.c_dmamap = sf->bbuf_dmap; 1313 cmd.c_dmaseg = 0; 1314 cmd.c_dmaoff = 0; 1315 bbuf = 1; 1316 len = SDMMC_SECTOR_SIZE; 1317 } 1318 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1319 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1320 } 1321 } 1322 1323 error = sdmmc_mmc_command(sc, &cmd); 1324 if (error) 1325 goto out; 1326 1327 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1328 if (cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 1329 memset(&cmd, 0, sizeof cmd); 1330 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1331 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1332 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1333 error = sdmmc_mmc_command(sc, &cmd); 1334 if (error) 1335 goto out; 1336 } 1337 } 1338 1339 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1340 do { 1341 memset(&cmd, 0, sizeof(cmd)); 1342 cmd.c_opcode = MMC_SEND_STATUS; 1343 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1344 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1345 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1346 error = sdmmc_mmc_command(sc, &cmd); 1347 if (error) 1348 break; 1349 /* XXX time out */ 1350 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1351 } 1352 1353 if (ISSET(sc->sc_caps, SMC_CAPS_DMA) && 1354 !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1355 bus_dma_segment_t *dm_segs = sc->sc_dmap->dm_segs; 1356 1357 if (bbuf) { 1358 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 1359 0, SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTREAD); 1360 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1361 SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTREAD); 1362 memcpy(data, sf->bbuf, SDMMC_SECTOR_SIZE); 1363 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1364 SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREREAD); 1365 } 1366 num += len; 1367 data += len; 1368 datalen -= len; 1369 blkno += (len / SDMMC_SECTOR_SIZE); 1370 1371 while (off + len >= dm_segs[seg].ds_len) { 1372 len -= dm_segs[seg++].ds_len; 1373 off = 0; 1374 } 1375 off += len; 1376 1377 if (seg < sc->sc_dmap->dm_nsegs) 1378 goto retry; 1379 } 1380 1381 out: 1382 return error; 1383 } 1384 1385 int 1386 sdmmc_mem_read_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1387 size_t datalen) 1388 { 1389 struct sdmmc_softc *sc = sf->sc; 1390 int error; 1391 1392 SDMMC_LOCK(sc); 1393 1394 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1395 error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 1396 goto out; 1397 } 1398 1399 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1400 error = sdmmc_mem_read_block_subr(sf, blkno, data, datalen); 1401 goto out; 1402 } 1403 1404 /* DMA transfer */ 1405 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1406 BUS_DMA_NOWAIT|BUS_DMA_READ); 1407 if (error) 1408 goto out; 1409 1410 #ifdef SDMMC_DEBUG 1411 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1412 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1413 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1414 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1415 } 1416 #endif 1417 1418 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1419 BUS_DMASYNC_PREREAD); 1420 1421 error = sdmmc_mem_read_block_subr(sf, blkno, data, datalen); 1422 if (error) 1423 goto unload; 1424 1425 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1426 BUS_DMASYNC_POSTREAD); 1427 unload: 1428 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1429 1430 out: 1431 SDMMC_UNLOCK(sc); 1432 1433 return error; 1434 } 1435 1436 /* write */ 1437 static int 1438 sdmmc_mem_single_write_block(struct sdmmc_function *sf, uint32_t blkno, 1439 u_char *data, size_t datalen) 1440 { 1441 struct sdmmc_softc *sc __diagused = sf->sc; 1442 int error = 0; 1443 int i; 1444 1445 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1446 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1447 1448 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1449 error = sdmmc_mem_write_block_subr(sf, blkno + i, 1450 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1451 if (error) 1452 break; 1453 } 1454 return error; 1455 } 1456 1457 static int 1458 sdmmc_mem_write_block_subr(struct sdmmc_function *sf, uint32_t blkno, 1459 u_char *data, size_t datalen) 1460 { 1461 struct sdmmc_softc *sc = sf->sc; 1462 struct sdmmc_command cmd; 1463 int error, bbuf, seg, off, len, num; 1464 1465 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1466 error = sdmmc_select_card(sc, sf); 1467 if (error) 1468 goto out; 1469 } 1470 1471 bbuf = 0; 1472 num = 0; 1473 seg = off = len = 0; 1474 retry: 1475 memset(&cmd, 0, sizeof(cmd)); 1476 cmd.c_data = data; 1477 cmd.c_datalen = datalen; 1478 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1479 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1480 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1481 cmd.c_arg = blkno; 1482 if (!ISSET(sf->flags, SFF_SDHC)) 1483 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1484 cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 1485 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1486 cmd.c_dmamap = sc->sc_dmap; 1487 if (!ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1488 len = sc->sc_dmap->dm_segs[seg].ds_len - off; 1489 len &= ~(SDMMC_SECTOR_SIZE - 1); 1490 cmd.c_datalen = len; 1491 cmd.c_dmaseg = seg; 1492 cmd.c_dmaoff = off; 1493 bbuf = 0; 1494 if (len == 0) { 1495 /* Use bounce buffer */ 1496 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1497 SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTWRITE); 1498 memcpy(sf->bbuf, data, SDMMC_SECTOR_SIZE); 1499 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1500 SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREWRITE); 1501 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, 1502 SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREWRITE); 1503 cmd.c_datalen = SDMMC_SECTOR_SIZE; 1504 cmd.c_dmamap = sf->bbuf_dmap; 1505 cmd.c_dmaseg = 0; 1506 cmd.c_dmaoff = 0; 1507 bbuf = 1; 1508 len = SDMMC_SECTOR_SIZE; 1509 } 1510 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1511 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1512 } 1513 } 1514 1515 error = sdmmc_mmc_command(sc, &cmd); 1516 if (error) 1517 goto out; 1518 1519 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1520 if (cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1521 memset(&cmd, 0, sizeof(cmd)); 1522 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1523 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1524 error = sdmmc_mmc_command(sc, &cmd); 1525 if (error) 1526 goto out; 1527 } 1528 } 1529 1530 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1531 do { 1532 memset(&cmd, 0, sizeof(cmd)); 1533 cmd.c_opcode = MMC_SEND_STATUS; 1534 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1535 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1536 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1537 error = sdmmc_mmc_command(sc, &cmd); 1538 if (error) 1539 break; 1540 /* XXX time out */ 1541 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1542 } 1543 1544 if (ISSET(sc->sc_caps, SMC_CAPS_DMA) && 1545 !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1546 bus_dma_segment_t *dm_segs = sc->sc_dmap->dm_segs; 1547 1548 if (bbuf) 1549 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 1550 0, SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTWRITE); 1551 num += len; 1552 data += len; 1553 datalen -= len; 1554 blkno += (len / SDMMC_SECTOR_SIZE); 1555 1556 while (off + len >= dm_segs[seg].ds_len) { 1557 len -= dm_segs[seg++].ds_len; 1558 off = 0; 1559 } 1560 off += len; 1561 1562 if (seg < sc->sc_dmap->dm_nsegs) 1563 goto retry; 1564 } 1565 1566 out: 1567 return error; 1568 } 1569 1570 int 1571 sdmmc_mem_write_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1572 size_t datalen) 1573 { 1574 struct sdmmc_softc *sc = sf->sc; 1575 int error; 1576 1577 SDMMC_LOCK(sc); 1578 1579 if (sdmmc_chip_write_protect(sc->sc_sct, sc->sc_sch)) { 1580 aprint_normal_dev(sc->sc_dev, "write-protected\n"); 1581 error = EIO; 1582 goto out; 1583 } 1584 1585 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1586 error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1587 goto out; 1588 } 1589 1590 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1591 error = sdmmc_mem_write_block_subr(sf, blkno, data, datalen); 1592 goto out; 1593 } 1594 1595 /* DMA transfer */ 1596 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1597 BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1598 if (error) 1599 goto out; 1600 1601 #ifdef SDMMC_DEBUG 1602 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1603 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1604 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1605 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1606 } 1607 #endif 1608 1609 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1610 BUS_DMASYNC_PREWRITE); 1611 1612 error = sdmmc_mem_write_block_subr(sf, blkno, data, datalen); 1613 if (error) 1614 goto unload; 1615 1616 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1617 BUS_DMASYNC_POSTWRITE); 1618 unload: 1619 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1620 1621 out: 1622 SDMMC_UNLOCK(sc); 1623 1624 return error; 1625 } 1626
Indexes created Wed Sep 24 22:09:59 GMT 2025