sdmmc_mem.c revision 1.36
1 /* $NetBSD: sdmmc_mem.c,v 1.36 2015/08/02 22:47:05 jmcneill Exp $ */ 2 /* $OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2007, 2008, 2009, 2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 /* Routines for SD/MMC memory cards. */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.36 2015/08/02 22:47:05 jmcneill Exp $"); 49 50 #ifdef _KERNEL_OPT 51 #include "opt_sdmmc.h" 52 #endif 53 54 #include <sys/param.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 60 #include <dev/sdmmc/sdmmcchip.h> 61 #include <dev/sdmmc/sdmmcreg.h> 62 #include <dev/sdmmc/sdmmcvar.h> 63 64 #ifdef SDMMC_DEBUG 65 #define DPRINTF(s) do { printf s; } while (/*CONSTCOND*/0) 66 #else 67 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 68 #endif 69 70 typedef struct { uint32_t _bits[512/32]; } __packed __aligned(4) sdmmc_bitfield512_t; 71 72 static int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 73 static int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 74 static int sdmmc_mem_send_cid(struct sdmmc_softc *, sdmmc_response *); 75 static int sdmmc_mem_send_csd(struct sdmmc_softc *, struct sdmmc_function *, 76 sdmmc_response *); 77 static int sdmmc_mem_send_scr(struct sdmmc_softc *, struct sdmmc_function *, 78 uint32_t *scr); 79 static int sdmmc_mem_decode_scr(struct sdmmc_softc *, struct sdmmc_function *); 80 static int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 81 static int sdmmc_set_bus_width(struct sdmmc_function *, int); 82 static int sdmmc_mem_sd_switch(struct sdmmc_function *, int, int, int, sdmmc_bitfield512_t *); 83 static int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, 84 uint8_t); 85 static int sdmmc_mem_spi_read_ocr(struct sdmmc_softc *, uint32_t, uint32_t *); 86 static int sdmmc_mem_single_read_block(struct sdmmc_function *, uint32_t, 87 u_char *, size_t); 88 static int sdmmc_mem_single_write_block(struct sdmmc_function *, uint32_t, 89 u_char *, size_t); 90 static int sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *, 91 uint32_t, u_char *, size_t); 92 static int sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *, 93 uint32_t, u_char *, size_t); 94 static int sdmmc_mem_read_block_subr(struct sdmmc_function *, bus_dmamap_t, 95 uint32_t, u_char *, size_t); 96 static int sdmmc_mem_write_block_subr(struct sdmmc_function *, bus_dmamap_t, 97 uint32_t, u_char *, size_t); 98 99 /* 100 * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 101 */ 102 int 103 sdmmc_mem_enable(struct sdmmc_softc *sc) 104 { 105 uint32_t host_ocr; 106 uint32_t card_ocr; 107 uint32_t new_ocr; 108 uint32_t ocr = 0; 109 int error; 110 111 SDMMC_LOCK(sc); 112 113 /* Set host mode to SD "combo" card or SD memory-only. */ 114 SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 115 116 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 117 sdmmc_spi_chip_initialize(sc->sc_spi_sct, sc->sc_sch); 118 119 /* Reset memory (*must* do that before CMD55 or CMD1). */ 120 sdmmc_go_idle_state(sc); 121 122 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 123 /* Check SD Ver.2 */ 124 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 125 if (error == 0 && card_ocr == 0x1aa) 126 SET(ocr, MMC_OCR_HCS); 127 } 128 129 /* 130 * Read the SD/MMC memory OCR value by issuing CMD55 followed 131 * by ACMD41 to read the OCR value from memory-only SD cards. 132 * MMC cards will not respond to CMD55 or ACMD41 and this is 133 * how we distinguish them from SD cards. 134 */ 135 mmc_mode: 136 error = sdmmc_mem_send_op_cond(sc, 137 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr); 138 if (error) { 139 if (ISSET(sc->sc_flags, SMF_SD_MODE) && 140 !ISSET(sc->sc_flags, SMF_IO_MODE)) { 141 /* Not a SD card, switch to MMC mode. */ 142 DPRINTF(("%s: switch to MMC mode\n", SDMMCDEVNAME(sc))); 143 CLR(sc->sc_flags, SMF_SD_MODE); 144 goto mmc_mode; 145 } 146 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 147 DPRINTF(("%s: couldn't read memory OCR\n", 148 SDMMCDEVNAME(sc))); 149 goto out; 150 } else { 151 /* Not a "combo" card. */ 152 CLR(sc->sc_flags, SMF_MEM_MODE); 153 error = 0; 154 goto out; 155 } 156 } 157 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 158 /* get card OCR */ 159 error = sdmmc_mem_spi_read_ocr(sc, ocr, &card_ocr); 160 if (error) { 161 DPRINTF(("%s: couldn't read SPI memory OCR\n", 162 SDMMCDEVNAME(sc))); 163 goto out; 164 } 165 } 166 167 /* Set the lowest voltage supported by the card and host. */ 168 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 169 error = sdmmc_set_bus_power(sc, host_ocr, card_ocr); 170 if (error) { 171 DPRINTF(("%s: couldn't supply voltage requested by card\n", 172 SDMMCDEVNAME(sc))); 173 goto out; 174 } 175 176 /* Tell the card(s) to enter the idle state (again). */ 177 sdmmc_go_idle_state(sc); 178 179 DPRINTF(("%s: host_ocr 0x%08x\n", SDMMCDEVNAME(sc), host_ocr)); 180 DPRINTF(("%s: card_ocr 0x%08x\n", SDMMCDEVNAME(sc), card_ocr)); 181 182 host_ocr &= card_ocr; /* only allow the common voltages */ 183 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 184 /* Check SD Ver.2 */ 185 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 186 if (error == 0 && card_ocr == 0x1aa) 187 SET(ocr, MMC_OCR_HCS); 188 189 if (sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch) & MMC_OCR_S18A) 190 SET(ocr, MMC_OCR_S18A); 191 } 192 host_ocr |= ocr; 193 194 /* Send the new OCR value until all cards are ready. */ 195 error = sdmmc_mem_send_op_cond(sc, host_ocr, &new_ocr); 196 if (error) { 197 DPRINTF(("%s: couldn't send memory OCR\n", SDMMCDEVNAME(sc))); 198 goto out; 199 } 200 201 if (ISSET(new_ocr, MMC_OCR_S18A) && sc->sc_sct->signal_voltage) { 202 /* 203 * Card and host support low voltage mode, begin switch 204 * sequence. 205 */ 206 struct sdmmc_command cmd; 207 memset(&cmd, 0, sizeof(cmd)); 208 cmd.c_arg = 0; 209 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 210 cmd.c_opcode = SD_VOLTAGE_SWITCH; 211 error = sdmmc_mmc_command(sc, &cmd); 212 if (error) { 213 DPRINTF(("%s: voltage switch command failed\n", 214 SDMMCDEVNAME(sc))); 215 goto out; 216 } 217 218 delay(1000); 219 220 /* 221 * Stop the clock 222 */ 223 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 224 SDMMC_SDCLK_OFF); 225 if (error) 226 goto out; 227 228 delay(1000); 229 230 /* 231 * Card switch command was successful, update host controller 232 * signal voltage setting. 233 */ 234 error = sdmmc_chip_signal_voltage(sc->sc_sct, 235 sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_180); 236 if (error) 237 goto out; 238 239 delay(5000); 240 241 /* 242 * Switch to SDR12 timing 243 */ 244 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 25000); 245 if (error) 246 goto out; 247 248 delay(1000); 249 250 SET(sc->sc_flags, SMF_UHS_MODE); 251 } 252 253 out: 254 SDMMC_UNLOCK(sc); 255 256 if (error) 257 printf("%s: %s failed with error %d\n", SDMMCDEVNAME(sc), 258 __func__, error); 259 260 return error; 261 } 262 263 /* 264 * Read the CSD and CID from all cards and assign each card a unique 265 * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 266 */ 267 void 268 sdmmc_mem_scan(struct sdmmc_softc *sc) 269 { 270 sdmmc_response resp; 271 struct sdmmc_function *sf; 272 uint16_t next_rca; 273 int error; 274 int retry; 275 276 SDMMC_LOCK(sc); 277 278 /* 279 * CMD2 is a broadcast command understood by SD cards and MMC 280 * cards. All cards begin to respond to the command, but back 281 * off if another card drives the CMD line to a different level. 282 * Only one card will get its entire response through. That 283 * card remains silent once it has been assigned a RCA. 284 */ 285 for (retry = 0; retry < 100; retry++) { 286 error = sdmmc_mem_send_cid(sc, &resp); 287 if (error) { 288 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && 289 error == ETIMEDOUT) { 290 /* No more cards there. */ 291 break; 292 } 293 DPRINTF(("%s: couldn't read CID\n", SDMMCDEVNAME(sc))); 294 break; 295 } 296 297 /* In MMC mode, find the next available RCA. */ 298 next_rca = 1; 299 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 300 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) 301 next_rca++; 302 } 303 304 /* Allocate a sdmmc_function structure. */ 305 sf = sdmmc_function_alloc(sc); 306 sf->rca = next_rca; 307 308 /* 309 * Remember the CID returned in the CMD2 response for 310 * later decoding. 311 */ 312 memcpy(sf->raw_cid, resp, sizeof(sf->raw_cid)); 313 314 /* 315 * Silence the card by assigning it a unique RCA, or 316 * querying it for its RCA in the case of SD. 317 */ 318 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 319 if (sdmmc_set_relative_addr(sc, sf) != 0) { 320 aprint_error_dev(sc->sc_dev, 321 "couldn't set mem RCA\n"); 322 sdmmc_function_free(sf); 323 break; 324 } 325 } 326 327 /* 328 * If this is a memory-only card, the card responding 329 * first becomes an alias for SDIO function 0. 330 */ 331 if (sc->sc_fn0 == NULL) 332 sc->sc_fn0 = sf; 333 334 SIMPLEQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 335 336 /* only one function in SPI mode */ 337 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 338 break; 339 } 340 341 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 342 /* Go to Data Transfer Mode, if possible. */ 343 sdmmc_chip_bus_rod(sc->sc_sct, sc->sc_sch, 0); 344 345 /* 346 * All cards are either inactive or awaiting further commands. 347 * Read the CSDs and decode the raw CID for each card. 348 */ 349 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) { 350 error = sdmmc_mem_send_csd(sc, sf, &resp); 351 if (error) { 352 SET(sf->flags, SFF_ERROR); 353 continue; 354 } 355 356 if (sdmmc_decode_csd(sc, resp, sf) != 0 || 357 sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 358 SET(sf->flags, SFF_ERROR); 359 continue; 360 } 361 362 #ifdef SDMMC_DEBUG 363 printf("%s: CID: ", SDMMCDEVNAME(sc)); 364 sdmmc_print_cid(&sf->cid); 365 #endif 366 } 367 368 SDMMC_UNLOCK(sc); 369 } 370 371 int 372 sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 373 struct sdmmc_function *sf) 374 { 375 /* TRAN_SPEED(2:0): transfer rate exponent */ 376 static const int speed_exponent[8] = { 377 100 * 1, /* 100 Kbits/s */ 378 1 * 1000, /* 1 Mbits/s */ 379 10 * 1000, /* 10 Mbits/s */ 380 100 * 1000, /* 100 Mbits/s */ 381 0, 382 0, 383 0, 384 0, 385 }; 386 /* TRAN_SPEED(6:3): time mantissa */ 387 static const int speed_mantissa[16] = { 388 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 389 }; 390 struct sdmmc_csd *csd = &sf->csd; 391 int e, m; 392 393 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 394 /* 395 * CSD version 1.0 corresponds to SD system 396 * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 397 */ 398 csd->csdver = SD_CSD_CSDVER(resp); 399 switch (csd->csdver) { 400 case SD_CSD_CSDVER_2_0: 401 DPRINTF(("%s: SD Ver.2.0\n", SDMMCDEVNAME(sc))); 402 SET(sf->flags, SFF_SDHC); 403 csd->capacity = SD_CSD_V2_CAPACITY(resp); 404 csd->read_bl_len = SD_CSD_V2_BL_LEN; 405 break; 406 407 case SD_CSD_CSDVER_1_0: 408 DPRINTF(("%s: SD Ver.1.0\n", SDMMCDEVNAME(sc))); 409 csd->capacity = SD_CSD_CAPACITY(resp); 410 csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 411 break; 412 413 default: 414 aprint_error_dev(sc->sc_dev, 415 "unknown SD CSD structure version 0x%x\n", 416 csd->csdver); 417 return 1; 418 } 419 420 csd->mmcver = SD_CSD_MMCVER(resp); 421 csd->write_bl_len = SD_CSD_WRITE_BL_LEN(resp); 422 csd->r2w_factor = SD_CSD_R2W_FACTOR(resp); 423 e = SD_CSD_SPEED_EXP(resp); 424 m = SD_CSD_SPEED_MANT(resp); 425 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 426 csd->ccc = SD_CSD_CCC(resp); 427 } else { 428 csd->csdver = MMC_CSD_CSDVER(resp); 429 if (csd->csdver == MMC_CSD_CSDVER_1_0) { 430 aprint_error_dev(sc->sc_dev, 431 "unknown MMC CSD structure version 0x%x\n", 432 csd->csdver); 433 return 1; 434 } 435 436 csd->mmcver = MMC_CSD_MMCVER(resp); 437 csd->capacity = MMC_CSD_CAPACITY(resp); 438 csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 439 csd->write_bl_len = MMC_CSD_WRITE_BL_LEN(resp); 440 csd->r2w_factor = MMC_CSD_R2W_FACTOR(resp); 441 e = MMC_CSD_TRAN_SPEED_EXP(resp); 442 m = MMC_CSD_TRAN_SPEED_MANT(resp); 443 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 444 } 445 if ((1 << csd->read_bl_len) > SDMMC_SECTOR_SIZE) 446 csd->capacity *= (1 << csd->read_bl_len) / SDMMC_SECTOR_SIZE; 447 448 #ifdef SDMMC_DUMP_CSD 449 sdmmc_print_csd(resp, csd); 450 #endif 451 452 return 0; 453 } 454 455 int 456 sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 457 struct sdmmc_function *sf) 458 { 459 struct sdmmc_cid *cid = &sf->cid; 460 461 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 462 cid->mid = SD_CID_MID(resp); 463 cid->oid = SD_CID_OID(resp); 464 SD_CID_PNM_CPY(resp, cid->pnm); 465 cid->rev = SD_CID_REV(resp); 466 cid->psn = SD_CID_PSN(resp); 467 cid->mdt = SD_CID_MDT(resp); 468 } else { 469 switch(sf->csd.mmcver) { 470 case MMC_CSD_MMCVER_1_0: 471 case MMC_CSD_MMCVER_1_4: 472 cid->mid = MMC_CID_MID_V1(resp); 473 MMC_CID_PNM_V1_CPY(resp, cid->pnm); 474 cid->rev = MMC_CID_REV_V1(resp); 475 cid->psn = MMC_CID_PSN_V1(resp); 476 cid->mdt = MMC_CID_MDT_V1(resp); 477 break; 478 case MMC_CSD_MMCVER_2_0: 479 case MMC_CSD_MMCVER_3_1: 480 case MMC_CSD_MMCVER_4_0: 481 cid->mid = MMC_CID_MID_V2(resp); 482 cid->oid = MMC_CID_OID_V2(resp); 483 MMC_CID_PNM_V2_CPY(resp, cid->pnm); 484 cid->psn = MMC_CID_PSN_V2(resp); 485 break; 486 default: 487 aprint_error_dev(sc->sc_dev, "unknown MMC version %d\n", 488 sf->csd.mmcver); 489 return 1; 490 } 491 } 492 return 0; 493 } 494 495 void 496 sdmmc_print_cid(struct sdmmc_cid *cid) 497 { 498 499 printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 500 " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 501 cid->mdt); 502 } 503 504 #ifdef SDMMC_DUMP_CSD 505 void 506 sdmmc_print_csd(sdmmc_response resp, struct sdmmc_csd *csd) 507 { 508 509 printf("csdver = %d\n", csd->csdver); 510 printf("mmcver = %d\n", csd->mmcver); 511 printf("capacity = 0x%08x\n", csd->capacity); 512 printf("read_bl_len = %d\n", csd->read_bl_len); 513 printf("write_bl_len = %d\n", csd->write_bl_len); 514 printf("r2w_factor = %d\n", csd->r2w_factor); 515 printf("tran_speed = %d\n", csd->tran_speed); 516 printf("ccc = 0x%x\n", csd->ccc); 517 } 518 #endif 519 520 /* 521 * Initialize a SD/MMC memory card. 522 */ 523 int 524 sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 525 { 526 int error = 0; 527 528 SDMMC_LOCK(sc); 529 530 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 531 error = sdmmc_select_card(sc, sf); 532 if (error) 533 goto out; 534 } 535 536 error = sdmmc_mem_set_blocklen(sc, sf, SDMMC_SECTOR_SIZE); 537 if (error) 538 goto out; 539 540 if (ISSET(sc->sc_flags, SMF_SD_MODE)) 541 error = sdmmc_mem_sd_init(sc, sf); 542 else 543 error = sdmmc_mem_mmc_init(sc, sf); 544 545 out: 546 SDMMC_UNLOCK(sc); 547 548 return error; 549 } 550 551 /* 552 * Get or set the card's memory OCR value (SD or MMC). 553 */ 554 int 555 sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 556 { 557 struct sdmmc_command cmd; 558 int error; 559 int retry; 560 561 /* Don't lock */ 562 563 DPRINTF(("%s: sdmmc_mem_send_op_cond: ocr=%#x\n", 564 SDMMCDEVNAME(sc), ocr)); 565 566 /* 567 * If we change the OCR value, retry the command until the OCR 568 * we receive in response has the "CARD BUSY" bit set, meaning 569 * that all cards are ready for identification. 570 */ 571 for (retry = 0; retry < 100; retry++) { 572 memset(&cmd, 0, sizeof(cmd)); 573 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? 574 ocr : (ocr & MMC_OCR_HCS); 575 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3 | SCF_RSP_SPI_R1; 576 577 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 578 cmd.c_opcode = SD_APP_OP_COND; 579 error = sdmmc_app_command(sc, NULL, &cmd); 580 } else { 581 cmd.c_opcode = MMC_SEND_OP_COND; 582 error = sdmmc_mmc_command(sc, &cmd); 583 } 584 if (error) 585 break; 586 587 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 588 if (!ISSET(MMC_SPI_R1(cmd.c_resp), R1_SPI_IDLE)) 589 break; 590 } else { 591 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 592 ocr == 0) 593 break; 594 } 595 596 error = ETIMEDOUT; 597 sdmmc_delay(10000); 598 } 599 if (error == 0 && 600 ocrp != NULL && 601 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 602 *ocrp = MMC_R3(cmd.c_resp); 603 DPRINTF(("%s: sdmmc_mem_send_op_cond: error=%d, ocr=%#x\n", 604 SDMMCDEVNAME(sc), error, MMC_R3(cmd.c_resp))); 605 return error; 606 } 607 608 int 609 sdmmc_mem_send_if_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 610 { 611 struct sdmmc_command cmd; 612 int error; 613 614 /* Don't lock */ 615 616 memset(&cmd, 0, sizeof(cmd)); 617 cmd.c_arg = ocr; 618 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R7 | SCF_RSP_SPI_R7; 619 cmd.c_opcode = SD_SEND_IF_COND; 620 621 error = sdmmc_mmc_command(sc, &cmd); 622 if (error == 0 && ocrp != NULL) { 623 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 624 *ocrp = MMC_SPI_R7(cmd.c_resp); 625 } else { 626 *ocrp = MMC_R7(cmd.c_resp); 627 } 628 DPRINTF(("%s: sdmmc_mem_send_if_cond: error=%d, ocr=%#x\n", 629 SDMMCDEVNAME(sc), error, *ocrp)); 630 } 631 return error; 632 } 633 634 /* 635 * Set the read block length appropriately for this card, according to 636 * the card CSD register value. 637 */ 638 int 639 sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf, 640 int block_len) 641 { 642 struct sdmmc_command cmd; 643 int error; 644 645 /* Don't lock */ 646 647 memset(&cmd, 0, sizeof(cmd)); 648 cmd.c_opcode = MMC_SET_BLOCKLEN; 649 cmd.c_arg = block_len; 650 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1; 651 652 error = sdmmc_mmc_command(sc, &cmd); 653 654 DPRINTF(("%s: sdmmc_mem_set_blocklen: read_bl_len=%d sector_size=%d\n", 655 SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, block_len)); 656 657 return error; 658 } 659 660 /* make 512-bit BE quantity __bitfield()-compatible */ 661 static void 662 sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) { 663 size_t i; 664 uint32_t tmp0, tmp1; 665 const size_t bitswords = __arraycount(buf->_bits); 666 for (i = 0; i < bitswords/2; i++) { 667 tmp0 = buf->_bits[i]; 668 tmp1 = buf->_bits[bitswords - 1 - i]; 669 buf->_bits[i] = be32toh(tmp1); 670 buf->_bits[bitswords - 1 - i] = be32toh(tmp0); 671 } 672 } 673 674 static int 675 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 676 { 677 static const struct { 678 int v; 679 int freq; 680 int uhs; 681 } switch_group0_functions[] = { 682 /* Default/SDR12 */ 683 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 684 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 25000, 0 }, 685 686 /* High-Speed/SDR25 */ 687 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 688 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 50000, 0 }, 689 690 /* SDR50 */ 691 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 100000, 1 }, 692 693 /* SDR104 */ 694 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 208000, 1 }, 695 696 #if notyet 697 /* DDR50 */ 698 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 50000, 1 }, 699 #endif 700 }; 701 int host_ocr, support_func, best_func, bus_clock, error, g, i; 702 sdmmc_bitfield512_t status; /* Switch Function Status */ 703 704 /* change bus clock */ 705 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 706 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock); 707 if (error) { 708 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 709 return error; 710 } 711 712 error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr); 713 if (error) { 714 aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n"); 715 return error; 716 } 717 error = sdmmc_mem_decode_scr(sc, sf); 718 if (error) 719 return error; 720 721 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 722 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 723 DPRINTF(("%s: change bus width\n", SDMMCDEVNAME(sc))); 724 error = sdmmc_set_bus_width(sf, 4); 725 if (error) { 726 aprint_error_dev(sc->sc_dev, 727 "can't change bus width (%d bit)\n", 4); 728 return error; 729 } 730 sf->width = 4; 731 } 732 733 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 734 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 735 DPRINTF(("%s: switch func mode 0\n", SDMMCDEVNAME(sc))); 736 error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status); 737 if (error) { 738 aprint_error_dev(sc->sc_dev, 739 "switch func mode 0 failed\n"); 740 return error; 741 } 742 743 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 744 support_func = SFUNC_STATUS_GROUP(&status, 1); 745 best_func = 0; 746 for (i = 0, g = 1; 747 i < __arraycount(switch_group0_functions); i++, g <<= 1) { 748 if (!(switch_group0_functions[i].v & host_ocr)) 749 continue; 750 if (switch_group0_functions[i].uhs && 751 !ISSET(sc->sc_flags, SMF_UHS_MODE)) 752 break; 753 if (g & support_func) 754 best_func = i; 755 } 756 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) && 757 best_func != 0) { 758 DPRINTF(("%s: switch func mode 1(func=%d)\n", 759 SDMMCDEVNAME(sc), best_func)); 760 error = 761 sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status); 762 if (error) { 763 aprint_error_dev(sc->sc_dev, 764 "switch func mode 1 failed:" 765 " group 1 function %d(0x%2x)\n", 766 best_func, support_func); 767 return error; 768 } 769 sf->csd.tran_speed = 770 switch_group0_functions[best_func].freq; 771 772 /* Wait 400KHz x 8 clock (2.5us * 8 + slop) */ 773 delay(25); 774 } 775 } 776 777 /* update bus clock */ 778 if (sc->sc_busclk > sf->csd.tran_speed) 779 sc->sc_busclk = sf->csd.tran_speed; 780 if (sc->sc_busclk == bus_clock) 781 return 0; 782 783 /* change bus clock */ 784 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk); 785 if (error) { 786 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 787 return error; 788 } 789 790 return 0; 791 } 792 793 static int 794 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 795 { 796 int width, value, hs_timing, bus_clock, error; 797 char ext_csd[512]; 798 uint32_t sectors = 0; 799 int host_ocr; 800 801 /* change bus clock */ 802 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 803 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock); 804 if (error) { 805 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 806 return error; 807 } 808 809 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 810 811 if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 812 error = sdmmc_mem_send_cxd_data(sc, 813 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 814 if (error) { 815 aprint_error_dev(sc->sc_dev, 816 "can't read EXT_CSD (error=%d)\n", error); 817 return error; 818 } 819 if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) && 820 (ext_csd[EXT_CSD_STRUCTURE] > EXT_CSD_STRUCTURE_VER_1_2)) { 821 aprint_error_dev(sc->sc_dev, 822 "unrecognised future version (%d)\n", 823 ext_csd[EXT_CSD_STRUCTURE]); 824 return ENOTSUP; 825 } 826 827 if (ISSET(host_ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V) && 828 ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_HS200_1_8V) { 829 sf->csd.tran_speed = 200000; /* 200MHz SDR */ 830 hs_timing = 2; 831 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_52M) { 832 sf->csd.tran_speed = 52000; /* 52MHz */ 833 hs_timing = 1; 834 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_26M) { 835 sf->csd.tran_speed = 26000; /* 26MHz */ 836 hs_timing = 0; 837 } else { 838 aprint_error_dev(sc->sc_dev, 839 "unknown CARD_TYPE: 0x%x\n", 840 ext_csd[EXT_CSD_CARD_TYPE]); 841 return ENOTSUP; 842 } 843 844 if (!ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 845 hs_timing = 0; 846 } 847 if (hs_timing) { 848 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 849 EXT_CSD_HS_TIMING, hs_timing); 850 if (error) { 851 aprint_error_dev(sc->sc_dev, 852 "can't change high speed\n"); 853 return error; 854 } 855 } 856 857 if (sc->sc_busclk > sf->csd.tran_speed) 858 sc->sc_busclk = sf->csd.tran_speed; 859 if (sc->sc_busclk != bus_clock) { 860 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 861 sc->sc_busclk); 862 if (error) { 863 aprint_error_dev(sc->sc_dev, 864 "can't change bus clock\n"); 865 return error; 866 } 867 } 868 869 if (hs_timing) { 870 error = sdmmc_mem_send_cxd_data(sc, 871 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 872 if (error) { 873 aprint_error_dev(sc->sc_dev, 874 "can't re-read EXT_CSD\n"); 875 return error; 876 } 877 if (ext_csd[EXT_CSD_HS_TIMING] != hs_timing) { 878 aprint_error_dev(sc->sc_dev, 879 "HS_TIMING set failed\n"); 880 return EINVAL; 881 } 882 } 883 884 sectors = ext_csd[EXT_CSD_SEC_COUNT + 0] << 0 | 885 ext_csd[EXT_CSD_SEC_COUNT + 1] << 8 | 886 ext_csd[EXT_CSD_SEC_COUNT + 2] << 16 | 887 ext_csd[EXT_CSD_SEC_COUNT + 3] << 24; 888 if (sectors > (2u * 1024 * 1024 * 1024) / 512) { 889 SET(sf->flags, SFF_SDHC); 890 sf->csd.capacity = sectors; 891 } 892 893 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 894 width = 8; 895 value = EXT_CSD_BUS_WIDTH_8; 896 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 897 width = 4; 898 value = EXT_CSD_BUS_WIDTH_4; 899 } else { 900 width = 1; 901 value = EXT_CSD_BUS_WIDTH_1; 902 } 903 904 if (width != 1) { 905 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 906 EXT_CSD_BUS_WIDTH, value); 907 if (error == 0) 908 error = sdmmc_chip_bus_width(sc->sc_sct, 909 sc->sc_sch, width); 910 else { 911 DPRINTF(("%s: can't change bus width" 912 " (%d bit)\n", SDMMCDEVNAME(sc), width)); 913 return error; 914 } 915 916 /* XXXX: need bus test? (using by CMD14 & CMD19) */ 917 } 918 sf->width = width; 919 } else { 920 if (sc->sc_busclk > sf->csd.tran_speed) 921 sc->sc_busclk = sf->csd.tran_speed; 922 if (sc->sc_busclk != bus_clock) { 923 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 924 sc->sc_busclk); 925 if (error) { 926 aprint_error_dev(sc->sc_dev, 927 "can't change bus clock\n"); 928 return error; 929 } 930 } 931 } 932 933 return 0; 934 } 935 936 static int 937 sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp) 938 { 939 struct sdmmc_command cmd; 940 int error; 941 942 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 943 memset(&cmd, 0, sizeof cmd); 944 cmd.c_opcode = MMC_ALL_SEND_CID; 945 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 946 947 error = sdmmc_mmc_command(sc, &cmd); 948 } else { 949 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CID, &cmd.c_resp, 950 sizeof(cmd.c_resp)); 951 } 952 953 #ifdef SDMMC_DEBUG 954 if (error == 0) 955 sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp)); 956 #endif 957 if (error == 0 && resp != NULL) 958 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 959 return error; 960 } 961 962 static int 963 sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf, 964 sdmmc_response *resp) 965 { 966 struct sdmmc_command cmd; 967 int error; 968 969 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 970 memset(&cmd, 0, sizeof cmd); 971 cmd.c_opcode = MMC_SEND_CSD; 972 cmd.c_arg = MMC_ARG_RCA(sf->rca); 973 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 974 975 error = sdmmc_mmc_command(sc, &cmd); 976 } else { 977 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CSD, &cmd.c_resp, 978 sizeof(cmd.c_resp)); 979 } 980 981 #ifdef SDMMC_DEBUG 982 if (error == 0) 983 sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp)); 984 #endif 985 if (error == 0 && resp != NULL) 986 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 987 return error; 988 } 989 990 static int 991 sdmmc_mem_send_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf, 992 uint32_t *scr) 993 { 994 struct sdmmc_command cmd; 995 bus_dma_segment_t ds[1]; 996 void *ptr = NULL; 997 int datalen = 8; 998 int rseg; 999 int error = 0; 1000 1001 /* Don't lock */ 1002 1003 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1004 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, 1005 ds, 1, &rseg, BUS_DMA_NOWAIT); 1006 if (error) 1007 goto out; 1008 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1009 BUS_DMA_NOWAIT); 1010 if (error) 1011 goto dmamem_free; 1012 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1013 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1014 if (error) 1015 goto dmamem_unmap; 1016 1017 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1018 BUS_DMASYNC_PREREAD); 1019 } else { 1020 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1021 if (ptr == NULL) 1022 goto out; 1023 } 1024 1025 memset(&cmd, 0, sizeof(cmd)); 1026 cmd.c_data = ptr; 1027 cmd.c_datalen = datalen; 1028 cmd.c_blklen = datalen; 1029 cmd.c_arg = 0; 1030 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1031 cmd.c_opcode = SD_APP_SEND_SCR; 1032 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1033 cmd.c_dmamap = sc->sc_dmap; 1034 1035 error = sdmmc_app_command(sc, sf, &cmd); 1036 if (error == 0) { 1037 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1038 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1039 BUS_DMASYNC_POSTREAD); 1040 } 1041 memcpy(scr, ptr, datalen); 1042 } 1043 1044 out: 1045 if (ptr != NULL) { 1046 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1047 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1048 dmamem_unmap: 1049 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1050 dmamem_free: 1051 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1052 } else { 1053 free(ptr, M_DEVBUF); 1054 } 1055 } 1056 DPRINTF(("%s: sdmem_mem_send_scr: error = %d\n", SDMMCDEVNAME(sc), 1057 error)); 1058 1059 #ifdef SDMMC_DEBUG 1060 if (error == 0) 1061 sdmmc_dump_data("SCR", scr, datalen); 1062 #endif 1063 return error; 1064 } 1065 1066 static int 1067 sdmmc_mem_decode_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf) 1068 { 1069 sdmmc_response resp; 1070 int ver; 1071 1072 memset(resp, 0, sizeof(resp)); 1073 /* 1074 * Change the raw-scr received from the DMA stream to resp. 1075 */ 1076 resp[0] = be32toh(sf->raw_scr[1]) >> 8; // LSW 1077 resp[1] = be32toh(sf->raw_scr[0]); // MSW 1078 resp[0] |= (resp[1] & 0xff) << 24; 1079 resp[1] >>= 8; 1080 1081 ver = SCR_STRUCTURE(resp); 1082 sf->scr.sd_spec = SCR_SD_SPEC(resp); 1083 sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 1084 1085 DPRINTF(("%s: sdmmc_mem_decode_scr: %08x%08x spec=%d, bus width=%d\n", 1086 SDMMCDEVNAME(sc), resp[1], resp[0], 1087 sf->scr.sd_spec, sf->scr.bus_width)); 1088 1089 if (ver != 0) { 1090 DPRINTF(("%s: unknown structure version: %d\n", 1091 SDMMCDEVNAME(sc), ver)); 1092 return EINVAL; 1093 } 1094 return 0; 1095 } 1096 1097 static int 1098 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 1099 size_t datalen) 1100 { 1101 struct sdmmc_command cmd; 1102 bus_dma_segment_t ds[1]; 1103 void *ptr = NULL; 1104 int rseg; 1105 int error = 0; 1106 1107 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1108 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, ds, 1109 1, &rseg, BUS_DMA_NOWAIT); 1110 if (error) 1111 goto out; 1112 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1113 BUS_DMA_NOWAIT); 1114 if (error) 1115 goto dmamem_free; 1116 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1117 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1118 if (error) 1119 goto dmamem_unmap; 1120 1121 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1122 BUS_DMASYNC_PREREAD); 1123 } else { 1124 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1125 if (ptr == NULL) 1126 goto out; 1127 } 1128 1129 memset(&cmd, 0, sizeof(cmd)); 1130 cmd.c_data = ptr; 1131 cmd.c_datalen = datalen; 1132 cmd.c_blklen = datalen; 1133 cmd.c_opcode = opcode; 1134 cmd.c_arg = 0; 1135 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_SPI_R1; 1136 if (opcode == MMC_SEND_EXT_CSD) 1137 SET(cmd.c_flags, SCF_RSP_R1); 1138 else 1139 SET(cmd.c_flags, SCF_RSP_R2); 1140 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1141 cmd.c_dmamap = sc->sc_dmap; 1142 1143 error = sdmmc_mmc_command(sc, &cmd); 1144 if (error == 0) { 1145 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1146 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1147 BUS_DMASYNC_POSTREAD); 1148 } 1149 memcpy(data, ptr, datalen); 1150 #ifdef SDMMC_DEBUG 1151 sdmmc_dump_data("CXD", data, datalen); 1152 #endif 1153 } 1154 1155 out: 1156 if (ptr != NULL) { 1157 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1158 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1159 dmamem_unmap: 1160 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1161 dmamem_free: 1162 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1163 } else { 1164 free(ptr, M_DEVBUF); 1165 } 1166 } 1167 return error; 1168 } 1169 1170 static int 1171 sdmmc_set_bus_width(struct sdmmc_function *sf, int width) 1172 { 1173 struct sdmmc_softc *sc = sf->sc; 1174 struct sdmmc_command cmd; 1175 int error; 1176 1177 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1178 return ENODEV; 1179 1180 memset(&cmd, 0, sizeof(cmd)); 1181 cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 1182 cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 1183 1184 switch (width) { 1185 case 1: 1186 cmd.c_arg = SD_ARG_BUS_WIDTH_1; 1187 break; 1188 1189 case 4: 1190 cmd.c_arg = SD_ARG_BUS_WIDTH_4; 1191 break; 1192 1193 default: 1194 return EINVAL; 1195 } 1196 1197 error = sdmmc_app_command(sc, sf, &cmd); 1198 if (error == 0) 1199 error = sdmmc_chip_bus_width(sc->sc_sct, sc->sc_sch, width); 1200 return error; 1201 } 1202 1203 static int 1204 sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 1205 int function, sdmmc_bitfield512_t *status) 1206 { 1207 struct sdmmc_softc *sc = sf->sc; 1208 struct sdmmc_command cmd; 1209 bus_dma_segment_t ds[1]; 1210 void *ptr = NULL; 1211 int gsft, rseg, error = 0; 1212 const int statlen = 64; 1213 1214 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 1215 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 1216 return EINVAL; 1217 1218 if (group <= 0 || group > 6 || 1219 function < 0 || function > 15) 1220 return EINVAL; 1221 1222 gsft = (group - 1) << 2; 1223 1224 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1225 error = bus_dmamem_alloc(sc->sc_dmat, statlen, PAGE_SIZE, 0, ds, 1226 1, &rseg, BUS_DMA_NOWAIT); 1227 if (error) 1228 goto out; 1229 error = bus_dmamem_map(sc->sc_dmat, ds, 1, statlen, &ptr, 1230 BUS_DMA_NOWAIT); 1231 if (error) 1232 goto dmamem_free; 1233 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, statlen, 1234 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1235 if (error) 1236 goto dmamem_unmap; 1237 1238 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1239 BUS_DMASYNC_PREREAD); 1240 } else { 1241 ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 1242 if (ptr == NULL) 1243 goto out; 1244 } 1245 1246 memset(&cmd, 0, sizeof(cmd)); 1247 cmd.c_data = ptr; 1248 cmd.c_datalen = statlen; 1249 cmd.c_blklen = statlen; 1250 cmd.c_opcode = SD_SEND_SWITCH_FUNC; 1251 cmd.c_arg = 1252 (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 1253 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1254 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1255 cmd.c_dmamap = sc->sc_dmap; 1256 1257 error = sdmmc_mmc_command(sc, &cmd); 1258 if (error == 0) { 1259 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1260 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1261 BUS_DMASYNC_POSTREAD); 1262 } 1263 memcpy(status, ptr, statlen); 1264 } 1265 1266 out: 1267 if (ptr != NULL) { 1268 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1269 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1270 dmamem_unmap: 1271 bus_dmamem_unmap(sc->sc_dmat, ptr, statlen); 1272 dmamem_free: 1273 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1274 } else { 1275 free(ptr, M_DEVBUF); 1276 } 1277 } 1278 1279 if (error == 0) 1280 sdmmc_be512_to_bitfield512(status); 1281 1282 return error; 1283 } 1284 1285 static int 1286 sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 1287 uint8_t value) 1288 { 1289 struct sdmmc_softc *sc = sf->sc; 1290 struct sdmmc_command cmd; 1291 1292 memset(&cmd, 0, sizeof(cmd)); 1293 cmd.c_opcode = MMC_SWITCH; 1294 cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 1295 (index << 16) | (value << 8) | set; 1296 cmd.c_flags = SCF_RSP_SPI_R1B | SCF_RSP_R1B | SCF_CMD_AC; 1297 1298 return sdmmc_mmc_command(sc, &cmd); 1299 } 1300 1301 /* 1302 * SPI mode function 1303 */ 1304 static int 1305 sdmmc_mem_spi_read_ocr(struct sdmmc_softc *sc, uint32_t hcs, uint32_t *card_ocr) 1306 { 1307 struct sdmmc_command cmd; 1308 int error; 1309 1310 memset(&cmd, 0, sizeof(cmd)); 1311 cmd.c_opcode = MMC_READ_OCR; 1312 cmd.c_arg = hcs ? MMC_OCR_HCS : 0; 1313 cmd.c_flags = SCF_RSP_SPI_R3; 1314 1315 error = sdmmc_mmc_command(sc, &cmd); 1316 if (error == 0 && card_ocr != NULL) 1317 *card_ocr = cmd.c_resp[1]; 1318 DPRINTF(("%s: sdmmc_mem_spi_read_ocr: error=%d, ocr=%#x\n", 1319 SDMMCDEVNAME(sc), error, cmd.c_resp[1])); 1320 return error; 1321 } 1322 1323 /* 1324 * read/write function 1325 */ 1326 /* read */ 1327 static int 1328 sdmmc_mem_single_read_block(struct sdmmc_function *sf, uint32_t blkno, 1329 u_char *data, size_t datalen) 1330 { 1331 struct sdmmc_softc *sc = sf->sc; 1332 int error = 0; 1333 int i; 1334 1335 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1336 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1337 1338 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1339 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno + i, 1340 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1341 if (error) 1342 break; 1343 } 1344 return error; 1345 } 1346 1347 /* 1348 * Simulate multi-segment dma transfer. 1349 */ 1350 static int 1351 sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *sf, 1352 uint32_t blkno, u_char *data, size_t datalen) 1353 { 1354 struct sdmmc_softc *sc = sf->sc; 1355 bool use_bbuf = false; 1356 int error = 0; 1357 int i; 1358 1359 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1360 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1361 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1362 use_bbuf = true; 1363 break; 1364 } 1365 } 1366 if (use_bbuf) { 1367 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1368 BUS_DMASYNC_PREREAD); 1369 1370 error = sdmmc_mem_read_block_subr(sf, sf->bbuf_dmap, 1371 blkno, data, datalen); 1372 if (error) { 1373 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1374 return error; 1375 } 1376 1377 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1378 BUS_DMASYNC_POSTREAD); 1379 1380 /* Copy from bounce buffer */ 1381 memcpy(data, sf->bbuf, datalen); 1382 1383 return 0; 1384 } 1385 1386 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1387 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1388 1389 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1390 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_READ); 1391 if (error) 1392 return error; 1393 1394 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1395 BUS_DMASYNC_PREREAD); 1396 1397 error = sdmmc_mem_read_block_subr(sf, sf->sseg_dmap, 1398 blkno, data, len); 1399 if (error) { 1400 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1401 return error; 1402 } 1403 1404 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1405 BUS_DMASYNC_POSTREAD); 1406 1407 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1408 1409 blkno += len / SDMMC_SECTOR_SIZE; 1410 data += len; 1411 } 1412 return 0; 1413 } 1414 1415 static int 1416 sdmmc_mem_read_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1417 uint32_t blkno, u_char *data, size_t datalen) 1418 { 1419 struct sdmmc_softc *sc = sf->sc; 1420 struct sdmmc_command cmd; 1421 int error; 1422 1423 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1424 error = sdmmc_select_card(sc, sf); 1425 if (error) 1426 goto out; 1427 } 1428 1429 memset(&cmd, 0, sizeof(cmd)); 1430 cmd.c_data = data; 1431 cmd.c_datalen = datalen; 1432 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1433 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1434 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1435 cmd.c_arg = blkno; 1436 if (!ISSET(sf->flags, SFF_SDHC)) 1437 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1438 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1439 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1440 cmd.c_dmamap = dmap; 1441 1442 error = sdmmc_mmc_command(sc, &cmd); 1443 if (error) 1444 goto out; 1445 1446 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1447 if (cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 1448 memset(&cmd, 0, sizeof cmd); 1449 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1450 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1451 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1452 error = sdmmc_mmc_command(sc, &cmd); 1453 if (error) 1454 goto out; 1455 } 1456 } 1457 1458 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1459 do { 1460 memset(&cmd, 0, sizeof(cmd)); 1461 cmd.c_opcode = MMC_SEND_STATUS; 1462 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1463 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1464 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1465 error = sdmmc_mmc_command(sc, &cmd); 1466 if (error) 1467 break; 1468 /* XXX time out */ 1469 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1470 } 1471 1472 out: 1473 return error; 1474 } 1475 1476 int 1477 sdmmc_mem_read_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1478 size_t datalen) 1479 { 1480 struct sdmmc_softc *sc = sf->sc; 1481 int error; 1482 1483 SDMMC_LOCK(sc); 1484 1485 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1486 error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 1487 goto out; 1488 } 1489 1490 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1491 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1492 datalen); 1493 goto out; 1494 } 1495 1496 /* DMA transfer */ 1497 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1498 BUS_DMA_NOWAIT|BUS_DMA_READ); 1499 if (error) 1500 goto out; 1501 1502 #ifdef SDMMC_DEBUG 1503 printf("data=%p, datalen=%zu\n", data, datalen); 1504 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1505 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1506 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1507 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1508 } 1509 #endif 1510 1511 if (sc->sc_dmap->dm_nsegs > 1 1512 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1513 error = sdmmc_mem_single_segment_dma_read_block(sf, blkno, 1514 data, datalen); 1515 goto unload; 1516 } 1517 1518 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1519 BUS_DMASYNC_PREREAD); 1520 1521 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1522 datalen); 1523 if (error) 1524 goto unload; 1525 1526 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1527 BUS_DMASYNC_POSTREAD); 1528 unload: 1529 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1530 1531 out: 1532 SDMMC_UNLOCK(sc); 1533 1534 return error; 1535 } 1536 1537 /* write */ 1538 static int 1539 sdmmc_mem_single_write_block(struct sdmmc_function *sf, uint32_t blkno, 1540 u_char *data, size_t datalen) 1541 { 1542 struct sdmmc_softc *sc = sf->sc; 1543 int error = 0; 1544 int i; 1545 1546 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1547 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1548 1549 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1550 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno + i, 1551 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1552 if (error) 1553 break; 1554 } 1555 return error; 1556 } 1557 1558 /* 1559 * Simulate multi-segment dma transfer. 1560 */ 1561 static int 1562 sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *sf, 1563 uint32_t blkno, u_char *data, size_t datalen) 1564 { 1565 struct sdmmc_softc *sc = sf->sc; 1566 bool use_bbuf = false; 1567 int error = 0; 1568 int i; 1569 1570 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1571 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1572 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1573 use_bbuf = true; 1574 break; 1575 } 1576 } 1577 if (use_bbuf) { 1578 /* Copy to bounce buffer */ 1579 memcpy(sf->bbuf, data, datalen); 1580 1581 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1582 BUS_DMASYNC_PREWRITE); 1583 1584 error = sdmmc_mem_write_block_subr(sf, sf->bbuf_dmap, 1585 blkno, data, datalen); 1586 if (error) { 1587 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1588 return error; 1589 } 1590 1591 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1592 BUS_DMASYNC_POSTWRITE); 1593 1594 return 0; 1595 } 1596 1597 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1598 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1599 1600 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1601 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1602 if (error) 1603 return error; 1604 1605 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1606 BUS_DMASYNC_PREWRITE); 1607 1608 error = sdmmc_mem_write_block_subr(sf, sf->sseg_dmap, 1609 blkno, data, len); 1610 if (error) { 1611 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1612 return error; 1613 } 1614 1615 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1616 BUS_DMASYNC_POSTWRITE); 1617 1618 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1619 1620 blkno += len / SDMMC_SECTOR_SIZE; 1621 data += len; 1622 } 1623 1624 return error; 1625 } 1626 1627 static int 1628 sdmmc_mem_write_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1629 uint32_t blkno, u_char *data, size_t datalen) 1630 { 1631 struct sdmmc_softc *sc = sf->sc; 1632 struct sdmmc_command cmd; 1633 int error; 1634 1635 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1636 error = sdmmc_select_card(sc, sf); 1637 if (error) 1638 goto out; 1639 } 1640 1641 memset(&cmd, 0, sizeof(cmd)); 1642 cmd.c_data = data; 1643 cmd.c_datalen = datalen; 1644 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1645 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1646 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1647 cmd.c_arg = blkno; 1648 if (!ISSET(sf->flags, SFF_SDHC)) 1649 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1650 cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 1651 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1652 cmd.c_dmamap = dmap; 1653 1654 error = sdmmc_mmc_command(sc, &cmd); 1655 if (error) 1656 goto out; 1657 1658 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1659 if (cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1660 memset(&cmd, 0, sizeof(cmd)); 1661 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1662 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1663 error = sdmmc_mmc_command(sc, &cmd); 1664 if (error) 1665 goto out; 1666 } 1667 } 1668 1669 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1670 do { 1671 memset(&cmd, 0, sizeof(cmd)); 1672 cmd.c_opcode = MMC_SEND_STATUS; 1673 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1674 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1675 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1676 error = sdmmc_mmc_command(sc, &cmd); 1677 if (error) 1678 break; 1679 /* XXX time out */ 1680 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1681 } 1682 1683 out: 1684 return error; 1685 } 1686 1687 int 1688 sdmmc_mem_write_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1689 size_t datalen) 1690 { 1691 struct sdmmc_softc *sc = sf->sc; 1692 int error; 1693 1694 SDMMC_LOCK(sc); 1695 1696 if (sdmmc_chip_write_protect(sc->sc_sct, sc->sc_sch)) { 1697 aprint_normal_dev(sc->sc_dev, "write-protected\n"); 1698 error = EIO; 1699 goto out; 1700 } 1701 1702 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1703 error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1704 goto out; 1705 } 1706 1707 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1708 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1709 datalen); 1710 goto out; 1711 } 1712 1713 /* DMA transfer */ 1714 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1715 BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1716 if (error) 1717 goto out; 1718 1719 #ifdef SDMMC_DEBUG 1720 aprint_normal_dev(sc->sc_dev, "%s: data=%p, datalen=%zu\n", 1721 __func__, data, datalen); 1722 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1723 aprint_normal_dev(sc->sc_dev, 1724 "%s: seg#%d: addr=%#lx, size=%#lx\n", __func__, i, 1725 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1726 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1727 } 1728 #endif 1729 1730 if (sc->sc_dmap->dm_nsegs > 1 1731 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1732 error = sdmmc_mem_single_segment_dma_write_block(sf, blkno, 1733 data, datalen); 1734 goto unload; 1735 } 1736 1737 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1738 BUS_DMASYNC_PREWRITE); 1739 1740 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1741 datalen); 1742 if (error) 1743 goto unload; 1744 1745 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1746 BUS_DMASYNC_POSTWRITE); 1747 unload: 1748 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1749 1750 out: 1751 SDMMC_UNLOCK(sc); 1752 1753 return error; 1754 } 1755
Indexes created Wed Sep 24 15:09:51 GMT 2025