sdmmc_mem.c revision 1.38
1 /* $NetBSD: sdmmc_mem.c,v 1.38 2015/08/03 05:32:50 mlelstv Exp $ */ 2 /* $OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2007, 2008, 2009, 2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 /* Routines for SD/MMC memory cards. */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.38 2015/08/03 05:32:50 mlelstv Exp $"); 49 50 #ifdef _KERNEL_OPT 51 #include "opt_sdmmc.h" 52 #endif 53 54 #include <sys/param.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 60 #include <dev/sdmmc/sdmmcchip.h> 61 #include <dev/sdmmc/sdmmcreg.h> 62 #include <dev/sdmmc/sdmmcvar.h> 63 64 #ifdef SDMMC_DEBUG 65 #define DPRINTF(s) do { printf s; } while (/*CONSTCOND*/0) 66 #else 67 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 68 #endif 69 70 typedef struct { uint32_t _bits[512/32]; } __packed __aligned(4) sdmmc_bitfield512_t; 71 72 static int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 73 static int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 74 static int sdmmc_mem_send_cid(struct sdmmc_softc *, sdmmc_response *); 75 static int sdmmc_mem_send_csd(struct sdmmc_softc *, struct sdmmc_function *, 76 sdmmc_response *); 77 static int sdmmc_mem_send_scr(struct sdmmc_softc *, struct sdmmc_function *, 78 uint32_t *scr); 79 static int sdmmc_mem_decode_scr(struct sdmmc_softc *, struct sdmmc_function *); 80 static int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 81 static int sdmmc_set_bus_width(struct sdmmc_function *, int); 82 static int sdmmc_mem_sd_switch(struct sdmmc_function *, int, int, int, sdmmc_bitfield512_t *); 83 static int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, 84 uint8_t); 85 static int sdmmc_mem_spi_read_ocr(struct sdmmc_softc *, uint32_t, uint32_t *); 86 static int sdmmc_mem_single_read_block(struct sdmmc_function *, uint32_t, 87 u_char *, size_t); 88 static int sdmmc_mem_single_write_block(struct sdmmc_function *, uint32_t, 89 u_char *, size_t); 90 static int sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *, 91 uint32_t, u_char *, size_t); 92 static int sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *, 93 uint32_t, u_char *, size_t); 94 static int sdmmc_mem_read_block_subr(struct sdmmc_function *, bus_dmamap_t, 95 uint32_t, u_char *, size_t); 96 static int sdmmc_mem_write_block_subr(struct sdmmc_function *, bus_dmamap_t, 97 uint32_t, u_char *, size_t); 98 99 /* 100 * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 101 */ 102 int 103 sdmmc_mem_enable(struct sdmmc_softc *sc) 104 { 105 uint32_t host_ocr; 106 uint32_t card_ocr; 107 uint32_t new_ocr; 108 uint32_t ocr = 0; 109 int error; 110 111 SDMMC_LOCK(sc); 112 113 /* Set host mode to SD "combo" card or SD memory-only. */ 114 SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 115 116 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 117 sdmmc_spi_chip_initialize(sc->sc_spi_sct, sc->sc_sch); 118 119 /* Reset memory (*must* do that before CMD55 or CMD1). */ 120 sdmmc_go_idle_state(sc); 121 122 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 123 /* Check SD Ver.2 */ 124 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 125 if (error == 0 && card_ocr == 0x1aa) 126 SET(ocr, MMC_OCR_HCS); 127 } 128 129 /* 130 * Read the SD/MMC memory OCR value by issuing CMD55 followed 131 * by ACMD41 to read the OCR value from memory-only SD cards. 132 * MMC cards will not respond to CMD55 or ACMD41 and this is 133 * how we distinguish them from SD cards. 134 */ 135 mmc_mode: 136 error = sdmmc_mem_send_op_cond(sc, 137 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr); 138 if (error) { 139 if (ISSET(sc->sc_flags, SMF_SD_MODE) && 140 !ISSET(sc->sc_flags, SMF_IO_MODE)) { 141 /* Not a SD card, switch to MMC mode. */ 142 DPRINTF(("%s: switch to MMC mode\n", SDMMCDEVNAME(sc))); 143 CLR(sc->sc_flags, SMF_SD_MODE); 144 goto mmc_mode; 145 } 146 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 147 DPRINTF(("%s: couldn't read memory OCR\n", 148 SDMMCDEVNAME(sc))); 149 goto out; 150 } else { 151 /* Not a "combo" card. */ 152 CLR(sc->sc_flags, SMF_MEM_MODE); 153 error = 0; 154 goto out; 155 } 156 } 157 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 158 /* get card OCR */ 159 error = sdmmc_mem_spi_read_ocr(sc, ocr, &card_ocr); 160 if (error) { 161 DPRINTF(("%s: couldn't read SPI memory OCR\n", 162 SDMMCDEVNAME(sc))); 163 goto out; 164 } 165 } 166 167 /* Set the lowest voltage supported by the card and host. */ 168 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 169 error = sdmmc_set_bus_power(sc, host_ocr, card_ocr); 170 if (error) { 171 DPRINTF(("%s: couldn't supply voltage requested by card\n", 172 SDMMCDEVNAME(sc))); 173 goto out; 174 } 175 176 /* Tell the card(s) to enter the idle state (again). */ 177 sdmmc_go_idle_state(sc); 178 179 DPRINTF(("%s: host_ocr 0x%08x\n", SDMMCDEVNAME(sc), host_ocr)); 180 DPRINTF(("%s: card_ocr 0x%08x\n", SDMMCDEVNAME(sc), card_ocr)); 181 182 host_ocr &= card_ocr; /* only allow the common voltages */ 183 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 184 /* Check SD Ver.2 */ 185 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 186 if (error == 0 && card_ocr == 0x1aa) 187 SET(ocr, MMC_OCR_HCS); 188 189 if (sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch) & MMC_OCR_S18A) 190 SET(ocr, MMC_OCR_S18A); 191 } 192 host_ocr |= ocr; 193 194 /* Send the new OCR value until all cards are ready. */ 195 error = sdmmc_mem_send_op_cond(sc, host_ocr, &new_ocr); 196 if (error) { 197 DPRINTF(("%s: couldn't send memory OCR\n", SDMMCDEVNAME(sc))); 198 goto out; 199 } 200 201 if (ISSET(new_ocr, MMC_OCR_S18A) && sc->sc_sct->signal_voltage) { 202 /* 203 * Card and host support low voltage mode, begin switch 204 * sequence. 205 */ 206 struct sdmmc_command cmd; 207 memset(&cmd, 0, sizeof(cmd)); 208 cmd.c_arg = 0; 209 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 210 cmd.c_opcode = SD_VOLTAGE_SWITCH; 211 error = sdmmc_mmc_command(sc, &cmd); 212 if (error) { 213 DPRINTF(("%s: voltage switch command failed\n", 214 SDMMCDEVNAME(sc))); 215 goto out; 216 } 217 218 delay(1000); 219 220 /* 221 * Stop the clock 222 */ 223 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 224 SDMMC_SDCLK_OFF); 225 if (error) 226 goto out; 227 228 delay(1000); 229 230 /* 231 * Card switch command was successful, update host controller 232 * signal voltage setting. 233 */ 234 error = sdmmc_chip_signal_voltage(sc->sc_sct, 235 sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_180); 236 if (error) 237 goto out; 238 239 delay(5000); 240 241 /* 242 * Switch to SDR12 timing 243 */ 244 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 25000); 245 if (error) 246 goto out; 247 248 delay(1000); 249 250 SET(sc->sc_flags, SMF_UHS_MODE); 251 } 252 253 out: 254 SDMMC_UNLOCK(sc); 255 256 if (error) 257 printf("%s: %s failed with error %d\n", SDMMCDEVNAME(sc), 258 __func__, error); 259 260 return error; 261 } 262 263 /* 264 * Read the CSD and CID from all cards and assign each card a unique 265 * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 266 */ 267 void 268 sdmmc_mem_scan(struct sdmmc_softc *sc) 269 { 270 sdmmc_response resp; 271 struct sdmmc_function *sf; 272 uint16_t next_rca; 273 int error; 274 int retry; 275 276 SDMMC_LOCK(sc); 277 278 /* 279 * CMD2 is a broadcast command understood by SD cards and MMC 280 * cards. All cards begin to respond to the command, but back 281 * off if another card drives the CMD line to a different level. 282 * Only one card will get its entire response through. That 283 * card remains silent once it has been assigned a RCA. 284 */ 285 for (retry = 0; retry < 100; retry++) { 286 error = sdmmc_mem_send_cid(sc, &resp); 287 if (error) { 288 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && 289 error == ETIMEDOUT) { 290 /* No more cards there. */ 291 break; 292 } 293 DPRINTF(("%s: couldn't read CID\n", SDMMCDEVNAME(sc))); 294 break; 295 } 296 297 /* In MMC mode, find the next available RCA. */ 298 next_rca = 1; 299 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 300 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) 301 next_rca++; 302 } 303 304 /* Allocate a sdmmc_function structure. */ 305 sf = sdmmc_function_alloc(sc); 306 sf->rca = next_rca; 307 308 /* 309 * Remember the CID returned in the CMD2 response for 310 * later decoding. 311 */ 312 memcpy(sf->raw_cid, resp, sizeof(sf->raw_cid)); 313 314 /* 315 * Silence the card by assigning it a unique RCA, or 316 * querying it for its RCA in the case of SD. 317 */ 318 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 319 if (sdmmc_set_relative_addr(sc, sf) != 0) { 320 aprint_error_dev(sc->sc_dev, 321 "couldn't set mem RCA\n"); 322 sdmmc_function_free(sf); 323 break; 324 } 325 } 326 327 /* 328 * If this is a memory-only card, the card responding 329 * first becomes an alias for SDIO function 0. 330 */ 331 if (sc->sc_fn0 == NULL) 332 sc->sc_fn0 = sf; 333 334 SIMPLEQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 335 336 /* only one function in SPI mode */ 337 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 338 break; 339 } 340 341 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 342 /* Go to Data Transfer Mode, if possible. */ 343 sdmmc_chip_bus_rod(sc->sc_sct, sc->sc_sch, 0); 344 345 /* 346 * All cards are either inactive or awaiting further commands. 347 * Read the CSDs and decode the raw CID for each card. 348 */ 349 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) { 350 error = sdmmc_mem_send_csd(sc, sf, &resp); 351 if (error) { 352 SET(sf->flags, SFF_ERROR); 353 continue; 354 } 355 356 if (sdmmc_decode_csd(sc, resp, sf) != 0 || 357 sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 358 SET(sf->flags, SFF_ERROR); 359 continue; 360 } 361 362 #ifdef SDMMC_DEBUG 363 printf("%s: CID: ", SDMMCDEVNAME(sc)); 364 sdmmc_print_cid(&sf->cid); 365 #endif 366 } 367 368 SDMMC_UNLOCK(sc); 369 } 370 371 int 372 sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 373 struct sdmmc_function *sf) 374 { 375 /* TRAN_SPEED(2:0): transfer rate exponent */ 376 static const int speed_exponent[8] = { 377 100 * 1, /* 100 Kbits/s */ 378 1 * 1000, /* 1 Mbits/s */ 379 10 * 1000, /* 10 Mbits/s */ 380 100 * 1000, /* 100 Mbits/s */ 381 0, 382 0, 383 0, 384 0, 385 }; 386 /* TRAN_SPEED(6:3): time mantissa */ 387 static const int speed_mantissa[16] = { 388 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 389 }; 390 struct sdmmc_csd *csd = &sf->csd; 391 int e, m; 392 393 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 394 /* 395 * CSD version 1.0 corresponds to SD system 396 * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 397 */ 398 csd->csdver = SD_CSD_CSDVER(resp); 399 switch (csd->csdver) { 400 case SD_CSD_CSDVER_2_0: 401 DPRINTF(("%s: SD Ver.2.0\n", SDMMCDEVNAME(sc))); 402 SET(sf->flags, SFF_SDHC); 403 csd->capacity = SD_CSD_V2_CAPACITY(resp); 404 csd->read_bl_len = SD_CSD_V2_BL_LEN; 405 break; 406 407 case SD_CSD_CSDVER_1_0: 408 DPRINTF(("%s: SD Ver.1.0\n", SDMMCDEVNAME(sc))); 409 csd->capacity = SD_CSD_CAPACITY(resp); 410 csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 411 break; 412 413 default: 414 aprint_error_dev(sc->sc_dev, 415 "unknown SD CSD structure version 0x%x\n", 416 csd->csdver); 417 return 1; 418 } 419 420 csd->mmcver = SD_CSD_MMCVER(resp); 421 csd->write_bl_len = SD_CSD_WRITE_BL_LEN(resp); 422 csd->r2w_factor = SD_CSD_R2W_FACTOR(resp); 423 e = SD_CSD_SPEED_EXP(resp); 424 m = SD_CSD_SPEED_MANT(resp); 425 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 426 csd->ccc = SD_CSD_CCC(resp); 427 } else { 428 csd->csdver = MMC_CSD_CSDVER(resp); 429 if (csd->csdver == MMC_CSD_CSDVER_1_0) { 430 aprint_error_dev(sc->sc_dev, 431 "unknown MMC CSD structure version 0x%x\n", 432 csd->csdver); 433 return 1; 434 } 435 436 csd->mmcver = MMC_CSD_MMCVER(resp); 437 csd->capacity = MMC_CSD_CAPACITY(resp); 438 csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 439 csd->write_bl_len = MMC_CSD_WRITE_BL_LEN(resp); 440 csd->r2w_factor = MMC_CSD_R2W_FACTOR(resp); 441 e = MMC_CSD_TRAN_SPEED_EXP(resp); 442 m = MMC_CSD_TRAN_SPEED_MANT(resp); 443 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 444 } 445 if ((1 << csd->read_bl_len) > SDMMC_SECTOR_SIZE) 446 csd->capacity *= (1 << csd->read_bl_len) / SDMMC_SECTOR_SIZE; 447 448 #ifdef SDMMC_DUMP_CSD 449 sdmmc_print_csd(resp, csd); 450 #endif 451 452 return 0; 453 } 454 455 int 456 sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 457 struct sdmmc_function *sf) 458 { 459 struct sdmmc_cid *cid = &sf->cid; 460 461 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 462 cid->mid = SD_CID_MID(resp); 463 cid->oid = SD_CID_OID(resp); 464 SD_CID_PNM_CPY(resp, cid->pnm); 465 cid->rev = SD_CID_REV(resp); 466 cid->psn = SD_CID_PSN(resp); 467 cid->mdt = SD_CID_MDT(resp); 468 } else { 469 switch(sf->csd.mmcver) { 470 case MMC_CSD_MMCVER_1_0: 471 case MMC_CSD_MMCVER_1_4: 472 cid->mid = MMC_CID_MID_V1(resp); 473 MMC_CID_PNM_V1_CPY(resp, cid->pnm); 474 cid->rev = MMC_CID_REV_V1(resp); 475 cid->psn = MMC_CID_PSN_V1(resp); 476 cid->mdt = MMC_CID_MDT_V1(resp); 477 break; 478 case MMC_CSD_MMCVER_2_0: 479 case MMC_CSD_MMCVER_3_1: 480 case MMC_CSD_MMCVER_4_0: 481 cid->mid = MMC_CID_MID_V2(resp); 482 cid->oid = MMC_CID_OID_V2(resp); 483 MMC_CID_PNM_V2_CPY(resp, cid->pnm); 484 cid->psn = MMC_CID_PSN_V2(resp); 485 break; 486 default: 487 aprint_error_dev(sc->sc_dev, "unknown MMC version %d\n", 488 sf->csd.mmcver); 489 return 1; 490 } 491 } 492 return 0; 493 } 494 495 void 496 sdmmc_print_cid(struct sdmmc_cid *cid) 497 { 498 499 printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 500 " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 501 cid->mdt); 502 } 503 504 #ifdef SDMMC_DUMP_CSD 505 void 506 sdmmc_print_csd(sdmmc_response resp, struct sdmmc_csd *csd) 507 { 508 509 printf("csdver = %d\n", csd->csdver); 510 printf("mmcver = %d\n", csd->mmcver); 511 printf("capacity = 0x%08x\n", csd->capacity); 512 printf("read_bl_len = %d\n", csd->read_bl_len); 513 printf("write_bl_len = %d\n", csd->write_bl_len); 514 printf("r2w_factor = %d\n", csd->r2w_factor); 515 printf("tran_speed = %d\n", csd->tran_speed); 516 printf("ccc = 0x%x\n", csd->ccc); 517 } 518 #endif 519 520 /* 521 * Initialize a SD/MMC memory card. 522 */ 523 int 524 sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 525 { 526 int error = 0; 527 528 SDMMC_LOCK(sc); 529 530 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 531 error = sdmmc_select_card(sc, sf); 532 if (error) 533 goto out; 534 } 535 536 error = sdmmc_mem_set_blocklen(sc, sf, SDMMC_SECTOR_SIZE); 537 if (error) 538 goto out; 539 540 if (ISSET(sc->sc_flags, SMF_SD_MODE)) 541 error = sdmmc_mem_sd_init(sc, sf); 542 else 543 error = sdmmc_mem_mmc_init(sc, sf); 544 545 out: 546 SDMMC_UNLOCK(sc); 547 548 return error; 549 } 550 551 /* 552 * Get or set the card's memory OCR value (SD or MMC). 553 */ 554 int 555 sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 556 { 557 struct sdmmc_command cmd; 558 int error; 559 int retry; 560 561 /* Don't lock */ 562 563 DPRINTF(("%s: sdmmc_mem_send_op_cond: ocr=%#x\n", 564 SDMMCDEVNAME(sc), ocr)); 565 566 /* 567 * If we change the OCR value, retry the command until the OCR 568 * we receive in response has the "CARD BUSY" bit set, meaning 569 * that all cards are ready for identification. 570 */ 571 for (retry = 0; retry < 100; retry++) { 572 memset(&cmd, 0, sizeof(cmd)); 573 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? 574 ocr : (ocr & MMC_OCR_HCS); 575 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3 | SCF_RSP_SPI_R1; 576 577 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 578 cmd.c_opcode = SD_APP_OP_COND; 579 error = sdmmc_app_command(sc, NULL, &cmd); 580 } else { 581 cmd.c_opcode = MMC_SEND_OP_COND; 582 error = sdmmc_mmc_command(sc, &cmd); 583 } 584 if (error) 585 break; 586 587 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 588 if (!ISSET(MMC_SPI_R1(cmd.c_resp), R1_SPI_IDLE)) 589 break; 590 } else { 591 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 592 ocr == 0) 593 break; 594 } 595 596 error = ETIMEDOUT; 597 sdmmc_delay(10000); 598 } 599 if (error == 0 && 600 ocrp != NULL && 601 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 602 *ocrp = MMC_R3(cmd.c_resp); 603 DPRINTF(("%s: sdmmc_mem_send_op_cond: error=%d, ocr=%#x\n", 604 SDMMCDEVNAME(sc), error, MMC_R3(cmd.c_resp))); 605 return error; 606 } 607 608 int 609 sdmmc_mem_send_if_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 610 { 611 struct sdmmc_command cmd; 612 int error; 613 614 /* Don't lock */ 615 616 memset(&cmd, 0, sizeof(cmd)); 617 cmd.c_arg = ocr; 618 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R7 | SCF_RSP_SPI_R7; 619 cmd.c_opcode = SD_SEND_IF_COND; 620 621 error = sdmmc_mmc_command(sc, &cmd); 622 if (error == 0 && ocrp != NULL) { 623 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 624 *ocrp = MMC_SPI_R7(cmd.c_resp); 625 } else { 626 *ocrp = MMC_R7(cmd.c_resp); 627 } 628 DPRINTF(("%s: sdmmc_mem_send_if_cond: error=%d, ocr=%#x\n", 629 SDMMCDEVNAME(sc), error, *ocrp)); 630 } 631 return error; 632 } 633 634 /* 635 * Set the read block length appropriately for this card, according to 636 * the card CSD register value. 637 */ 638 int 639 sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf, 640 int block_len) 641 { 642 struct sdmmc_command cmd; 643 int error; 644 645 /* Don't lock */ 646 647 memset(&cmd, 0, sizeof(cmd)); 648 cmd.c_opcode = MMC_SET_BLOCKLEN; 649 cmd.c_arg = block_len; 650 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1; 651 652 error = sdmmc_mmc_command(sc, &cmd); 653 654 DPRINTF(("%s: sdmmc_mem_set_blocklen: read_bl_len=%d sector_size=%d\n", 655 SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, block_len)); 656 657 return error; 658 } 659 660 /* make 512-bit BE quantity __bitfield()-compatible */ 661 static void 662 sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) { 663 size_t i; 664 uint32_t tmp0, tmp1; 665 const size_t bitswords = __arraycount(buf->_bits); 666 for (i = 0; i < bitswords/2; i++) { 667 tmp0 = buf->_bits[i]; 668 tmp1 = buf->_bits[bitswords - 1 - i]; 669 buf->_bits[i] = be32toh(tmp1); 670 buf->_bits[bitswords - 1 - i] = be32toh(tmp0); 671 } 672 } 673 674 static int 675 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 676 { 677 static const struct { 678 int v; 679 int freq; 680 int uhs; 681 } switch_group0_functions[] = { 682 /* Default/SDR12 */ 683 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 684 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 25000, 0 }, 685 686 /* High-Speed/SDR25 */ 687 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 688 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 50000, 0 }, 689 690 /* SDR50 */ 691 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 100000, 1 }, 692 693 /* SDR104 */ 694 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 208000, 1 }, 695 696 #if notyet 697 /* DDR50 */ 698 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 50000, 1 }, 699 #endif 700 }; 701 int host_ocr, support_func, best_func, bus_clock, error, g, i; 702 sdmmc_bitfield512_t status; /* Switch Function Status */ 703 704 /* change bus clock */ 705 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 706 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock); 707 if (error) { 708 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 709 return error; 710 } 711 712 error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr); 713 if (error) { 714 aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n"); 715 return error; 716 } 717 error = sdmmc_mem_decode_scr(sc, sf); 718 if (error) 719 return error; 720 721 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 722 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 723 DPRINTF(("%s: change bus width\n", SDMMCDEVNAME(sc))); 724 error = sdmmc_set_bus_width(sf, 4); 725 if (error) { 726 aprint_error_dev(sc->sc_dev, 727 "can't change bus width (%d bit)\n", 4); 728 return error; 729 } 730 sf->width = 4; 731 } 732 733 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 734 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 735 DPRINTF(("%s: switch func mode 0\n", SDMMCDEVNAME(sc))); 736 error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status); 737 if (error) { 738 aprint_error_dev(sc->sc_dev, 739 "switch func mode 0 failed\n"); 740 return error; 741 } 742 743 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 744 support_func = SFUNC_STATUS_GROUP(&status, 1); 745 DPRINTF(("%s: support_func %#x\n", SDMMCDEVNAME(sc), support_func)); 746 best_func = 0; 747 for (i = 0, g = 1; 748 i < __arraycount(switch_group0_functions); i++, g <<= 1) { 749 if (!(switch_group0_functions[i].v & host_ocr)) 750 continue; 751 if (switch_group0_functions[i].uhs && 752 !ISSET(sc->sc_flags, SMF_UHS_MODE)) 753 break; 754 if (g & support_func) 755 best_func = i; 756 } 757 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) && 758 best_func != 0) { 759 DPRINTF(("%s: switch func mode 1(func=%d)\n", 760 SDMMCDEVNAME(sc), best_func)); 761 error = 762 sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status); 763 if (error) { 764 aprint_error_dev(sc->sc_dev, 765 "switch func mode 1 failed:" 766 " group 1 function %d(0x%2x)\n", 767 best_func, support_func); 768 return error; 769 } 770 sf->csd.tran_speed = 771 switch_group0_functions[best_func].freq; 772 773 /* Wait 400KHz x 8 clock (2.5us * 8 + slop) */ 774 delay(25); 775 } 776 } 777 778 /* update bus clock */ 779 if (sc->sc_busclk > sf->csd.tran_speed) 780 sc->sc_busclk = sf->csd.tran_speed; 781 if (sc->sc_busclk == bus_clock) 782 return 0; 783 784 /* change bus clock */ 785 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk); 786 if (error) { 787 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 788 return error; 789 } 790 791 return 0; 792 } 793 794 static int 795 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 796 { 797 int width, value, hs_timing, bus_clock, error; 798 char ext_csd[512]; 799 uint32_t sectors = 0; 800 int host_ocr; 801 802 /* change bus clock */ 803 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 804 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock); 805 if (error) { 806 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 807 return error; 808 } 809 810 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 811 812 if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 813 error = sdmmc_mem_send_cxd_data(sc, 814 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 815 if (error) { 816 aprint_error_dev(sc->sc_dev, 817 "can't read EXT_CSD (error=%d)\n", error); 818 return error; 819 } 820 if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) && 821 (ext_csd[EXT_CSD_STRUCTURE] > EXT_CSD_STRUCTURE_VER_1_2)) { 822 aprint_error_dev(sc->sc_dev, 823 "unrecognised future version (%d)\n", 824 ext_csd[EXT_CSD_STRUCTURE]); 825 return ENOTSUP; 826 } 827 828 if (ISSET(host_ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V) && 829 ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_HS200_1_8V) { 830 sf->csd.tran_speed = 200000; /* 200MHz SDR */ 831 hs_timing = 2; 832 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_52M) { 833 sf->csd.tran_speed = 52000; /* 52MHz */ 834 hs_timing = 1; 835 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_26M) { 836 sf->csd.tran_speed = 26000; /* 26MHz */ 837 hs_timing = 0; 838 } else { 839 aprint_error_dev(sc->sc_dev, 840 "unknown CARD_TYPE: 0x%x\n", 841 ext_csd[EXT_CSD_CARD_TYPE]); 842 return ENOTSUP; 843 } 844 845 if (!ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 846 hs_timing = 0; 847 } 848 if (hs_timing) { 849 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 850 EXT_CSD_HS_TIMING, hs_timing); 851 if (error) { 852 aprint_error_dev(sc->sc_dev, 853 "can't change high speed\n"); 854 return error; 855 } 856 } 857 858 if (sc->sc_busclk > sf->csd.tran_speed) 859 sc->sc_busclk = sf->csd.tran_speed; 860 if (sc->sc_busclk != bus_clock) { 861 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 862 sc->sc_busclk); 863 if (error) { 864 aprint_error_dev(sc->sc_dev, 865 "can't change bus clock\n"); 866 return error; 867 } 868 } 869 870 if (hs_timing) { 871 error = sdmmc_mem_send_cxd_data(sc, 872 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 873 if (error) { 874 aprint_error_dev(sc->sc_dev, 875 "can't re-read EXT_CSD\n"); 876 return error; 877 } 878 if (ext_csd[EXT_CSD_HS_TIMING] != hs_timing) { 879 aprint_error_dev(sc->sc_dev, 880 "HS_TIMING set failed\n"); 881 return EINVAL; 882 } 883 } 884 885 sectors = ext_csd[EXT_CSD_SEC_COUNT + 0] << 0 | 886 ext_csd[EXT_CSD_SEC_COUNT + 1] << 8 | 887 ext_csd[EXT_CSD_SEC_COUNT + 2] << 16 | 888 ext_csd[EXT_CSD_SEC_COUNT + 3] << 24; 889 if (sectors > (2u * 1024 * 1024 * 1024) / 512) { 890 SET(sf->flags, SFF_SDHC); 891 sf->csd.capacity = sectors; 892 } 893 894 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 895 width = 8; 896 value = EXT_CSD_BUS_WIDTH_8; 897 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 898 width = 4; 899 value = EXT_CSD_BUS_WIDTH_4; 900 } else { 901 width = 1; 902 value = EXT_CSD_BUS_WIDTH_1; 903 } 904 905 if (width != 1) { 906 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 907 EXT_CSD_BUS_WIDTH, value); 908 if (error == 0) 909 error = sdmmc_chip_bus_width(sc->sc_sct, 910 sc->sc_sch, width); 911 else { 912 DPRINTF(("%s: can't change bus width" 913 " (%d bit)\n", SDMMCDEVNAME(sc), width)); 914 return error; 915 } 916 917 /* XXXX: need bus test? (using by CMD14 & CMD19) */ 918 } 919 sf->width = width; 920 } else { 921 if (sc->sc_busclk > sf->csd.tran_speed) 922 sc->sc_busclk = sf->csd.tran_speed; 923 if (sc->sc_busclk != bus_clock) { 924 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 925 sc->sc_busclk); 926 if (error) { 927 aprint_error_dev(sc->sc_dev, 928 "can't change bus clock\n"); 929 return error; 930 } 931 } 932 } 933 934 return 0; 935 } 936 937 static int 938 sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp) 939 { 940 struct sdmmc_command cmd; 941 int error; 942 943 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 944 memset(&cmd, 0, sizeof cmd); 945 cmd.c_opcode = MMC_ALL_SEND_CID; 946 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 947 948 error = sdmmc_mmc_command(sc, &cmd); 949 } else { 950 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CID, &cmd.c_resp, 951 sizeof(cmd.c_resp)); 952 } 953 954 #ifdef SDMMC_DEBUG 955 if (error == 0) 956 sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp)); 957 #endif 958 if (error == 0 && resp != NULL) 959 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 960 return error; 961 } 962 963 static int 964 sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf, 965 sdmmc_response *resp) 966 { 967 struct sdmmc_command cmd; 968 int error; 969 970 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 971 memset(&cmd, 0, sizeof cmd); 972 cmd.c_opcode = MMC_SEND_CSD; 973 cmd.c_arg = MMC_ARG_RCA(sf->rca); 974 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 975 976 error = sdmmc_mmc_command(sc, &cmd); 977 } else { 978 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CSD, &cmd.c_resp, 979 sizeof(cmd.c_resp)); 980 } 981 982 #ifdef SDMMC_DEBUG 983 if (error == 0) 984 sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp)); 985 #endif 986 if (error == 0 && resp != NULL) 987 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 988 return error; 989 } 990 991 static int 992 sdmmc_mem_send_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf, 993 uint32_t *scr) 994 { 995 struct sdmmc_command cmd; 996 bus_dma_segment_t ds[1]; 997 void *ptr = NULL; 998 int datalen = 8; 999 int rseg; 1000 int error = 0; 1001 1002 /* Don't lock */ 1003 1004 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1005 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, 1006 ds, 1, &rseg, BUS_DMA_NOWAIT); 1007 if (error) 1008 goto out; 1009 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1010 BUS_DMA_NOWAIT); 1011 if (error) 1012 goto dmamem_free; 1013 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1014 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1015 if (error) 1016 goto dmamem_unmap; 1017 1018 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1019 BUS_DMASYNC_PREREAD); 1020 } else { 1021 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1022 if (ptr == NULL) 1023 goto out; 1024 } 1025 1026 memset(&cmd, 0, sizeof(cmd)); 1027 cmd.c_data = ptr; 1028 cmd.c_datalen = datalen; 1029 cmd.c_blklen = datalen; 1030 cmd.c_arg = 0; 1031 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1032 cmd.c_opcode = SD_APP_SEND_SCR; 1033 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1034 cmd.c_dmamap = sc->sc_dmap; 1035 1036 error = sdmmc_app_command(sc, sf, &cmd); 1037 if (error == 0) { 1038 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1039 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1040 BUS_DMASYNC_POSTREAD); 1041 } 1042 memcpy(scr, ptr, datalen); 1043 } 1044 1045 out: 1046 if (ptr != NULL) { 1047 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1048 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1049 dmamem_unmap: 1050 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1051 dmamem_free: 1052 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1053 } else { 1054 free(ptr, M_DEVBUF); 1055 } 1056 } 1057 DPRINTF(("%s: sdmem_mem_send_scr: error = %d\n", SDMMCDEVNAME(sc), 1058 error)); 1059 1060 #ifdef SDMMC_DEBUG 1061 if (error == 0) 1062 sdmmc_dump_data("SCR", scr, datalen); 1063 #endif 1064 return error; 1065 } 1066 1067 static int 1068 sdmmc_mem_decode_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf) 1069 { 1070 sdmmc_response resp; 1071 int ver; 1072 1073 memset(resp, 0, sizeof(resp)); 1074 /* 1075 * Change the raw-scr received from the DMA stream to resp. 1076 */ 1077 resp[0] = be32toh(sf->raw_scr[1]) >> 8; // LSW 1078 resp[1] = be32toh(sf->raw_scr[0]); // MSW 1079 resp[0] |= (resp[1] & 0xff) << 24; 1080 resp[1] >>= 8; 1081 1082 ver = SCR_STRUCTURE(resp); 1083 sf->scr.sd_spec = SCR_SD_SPEC(resp); 1084 sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 1085 1086 DPRINTF(("%s: sdmmc_mem_decode_scr: %08x%08x spec=%d, bus width=%d\n", 1087 SDMMCDEVNAME(sc), resp[1], resp[0], 1088 sf->scr.sd_spec, sf->scr.bus_width)); 1089 1090 if (ver != 0) { 1091 DPRINTF(("%s: unknown structure version: %d\n", 1092 SDMMCDEVNAME(sc), ver)); 1093 return EINVAL; 1094 } 1095 return 0; 1096 } 1097 1098 static int 1099 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 1100 size_t datalen) 1101 { 1102 struct sdmmc_command cmd; 1103 bus_dma_segment_t ds[1]; 1104 void *ptr = NULL; 1105 int rseg; 1106 int error = 0; 1107 1108 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1109 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, ds, 1110 1, &rseg, BUS_DMA_NOWAIT); 1111 if (error) 1112 goto out; 1113 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1114 BUS_DMA_NOWAIT); 1115 if (error) 1116 goto dmamem_free; 1117 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1118 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1119 if (error) 1120 goto dmamem_unmap; 1121 1122 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1123 BUS_DMASYNC_PREREAD); 1124 } else { 1125 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1126 if (ptr == NULL) 1127 goto out; 1128 } 1129 1130 memset(&cmd, 0, sizeof(cmd)); 1131 cmd.c_data = ptr; 1132 cmd.c_datalen = datalen; 1133 cmd.c_blklen = datalen; 1134 cmd.c_opcode = opcode; 1135 cmd.c_arg = 0; 1136 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_SPI_R1; 1137 if (opcode == MMC_SEND_EXT_CSD) 1138 SET(cmd.c_flags, SCF_RSP_R1); 1139 else 1140 SET(cmd.c_flags, SCF_RSP_R2); 1141 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1142 cmd.c_dmamap = sc->sc_dmap; 1143 1144 error = sdmmc_mmc_command(sc, &cmd); 1145 if (error == 0) { 1146 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1147 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1148 BUS_DMASYNC_POSTREAD); 1149 } 1150 memcpy(data, ptr, datalen); 1151 #ifdef SDMMC_DEBUG 1152 sdmmc_dump_data("CXD", data, datalen); 1153 #endif 1154 } 1155 1156 out: 1157 if (ptr != NULL) { 1158 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1159 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1160 dmamem_unmap: 1161 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1162 dmamem_free: 1163 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1164 } else { 1165 free(ptr, M_DEVBUF); 1166 } 1167 } 1168 return error; 1169 } 1170 1171 static int 1172 sdmmc_set_bus_width(struct sdmmc_function *sf, int width) 1173 { 1174 struct sdmmc_softc *sc = sf->sc; 1175 struct sdmmc_command cmd; 1176 int error; 1177 1178 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1179 return ENODEV; 1180 1181 memset(&cmd, 0, sizeof(cmd)); 1182 cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 1183 cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 1184 1185 switch (width) { 1186 case 1: 1187 cmd.c_arg = SD_ARG_BUS_WIDTH_1; 1188 break; 1189 1190 case 4: 1191 cmd.c_arg = SD_ARG_BUS_WIDTH_4; 1192 break; 1193 1194 default: 1195 return EINVAL; 1196 } 1197 1198 error = sdmmc_app_command(sc, sf, &cmd); 1199 if (error == 0) 1200 error = sdmmc_chip_bus_width(sc->sc_sct, sc->sc_sch, width); 1201 return error; 1202 } 1203 1204 static int 1205 sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 1206 int function, sdmmc_bitfield512_t *status) 1207 { 1208 struct sdmmc_softc *sc = sf->sc; 1209 struct sdmmc_command cmd; 1210 bus_dma_segment_t ds[1]; 1211 void *ptr = NULL; 1212 int gsft, rseg, error = 0; 1213 const int statlen = 64; 1214 1215 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 1216 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 1217 return EINVAL; 1218 1219 if (group <= 0 || group > 6 || 1220 function < 0 || function > 15) 1221 return EINVAL; 1222 1223 gsft = (group - 1) << 2; 1224 1225 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1226 error = bus_dmamem_alloc(sc->sc_dmat, statlen, PAGE_SIZE, 0, ds, 1227 1, &rseg, BUS_DMA_NOWAIT); 1228 if (error) 1229 goto out; 1230 error = bus_dmamem_map(sc->sc_dmat, ds, 1, statlen, &ptr, 1231 BUS_DMA_NOWAIT); 1232 if (error) 1233 goto dmamem_free; 1234 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, statlen, 1235 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1236 if (error) 1237 goto dmamem_unmap; 1238 1239 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1240 BUS_DMASYNC_PREREAD); 1241 } else { 1242 ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 1243 if (ptr == NULL) 1244 goto out; 1245 } 1246 1247 memset(&cmd, 0, sizeof(cmd)); 1248 cmd.c_data = ptr; 1249 cmd.c_datalen = statlen; 1250 cmd.c_blklen = statlen; 1251 cmd.c_opcode = SD_SEND_SWITCH_FUNC; 1252 cmd.c_arg = 1253 (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 1254 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1255 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1256 cmd.c_dmamap = sc->sc_dmap; 1257 1258 error = sdmmc_mmc_command(sc, &cmd); 1259 if (error == 0) { 1260 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1261 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1262 BUS_DMASYNC_POSTREAD); 1263 } 1264 memcpy(status, ptr, statlen); 1265 } 1266 1267 out: 1268 if (ptr != NULL) { 1269 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1270 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1271 dmamem_unmap: 1272 bus_dmamem_unmap(sc->sc_dmat, ptr, statlen); 1273 dmamem_free: 1274 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1275 } else { 1276 free(ptr, M_DEVBUF); 1277 } 1278 } 1279 1280 if (error == 0) 1281 sdmmc_be512_to_bitfield512(status); 1282 1283 return error; 1284 } 1285 1286 static int 1287 sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 1288 uint8_t value) 1289 { 1290 struct sdmmc_softc *sc = sf->sc; 1291 struct sdmmc_command cmd; 1292 1293 memset(&cmd, 0, sizeof(cmd)); 1294 cmd.c_opcode = MMC_SWITCH; 1295 cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 1296 (index << 16) | (value << 8) | set; 1297 cmd.c_flags = SCF_RSP_SPI_R1B | SCF_RSP_R1B | SCF_CMD_AC; 1298 1299 return sdmmc_mmc_command(sc, &cmd); 1300 } 1301 1302 /* 1303 * SPI mode function 1304 */ 1305 static int 1306 sdmmc_mem_spi_read_ocr(struct sdmmc_softc *sc, uint32_t hcs, uint32_t *card_ocr) 1307 { 1308 struct sdmmc_command cmd; 1309 int error; 1310 1311 memset(&cmd, 0, sizeof(cmd)); 1312 cmd.c_opcode = MMC_READ_OCR; 1313 cmd.c_arg = hcs ? MMC_OCR_HCS : 0; 1314 cmd.c_flags = SCF_RSP_SPI_R3; 1315 1316 error = sdmmc_mmc_command(sc, &cmd); 1317 if (error == 0 && card_ocr != NULL) 1318 *card_ocr = cmd.c_resp[1]; 1319 DPRINTF(("%s: sdmmc_mem_spi_read_ocr: error=%d, ocr=%#x\n", 1320 SDMMCDEVNAME(sc), error, cmd.c_resp[1])); 1321 return error; 1322 } 1323 1324 /* 1325 * read/write function 1326 */ 1327 /* read */ 1328 static int 1329 sdmmc_mem_single_read_block(struct sdmmc_function *sf, uint32_t blkno, 1330 u_char *data, size_t datalen) 1331 { 1332 struct sdmmc_softc *sc = sf->sc; 1333 int error = 0; 1334 int i; 1335 1336 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1337 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1338 1339 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1340 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno + i, 1341 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1342 if (error) 1343 break; 1344 } 1345 return error; 1346 } 1347 1348 /* 1349 * Simulate multi-segment dma transfer. 1350 */ 1351 static int 1352 sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *sf, 1353 uint32_t blkno, u_char *data, size_t datalen) 1354 { 1355 struct sdmmc_softc *sc = sf->sc; 1356 bool use_bbuf = false; 1357 int error = 0; 1358 int i; 1359 1360 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1361 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1362 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1363 use_bbuf = true; 1364 break; 1365 } 1366 } 1367 if (use_bbuf) { 1368 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1369 BUS_DMASYNC_PREREAD); 1370 1371 error = sdmmc_mem_read_block_subr(sf, sf->bbuf_dmap, 1372 blkno, data, datalen); 1373 if (error) { 1374 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1375 return error; 1376 } 1377 1378 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1379 BUS_DMASYNC_POSTREAD); 1380 1381 /* Copy from bounce buffer */ 1382 memcpy(data, sf->bbuf, datalen); 1383 1384 return 0; 1385 } 1386 1387 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1388 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1389 1390 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1391 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_READ); 1392 if (error) 1393 return error; 1394 1395 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1396 BUS_DMASYNC_PREREAD); 1397 1398 error = sdmmc_mem_read_block_subr(sf, sf->sseg_dmap, 1399 blkno, data, len); 1400 if (error) { 1401 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1402 return error; 1403 } 1404 1405 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1406 BUS_DMASYNC_POSTREAD); 1407 1408 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1409 1410 blkno += len / SDMMC_SECTOR_SIZE; 1411 data += len; 1412 } 1413 return 0; 1414 } 1415 1416 static int 1417 sdmmc_mem_read_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1418 uint32_t blkno, u_char *data, size_t datalen) 1419 { 1420 struct sdmmc_softc *sc = sf->sc; 1421 struct sdmmc_command cmd; 1422 int error; 1423 1424 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1425 error = sdmmc_select_card(sc, sf); 1426 if (error) 1427 goto out; 1428 } 1429 1430 memset(&cmd, 0, sizeof(cmd)); 1431 cmd.c_data = data; 1432 cmd.c_datalen = datalen; 1433 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1434 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1435 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1436 cmd.c_arg = blkno; 1437 if (!ISSET(sf->flags, SFF_SDHC)) 1438 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1439 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1440 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1441 cmd.c_dmamap = dmap; 1442 1443 error = sdmmc_mmc_command(sc, &cmd); 1444 if (error) 1445 goto out; 1446 1447 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1448 if (cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 1449 memset(&cmd, 0, sizeof cmd); 1450 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1451 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1452 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1453 error = sdmmc_mmc_command(sc, &cmd); 1454 if (error) 1455 goto out; 1456 } 1457 } 1458 1459 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1460 do { 1461 memset(&cmd, 0, sizeof(cmd)); 1462 cmd.c_opcode = MMC_SEND_STATUS; 1463 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1464 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1465 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1466 error = sdmmc_mmc_command(sc, &cmd); 1467 if (error) 1468 break; 1469 /* XXX time out */ 1470 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1471 } 1472 1473 out: 1474 return error; 1475 } 1476 1477 int 1478 sdmmc_mem_read_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1479 size_t datalen) 1480 { 1481 struct sdmmc_softc *sc = sf->sc; 1482 int error; 1483 1484 SDMMC_LOCK(sc); 1485 mutex_enter(&sc->sc_mtx); 1486 1487 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1488 error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 1489 goto out; 1490 } 1491 1492 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1493 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1494 datalen); 1495 goto out; 1496 } 1497 1498 /* DMA transfer */ 1499 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1500 BUS_DMA_NOWAIT|BUS_DMA_READ); 1501 if (error) 1502 goto out; 1503 1504 #ifdef SDMMC_DEBUG 1505 printf("data=%p, datalen=%zu\n", data, datalen); 1506 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1507 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1508 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1509 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1510 } 1511 #endif 1512 1513 if (sc->sc_dmap->dm_nsegs > 1 1514 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1515 error = sdmmc_mem_single_segment_dma_read_block(sf, blkno, 1516 data, datalen); 1517 goto unload; 1518 } 1519 1520 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1521 BUS_DMASYNC_PREREAD); 1522 1523 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1524 datalen); 1525 if (error) 1526 goto unload; 1527 1528 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1529 BUS_DMASYNC_POSTREAD); 1530 unload: 1531 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1532 1533 out: 1534 mutex_exit(&sc->sc_mtx); 1535 SDMMC_UNLOCK(sc); 1536 1537 return error; 1538 } 1539 1540 /* write */ 1541 static int 1542 sdmmc_mem_single_write_block(struct sdmmc_function *sf, uint32_t blkno, 1543 u_char *data, size_t datalen) 1544 { 1545 struct sdmmc_softc *sc = sf->sc; 1546 int error = 0; 1547 int i; 1548 1549 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1550 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1551 1552 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1553 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno + i, 1554 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1555 if (error) 1556 break; 1557 } 1558 return error; 1559 } 1560 1561 /* 1562 * Simulate multi-segment dma transfer. 1563 */ 1564 static int 1565 sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *sf, 1566 uint32_t blkno, u_char *data, size_t datalen) 1567 { 1568 struct sdmmc_softc *sc = sf->sc; 1569 bool use_bbuf = false; 1570 int error = 0; 1571 int i; 1572 1573 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1574 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1575 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1576 use_bbuf = true; 1577 break; 1578 } 1579 } 1580 if (use_bbuf) { 1581 /* Copy to bounce buffer */ 1582 memcpy(sf->bbuf, data, datalen); 1583 1584 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1585 BUS_DMASYNC_PREWRITE); 1586 1587 error = sdmmc_mem_write_block_subr(sf, sf->bbuf_dmap, 1588 blkno, data, datalen); 1589 if (error) { 1590 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1591 return error; 1592 } 1593 1594 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1595 BUS_DMASYNC_POSTWRITE); 1596 1597 return 0; 1598 } 1599 1600 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1601 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1602 1603 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1604 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1605 if (error) 1606 return error; 1607 1608 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1609 BUS_DMASYNC_PREWRITE); 1610 1611 error = sdmmc_mem_write_block_subr(sf, sf->sseg_dmap, 1612 blkno, data, len); 1613 if (error) { 1614 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1615 return error; 1616 } 1617 1618 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1619 BUS_DMASYNC_POSTWRITE); 1620 1621 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1622 1623 blkno += len / SDMMC_SECTOR_SIZE; 1624 data += len; 1625 } 1626 1627 return error; 1628 } 1629 1630 static int 1631 sdmmc_mem_write_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1632 uint32_t blkno, u_char *data, size_t datalen) 1633 { 1634 struct sdmmc_softc *sc = sf->sc; 1635 struct sdmmc_command cmd; 1636 int error; 1637 1638 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1639 error = sdmmc_select_card(sc, sf); 1640 if (error) 1641 goto out; 1642 } 1643 1644 memset(&cmd, 0, sizeof(cmd)); 1645 cmd.c_data = data; 1646 cmd.c_datalen = datalen; 1647 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1648 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1649 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1650 cmd.c_arg = blkno; 1651 if (!ISSET(sf->flags, SFF_SDHC)) 1652 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1653 cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 1654 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1655 cmd.c_dmamap = dmap; 1656 1657 error = sdmmc_mmc_command(sc, &cmd); 1658 if (error) 1659 goto out; 1660 1661 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1662 if (cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1663 memset(&cmd, 0, sizeof(cmd)); 1664 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1665 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1666 error = sdmmc_mmc_command(sc, &cmd); 1667 if (error) 1668 goto out; 1669 } 1670 } 1671 1672 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1673 do { 1674 memset(&cmd, 0, sizeof(cmd)); 1675 cmd.c_opcode = MMC_SEND_STATUS; 1676 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1677 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1678 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1679 error = sdmmc_mmc_command(sc, &cmd); 1680 if (error) 1681 break; 1682 /* XXX time out */ 1683 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1684 } 1685 1686 out: 1687 return error; 1688 } 1689 1690 int 1691 sdmmc_mem_write_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1692 size_t datalen) 1693 { 1694 struct sdmmc_softc *sc = sf->sc; 1695 int error; 1696 1697 SDMMC_LOCK(sc); 1698 mutex_enter(&sc->sc_mtx); 1699 1700 if (sdmmc_chip_write_protect(sc->sc_sct, sc->sc_sch)) { 1701 aprint_normal_dev(sc->sc_dev, "write-protected\n"); 1702 error = EIO; 1703 goto out; 1704 } 1705 1706 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1707 error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1708 goto out; 1709 } 1710 1711 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1712 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1713 datalen); 1714 goto out; 1715 } 1716 1717 /* DMA transfer */ 1718 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1719 BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1720 if (error) 1721 goto out; 1722 1723 #ifdef SDMMC_DEBUG 1724 aprint_normal_dev(sc->sc_dev, "%s: data=%p, datalen=%zu\n", 1725 __func__, data, datalen); 1726 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1727 aprint_normal_dev(sc->sc_dev, 1728 "%s: seg#%d: addr=%#lx, size=%#lx\n", __func__, i, 1729 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1730 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1731 } 1732 #endif 1733 1734 if (sc->sc_dmap->dm_nsegs > 1 1735 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1736 error = sdmmc_mem_single_segment_dma_write_block(sf, blkno, 1737 data, datalen); 1738 goto unload; 1739 } 1740 1741 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1742 BUS_DMASYNC_PREWRITE); 1743 1744 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1745 datalen); 1746 if (error) 1747 goto unload; 1748 1749 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1750 BUS_DMASYNC_POSTWRITE); 1751 unload: 1752 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1753 1754 out: 1755 mutex_exit(&sc->sc_mtx); 1756 SDMMC_UNLOCK(sc); 1757 1758 return error; 1759 } 1760
Indexes created Fri Sep 26 20:09:58 GMT 2025