sdmmc_mem.c revision 1.40
1 /* $NetBSD: sdmmc_mem.c,v 1.40 2015/08/03 11:24:17 jmcneill Exp $ */ 2 /* $OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2007, 2008, 2009, 2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 /* Routines for SD/MMC memory cards. */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.40 2015/08/03 11:24:17 jmcneill Exp $"); 49 50 #ifdef _KERNEL_OPT 51 #include "opt_sdmmc.h" 52 #endif 53 54 #include <sys/param.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 60 #include <dev/sdmmc/sdmmcchip.h> 61 #include <dev/sdmmc/sdmmcreg.h> 62 #include <dev/sdmmc/sdmmcvar.h> 63 64 #ifdef SDMMC_DEBUG 65 #define DPRINTF(s) do { printf s; } while (/*CONSTCOND*/0) 66 #else 67 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 68 #endif 69 70 typedef struct { uint32_t _bits[512/32]; } __packed __aligned(4) sdmmc_bitfield512_t; 71 72 static int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 73 static int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 74 static int sdmmc_mem_send_cid(struct sdmmc_softc *, sdmmc_response *); 75 static int sdmmc_mem_send_csd(struct sdmmc_softc *, struct sdmmc_function *, 76 sdmmc_response *); 77 static int sdmmc_mem_send_scr(struct sdmmc_softc *, struct sdmmc_function *, 78 uint32_t *scr); 79 static int sdmmc_mem_decode_scr(struct sdmmc_softc *, struct sdmmc_function *); 80 static int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 81 static int sdmmc_set_bus_width(struct sdmmc_function *, int); 82 static int sdmmc_mem_sd_switch(struct sdmmc_function *, int, int, int, sdmmc_bitfield512_t *); 83 static int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, 84 uint8_t); 85 static int sdmmc_mem_spi_read_ocr(struct sdmmc_softc *, uint32_t, uint32_t *); 86 static int sdmmc_mem_single_read_block(struct sdmmc_function *, uint32_t, 87 u_char *, size_t); 88 static int sdmmc_mem_single_write_block(struct sdmmc_function *, uint32_t, 89 u_char *, size_t); 90 static int sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *, 91 uint32_t, u_char *, size_t); 92 static int sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *, 93 uint32_t, u_char *, size_t); 94 static int sdmmc_mem_read_block_subr(struct sdmmc_function *, bus_dmamap_t, 95 uint32_t, u_char *, size_t); 96 static int sdmmc_mem_write_block_subr(struct sdmmc_function *, bus_dmamap_t, 97 uint32_t, u_char *, size_t); 98 99 static const struct { 100 const char *name; 101 int v; 102 int freq; 103 } switch_group0_functions[] = { 104 /* Default/SDR12 */ 105 { "Default/SDR12", 0, 25000 }, 106 107 /* High-Speed/SDR25 */ 108 { "High-Speed/SDR25", SMC_CAPS_SD_HIGHSPEED, 50000 }, 109 110 /* SDR50 */ 111 { "SDR50", SMC_CAPS_UHS_SDR50, 100000 }, 112 113 /* SDR104 */ 114 { "SDR104", SMC_CAPS_UHS_SDR104, 208000 }, 115 116 /* DDR50 */ 117 { "DDR50", SMC_CAPS_UHS_DDR50, 50000 }, 118 }; 119 120 /* 121 * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 122 */ 123 int 124 sdmmc_mem_enable(struct sdmmc_softc *sc) 125 { 126 uint32_t host_ocr; 127 uint32_t card_ocr; 128 uint32_t new_ocr; 129 uint32_t ocr = 0; 130 int error; 131 132 SDMMC_LOCK(sc); 133 134 /* Set host mode to SD "combo" card or SD memory-only. */ 135 SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 136 137 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 138 sdmmc_spi_chip_initialize(sc->sc_spi_sct, sc->sc_sch); 139 140 /* Reset memory (*must* do that before CMD55 or CMD1). */ 141 sdmmc_go_idle_state(sc); 142 143 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 144 /* Check SD Ver.2 */ 145 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 146 if (error == 0 && card_ocr == 0x1aa) 147 SET(ocr, MMC_OCR_HCS); 148 } 149 150 /* 151 * Read the SD/MMC memory OCR value by issuing CMD55 followed 152 * by ACMD41 to read the OCR value from memory-only SD cards. 153 * MMC cards will not respond to CMD55 or ACMD41 and this is 154 * how we distinguish them from SD cards. 155 */ 156 mmc_mode: 157 error = sdmmc_mem_send_op_cond(sc, 158 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr); 159 if (error) { 160 if (ISSET(sc->sc_flags, SMF_SD_MODE) && 161 !ISSET(sc->sc_flags, SMF_IO_MODE)) { 162 /* Not a SD card, switch to MMC mode. */ 163 DPRINTF(("%s: switch to MMC mode\n", SDMMCDEVNAME(sc))); 164 CLR(sc->sc_flags, SMF_SD_MODE); 165 goto mmc_mode; 166 } 167 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 168 DPRINTF(("%s: couldn't read memory OCR\n", 169 SDMMCDEVNAME(sc))); 170 goto out; 171 } else { 172 /* Not a "combo" card. */ 173 CLR(sc->sc_flags, SMF_MEM_MODE); 174 error = 0; 175 goto out; 176 } 177 } 178 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 179 /* get card OCR */ 180 error = sdmmc_mem_spi_read_ocr(sc, ocr, &card_ocr); 181 if (error) { 182 DPRINTF(("%s: couldn't read SPI memory OCR\n", 183 SDMMCDEVNAME(sc))); 184 goto out; 185 } 186 } 187 188 /* Set the lowest voltage supported by the card and host. */ 189 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 190 error = sdmmc_set_bus_power(sc, host_ocr, card_ocr); 191 if (error) { 192 DPRINTF(("%s: couldn't supply voltage requested by card\n", 193 SDMMCDEVNAME(sc))); 194 goto out; 195 } 196 197 /* Tell the card(s) to enter the idle state (again). */ 198 sdmmc_go_idle_state(sc); 199 200 DPRINTF(("%s: host_ocr 0x%08x\n", SDMMCDEVNAME(sc), host_ocr)); 201 DPRINTF(("%s: card_ocr 0x%08x\n", SDMMCDEVNAME(sc), card_ocr)); 202 203 host_ocr &= card_ocr; /* only allow the common voltages */ 204 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 205 /* Check SD Ver.2 */ 206 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 207 if (error == 0 && card_ocr == 0x1aa) 208 SET(ocr, MMC_OCR_HCS); 209 210 if (sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch) & MMC_OCR_S18A) 211 SET(ocr, MMC_OCR_S18A); 212 } 213 host_ocr |= ocr; 214 215 /* Send the new OCR value until all cards are ready. */ 216 error = sdmmc_mem_send_op_cond(sc, host_ocr, &new_ocr); 217 if (error) { 218 DPRINTF(("%s: couldn't send memory OCR\n", SDMMCDEVNAME(sc))); 219 goto out; 220 } 221 222 if (ISSET(new_ocr, MMC_OCR_S18A) && sc->sc_sct->signal_voltage) { 223 /* 224 * Card and host support low voltage mode, begin switch 225 * sequence. 226 */ 227 struct sdmmc_command cmd; 228 memset(&cmd, 0, sizeof(cmd)); 229 cmd.c_arg = 0; 230 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 231 cmd.c_opcode = SD_VOLTAGE_SWITCH; 232 error = sdmmc_mmc_command(sc, &cmd); 233 if (error) { 234 DPRINTF(("%s: voltage switch command failed\n", 235 SDMMCDEVNAME(sc))); 236 goto out; 237 } 238 239 delay(1000); 240 241 /* 242 * Stop the clock 243 */ 244 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 245 SDMMC_SDCLK_OFF, false); 246 if (error) 247 goto out; 248 249 delay(1000); 250 251 /* 252 * Card switch command was successful, update host controller 253 * signal voltage setting. 254 */ 255 error = sdmmc_chip_signal_voltage(sc->sc_sct, 256 sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_180); 257 if (error) 258 goto out; 259 260 delay(5000); 261 262 /* 263 * Switch to SDR12 timing 264 */ 265 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 25000, 266 false); 267 if (error) 268 goto out; 269 270 delay(1000); 271 272 SET(sc->sc_flags, SMF_UHS_MODE); 273 } 274 275 out: 276 SDMMC_UNLOCK(sc); 277 278 if (error) 279 printf("%s: %s failed with error %d\n", SDMMCDEVNAME(sc), 280 __func__, error); 281 282 return error; 283 } 284 285 /* 286 * Read the CSD and CID from all cards and assign each card a unique 287 * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 288 */ 289 void 290 sdmmc_mem_scan(struct sdmmc_softc *sc) 291 { 292 sdmmc_response resp; 293 struct sdmmc_function *sf; 294 uint16_t next_rca; 295 int error; 296 int retry; 297 298 SDMMC_LOCK(sc); 299 300 /* 301 * CMD2 is a broadcast command understood by SD cards and MMC 302 * cards. All cards begin to respond to the command, but back 303 * off if another card drives the CMD line to a different level. 304 * Only one card will get its entire response through. That 305 * card remains silent once it has been assigned a RCA. 306 */ 307 for (retry = 0; retry < 100; retry++) { 308 error = sdmmc_mem_send_cid(sc, &resp); 309 if (error) { 310 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && 311 error == ETIMEDOUT) { 312 /* No more cards there. */ 313 break; 314 } 315 DPRINTF(("%s: couldn't read CID\n", SDMMCDEVNAME(sc))); 316 break; 317 } 318 319 /* In MMC mode, find the next available RCA. */ 320 next_rca = 1; 321 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 322 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) 323 next_rca++; 324 } 325 326 /* Allocate a sdmmc_function structure. */ 327 sf = sdmmc_function_alloc(sc); 328 sf->rca = next_rca; 329 330 /* 331 * Remember the CID returned in the CMD2 response for 332 * later decoding. 333 */ 334 memcpy(sf->raw_cid, resp, sizeof(sf->raw_cid)); 335 336 /* 337 * Silence the card by assigning it a unique RCA, or 338 * querying it for its RCA in the case of SD. 339 */ 340 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 341 if (sdmmc_set_relative_addr(sc, sf) != 0) { 342 aprint_error_dev(sc->sc_dev, 343 "couldn't set mem RCA\n"); 344 sdmmc_function_free(sf); 345 break; 346 } 347 } 348 349 /* 350 * If this is a memory-only card, the card responding 351 * first becomes an alias for SDIO function 0. 352 */ 353 if (sc->sc_fn0 == NULL) 354 sc->sc_fn0 = sf; 355 356 SIMPLEQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 357 358 /* only one function in SPI mode */ 359 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 360 break; 361 } 362 363 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 364 /* Go to Data Transfer Mode, if possible. */ 365 sdmmc_chip_bus_rod(sc->sc_sct, sc->sc_sch, 0); 366 367 /* 368 * All cards are either inactive or awaiting further commands. 369 * Read the CSDs and decode the raw CID for each card. 370 */ 371 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) { 372 error = sdmmc_mem_send_csd(sc, sf, &resp); 373 if (error) { 374 SET(sf->flags, SFF_ERROR); 375 continue; 376 } 377 378 if (sdmmc_decode_csd(sc, resp, sf) != 0 || 379 sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 380 SET(sf->flags, SFF_ERROR); 381 continue; 382 } 383 384 #ifdef SDMMC_DEBUG 385 printf("%s: CID: ", SDMMCDEVNAME(sc)); 386 sdmmc_print_cid(&sf->cid); 387 #endif 388 } 389 390 SDMMC_UNLOCK(sc); 391 } 392 393 int 394 sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 395 struct sdmmc_function *sf) 396 { 397 /* TRAN_SPEED(2:0): transfer rate exponent */ 398 static const int speed_exponent[8] = { 399 100 * 1, /* 100 Kbits/s */ 400 1 * 1000, /* 1 Mbits/s */ 401 10 * 1000, /* 10 Mbits/s */ 402 100 * 1000, /* 100 Mbits/s */ 403 0, 404 0, 405 0, 406 0, 407 }; 408 /* TRAN_SPEED(6:3): time mantissa */ 409 static const int speed_mantissa[16] = { 410 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 411 }; 412 struct sdmmc_csd *csd = &sf->csd; 413 int e, m; 414 415 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 416 /* 417 * CSD version 1.0 corresponds to SD system 418 * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 419 */ 420 csd->csdver = SD_CSD_CSDVER(resp); 421 switch (csd->csdver) { 422 case SD_CSD_CSDVER_2_0: 423 DPRINTF(("%s: SD Ver.2.0\n", SDMMCDEVNAME(sc))); 424 SET(sf->flags, SFF_SDHC); 425 csd->capacity = SD_CSD_V2_CAPACITY(resp); 426 csd->read_bl_len = SD_CSD_V2_BL_LEN; 427 break; 428 429 case SD_CSD_CSDVER_1_0: 430 DPRINTF(("%s: SD Ver.1.0\n", SDMMCDEVNAME(sc))); 431 csd->capacity = SD_CSD_CAPACITY(resp); 432 csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 433 break; 434 435 default: 436 aprint_error_dev(sc->sc_dev, 437 "unknown SD CSD structure version 0x%x\n", 438 csd->csdver); 439 return 1; 440 } 441 442 csd->mmcver = SD_CSD_MMCVER(resp); 443 csd->write_bl_len = SD_CSD_WRITE_BL_LEN(resp); 444 csd->r2w_factor = SD_CSD_R2W_FACTOR(resp); 445 e = SD_CSD_SPEED_EXP(resp); 446 m = SD_CSD_SPEED_MANT(resp); 447 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 448 csd->ccc = SD_CSD_CCC(resp); 449 } else { 450 csd->csdver = MMC_CSD_CSDVER(resp); 451 if (csd->csdver == MMC_CSD_CSDVER_1_0) { 452 aprint_error_dev(sc->sc_dev, 453 "unknown MMC CSD structure version 0x%x\n", 454 csd->csdver); 455 return 1; 456 } 457 458 csd->mmcver = MMC_CSD_MMCVER(resp); 459 csd->capacity = MMC_CSD_CAPACITY(resp); 460 csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 461 csd->write_bl_len = MMC_CSD_WRITE_BL_LEN(resp); 462 csd->r2w_factor = MMC_CSD_R2W_FACTOR(resp); 463 e = MMC_CSD_TRAN_SPEED_EXP(resp); 464 m = MMC_CSD_TRAN_SPEED_MANT(resp); 465 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 466 } 467 if ((1 << csd->read_bl_len) > SDMMC_SECTOR_SIZE) 468 csd->capacity *= (1 << csd->read_bl_len) / SDMMC_SECTOR_SIZE; 469 470 #ifdef SDMMC_DUMP_CSD 471 sdmmc_print_csd(resp, csd); 472 #endif 473 474 return 0; 475 } 476 477 int 478 sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 479 struct sdmmc_function *sf) 480 { 481 struct sdmmc_cid *cid = &sf->cid; 482 483 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 484 cid->mid = SD_CID_MID(resp); 485 cid->oid = SD_CID_OID(resp); 486 SD_CID_PNM_CPY(resp, cid->pnm); 487 cid->rev = SD_CID_REV(resp); 488 cid->psn = SD_CID_PSN(resp); 489 cid->mdt = SD_CID_MDT(resp); 490 } else { 491 switch(sf->csd.mmcver) { 492 case MMC_CSD_MMCVER_1_0: 493 case MMC_CSD_MMCVER_1_4: 494 cid->mid = MMC_CID_MID_V1(resp); 495 MMC_CID_PNM_V1_CPY(resp, cid->pnm); 496 cid->rev = MMC_CID_REV_V1(resp); 497 cid->psn = MMC_CID_PSN_V1(resp); 498 cid->mdt = MMC_CID_MDT_V1(resp); 499 break; 500 case MMC_CSD_MMCVER_2_0: 501 case MMC_CSD_MMCVER_3_1: 502 case MMC_CSD_MMCVER_4_0: 503 cid->mid = MMC_CID_MID_V2(resp); 504 cid->oid = MMC_CID_OID_V2(resp); 505 MMC_CID_PNM_V2_CPY(resp, cid->pnm); 506 cid->psn = MMC_CID_PSN_V2(resp); 507 break; 508 default: 509 aprint_error_dev(sc->sc_dev, "unknown MMC version %d\n", 510 sf->csd.mmcver); 511 return 1; 512 } 513 } 514 return 0; 515 } 516 517 void 518 sdmmc_print_cid(struct sdmmc_cid *cid) 519 { 520 521 printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 522 " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 523 cid->mdt); 524 } 525 526 #ifdef SDMMC_DUMP_CSD 527 void 528 sdmmc_print_csd(sdmmc_response resp, struct sdmmc_csd *csd) 529 { 530 531 printf("csdver = %d\n", csd->csdver); 532 printf("mmcver = %d\n", csd->mmcver); 533 printf("capacity = 0x%08x\n", csd->capacity); 534 printf("read_bl_len = %d\n", csd->read_bl_len); 535 printf("write_bl_len = %d\n", csd->write_bl_len); 536 printf("r2w_factor = %d\n", csd->r2w_factor); 537 printf("tran_speed = %d\n", csd->tran_speed); 538 printf("ccc = 0x%x\n", csd->ccc); 539 } 540 #endif 541 542 /* 543 * Initialize a SD/MMC memory card. 544 */ 545 int 546 sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 547 { 548 int error = 0; 549 550 SDMMC_LOCK(sc); 551 552 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 553 error = sdmmc_select_card(sc, sf); 554 if (error) 555 goto out; 556 } 557 558 error = sdmmc_mem_set_blocklen(sc, sf, SDMMC_SECTOR_SIZE); 559 if (error) 560 goto out; 561 562 if (ISSET(sc->sc_flags, SMF_SD_MODE)) 563 error = sdmmc_mem_sd_init(sc, sf); 564 else 565 error = sdmmc_mem_mmc_init(sc, sf); 566 567 out: 568 SDMMC_UNLOCK(sc); 569 570 return error; 571 } 572 573 /* 574 * Get or set the card's memory OCR value (SD or MMC). 575 */ 576 int 577 sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 578 { 579 struct sdmmc_command cmd; 580 int error; 581 int retry; 582 583 /* Don't lock */ 584 585 DPRINTF(("%s: sdmmc_mem_send_op_cond: ocr=%#x\n", 586 SDMMCDEVNAME(sc), ocr)); 587 588 /* 589 * If we change the OCR value, retry the command until the OCR 590 * we receive in response has the "CARD BUSY" bit set, meaning 591 * that all cards are ready for identification. 592 */ 593 for (retry = 0; retry < 100; retry++) { 594 memset(&cmd, 0, sizeof(cmd)); 595 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? 596 ocr : (ocr & MMC_OCR_HCS); 597 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3 | SCF_RSP_SPI_R1; 598 599 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 600 cmd.c_opcode = SD_APP_OP_COND; 601 error = sdmmc_app_command(sc, NULL, &cmd); 602 } else { 603 cmd.c_opcode = MMC_SEND_OP_COND; 604 error = sdmmc_mmc_command(sc, &cmd); 605 } 606 if (error) 607 break; 608 609 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 610 if (!ISSET(MMC_SPI_R1(cmd.c_resp), R1_SPI_IDLE)) 611 break; 612 } else { 613 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 614 ocr == 0) 615 break; 616 } 617 618 error = ETIMEDOUT; 619 sdmmc_delay(10000); 620 } 621 if (error == 0 && 622 ocrp != NULL && 623 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 624 *ocrp = MMC_R3(cmd.c_resp); 625 DPRINTF(("%s: sdmmc_mem_send_op_cond: error=%d, ocr=%#x\n", 626 SDMMCDEVNAME(sc), error, MMC_R3(cmd.c_resp))); 627 return error; 628 } 629 630 int 631 sdmmc_mem_send_if_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 632 { 633 struct sdmmc_command cmd; 634 int error; 635 636 /* Don't lock */ 637 638 memset(&cmd, 0, sizeof(cmd)); 639 cmd.c_arg = ocr; 640 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R7 | SCF_RSP_SPI_R7; 641 cmd.c_opcode = SD_SEND_IF_COND; 642 643 error = sdmmc_mmc_command(sc, &cmd); 644 if (error == 0 && ocrp != NULL) { 645 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 646 *ocrp = MMC_SPI_R7(cmd.c_resp); 647 } else { 648 *ocrp = MMC_R7(cmd.c_resp); 649 } 650 DPRINTF(("%s: sdmmc_mem_send_if_cond: error=%d, ocr=%#x\n", 651 SDMMCDEVNAME(sc), error, *ocrp)); 652 } 653 return error; 654 } 655 656 /* 657 * Set the read block length appropriately for this card, according to 658 * the card CSD register value. 659 */ 660 int 661 sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf, 662 int block_len) 663 { 664 struct sdmmc_command cmd; 665 int error; 666 667 /* Don't lock */ 668 669 memset(&cmd, 0, sizeof(cmd)); 670 cmd.c_opcode = MMC_SET_BLOCKLEN; 671 cmd.c_arg = block_len; 672 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1; 673 674 error = sdmmc_mmc_command(sc, &cmd); 675 676 DPRINTF(("%s: sdmmc_mem_set_blocklen: read_bl_len=%d sector_size=%d\n", 677 SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, block_len)); 678 679 return error; 680 } 681 682 /* make 512-bit BE quantity __bitfield()-compatible */ 683 static void 684 sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) { 685 size_t i; 686 uint32_t tmp0, tmp1; 687 const size_t bitswords = __arraycount(buf->_bits); 688 for (i = 0; i < bitswords/2; i++) { 689 tmp0 = buf->_bits[i]; 690 tmp1 = buf->_bits[bitswords - 1 - i]; 691 buf->_bits[i] = be32toh(tmp1); 692 buf->_bits[bitswords - 1 - i] = be32toh(tmp0); 693 } 694 } 695 696 static int 697 sdmmc_mem_select_transfer_mode(struct sdmmc_softc *sc, int support_func) 698 { 699 if (ISSET(sc->sc_flags, SMF_UHS_MODE)) { 700 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR104) && 701 ISSET(support_func, SD_ACCESS_MODE_SDR104)) { 702 return SD_ACCESS_MODE_SDR104; 703 } 704 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_DDR50) && 705 ISSET(support_func, SD_ACCESS_MODE_DDR50)) { 706 return SD_ACCESS_MODE_DDR50; 707 } 708 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR50) && 709 ISSET(support_func, SD_ACCESS_MODE_SDR50)) { 710 return SD_ACCESS_MODE_SDR50; 711 } 712 } 713 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) && 714 ISSET(support_func, SD_ACCESS_MODE_SDR25)) { 715 return SD_ACCESS_MODE_SDR25; 716 } 717 return SD_ACCESS_MODE_SDR12; 718 } 719 720 static int 721 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 722 { 723 int support_func, best_func, bus_clock, error, i; 724 sdmmc_bitfield512_t status; /* Switch Function Status */ 725 bool ddr = false; 726 727 /* change bus clock */ 728 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 729 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock, false); 730 if (error) { 731 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 732 return error; 733 } 734 735 error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr); 736 if (error) { 737 aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n"); 738 return error; 739 } 740 error = sdmmc_mem_decode_scr(sc, sf); 741 if (error) 742 return error; 743 744 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 745 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 746 DPRINTF(("%s: change bus width\n", SDMMCDEVNAME(sc))); 747 error = sdmmc_set_bus_width(sf, 4); 748 if (error) { 749 aprint_error_dev(sc->sc_dev, 750 "can't change bus width (%d bit)\n", 4); 751 return error; 752 } 753 sf->width = 4; 754 } 755 756 best_func = 0; 757 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 758 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 759 DPRINTF(("%s: switch func mode 0\n", SDMMCDEVNAME(sc))); 760 error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status); 761 if (error) { 762 aprint_error_dev(sc->sc_dev, 763 "switch func mode 0 failed\n"); 764 return error; 765 } 766 767 support_func = SFUNC_STATUS_GROUP(&status, 1); 768 769 for (i = 0; i < __arraycount(switch_group0_functions); i++) { 770 if (!(support_func & (1 << i))) 771 continue; 772 DPRINTF(("%s: card supports mode %s\n", 773 SDMMCDEVNAME(sc), 774 switch_group0_functions[i].name)); 775 } 776 777 best_func = sdmmc_mem_select_transfer_mode(sc, support_func); 778 779 DPRINTF(("%s: using mode %s\n", SDMMCDEVNAME(sc), 780 switch_group0_functions[best_func].name)); 781 782 if (best_func != 0) { 783 DPRINTF(("%s: switch func mode 1(func=%d)\n", 784 SDMMCDEVNAME(sc), best_func)); 785 error = 786 sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status); 787 if (error) { 788 aprint_error_dev(sc->sc_dev, 789 "switch func mode 1 failed:" 790 " group 1 function %d(0x%2x)\n", 791 best_func, support_func); 792 return error; 793 } 794 sf->csd.tran_speed = 795 switch_group0_functions[best_func].freq; 796 797 if (best_func == SD_ACCESS_MODE_DDR50) 798 ddr = true; 799 800 /* Wait 400KHz x 8 clock (2.5us * 8 + slop) */ 801 delay(25); 802 } 803 } 804 805 /* update bus clock */ 806 if (sc->sc_busclk > sf->csd.tran_speed) 807 sc->sc_busclk = sf->csd.tran_speed; 808 if (sc->sc_busclk == bus_clock && sc->sc_busddr == ddr) 809 return 0; 810 811 /* change bus clock */ 812 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk, 813 ddr); 814 if (error) { 815 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 816 return error; 817 } 818 819 sc->sc_transfer_mode = switch_group0_functions[best_func].name; 820 sc->sc_busddr = ddr; 821 822 return 0; 823 } 824 825 static int 826 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 827 { 828 int width, value, hs_timing, bus_clock, error; 829 char ext_csd[512]; 830 uint32_t sectors = 0; 831 832 sc->sc_transfer_mode = NULL; 833 834 /* change bus clock */ 835 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 836 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock, false); 837 if (error) { 838 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 839 return error; 840 } 841 842 if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 843 error = sdmmc_mem_send_cxd_data(sc, 844 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 845 if (error) { 846 aprint_error_dev(sc->sc_dev, 847 "can't read EXT_CSD (error=%d)\n", error); 848 return error; 849 } 850 if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) && 851 (ext_csd[EXT_CSD_STRUCTURE] > EXT_CSD_STRUCTURE_VER_1_2)) { 852 aprint_error_dev(sc->sc_dev, 853 "unrecognised future version (%d)\n", 854 ext_csd[EXT_CSD_STRUCTURE]); 855 return ENOTSUP; 856 } 857 858 sc->sc_transfer_mode = NULL; 859 if (ISSET(sc->sc_caps, SMC_CAPS_MMC_HS200) && 860 ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_HS200_1_8V) { 861 sf->csd.tran_speed = 200000; /* 200MHz SDR */ 862 hs_timing = 2; 863 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_52M) { 864 sf->csd.tran_speed = 52000; /* 52MHz */ 865 hs_timing = 1; 866 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_26M) { 867 sf->csd.tran_speed = 26000; /* 26MHz */ 868 hs_timing = 0; 869 } else { 870 aprint_error_dev(sc->sc_dev, 871 "unknown CARD_TYPE: 0x%x\n", 872 ext_csd[EXT_CSD_CARD_TYPE]); 873 return ENOTSUP; 874 } 875 876 if (hs_timing == 2) { 877 error = sdmmc_chip_signal_voltage(sc->sc_sct, 878 sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_180); 879 if (error) 880 hs_timing = 1; 881 } 882 883 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 884 width = 8; 885 value = EXT_CSD_BUS_WIDTH_8; 886 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 887 width = 4; 888 value = EXT_CSD_BUS_WIDTH_4; 889 } else { 890 width = 1; 891 value = EXT_CSD_BUS_WIDTH_1; 892 } 893 894 if (width != 1) { 895 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 896 EXT_CSD_BUS_WIDTH, value); 897 if (error == 0) 898 error = sdmmc_chip_bus_width(sc->sc_sct, 899 sc->sc_sch, width); 900 else { 901 DPRINTF(("%s: can't change bus width" 902 " (%d bit)\n", SDMMCDEVNAME(sc), width)); 903 return error; 904 } 905 906 /* XXXX: need bus test? (using by CMD14 & CMD19) */ 907 } 908 sf->width = width; 909 910 if (hs_timing == 1 && 911 !ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 912 hs_timing = 0; 913 } 914 if (hs_timing) { 915 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 916 EXT_CSD_HS_TIMING, hs_timing); 917 if (error) { 918 aprint_error_dev(sc->sc_dev, 919 "can't change high speed\n"); 920 return error; 921 } 922 } 923 924 if (sc->sc_busclk > sf->csd.tran_speed) 925 sc->sc_busclk = sf->csd.tran_speed; 926 if (sc->sc_busclk != bus_clock) { 927 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 928 sc->sc_busclk, false); 929 if (error) { 930 aprint_error_dev(sc->sc_dev, 931 "can't change bus clock\n"); 932 return error; 933 } 934 } 935 936 if (hs_timing) { 937 error = sdmmc_mem_send_cxd_data(sc, 938 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 939 if (error) { 940 aprint_error_dev(sc->sc_dev, 941 "can't re-read EXT_CSD\n"); 942 return error; 943 } 944 if (ext_csd[EXT_CSD_HS_TIMING] != hs_timing) { 945 aprint_error_dev(sc->sc_dev, 946 "HS_TIMING set failed\n"); 947 return EINVAL; 948 } 949 } 950 951 sectors = ext_csd[EXT_CSD_SEC_COUNT + 0] << 0 | 952 ext_csd[EXT_CSD_SEC_COUNT + 1] << 8 | 953 ext_csd[EXT_CSD_SEC_COUNT + 2] << 16 | 954 ext_csd[EXT_CSD_SEC_COUNT + 3] << 24; 955 if (sectors > (2u * 1024 * 1024 * 1024) / 512) { 956 SET(sf->flags, SFF_SDHC); 957 sf->csd.capacity = sectors; 958 } 959 960 if (hs_timing == 2) { 961 sc->sc_transfer_mode = "HS200"; 962 } else { 963 sc->sc_transfer_mode = NULL; 964 } 965 } else { 966 if (sc->sc_busclk > sf->csd.tran_speed) 967 sc->sc_busclk = sf->csd.tran_speed; 968 if (sc->sc_busclk != bus_clock) { 969 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 970 sc->sc_busclk, false); 971 if (error) { 972 aprint_error_dev(sc->sc_dev, 973 "can't change bus clock\n"); 974 return error; 975 } 976 } 977 } 978 979 return 0; 980 } 981 982 static int 983 sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp) 984 { 985 struct sdmmc_command cmd; 986 int error; 987 988 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 989 memset(&cmd, 0, sizeof cmd); 990 cmd.c_opcode = MMC_ALL_SEND_CID; 991 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 992 993 error = sdmmc_mmc_command(sc, &cmd); 994 } else { 995 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CID, &cmd.c_resp, 996 sizeof(cmd.c_resp)); 997 } 998 999 #ifdef SDMMC_DEBUG 1000 if (error == 0) 1001 sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp)); 1002 #endif 1003 if (error == 0 && resp != NULL) 1004 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 1005 return error; 1006 } 1007 1008 static int 1009 sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf, 1010 sdmmc_response *resp) 1011 { 1012 struct sdmmc_command cmd; 1013 int error; 1014 1015 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1016 memset(&cmd, 0, sizeof cmd); 1017 cmd.c_opcode = MMC_SEND_CSD; 1018 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1019 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 1020 1021 error = sdmmc_mmc_command(sc, &cmd); 1022 } else { 1023 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CSD, &cmd.c_resp, 1024 sizeof(cmd.c_resp)); 1025 } 1026 1027 #ifdef SDMMC_DEBUG 1028 if (error == 0) 1029 sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp)); 1030 #endif 1031 if (error == 0 && resp != NULL) 1032 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 1033 return error; 1034 } 1035 1036 static int 1037 sdmmc_mem_send_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf, 1038 uint32_t *scr) 1039 { 1040 struct sdmmc_command cmd; 1041 bus_dma_segment_t ds[1]; 1042 void *ptr = NULL; 1043 int datalen = 8; 1044 int rseg; 1045 int error = 0; 1046 1047 /* Don't lock */ 1048 1049 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1050 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, 1051 ds, 1, &rseg, BUS_DMA_NOWAIT); 1052 if (error) 1053 goto out; 1054 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1055 BUS_DMA_NOWAIT); 1056 if (error) 1057 goto dmamem_free; 1058 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1059 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1060 if (error) 1061 goto dmamem_unmap; 1062 1063 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1064 BUS_DMASYNC_PREREAD); 1065 } else { 1066 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1067 if (ptr == NULL) 1068 goto out; 1069 } 1070 1071 memset(&cmd, 0, sizeof(cmd)); 1072 cmd.c_data = ptr; 1073 cmd.c_datalen = datalen; 1074 cmd.c_blklen = datalen; 1075 cmd.c_arg = 0; 1076 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1077 cmd.c_opcode = SD_APP_SEND_SCR; 1078 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1079 cmd.c_dmamap = sc->sc_dmap; 1080 1081 error = sdmmc_app_command(sc, sf, &cmd); 1082 if (error == 0) { 1083 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1084 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1085 BUS_DMASYNC_POSTREAD); 1086 } 1087 memcpy(scr, ptr, datalen); 1088 } 1089 1090 out: 1091 if (ptr != NULL) { 1092 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1093 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1094 dmamem_unmap: 1095 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1096 dmamem_free: 1097 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1098 } else { 1099 free(ptr, M_DEVBUF); 1100 } 1101 } 1102 DPRINTF(("%s: sdmem_mem_send_scr: error = %d\n", SDMMCDEVNAME(sc), 1103 error)); 1104 1105 #ifdef SDMMC_DEBUG 1106 if (error == 0) 1107 sdmmc_dump_data("SCR", scr, datalen); 1108 #endif 1109 return error; 1110 } 1111 1112 static int 1113 sdmmc_mem_decode_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf) 1114 { 1115 sdmmc_response resp; 1116 int ver; 1117 1118 memset(resp, 0, sizeof(resp)); 1119 /* 1120 * Change the raw-scr received from the DMA stream to resp. 1121 */ 1122 resp[0] = be32toh(sf->raw_scr[1]) >> 8; // LSW 1123 resp[1] = be32toh(sf->raw_scr[0]); // MSW 1124 resp[0] |= (resp[1] & 0xff) << 24; 1125 resp[1] >>= 8; 1126 1127 ver = SCR_STRUCTURE(resp); 1128 sf->scr.sd_spec = SCR_SD_SPEC(resp); 1129 sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 1130 1131 DPRINTF(("%s: sdmmc_mem_decode_scr: %08x%08x ver=%d, spec=%d, bus width=%d\n", 1132 SDMMCDEVNAME(sc), resp[1], resp[0], 1133 ver, sf->scr.sd_spec, sf->scr.bus_width)); 1134 1135 if (ver != 0 && ver != 1) { 1136 DPRINTF(("%s: unknown structure version: %d\n", 1137 SDMMCDEVNAME(sc), ver)); 1138 return EINVAL; 1139 } 1140 return 0; 1141 } 1142 1143 static int 1144 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 1145 size_t datalen) 1146 { 1147 struct sdmmc_command cmd; 1148 bus_dma_segment_t ds[1]; 1149 void *ptr = NULL; 1150 int rseg; 1151 int error = 0; 1152 1153 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1154 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, ds, 1155 1, &rseg, BUS_DMA_NOWAIT); 1156 if (error) 1157 goto out; 1158 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1159 BUS_DMA_NOWAIT); 1160 if (error) 1161 goto dmamem_free; 1162 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1163 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1164 if (error) 1165 goto dmamem_unmap; 1166 1167 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1168 BUS_DMASYNC_PREREAD); 1169 } else { 1170 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1171 if (ptr == NULL) 1172 goto out; 1173 } 1174 1175 memset(&cmd, 0, sizeof(cmd)); 1176 cmd.c_data = ptr; 1177 cmd.c_datalen = datalen; 1178 cmd.c_blklen = datalen; 1179 cmd.c_opcode = opcode; 1180 cmd.c_arg = 0; 1181 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_SPI_R1; 1182 if (opcode == MMC_SEND_EXT_CSD) 1183 SET(cmd.c_flags, SCF_RSP_R1); 1184 else 1185 SET(cmd.c_flags, SCF_RSP_R2); 1186 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1187 cmd.c_dmamap = sc->sc_dmap; 1188 1189 error = sdmmc_mmc_command(sc, &cmd); 1190 if (error == 0) { 1191 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1192 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1193 BUS_DMASYNC_POSTREAD); 1194 } 1195 memcpy(data, ptr, datalen); 1196 #ifdef SDMMC_DEBUG 1197 sdmmc_dump_data("CXD", data, datalen); 1198 #endif 1199 } 1200 1201 out: 1202 if (ptr != NULL) { 1203 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1204 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1205 dmamem_unmap: 1206 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1207 dmamem_free: 1208 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1209 } else { 1210 free(ptr, M_DEVBUF); 1211 } 1212 } 1213 return error; 1214 } 1215 1216 static int 1217 sdmmc_set_bus_width(struct sdmmc_function *sf, int width) 1218 { 1219 struct sdmmc_softc *sc = sf->sc; 1220 struct sdmmc_command cmd; 1221 int error; 1222 1223 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1224 return ENODEV; 1225 1226 memset(&cmd, 0, sizeof(cmd)); 1227 cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 1228 cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 1229 1230 switch (width) { 1231 case 1: 1232 cmd.c_arg = SD_ARG_BUS_WIDTH_1; 1233 break; 1234 1235 case 4: 1236 cmd.c_arg = SD_ARG_BUS_WIDTH_4; 1237 break; 1238 1239 default: 1240 return EINVAL; 1241 } 1242 1243 error = sdmmc_app_command(sc, sf, &cmd); 1244 if (error == 0) 1245 error = sdmmc_chip_bus_width(sc->sc_sct, sc->sc_sch, width); 1246 return error; 1247 } 1248 1249 static int 1250 sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 1251 int function, sdmmc_bitfield512_t *status) 1252 { 1253 struct sdmmc_softc *sc = sf->sc; 1254 struct sdmmc_command cmd; 1255 bus_dma_segment_t ds[1]; 1256 void *ptr = NULL; 1257 int gsft, rseg, error = 0; 1258 const int statlen = 64; 1259 1260 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 1261 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 1262 return EINVAL; 1263 1264 if (group <= 0 || group > 6 || 1265 function < 0 || function > 15) 1266 return EINVAL; 1267 1268 gsft = (group - 1) << 2; 1269 1270 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1271 error = bus_dmamem_alloc(sc->sc_dmat, statlen, PAGE_SIZE, 0, ds, 1272 1, &rseg, BUS_DMA_NOWAIT); 1273 if (error) 1274 goto out; 1275 error = bus_dmamem_map(sc->sc_dmat, ds, 1, statlen, &ptr, 1276 BUS_DMA_NOWAIT); 1277 if (error) 1278 goto dmamem_free; 1279 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, statlen, 1280 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1281 if (error) 1282 goto dmamem_unmap; 1283 1284 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1285 BUS_DMASYNC_PREREAD); 1286 } else { 1287 ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 1288 if (ptr == NULL) 1289 goto out; 1290 } 1291 1292 memset(&cmd, 0, sizeof(cmd)); 1293 cmd.c_data = ptr; 1294 cmd.c_datalen = statlen; 1295 cmd.c_blklen = statlen; 1296 cmd.c_opcode = SD_SEND_SWITCH_FUNC; 1297 cmd.c_arg = 1298 (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 1299 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1300 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1301 cmd.c_dmamap = sc->sc_dmap; 1302 1303 error = sdmmc_mmc_command(sc, &cmd); 1304 if (error == 0) { 1305 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1306 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1307 BUS_DMASYNC_POSTREAD); 1308 } 1309 memcpy(status, ptr, statlen); 1310 } 1311 1312 out: 1313 if (ptr != NULL) { 1314 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1315 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1316 dmamem_unmap: 1317 bus_dmamem_unmap(sc->sc_dmat, ptr, statlen); 1318 dmamem_free: 1319 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1320 } else { 1321 free(ptr, M_DEVBUF); 1322 } 1323 } 1324 1325 if (error == 0) 1326 sdmmc_be512_to_bitfield512(status); 1327 1328 return error; 1329 } 1330 1331 static int 1332 sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 1333 uint8_t value) 1334 { 1335 struct sdmmc_softc *sc = sf->sc; 1336 struct sdmmc_command cmd; 1337 1338 memset(&cmd, 0, sizeof(cmd)); 1339 cmd.c_opcode = MMC_SWITCH; 1340 cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 1341 (index << 16) | (value << 8) | set; 1342 cmd.c_flags = SCF_RSP_SPI_R1B | SCF_RSP_R1B | SCF_CMD_AC; 1343 1344 return sdmmc_mmc_command(sc, &cmd); 1345 } 1346 1347 /* 1348 * SPI mode function 1349 */ 1350 static int 1351 sdmmc_mem_spi_read_ocr(struct sdmmc_softc *sc, uint32_t hcs, uint32_t *card_ocr) 1352 { 1353 struct sdmmc_command cmd; 1354 int error; 1355 1356 memset(&cmd, 0, sizeof(cmd)); 1357 cmd.c_opcode = MMC_READ_OCR; 1358 cmd.c_arg = hcs ? MMC_OCR_HCS : 0; 1359 cmd.c_flags = SCF_RSP_SPI_R3; 1360 1361 error = sdmmc_mmc_command(sc, &cmd); 1362 if (error == 0 && card_ocr != NULL) 1363 *card_ocr = cmd.c_resp[1]; 1364 DPRINTF(("%s: sdmmc_mem_spi_read_ocr: error=%d, ocr=%#x\n", 1365 SDMMCDEVNAME(sc), error, cmd.c_resp[1])); 1366 return error; 1367 } 1368 1369 /* 1370 * read/write function 1371 */ 1372 /* read */ 1373 static int 1374 sdmmc_mem_single_read_block(struct sdmmc_function *sf, uint32_t blkno, 1375 u_char *data, size_t datalen) 1376 { 1377 struct sdmmc_softc *sc = sf->sc; 1378 int error = 0; 1379 int i; 1380 1381 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1382 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1383 1384 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1385 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno + i, 1386 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1387 if (error) 1388 break; 1389 } 1390 return error; 1391 } 1392 1393 /* 1394 * Simulate multi-segment dma transfer. 1395 */ 1396 static int 1397 sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *sf, 1398 uint32_t blkno, u_char *data, size_t datalen) 1399 { 1400 struct sdmmc_softc *sc = sf->sc; 1401 bool use_bbuf = false; 1402 int error = 0; 1403 int i; 1404 1405 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1406 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1407 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1408 use_bbuf = true; 1409 break; 1410 } 1411 } 1412 if (use_bbuf) { 1413 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1414 BUS_DMASYNC_PREREAD); 1415 1416 error = sdmmc_mem_read_block_subr(sf, sf->bbuf_dmap, 1417 blkno, data, datalen); 1418 if (error) { 1419 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1420 return error; 1421 } 1422 1423 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1424 BUS_DMASYNC_POSTREAD); 1425 1426 /* Copy from bounce buffer */ 1427 memcpy(data, sf->bbuf, datalen); 1428 1429 return 0; 1430 } 1431 1432 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1433 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1434 1435 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1436 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_READ); 1437 if (error) 1438 return error; 1439 1440 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1441 BUS_DMASYNC_PREREAD); 1442 1443 error = sdmmc_mem_read_block_subr(sf, sf->sseg_dmap, 1444 blkno, data, len); 1445 if (error) { 1446 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1447 return error; 1448 } 1449 1450 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1451 BUS_DMASYNC_POSTREAD); 1452 1453 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1454 1455 blkno += len / SDMMC_SECTOR_SIZE; 1456 data += len; 1457 } 1458 return 0; 1459 } 1460 1461 static int 1462 sdmmc_mem_read_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1463 uint32_t blkno, u_char *data, size_t datalen) 1464 { 1465 struct sdmmc_softc *sc = sf->sc; 1466 struct sdmmc_command cmd; 1467 int error; 1468 1469 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1470 error = sdmmc_select_card(sc, sf); 1471 if (error) 1472 goto out; 1473 } 1474 1475 memset(&cmd, 0, sizeof(cmd)); 1476 cmd.c_data = data; 1477 cmd.c_datalen = datalen; 1478 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1479 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1480 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1481 cmd.c_arg = blkno; 1482 if (!ISSET(sf->flags, SFF_SDHC)) 1483 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1484 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1485 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1486 cmd.c_dmamap = dmap; 1487 1488 error = sdmmc_mmc_command(sc, &cmd); 1489 if (error) 1490 goto out; 1491 1492 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1493 if (cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 1494 memset(&cmd, 0, sizeof cmd); 1495 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1496 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1497 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1498 error = sdmmc_mmc_command(sc, &cmd); 1499 if (error) 1500 goto out; 1501 } 1502 } 1503 1504 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1505 do { 1506 memset(&cmd, 0, sizeof(cmd)); 1507 cmd.c_opcode = MMC_SEND_STATUS; 1508 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1509 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1510 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1511 error = sdmmc_mmc_command(sc, &cmd); 1512 if (error) 1513 break; 1514 /* XXX time out */ 1515 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1516 } 1517 1518 out: 1519 return error; 1520 } 1521 1522 int 1523 sdmmc_mem_read_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1524 size_t datalen) 1525 { 1526 struct sdmmc_softc *sc = sf->sc; 1527 int error; 1528 1529 SDMMC_LOCK(sc); 1530 mutex_enter(&sc->sc_mtx); 1531 1532 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1533 error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 1534 goto out; 1535 } 1536 1537 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1538 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1539 datalen); 1540 goto out; 1541 } 1542 1543 /* DMA transfer */ 1544 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1545 BUS_DMA_NOWAIT|BUS_DMA_READ); 1546 if (error) 1547 goto out; 1548 1549 #ifdef SDMMC_DEBUG 1550 printf("data=%p, datalen=%zu\n", data, datalen); 1551 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1552 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1553 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1554 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1555 } 1556 #endif 1557 1558 if (sc->sc_dmap->dm_nsegs > 1 1559 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1560 error = sdmmc_mem_single_segment_dma_read_block(sf, blkno, 1561 data, datalen); 1562 goto unload; 1563 } 1564 1565 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1566 BUS_DMASYNC_PREREAD); 1567 1568 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1569 datalen); 1570 if (error) 1571 goto unload; 1572 1573 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1574 BUS_DMASYNC_POSTREAD); 1575 unload: 1576 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1577 1578 out: 1579 mutex_exit(&sc->sc_mtx); 1580 SDMMC_UNLOCK(sc); 1581 1582 return error; 1583 } 1584 1585 /* write */ 1586 static int 1587 sdmmc_mem_single_write_block(struct sdmmc_function *sf, uint32_t blkno, 1588 u_char *data, size_t datalen) 1589 { 1590 struct sdmmc_softc *sc = sf->sc; 1591 int error = 0; 1592 int i; 1593 1594 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1595 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1596 1597 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1598 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno + i, 1599 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1600 if (error) 1601 break; 1602 } 1603 return error; 1604 } 1605 1606 /* 1607 * Simulate multi-segment dma transfer. 1608 */ 1609 static int 1610 sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *sf, 1611 uint32_t blkno, u_char *data, size_t datalen) 1612 { 1613 struct sdmmc_softc *sc = sf->sc; 1614 bool use_bbuf = false; 1615 int error = 0; 1616 int i; 1617 1618 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1619 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1620 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1621 use_bbuf = true; 1622 break; 1623 } 1624 } 1625 if (use_bbuf) { 1626 /* Copy to bounce buffer */ 1627 memcpy(sf->bbuf, data, datalen); 1628 1629 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1630 BUS_DMASYNC_PREWRITE); 1631 1632 error = sdmmc_mem_write_block_subr(sf, sf->bbuf_dmap, 1633 blkno, data, datalen); 1634 if (error) { 1635 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1636 return error; 1637 } 1638 1639 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1640 BUS_DMASYNC_POSTWRITE); 1641 1642 return 0; 1643 } 1644 1645 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1646 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1647 1648 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1649 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1650 if (error) 1651 return error; 1652 1653 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1654 BUS_DMASYNC_PREWRITE); 1655 1656 error = sdmmc_mem_write_block_subr(sf, sf->sseg_dmap, 1657 blkno, data, len); 1658 if (error) { 1659 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1660 return error; 1661 } 1662 1663 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1664 BUS_DMASYNC_POSTWRITE); 1665 1666 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1667 1668 blkno += len / SDMMC_SECTOR_SIZE; 1669 data += len; 1670 } 1671 1672 return error; 1673 } 1674 1675 static int 1676 sdmmc_mem_write_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1677 uint32_t blkno, u_char *data, size_t datalen) 1678 { 1679 struct sdmmc_softc *sc = sf->sc; 1680 struct sdmmc_command cmd; 1681 int error; 1682 1683 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1684 error = sdmmc_select_card(sc, sf); 1685 if (error) 1686 goto out; 1687 } 1688 1689 memset(&cmd, 0, sizeof(cmd)); 1690 cmd.c_data = data; 1691 cmd.c_datalen = datalen; 1692 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1693 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1694 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1695 cmd.c_arg = blkno; 1696 if (!ISSET(sf->flags, SFF_SDHC)) 1697 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1698 cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 1699 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1700 cmd.c_dmamap = dmap; 1701 1702 error = sdmmc_mmc_command(sc, &cmd); 1703 if (error) 1704 goto out; 1705 1706 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1707 if (cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1708 memset(&cmd, 0, sizeof(cmd)); 1709 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1710 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1711 error = sdmmc_mmc_command(sc, &cmd); 1712 if (error) 1713 goto out; 1714 } 1715 } 1716 1717 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1718 do { 1719 memset(&cmd, 0, sizeof(cmd)); 1720 cmd.c_opcode = MMC_SEND_STATUS; 1721 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1722 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1723 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1724 error = sdmmc_mmc_command(sc, &cmd); 1725 if (error) 1726 break; 1727 /* XXX time out */ 1728 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1729 } 1730 1731 out: 1732 return error; 1733 } 1734 1735 int 1736 sdmmc_mem_write_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1737 size_t datalen) 1738 { 1739 struct sdmmc_softc *sc = sf->sc; 1740 int error; 1741 1742 SDMMC_LOCK(sc); 1743 mutex_enter(&sc->sc_mtx); 1744 1745 if (sdmmc_chip_write_protect(sc->sc_sct, sc->sc_sch)) { 1746 aprint_normal_dev(sc->sc_dev, "write-protected\n"); 1747 error = EIO; 1748 goto out; 1749 } 1750 1751 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1752 error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1753 goto out; 1754 } 1755 1756 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1757 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1758 datalen); 1759 goto out; 1760 } 1761 1762 /* DMA transfer */ 1763 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1764 BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1765 if (error) 1766 goto out; 1767 1768 #ifdef SDMMC_DEBUG 1769 aprint_normal_dev(sc->sc_dev, "%s: data=%p, datalen=%zu\n", 1770 __func__, data, datalen); 1771 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1772 aprint_normal_dev(sc->sc_dev, 1773 "%s: seg#%d: addr=%#lx, size=%#lx\n", __func__, i, 1774 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1775 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1776 } 1777 #endif 1778 1779 if (sc->sc_dmap->dm_nsegs > 1 1780 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1781 error = sdmmc_mem_single_segment_dma_write_block(sf, blkno, 1782 data, datalen); 1783 goto unload; 1784 } 1785 1786 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1787 BUS_DMASYNC_PREWRITE); 1788 1789 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1790 datalen); 1791 if (error) 1792 goto unload; 1793 1794 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1795 BUS_DMASYNC_POSTWRITE); 1796 unload: 1797 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1798 1799 out: 1800 mutex_exit(&sc->sc_mtx); 1801 SDMMC_UNLOCK(sc); 1802 1803 return error; 1804 } 1805
Indexes created Thu Sep 25 06:09:39 GMT 2025