sdmmc_mem.c revision 1.41
1 /* $NetBSD: sdmmc_mem.c,v 1.41 2015/08/03 12:10:29 jmcneill Exp $ */ 2 /* $OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2007, 2008, 2009, 2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 /* Routines for SD/MMC memory cards. */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.41 2015/08/03 12:10:29 jmcneill Exp $"); 49 50 #ifdef _KERNEL_OPT 51 #include "opt_sdmmc.h" 52 #endif 53 54 #include <sys/param.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 60 #include <dev/sdmmc/sdmmcchip.h> 61 #include <dev/sdmmc/sdmmcreg.h> 62 #include <dev/sdmmc/sdmmcvar.h> 63 64 #ifdef SDMMC_DEBUG 65 #define DPRINTF(s) do { printf s; } while (/*CONSTCOND*/0) 66 #else 67 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 68 #endif 69 70 typedef struct { uint32_t _bits[512/32]; } __packed __aligned(4) sdmmc_bitfield512_t; 71 72 static int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 73 static int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 74 static int sdmmc_mem_send_cid(struct sdmmc_softc *, sdmmc_response *); 75 static int sdmmc_mem_send_csd(struct sdmmc_softc *, struct sdmmc_function *, 76 sdmmc_response *); 77 static int sdmmc_mem_send_scr(struct sdmmc_softc *, struct sdmmc_function *, 78 uint32_t *scr); 79 static int sdmmc_mem_decode_scr(struct sdmmc_softc *, struct sdmmc_function *); 80 static int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 81 static int sdmmc_set_bus_width(struct sdmmc_function *, int); 82 static int sdmmc_mem_sd_switch(struct sdmmc_function *, int, int, int, sdmmc_bitfield512_t *); 83 static int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, 84 uint8_t); 85 static int sdmmc_mem_spi_read_ocr(struct sdmmc_softc *, uint32_t, uint32_t *); 86 static int sdmmc_mem_single_read_block(struct sdmmc_function *, uint32_t, 87 u_char *, size_t); 88 static int sdmmc_mem_single_write_block(struct sdmmc_function *, uint32_t, 89 u_char *, size_t); 90 static int sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *, 91 uint32_t, u_char *, size_t); 92 static int sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *, 93 uint32_t, u_char *, size_t); 94 static int sdmmc_mem_read_block_subr(struct sdmmc_function *, bus_dmamap_t, 95 uint32_t, u_char *, size_t); 96 static int sdmmc_mem_write_block_subr(struct sdmmc_function *, bus_dmamap_t, 97 uint32_t, u_char *, size_t); 98 99 static const struct { 100 const char *name; 101 int v; 102 int freq; 103 } switch_group0_functions[] = { 104 /* Default/SDR12 */ 105 { "Default/SDR12", 0, 25000 }, 106 107 /* High-Speed/SDR25 */ 108 { "High-Speed/SDR25", SMC_CAPS_SD_HIGHSPEED, 50000 }, 109 110 /* SDR50 */ 111 { "SDR50", SMC_CAPS_UHS_SDR50, 100000 }, 112 113 /* SDR104 */ 114 { "SDR104", SMC_CAPS_UHS_SDR104, 208000 }, 115 116 /* DDR50 */ 117 { "DDR50", SMC_CAPS_UHS_DDR50, 50000 }, 118 }; 119 120 /* 121 * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 122 */ 123 int 124 sdmmc_mem_enable(struct sdmmc_softc *sc) 125 { 126 uint32_t host_ocr; 127 uint32_t card_ocr; 128 uint32_t new_ocr; 129 uint32_t ocr = 0; 130 int error; 131 132 SDMMC_LOCK(sc); 133 134 /* Set host mode to SD "combo" card or SD memory-only. */ 135 CLR(sc->sc_flags, SMF_UHS_MODE); 136 SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 137 138 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 139 sdmmc_spi_chip_initialize(sc->sc_spi_sct, sc->sc_sch); 140 141 /* Reset memory (*must* do that before CMD55 or CMD1). */ 142 sdmmc_go_idle_state(sc); 143 144 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 145 /* Check SD Ver.2 */ 146 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 147 if (error == 0 && card_ocr == 0x1aa) 148 SET(ocr, MMC_OCR_HCS); 149 } 150 151 /* 152 * Read the SD/MMC memory OCR value by issuing CMD55 followed 153 * by ACMD41 to read the OCR value from memory-only SD cards. 154 * MMC cards will not respond to CMD55 or ACMD41 and this is 155 * how we distinguish them from SD cards. 156 */ 157 mmc_mode: 158 error = sdmmc_mem_send_op_cond(sc, 159 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr); 160 if (error) { 161 if (ISSET(sc->sc_flags, SMF_SD_MODE) && 162 !ISSET(sc->sc_flags, SMF_IO_MODE)) { 163 /* Not a SD card, switch to MMC mode. */ 164 DPRINTF(("%s: switch to MMC mode\n", SDMMCDEVNAME(sc))); 165 CLR(sc->sc_flags, SMF_SD_MODE); 166 goto mmc_mode; 167 } 168 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 169 DPRINTF(("%s: couldn't read memory OCR\n", 170 SDMMCDEVNAME(sc))); 171 goto out; 172 } else { 173 /* Not a "combo" card. */ 174 CLR(sc->sc_flags, SMF_MEM_MODE); 175 error = 0; 176 goto out; 177 } 178 } 179 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 180 /* get card OCR */ 181 error = sdmmc_mem_spi_read_ocr(sc, ocr, &card_ocr); 182 if (error) { 183 DPRINTF(("%s: couldn't read SPI memory OCR\n", 184 SDMMCDEVNAME(sc))); 185 goto out; 186 } 187 } 188 189 /* Set the lowest voltage supported by the card and host. */ 190 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 191 error = sdmmc_set_bus_power(sc, host_ocr, card_ocr); 192 if (error) { 193 DPRINTF(("%s: couldn't supply voltage requested by card\n", 194 SDMMCDEVNAME(sc))); 195 goto out; 196 } 197 198 /* Tell the card(s) to enter the idle state (again). */ 199 sdmmc_go_idle_state(sc); 200 201 DPRINTF(("%s: host_ocr 0x%08x\n", SDMMCDEVNAME(sc), host_ocr)); 202 DPRINTF(("%s: card_ocr 0x%08x\n", SDMMCDEVNAME(sc), card_ocr)); 203 204 host_ocr &= card_ocr; /* only allow the common voltages */ 205 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 206 /* Check SD Ver.2 */ 207 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 208 if (error == 0 && card_ocr == 0x1aa) 209 SET(ocr, MMC_OCR_HCS); 210 211 if (sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch) & MMC_OCR_S18A) 212 SET(ocr, MMC_OCR_S18A); 213 } 214 host_ocr |= ocr; 215 216 /* Send the new OCR value until all cards are ready. */ 217 error = sdmmc_mem_send_op_cond(sc, host_ocr, &new_ocr); 218 if (error) { 219 DPRINTF(("%s: couldn't send memory OCR\n", SDMMCDEVNAME(sc))); 220 goto out; 221 } 222 223 if (ISSET(new_ocr, MMC_OCR_S18A) && sc->sc_sct->signal_voltage) { 224 /* 225 * Card and host support low voltage mode, begin switch 226 * sequence. 227 */ 228 struct sdmmc_command cmd; 229 memset(&cmd, 0, sizeof(cmd)); 230 cmd.c_arg = 0; 231 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 232 cmd.c_opcode = SD_VOLTAGE_SWITCH; 233 error = sdmmc_mmc_command(sc, &cmd); 234 if (error) { 235 DPRINTF(("%s: voltage switch command failed\n", 236 SDMMCDEVNAME(sc))); 237 goto out; 238 } 239 240 delay(1000); 241 242 /* 243 * Stop the clock 244 */ 245 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 246 SDMMC_SDCLK_OFF, false); 247 if (error) 248 goto out; 249 250 delay(1000); 251 252 /* 253 * Card switch command was successful, update host controller 254 * signal voltage setting. 255 */ 256 error = sdmmc_chip_signal_voltage(sc->sc_sct, 257 sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_180); 258 if (error) 259 goto out; 260 261 delay(5000); 262 263 /* 264 * Switch to SDR12 timing 265 */ 266 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 25000, 267 false); 268 if (error) 269 goto out; 270 271 delay(1000); 272 273 SET(sc->sc_flags, SMF_UHS_MODE); 274 } 275 276 out: 277 SDMMC_UNLOCK(sc); 278 279 if (error) 280 printf("%s: %s failed with error %d\n", SDMMCDEVNAME(sc), 281 __func__, error); 282 283 return error; 284 } 285 286 /* 287 * Read the CSD and CID from all cards and assign each card a unique 288 * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 289 */ 290 void 291 sdmmc_mem_scan(struct sdmmc_softc *sc) 292 { 293 sdmmc_response resp; 294 struct sdmmc_function *sf; 295 uint16_t next_rca; 296 int error; 297 int retry; 298 299 SDMMC_LOCK(sc); 300 301 /* 302 * CMD2 is a broadcast command understood by SD cards and MMC 303 * cards. All cards begin to respond to the command, but back 304 * off if another card drives the CMD line to a different level. 305 * Only one card will get its entire response through. That 306 * card remains silent once it has been assigned a RCA. 307 */ 308 for (retry = 0; retry < 100; retry++) { 309 error = sdmmc_mem_send_cid(sc, &resp); 310 if (error) { 311 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && 312 error == ETIMEDOUT) { 313 /* No more cards there. */ 314 break; 315 } 316 DPRINTF(("%s: couldn't read CID\n", SDMMCDEVNAME(sc))); 317 break; 318 } 319 320 /* In MMC mode, find the next available RCA. */ 321 next_rca = 1; 322 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 323 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) 324 next_rca++; 325 } 326 327 /* Allocate a sdmmc_function structure. */ 328 sf = sdmmc_function_alloc(sc); 329 sf->rca = next_rca; 330 331 /* 332 * Remember the CID returned in the CMD2 response for 333 * later decoding. 334 */ 335 memcpy(sf->raw_cid, resp, sizeof(sf->raw_cid)); 336 337 /* 338 * Silence the card by assigning it a unique RCA, or 339 * querying it for its RCA in the case of SD. 340 */ 341 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 342 if (sdmmc_set_relative_addr(sc, sf) != 0) { 343 aprint_error_dev(sc->sc_dev, 344 "couldn't set mem RCA\n"); 345 sdmmc_function_free(sf); 346 break; 347 } 348 } 349 350 /* 351 * If this is a memory-only card, the card responding 352 * first becomes an alias for SDIO function 0. 353 */ 354 if (sc->sc_fn0 == NULL) 355 sc->sc_fn0 = sf; 356 357 SIMPLEQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 358 359 /* only one function in SPI mode */ 360 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 361 break; 362 } 363 364 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 365 /* Go to Data Transfer Mode, if possible. */ 366 sdmmc_chip_bus_rod(sc->sc_sct, sc->sc_sch, 0); 367 368 /* 369 * All cards are either inactive or awaiting further commands. 370 * Read the CSDs and decode the raw CID for each card. 371 */ 372 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) { 373 error = sdmmc_mem_send_csd(sc, sf, &resp); 374 if (error) { 375 SET(sf->flags, SFF_ERROR); 376 continue; 377 } 378 379 if (sdmmc_decode_csd(sc, resp, sf) != 0 || 380 sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 381 SET(sf->flags, SFF_ERROR); 382 continue; 383 } 384 385 #ifdef SDMMC_DEBUG 386 printf("%s: CID: ", SDMMCDEVNAME(sc)); 387 sdmmc_print_cid(&sf->cid); 388 #endif 389 } 390 391 SDMMC_UNLOCK(sc); 392 } 393 394 int 395 sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 396 struct sdmmc_function *sf) 397 { 398 /* TRAN_SPEED(2:0): transfer rate exponent */ 399 static const int speed_exponent[8] = { 400 100 * 1, /* 100 Kbits/s */ 401 1 * 1000, /* 1 Mbits/s */ 402 10 * 1000, /* 10 Mbits/s */ 403 100 * 1000, /* 100 Mbits/s */ 404 0, 405 0, 406 0, 407 0, 408 }; 409 /* TRAN_SPEED(6:3): time mantissa */ 410 static const int speed_mantissa[16] = { 411 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 412 }; 413 struct sdmmc_csd *csd = &sf->csd; 414 int e, m; 415 416 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 417 /* 418 * CSD version 1.0 corresponds to SD system 419 * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 420 */ 421 csd->csdver = SD_CSD_CSDVER(resp); 422 switch (csd->csdver) { 423 case SD_CSD_CSDVER_2_0: 424 DPRINTF(("%s: SD Ver.2.0\n", SDMMCDEVNAME(sc))); 425 SET(sf->flags, SFF_SDHC); 426 csd->capacity = SD_CSD_V2_CAPACITY(resp); 427 csd->read_bl_len = SD_CSD_V2_BL_LEN; 428 break; 429 430 case SD_CSD_CSDVER_1_0: 431 DPRINTF(("%s: SD Ver.1.0\n", SDMMCDEVNAME(sc))); 432 csd->capacity = SD_CSD_CAPACITY(resp); 433 csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 434 break; 435 436 default: 437 aprint_error_dev(sc->sc_dev, 438 "unknown SD CSD structure version 0x%x\n", 439 csd->csdver); 440 return 1; 441 } 442 443 csd->mmcver = SD_CSD_MMCVER(resp); 444 csd->write_bl_len = SD_CSD_WRITE_BL_LEN(resp); 445 csd->r2w_factor = SD_CSD_R2W_FACTOR(resp); 446 e = SD_CSD_SPEED_EXP(resp); 447 m = SD_CSD_SPEED_MANT(resp); 448 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 449 csd->ccc = SD_CSD_CCC(resp); 450 } else { 451 csd->csdver = MMC_CSD_CSDVER(resp); 452 if (csd->csdver == MMC_CSD_CSDVER_1_0) { 453 aprint_error_dev(sc->sc_dev, 454 "unknown MMC CSD structure version 0x%x\n", 455 csd->csdver); 456 return 1; 457 } 458 459 csd->mmcver = MMC_CSD_MMCVER(resp); 460 csd->capacity = MMC_CSD_CAPACITY(resp); 461 csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 462 csd->write_bl_len = MMC_CSD_WRITE_BL_LEN(resp); 463 csd->r2w_factor = MMC_CSD_R2W_FACTOR(resp); 464 e = MMC_CSD_TRAN_SPEED_EXP(resp); 465 m = MMC_CSD_TRAN_SPEED_MANT(resp); 466 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 467 } 468 if ((1 << csd->read_bl_len) > SDMMC_SECTOR_SIZE) 469 csd->capacity *= (1 << csd->read_bl_len) / SDMMC_SECTOR_SIZE; 470 471 #ifdef SDMMC_DUMP_CSD 472 sdmmc_print_csd(resp, csd); 473 #endif 474 475 return 0; 476 } 477 478 int 479 sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 480 struct sdmmc_function *sf) 481 { 482 struct sdmmc_cid *cid = &sf->cid; 483 484 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 485 cid->mid = SD_CID_MID(resp); 486 cid->oid = SD_CID_OID(resp); 487 SD_CID_PNM_CPY(resp, cid->pnm); 488 cid->rev = SD_CID_REV(resp); 489 cid->psn = SD_CID_PSN(resp); 490 cid->mdt = SD_CID_MDT(resp); 491 } else { 492 switch(sf->csd.mmcver) { 493 case MMC_CSD_MMCVER_1_0: 494 case MMC_CSD_MMCVER_1_4: 495 cid->mid = MMC_CID_MID_V1(resp); 496 MMC_CID_PNM_V1_CPY(resp, cid->pnm); 497 cid->rev = MMC_CID_REV_V1(resp); 498 cid->psn = MMC_CID_PSN_V1(resp); 499 cid->mdt = MMC_CID_MDT_V1(resp); 500 break; 501 case MMC_CSD_MMCVER_2_0: 502 case MMC_CSD_MMCVER_3_1: 503 case MMC_CSD_MMCVER_4_0: 504 cid->mid = MMC_CID_MID_V2(resp); 505 cid->oid = MMC_CID_OID_V2(resp); 506 MMC_CID_PNM_V2_CPY(resp, cid->pnm); 507 cid->psn = MMC_CID_PSN_V2(resp); 508 break; 509 default: 510 aprint_error_dev(sc->sc_dev, "unknown MMC version %d\n", 511 sf->csd.mmcver); 512 return 1; 513 } 514 } 515 return 0; 516 } 517 518 void 519 sdmmc_print_cid(struct sdmmc_cid *cid) 520 { 521 522 printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 523 " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 524 cid->mdt); 525 } 526 527 #ifdef SDMMC_DUMP_CSD 528 void 529 sdmmc_print_csd(sdmmc_response resp, struct sdmmc_csd *csd) 530 { 531 532 printf("csdver = %d\n", csd->csdver); 533 printf("mmcver = %d\n", csd->mmcver); 534 printf("capacity = 0x%08x\n", csd->capacity); 535 printf("read_bl_len = %d\n", csd->read_bl_len); 536 printf("write_bl_len = %d\n", csd->write_bl_len); 537 printf("r2w_factor = %d\n", csd->r2w_factor); 538 printf("tran_speed = %d\n", csd->tran_speed); 539 printf("ccc = 0x%x\n", csd->ccc); 540 } 541 #endif 542 543 /* 544 * Initialize a SD/MMC memory card. 545 */ 546 int 547 sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 548 { 549 int error = 0; 550 551 SDMMC_LOCK(sc); 552 553 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 554 error = sdmmc_select_card(sc, sf); 555 if (error) 556 goto out; 557 } 558 559 error = sdmmc_mem_set_blocklen(sc, sf, SDMMC_SECTOR_SIZE); 560 if (error) 561 goto out; 562 563 if (ISSET(sc->sc_flags, SMF_SD_MODE)) 564 error = sdmmc_mem_sd_init(sc, sf); 565 else 566 error = sdmmc_mem_mmc_init(sc, sf); 567 568 out: 569 SDMMC_UNLOCK(sc); 570 571 return error; 572 } 573 574 /* 575 * Get or set the card's memory OCR value (SD or MMC). 576 */ 577 int 578 sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 579 { 580 struct sdmmc_command cmd; 581 int error; 582 int retry; 583 584 /* Don't lock */ 585 586 DPRINTF(("%s: sdmmc_mem_send_op_cond: ocr=%#x\n", 587 SDMMCDEVNAME(sc), ocr)); 588 589 /* 590 * If we change the OCR value, retry the command until the OCR 591 * we receive in response has the "CARD BUSY" bit set, meaning 592 * that all cards are ready for identification. 593 */ 594 for (retry = 0; retry < 100; retry++) { 595 memset(&cmd, 0, sizeof(cmd)); 596 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? 597 ocr : (ocr & MMC_OCR_HCS); 598 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3 | SCF_RSP_SPI_R1; 599 600 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 601 cmd.c_opcode = SD_APP_OP_COND; 602 error = sdmmc_app_command(sc, NULL, &cmd); 603 } else { 604 cmd.c_opcode = MMC_SEND_OP_COND; 605 error = sdmmc_mmc_command(sc, &cmd); 606 } 607 if (error) 608 break; 609 610 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 611 if (!ISSET(MMC_SPI_R1(cmd.c_resp), R1_SPI_IDLE)) 612 break; 613 } else { 614 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 615 ocr == 0) 616 break; 617 } 618 619 error = ETIMEDOUT; 620 sdmmc_delay(10000); 621 } 622 if (error == 0 && 623 ocrp != NULL && 624 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 625 *ocrp = MMC_R3(cmd.c_resp); 626 DPRINTF(("%s: sdmmc_mem_send_op_cond: error=%d, ocr=%#x\n", 627 SDMMCDEVNAME(sc), error, MMC_R3(cmd.c_resp))); 628 return error; 629 } 630 631 int 632 sdmmc_mem_send_if_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 633 { 634 struct sdmmc_command cmd; 635 int error; 636 637 /* Don't lock */ 638 639 memset(&cmd, 0, sizeof(cmd)); 640 cmd.c_arg = ocr; 641 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R7 | SCF_RSP_SPI_R7; 642 cmd.c_opcode = SD_SEND_IF_COND; 643 644 error = sdmmc_mmc_command(sc, &cmd); 645 if (error == 0 && ocrp != NULL) { 646 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 647 *ocrp = MMC_SPI_R7(cmd.c_resp); 648 } else { 649 *ocrp = MMC_R7(cmd.c_resp); 650 } 651 DPRINTF(("%s: sdmmc_mem_send_if_cond: error=%d, ocr=%#x\n", 652 SDMMCDEVNAME(sc), error, *ocrp)); 653 } 654 return error; 655 } 656 657 /* 658 * Set the read block length appropriately for this card, according to 659 * the card CSD register value. 660 */ 661 int 662 sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf, 663 int block_len) 664 { 665 struct sdmmc_command cmd; 666 int error; 667 668 /* Don't lock */ 669 670 memset(&cmd, 0, sizeof(cmd)); 671 cmd.c_opcode = MMC_SET_BLOCKLEN; 672 cmd.c_arg = block_len; 673 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1; 674 675 error = sdmmc_mmc_command(sc, &cmd); 676 677 DPRINTF(("%s: sdmmc_mem_set_blocklen: read_bl_len=%d sector_size=%d\n", 678 SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, block_len)); 679 680 return error; 681 } 682 683 /* make 512-bit BE quantity __bitfield()-compatible */ 684 static void 685 sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) { 686 size_t i; 687 uint32_t tmp0, tmp1; 688 const size_t bitswords = __arraycount(buf->_bits); 689 for (i = 0; i < bitswords/2; i++) { 690 tmp0 = buf->_bits[i]; 691 tmp1 = buf->_bits[bitswords - 1 - i]; 692 buf->_bits[i] = be32toh(tmp1); 693 buf->_bits[bitswords - 1 - i] = be32toh(tmp0); 694 } 695 } 696 697 static int 698 sdmmc_mem_select_transfer_mode(struct sdmmc_softc *sc, int support_func) 699 { 700 if (ISSET(sc->sc_flags, SMF_UHS_MODE)) { 701 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR104) && 702 ISSET(support_func, SD_ACCESS_MODE_SDR104)) { 703 return SD_ACCESS_MODE_SDR104; 704 } 705 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_DDR50) && 706 ISSET(support_func, SD_ACCESS_MODE_DDR50)) { 707 return SD_ACCESS_MODE_DDR50; 708 } 709 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR50) && 710 ISSET(support_func, SD_ACCESS_MODE_SDR50)) { 711 return SD_ACCESS_MODE_SDR50; 712 } 713 } 714 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) && 715 ISSET(support_func, SD_ACCESS_MODE_SDR25)) { 716 return SD_ACCESS_MODE_SDR25; 717 } 718 return SD_ACCESS_MODE_SDR12; 719 } 720 721 static int 722 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 723 { 724 int support_func, best_func, bus_clock, error, i; 725 sdmmc_bitfield512_t status; /* Switch Function Status */ 726 bool ddr = false; 727 728 /* change bus clock */ 729 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 730 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock, false); 731 if (error) { 732 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 733 return error; 734 } 735 736 error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr); 737 if (error) { 738 aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n"); 739 return error; 740 } 741 error = sdmmc_mem_decode_scr(sc, sf); 742 if (error) 743 return error; 744 745 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 746 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 747 DPRINTF(("%s: change bus width\n", SDMMCDEVNAME(sc))); 748 error = sdmmc_set_bus_width(sf, 4); 749 if (error) { 750 aprint_error_dev(sc->sc_dev, 751 "can't change bus width (%d bit)\n", 4); 752 return error; 753 } 754 sf->width = 4; 755 } 756 757 best_func = 0; 758 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 759 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 760 DPRINTF(("%s: switch func mode 0\n", SDMMCDEVNAME(sc))); 761 error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status); 762 if (error) { 763 aprint_error_dev(sc->sc_dev, 764 "switch func mode 0 failed\n"); 765 return error; 766 } 767 768 support_func = SFUNC_STATUS_GROUP(&status, 1); 769 770 for (i = 0; i < __arraycount(switch_group0_functions); i++) { 771 if (!(support_func & (1 << i))) 772 continue; 773 DPRINTF(("%s: card supports mode %s\n", 774 SDMMCDEVNAME(sc), 775 switch_group0_functions[i].name)); 776 } 777 778 best_func = sdmmc_mem_select_transfer_mode(sc, support_func); 779 780 DPRINTF(("%s: using mode %s\n", SDMMCDEVNAME(sc), 781 switch_group0_functions[best_func].name)); 782 783 if (best_func != 0) { 784 DPRINTF(("%s: switch func mode 1(func=%d)\n", 785 SDMMCDEVNAME(sc), best_func)); 786 error = 787 sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status); 788 if (error) { 789 aprint_error_dev(sc->sc_dev, 790 "switch func mode 1 failed:" 791 " group 1 function %d(0x%2x)\n", 792 best_func, support_func); 793 return error; 794 } 795 sf->csd.tran_speed = 796 switch_group0_functions[best_func].freq; 797 798 if (best_func == SD_ACCESS_MODE_DDR50) 799 ddr = true; 800 801 /* Wait 400KHz x 8 clock (2.5us * 8 + slop) */ 802 delay(25); 803 } 804 } 805 806 /* update bus clock */ 807 if (sc->sc_busclk > sf->csd.tran_speed) 808 sc->sc_busclk = sf->csd.tran_speed; 809 if (sc->sc_busclk == bus_clock && sc->sc_busddr == ddr) 810 return 0; 811 812 /* change bus clock */ 813 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk, 814 ddr); 815 if (error) { 816 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 817 return error; 818 } 819 820 sc->sc_transfer_mode = switch_group0_functions[best_func].name; 821 sc->sc_busddr = ddr; 822 823 return 0; 824 } 825 826 static int 827 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 828 { 829 int width, value, hs_timing, bus_clock, error; 830 char ext_csd[512]; 831 uint32_t sectors = 0; 832 833 sc->sc_transfer_mode = NULL; 834 835 /* change bus clock */ 836 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 837 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock, false); 838 if (error) { 839 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 840 return error; 841 } 842 843 if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 844 error = sdmmc_mem_send_cxd_data(sc, 845 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 846 if (error) { 847 aprint_error_dev(sc->sc_dev, 848 "can't read EXT_CSD (error=%d)\n", error); 849 return error; 850 } 851 if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) && 852 (ext_csd[EXT_CSD_STRUCTURE] > EXT_CSD_STRUCTURE_VER_1_2)) { 853 aprint_error_dev(sc->sc_dev, 854 "unrecognised future version (%d)\n", 855 ext_csd[EXT_CSD_STRUCTURE]); 856 return ENOTSUP; 857 } 858 859 sc->sc_transfer_mode = NULL; 860 if (ISSET(sc->sc_caps, SMC_CAPS_MMC_HS200) && 861 ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_HS200_1_8V) { 862 sf->csd.tran_speed = 200000; /* 200MHz SDR */ 863 hs_timing = 2; 864 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_52M) { 865 sf->csd.tran_speed = 52000; /* 52MHz */ 866 hs_timing = 1; 867 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_26M) { 868 sf->csd.tran_speed = 26000; /* 26MHz */ 869 hs_timing = 0; 870 } else { 871 aprint_error_dev(sc->sc_dev, 872 "unknown CARD_TYPE: 0x%x\n", 873 ext_csd[EXT_CSD_CARD_TYPE]); 874 return ENOTSUP; 875 } 876 877 if (hs_timing == 2) { 878 error = sdmmc_chip_signal_voltage(sc->sc_sct, 879 sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_180); 880 if (error) 881 hs_timing = 1; 882 } 883 884 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 885 width = 8; 886 value = EXT_CSD_BUS_WIDTH_8; 887 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 888 width = 4; 889 value = EXT_CSD_BUS_WIDTH_4; 890 } else { 891 width = 1; 892 value = EXT_CSD_BUS_WIDTH_1; 893 } 894 895 if (width != 1) { 896 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 897 EXT_CSD_BUS_WIDTH, value); 898 if (error == 0) 899 error = sdmmc_chip_bus_width(sc->sc_sct, 900 sc->sc_sch, width); 901 else { 902 DPRINTF(("%s: can't change bus width" 903 " (%d bit)\n", SDMMCDEVNAME(sc), width)); 904 return error; 905 } 906 907 /* XXXX: need bus test? (using by CMD14 & CMD19) */ 908 } 909 sf->width = width; 910 911 if (hs_timing == 1 && 912 !ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 913 hs_timing = 0; 914 } 915 if (hs_timing) { 916 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 917 EXT_CSD_HS_TIMING, hs_timing); 918 if (error) { 919 aprint_error_dev(sc->sc_dev, 920 "can't change high speed\n"); 921 return error; 922 } 923 } 924 925 if (sc->sc_busclk > sf->csd.tran_speed) 926 sc->sc_busclk = sf->csd.tran_speed; 927 if (sc->sc_busclk != bus_clock) { 928 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 929 sc->sc_busclk, false); 930 if (error) { 931 aprint_error_dev(sc->sc_dev, 932 "can't change bus clock\n"); 933 return error; 934 } 935 } 936 937 if (hs_timing) { 938 error = sdmmc_mem_send_cxd_data(sc, 939 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 940 if (error) { 941 aprint_error_dev(sc->sc_dev, 942 "can't re-read EXT_CSD\n"); 943 return error; 944 } 945 if (ext_csd[EXT_CSD_HS_TIMING] != hs_timing) { 946 aprint_error_dev(sc->sc_dev, 947 "HS_TIMING set failed\n"); 948 return EINVAL; 949 } 950 } 951 952 sectors = ext_csd[EXT_CSD_SEC_COUNT + 0] << 0 | 953 ext_csd[EXT_CSD_SEC_COUNT + 1] << 8 | 954 ext_csd[EXT_CSD_SEC_COUNT + 2] << 16 | 955 ext_csd[EXT_CSD_SEC_COUNT + 3] << 24; 956 if (sectors > (2u * 1024 * 1024 * 1024) / 512) { 957 SET(sf->flags, SFF_SDHC); 958 sf->csd.capacity = sectors; 959 } 960 961 if (hs_timing == 2) { 962 sc->sc_transfer_mode = "HS200"; 963 } else { 964 sc->sc_transfer_mode = NULL; 965 } 966 } else { 967 if (sc->sc_busclk > sf->csd.tran_speed) 968 sc->sc_busclk = sf->csd.tran_speed; 969 if (sc->sc_busclk != bus_clock) { 970 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 971 sc->sc_busclk, false); 972 if (error) { 973 aprint_error_dev(sc->sc_dev, 974 "can't change bus clock\n"); 975 return error; 976 } 977 } 978 } 979 980 return 0; 981 } 982 983 static int 984 sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp) 985 { 986 struct sdmmc_command cmd; 987 int error; 988 989 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 990 memset(&cmd, 0, sizeof cmd); 991 cmd.c_opcode = MMC_ALL_SEND_CID; 992 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 993 994 error = sdmmc_mmc_command(sc, &cmd); 995 } else { 996 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CID, &cmd.c_resp, 997 sizeof(cmd.c_resp)); 998 } 999 1000 #ifdef SDMMC_DEBUG 1001 if (error == 0) 1002 sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp)); 1003 #endif 1004 if (error == 0 && resp != NULL) 1005 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 1006 return error; 1007 } 1008 1009 static int 1010 sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf, 1011 sdmmc_response *resp) 1012 { 1013 struct sdmmc_command cmd; 1014 int error; 1015 1016 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1017 memset(&cmd, 0, sizeof cmd); 1018 cmd.c_opcode = MMC_SEND_CSD; 1019 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1020 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 1021 1022 error = sdmmc_mmc_command(sc, &cmd); 1023 } else { 1024 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CSD, &cmd.c_resp, 1025 sizeof(cmd.c_resp)); 1026 } 1027 1028 #ifdef SDMMC_DEBUG 1029 if (error == 0) 1030 sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp)); 1031 #endif 1032 if (error == 0 && resp != NULL) 1033 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 1034 return error; 1035 } 1036 1037 static int 1038 sdmmc_mem_send_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf, 1039 uint32_t *scr) 1040 { 1041 struct sdmmc_command cmd; 1042 bus_dma_segment_t ds[1]; 1043 void *ptr = NULL; 1044 int datalen = 8; 1045 int rseg; 1046 int error = 0; 1047 1048 /* Don't lock */ 1049 1050 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1051 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, 1052 ds, 1, &rseg, BUS_DMA_NOWAIT); 1053 if (error) 1054 goto out; 1055 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1056 BUS_DMA_NOWAIT); 1057 if (error) 1058 goto dmamem_free; 1059 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1060 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1061 if (error) 1062 goto dmamem_unmap; 1063 1064 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1065 BUS_DMASYNC_PREREAD); 1066 } else { 1067 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1068 if (ptr == NULL) 1069 goto out; 1070 } 1071 1072 memset(&cmd, 0, sizeof(cmd)); 1073 cmd.c_data = ptr; 1074 cmd.c_datalen = datalen; 1075 cmd.c_blklen = datalen; 1076 cmd.c_arg = 0; 1077 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1078 cmd.c_opcode = SD_APP_SEND_SCR; 1079 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1080 cmd.c_dmamap = sc->sc_dmap; 1081 1082 error = sdmmc_app_command(sc, sf, &cmd); 1083 if (error == 0) { 1084 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1085 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1086 BUS_DMASYNC_POSTREAD); 1087 } 1088 memcpy(scr, ptr, datalen); 1089 } 1090 1091 out: 1092 if (ptr != NULL) { 1093 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1094 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1095 dmamem_unmap: 1096 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1097 dmamem_free: 1098 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1099 } else { 1100 free(ptr, M_DEVBUF); 1101 } 1102 } 1103 DPRINTF(("%s: sdmem_mem_send_scr: error = %d\n", SDMMCDEVNAME(sc), 1104 error)); 1105 1106 #ifdef SDMMC_DEBUG 1107 if (error == 0) 1108 sdmmc_dump_data("SCR", scr, datalen); 1109 #endif 1110 return error; 1111 } 1112 1113 static int 1114 sdmmc_mem_decode_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf) 1115 { 1116 sdmmc_response resp; 1117 int ver; 1118 1119 memset(resp, 0, sizeof(resp)); 1120 /* 1121 * Change the raw-scr received from the DMA stream to resp. 1122 */ 1123 resp[0] = be32toh(sf->raw_scr[1]) >> 8; // LSW 1124 resp[1] = be32toh(sf->raw_scr[0]); // MSW 1125 resp[0] |= (resp[1] & 0xff) << 24; 1126 resp[1] >>= 8; 1127 1128 ver = SCR_STRUCTURE(resp); 1129 sf->scr.sd_spec = SCR_SD_SPEC(resp); 1130 sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 1131 1132 DPRINTF(("%s: sdmmc_mem_decode_scr: %08x%08x ver=%d, spec=%d, bus width=%d\n", 1133 SDMMCDEVNAME(sc), resp[1], resp[0], 1134 ver, sf->scr.sd_spec, sf->scr.bus_width)); 1135 1136 if (ver != 0 && ver != 1) { 1137 DPRINTF(("%s: unknown structure version: %d\n", 1138 SDMMCDEVNAME(sc), ver)); 1139 return EINVAL; 1140 } 1141 return 0; 1142 } 1143 1144 static int 1145 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 1146 size_t datalen) 1147 { 1148 struct sdmmc_command cmd; 1149 bus_dma_segment_t ds[1]; 1150 void *ptr = NULL; 1151 int rseg; 1152 int error = 0; 1153 1154 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1155 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, ds, 1156 1, &rseg, BUS_DMA_NOWAIT); 1157 if (error) 1158 goto out; 1159 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1160 BUS_DMA_NOWAIT); 1161 if (error) 1162 goto dmamem_free; 1163 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1164 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1165 if (error) 1166 goto dmamem_unmap; 1167 1168 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1169 BUS_DMASYNC_PREREAD); 1170 } else { 1171 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1172 if (ptr == NULL) 1173 goto out; 1174 } 1175 1176 memset(&cmd, 0, sizeof(cmd)); 1177 cmd.c_data = ptr; 1178 cmd.c_datalen = datalen; 1179 cmd.c_blklen = datalen; 1180 cmd.c_opcode = opcode; 1181 cmd.c_arg = 0; 1182 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_SPI_R1; 1183 if (opcode == MMC_SEND_EXT_CSD) 1184 SET(cmd.c_flags, SCF_RSP_R1); 1185 else 1186 SET(cmd.c_flags, SCF_RSP_R2); 1187 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1188 cmd.c_dmamap = sc->sc_dmap; 1189 1190 error = sdmmc_mmc_command(sc, &cmd); 1191 if (error == 0) { 1192 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1193 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1194 BUS_DMASYNC_POSTREAD); 1195 } 1196 memcpy(data, ptr, datalen); 1197 #ifdef SDMMC_DEBUG 1198 sdmmc_dump_data("CXD", data, datalen); 1199 #endif 1200 } 1201 1202 out: 1203 if (ptr != NULL) { 1204 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1205 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1206 dmamem_unmap: 1207 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1208 dmamem_free: 1209 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1210 } else { 1211 free(ptr, M_DEVBUF); 1212 } 1213 } 1214 return error; 1215 } 1216 1217 static int 1218 sdmmc_set_bus_width(struct sdmmc_function *sf, int width) 1219 { 1220 struct sdmmc_softc *sc = sf->sc; 1221 struct sdmmc_command cmd; 1222 int error; 1223 1224 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1225 return ENODEV; 1226 1227 memset(&cmd, 0, sizeof(cmd)); 1228 cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 1229 cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 1230 1231 switch (width) { 1232 case 1: 1233 cmd.c_arg = SD_ARG_BUS_WIDTH_1; 1234 break; 1235 1236 case 4: 1237 cmd.c_arg = SD_ARG_BUS_WIDTH_4; 1238 break; 1239 1240 default: 1241 return EINVAL; 1242 } 1243 1244 error = sdmmc_app_command(sc, sf, &cmd); 1245 if (error == 0) 1246 error = sdmmc_chip_bus_width(sc->sc_sct, sc->sc_sch, width); 1247 return error; 1248 } 1249 1250 static int 1251 sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 1252 int function, sdmmc_bitfield512_t *status) 1253 { 1254 struct sdmmc_softc *sc = sf->sc; 1255 struct sdmmc_command cmd; 1256 bus_dma_segment_t ds[1]; 1257 void *ptr = NULL; 1258 int gsft, rseg, error = 0; 1259 const int statlen = 64; 1260 1261 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 1262 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 1263 return EINVAL; 1264 1265 if (group <= 0 || group > 6 || 1266 function < 0 || function > 15) 1267 return EINVAL; 1268 1269 gsft = (group - 1) << 2; 1270 1271 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1272 error = bus_dmamem_alloc(sc->sc_dmat, statlen, PAGE_SIZE, 0, ds, 1273 1, &rseg, BUS_DMA_NOWAIT); 1274 if (error) 1275 goto out; 1276 error = bus_dmamem_map(sc->sc_dmat, ds, 1, statlen, &ptr, 1277 BUS_DMA_NOWAIT); 1278 if (error) 1279 goto dmamem_free; 1280 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, statlen, 1281 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1282 if (error) 1283 goto dmamem_unmap; 1284 1285 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1286 BUS_DMASYNC_PREREAD); 1287 } else { 1288 ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 1289 if (ptr == NULL) 1290 goto out; 1291 } 1292 1293 memset(&cmd, 0, sizeof(cmd)); 1294 cmd.c_data = ptr; 1295 cmd.c_datalen = statlen; 1296 cmd.c_blklen = statlen; 1297 cmd.c_opcode = SD_SEND_SWITCH_FUNC; 1298 cmd.c_arg = 1299 (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 1300 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1301 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1302 cmd.c_dmamap = sc->sc_dmap; 1303 1304 error = sdmmc_mmc_command(sc, &cmd); 1305 if (error == 0) { 1306 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1307 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1308 BUS_DMASYNC_POSTREAD); 1309 } 1310 memcpy(status, ptr, statlen); 1311 } 1312 1313 out: 1314 if (ptr != NULL) { 1315 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1316 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1317 dmamem_unmap: 1318 bus_dmamem_unmap(sc->sc_dmat, ptr, statlen); 1319 dmamem_free: 1320 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1321 } else { 1322 free(ptr, M_DEVBUF); 1323 } 1324 } 1325 1326 if (error == 0) 1327 sdmmc_be512_to_bitfield512(status); 1328 1329 return error; 1330 } 1331 1332 static int 1333 sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 1334 uint8_t value) 1335 { 1336 struct sdmmc_softc *sc = sf->sc; 1337 struct sdmmc_command cmd; 1338 1339 memset(&cmd, 0, sizeof(cmd)); 1340 cmd.c_opcode = MMC_SWITCH; 1341 cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 1342 (index << 16) | (value << 8) | set; 1343 cmd.c_flags = SCF_RSP_SPI_R1B | SCF_RSP_R1B | SCF_CMD_AC; 1344 1345 return sdmmc_mmc_command(sc, &cmd); 1346 } 1347 1348 /* 1349 * SPI mode function 1350 */ 1351 static int 1352 sdmmc_mem_spi_read_ocr(struct sdmmc_softc *sc, uint32_t hcs, uint32_t *card_ocr) 1353 { 1354 struct sdmmc_command cmd; 1355 int error; 1356 1357 memset(&cmd, 0, sizeof(cmd)); 1358 cmd.c_opcode = MMC_READ_OCR; 1359 cmd.c_arg = hcs ? MMC_OCR_HCS : 0; 1360 cmd.c_flags = SCF_RSP_SPI_R3; 1361 1362 error = sdmmc_mmc_command(sc, &cmd); 1363 if (error == 0 && card_ocr != NULL) 1364 *card_ocr = cmd.c_resp[1]; 1365 DPRINTF(("%s: sdmmc_mem_spi_read_ocr: error=%d, ocr=%#x\n", 1366 SDMMCDEVNAME(sc), error, cmd.c_resp[1])); 1367 return error; 1368 } 1369 1370 /* 1371 * read/write function 1372 */ 1373 /* read */ 1374 static int 1375 sdmmc_mem_single_read_block(struct sdmmc_function *sf, uint32_t blkno, 1376 u_char *data, size_t datalen) 1377 { 1378 struct sdmmc_softc *sc = sf->sc; 1379 int error = 0; 1380 int i; 1381 1382 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1383 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1384 1385 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1386 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno + i, 1387 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1388 if (error) 1389 break; 1390 } 1391 return error; 1392 } 1393 1394 /* 1395 * Simulate multi-segment dma transfer. 1396 */ 1397 static int 1398 sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *sf, 1399 uint32_t blkno, u_char *data, size_t datalen) 1400 { 1401 struct sdmmc_softc *sc = sf->sc; 1402 bool use_bbuf = false; 1403 int error = 0; 1404 int i; 1405 1406 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1407 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1408 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1409 use_bbuf = true; 1410 break; 1411 } 1412 } 1413 if (use_bbuf) { 1414 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1415 BUS_DMASYNC_PREREAD); 1416 1417 error = sdmmc_mem_read_block_subr(sf, sf->bbuf_dmap, 1418 blkno, data, datalen); 1419 if (error) { 1420 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1421 return error; 1422 } 1423 1424 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1425 BUS_DMASYNC_POSTREAD); 1426 1427 /* Copy from bounce buffer */ 1428 memcpy(data, sf->bbuf, datalen); 1429 1430 return 0; 1431 } 1432 1433 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1434 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1435 1436 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1437 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_READ); 1438 if (error) 1439 return error; 1440 1441 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1442 BUS_DMASYNC_PREREAD); 1443 1444 error = sdmmc_mem_read_block_subr(sf, sf->sseg_dmap, 1445 blkno, data, len); 1446 if (error) { 1447 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1448 return error; 1449 } 1450 1451 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1452 BUS_DMASYNC_POSTREAD); 1453 1454 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1455 1456 blkno += len / SDMMC_SECTOR_SIZE; 1457 data += len; 1458 } 1459 return 0; 1460 } 1461 1462 static int 1463 sdmmc_mem_read_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1464 uint32_t blkno, u_char *data, size_t datalen) 1465 { 1466 struct sdmmc_softc *sc = sf->sc; 1467 struct sdmmc_command cmd; 1468 int error; 1469 1470 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1471 error = sdmmc_select_card(sc, sf); 1472 if (error) 1473 goto out; 1474 } 1475 1476 memset(&cmd, 0, sizeof(cmd)); 1477 cmd.c_data = data; 1478 cmd.c_datalen = datalen; 1479 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1480 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1481 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1482 cmd.c_arg = blkno; 1483 if (!ISSET(sf->flags, SFF_SDHC)) 1484 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1485 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1486 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1487 cmd.c_dmamap = dmap; 1488 1489 error = sdmmc_mmc_command(sc, &cmd); 1490 if (error) 1491 goto out; 1492 1493 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1494 if (cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 1495 memset(&cmd, 0, sizeof cmd); 1496 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1497 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1498 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1499 error = sdmmc_mmc_command(sc, &cmd); 1500 if (error) 1501 goto out; 1502 } 1503 } 1504 1505 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1506 do { 1507 memset(&cmd, 0, sizeof(cmd)); 1508 cmd.c_opcode = MMC_SEND_STATUS; 1509 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1510 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1511 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1512 error = sdmmc_mmc_command(sc, &cmd); 1513 if (error) 1514 break; 1515 /* XXX time out */ 1516 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1517 } 1518 1519 out: 1520 return error; 1521 } 1522 1523 int 1524 sdmmc_mem_read_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1525 size_t datalen) 1526 { 1527 struct sdmmc_softc *sc = sf->sc; 1528 int error; 1529 1530 SDMMC_LOCK(sc); 1531 mutex_enter(&sc->sc_mtx); 1532 1533 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1534 error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 1535 goto out; 1536 } 1537 1538 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1539 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1540 datalen); 1541 goto out; 1542 } 1543 1544 /* DMA transfer */ 1545 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1546 BUS_DMA_NOWAIT|BUS_DMA_READ); 1547 if (error) 1548 goto out; 1549 1550 #ifdef SDMMC_DEBUG 1551 printf("data=%p, datalen=%zu\n", data, datalen); 1552 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1553 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1554 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1555 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1556 } 1557 #endif 1558 1559 if (sc->sc_dmap->dm_nsegs > 1 1560 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1561 error = sdmmc_mem_single_segment_dma_read_block(sf, blkno, 1562 data, datalen); 1563 goto unload; 1564 } 1565 1566 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1567 BUS_DMASYNC_PREREAD); 1568 1569 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1570 datalen); 1571 if (error) 1572 goto unload; 1573 1574 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1575 BUS_DMASYNC_POSTREAD); 1576 unload: 1577 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1578 1579 out: 1580 mutex_exit(&sc->sc_mtx); 1581 SDMMC_UNLOCK(sc); 1582 1583 return error; 1584 } 1585 1586 /* write */ 1587 static int 1588 sdmmc_mem_single_write_block(struct sdmmc_function *sf, uint32_t blkno, 1589 u_char *data, size_t datalen) 1590 { 1591 struct sdmmc_softc *sc = sf->sc; 1592 int error = 0; 1593 int i; 1594 1595 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1596 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1597 1598 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1599 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno + i, 1600 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1601 if (error) 1602 break; 1603 } 1604 return error; 1605 } 1606 1607 /* 1608 * Simulate multi-segment dma transfer. 1609 */ 1610 static int 1611 sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *sf, 1612 uint32_t blkno, u_char *data, size_t datalen) 1613 { 1614 struct sdmmc_softc *sc = sf->sc; 1615 bool use_bbuf = false; 1616 int error = 0; 1617 int i; 1618 1619 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1620 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1621 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1622 use_bbuf = true; 1623 break; 1624 } 1625 } 1626 if (use_bbuf) { 1627 /* Copy to bounce buffer */ 1628 memcpy(sf->bbuf, data, datalen); 1629 1630 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1631 BUS_DMASYNC_PREWRITE); 1632 1633 error = sdmmc_mem_write_block_subr(sf, sf->bbuf_dmap, 1634 blkno, data, datalen); 1635 if (error) { 1636 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1637 return error; 1638 } 1639 1640 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1641 BUS_DMASYNC_POSTWRITE); 1642 1643 return 0; 1644 } 1645 1646 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1647 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1648 1649 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1650 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1651 if (error) 1652 return error; 1653 1654 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1655 BUS_DMASYNC_PREWRITE); 1656 1657 error = sdmmc_mem_write_block_subr(sf, sf->sseg_dmap, 1658 blkno, data, len); 1659 if (error) { 1660 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1661 return error; 1662 } 1663 1664 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1665 BUS_DMASYNC_POSTWRITE); 1666 1667 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1668 1669 blkno += len / SDMMC_SECTOR_SIZE; 1670 data += len; 1671 } 1672 1673 return error; 1674 } 1675 1676 static int 1677 sdmmc_mem_write_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1678 uint32_t blkno, u_char *data, size_t datalen) 1679 { 1680 struct sdmmc_softc *sc = sf->sc; 1681 struct sdmmc_command cmd; 1682 int error; 1683 1684 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1685 error = sdmmc_select_card(sc, sf); 1686 if (error) 1687 goto out; 1688 } 1689 1690 memset(&cmd, 0, sizeof(cmd)); 1691 cmd.c_data = data; 1692 cmd.c_datalen = datalen; 1693 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1694 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1695 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1696 cmd.c_arg = blkno; 1697 if (!ISSET(sf->flags, SFF_SDHC)) 1698 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1699 cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 1700 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1701 cmd.c_dmamap = dmap; 1702 1703 error = sdmmc_mmc_command(sc, &cmd); 1704 if (error) 1705 goto out; 1706 1707 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1708 if (cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1709 memset(&cmd, 0, sizeof(cmd)); 1710 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1711 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1712 error = sdmmc_mmc_command(sc, &cmd); 1713 if (error) 1714 goto out; 1715 } 1716 } 1717 1718 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1719 do { 1720 memset(&cmd, 0, sizeof(cmd)); 1721 cmd.c_opcode = MMC_SEND_STATUS; 1722 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1723 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1724 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1725 error = sdmmc_mmc_command(sc, &cmd); 1726 if (error) 1727 break; 1728 /* XXX time out */ 1729 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1730 } 1731 1732 out: 1733 return error; 1734 } 1735 1736 int 1737 sdmmc_mem_write_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1738 size_t datalen) 1739 { 1740 struct sdmmc_softc *sc = sf->sc; 1741 int error; 1742 1743 SDMMC_LOCK(sc); 1744 mutex_enter(&sc->sc_mtx); 1745 1746 if (sdmmc_chip_write_protect(sc->sc_sct, sc->sc_sch)) { 1747 aprint_normal_dev(sc->sc_dev, "write-protected\n"); 1748 error = EIO; 1749 goto out; 1750 } 1751 1752 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1753 error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1754 goto out; 1755 } 1756 1757 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1758 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1759 datalen); 1760 goto out; 1761 } 1762 1763 /* DMA transfer */ 1764 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1765 BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1766 if (error) 1767 goto out; 1768 1769 #ifdef SDMMC_DEBUG 1770 aprint_normal_dev(sc->sc_dev, "%s: data=%p, datalen=%zu\n", 1771 __func__, data, datalen); 1772 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1773 aprint_normal_dev(sc->sc_dev, 1774 "%s: seg#%d: addr=%#lx, size=%#lx\n", __func__, i, 1775 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1776 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1777 } 1778 #endif 1779 1780 if (sc->sc_dmap->dm_nsegs > 1 1781 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1782 error = sdmmc_mem_single_segment_dma_write_block(sf, blkno, 1783 data, datalen); 1784 goto unload; 1785 } 1786 1787 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1788 BUS_DMASYNC_PREWRITE); 1789 1790 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1791 datalen); 1792 if (error) 1793 goto unload; 1794 1795 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1796 BUS_DMASYNC_POSTWRITE); 1797 unload: 1798 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1799 1800 out: 1801 mutex_exit(&sc->sc_mtx); 1802 SDMMC_UNLOCK(sc); 1803 1804 return error; 1805 } 1806
Indexes created Wed Sep 24 05:09:52 GMT 2025