sdmmc_mem.c revision 1.43
1 /* $NetBSD: sdmmc_mem.c,v 1.43 2015/08/04 00:32:05 jmcneill Exp $ */ 2 /* $OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2007, 2008, 2009, 2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 /* Routines for SD/MMC memory cards. */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.43 2015/08/04 00:32:05 jmcneill Exp $"); 49 50 #ifdef _KERNEL_OPT 51 #include "opt_sdmmc.h" 52 #endif 53 54 #include <sys/param.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 60 #include <dev/sdmmc/sdmmcchip.h> 61 #include <dev/sdmmc/sdmmcreg.h> 62 #include <dev/sdmmc/sdmmcvar.h> 63 64 #ifdef SDMMC_DEBUG 65 #define DPRINTF(s) do { printf s; } while (/*CONSTCOND*/0) 66 #else 67 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 68 #endif 69 70 typedef struct { uint32_t _bits[512/32]; } __packed __aligned(4) sdmmc_bitfield512_t; 71 72 static int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 73 static int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 74 static int sdmmc_mem_send_cid(struct sdmmc_softc *, sdmmc_response *); 75 static int sdmmc_mem_send_csd(struct sdmmc_softc *, struct sdmmc_function *, 76 sdmmc_response *); 77 static int sdmmc_mem_send_scr(struct sdmmc_softc *, struct sdmmc_function *, 78 uint32_t *scr); 79 static int sdmmc_mem_decode_scr(struct sdmmc_softc *, struct sdmmc_function *); 80 static int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 81 static int sdmmc_set_bus_width(struct sdmmc_function *, int); 82 static int sdmmc_mem_sd_switch(struct sdmmc_function *, int, int, int, sdmmc_bitfield512_t *); 83 static int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, 84 uint8_t); 85 static int sdmmc_mem_spi_read_ocr(struct sdmmc_softc *, uint32_t, uint32_t *); 86 static int sdmmc_mem_single_read_block(struct sdmmc_function *, uint32_t, 87 u_char *, size_t); 88 static int sdmmc_mem_single_write_block(struct sdmmc_function *, uint32_t, 89 u_char *, size_t); 90 static int sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *, 91 uint32_t, u_char *, size_t); 92 static int sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *, 93 uint32_t, u_char *, size_t); 94 static int sdmmc_mem_read_block_subr(struct sdmmc_function *, bus_dmamap_t, 95 uint32_t, u_char *, size_t); 96 static int sdmmc_mem_write_block_subr(struct sdmmc_function *, bus_dmamap_t, 97 uint32_t, u_char *, size_t); 98 99 static const struct { 100 const char *name; 101 int v; 102 int freq; 103 } switch_group0_functions[] = { 104 /* Default/SDR12 */ 105 { "Default/SDR12", 0, 25000 }, 106 107 /* High-Speed/SDR25 */ 108 { "High-Speed/SDR25", SMC_CAPS_SD_HIGHSPEED, 50000 }, 109 110 /* SDR50 */ 111 { "SDR50", SMC_CAPS_UHS_SDR50, 100000 }, 112 113 /* SDR104 */ 114 { "SDR104", SMC_CAPS_UHS_SDR104, 208000 }, 115 116 /* DDR50 */ 117 { "DDR50", SMC_CAPS_UHS_DDR50, 50000 }, 118 }; 119 120 /* 121 * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 122 */ 123 int 124 sdmmc_mem_enable(struct sdmmc_softc *sc) 125 { 126 uint32_t host_ocr; 127 uint32_t card_ocr; 128 uint32_t new_ocr; 129 uint32_t ocr = 0; 130 int error; 131 132 SDMMC_LOCK(sc); 133 134 /* Set host mode to SD "combo" card or SD memory-only. */ 135 CLR(sc->sc_flags, SMF_UHS_MODE); 136 SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 137 138 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 139 sdmmc_spi_chip_initialize(sc->sc_spi_sct, sc->sc_sch); 140 141 /* Set 3.3V signaling */ 142 if (sc->sc_sct->signal_voltage) { 143 error = sdmmc_chip_signal_voltage(sc->sc_sct, 144 sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_330); 145 if (error) 146 goto out; 147 148 delay(5000); 149 } 150 151 /* Reset memory (*must* do that before CMD55 or CMD1). */ 152 sdmmc_go_idle_state(sc); 153 154 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 155 /* Check SD Ver.2 */ 156 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 157 if (error == 0 && card_ocr == 0x1aa) 158 SET(ocr, MMC_OCR_HCS); 159 } 160 161 /* 162 * Read the SD/MMC memory OCR value by issuing CMD55 followed 163 * by ACMD41 to read the OCR value from memory-only SD cards. 164 * MMC cards will not respond to CMD55 or ACMD41 and this is 165 * how we distinguish them from SD cards. 166 */ 167 mmc_mode: 168 error = sdmmc_mem_send_op_cond(sc, 169 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr); 170 if (error) { 171 if (ISSET(sc->sc_flags, SMF_SD_MODE) && 172 !ISSET(sc->sc_flags, SMF_IO_MODE)) { 173 /* Not a SD card, switch to MMC mode. */ 174 DPRINTF(("%s: switch to MMC mode\n", SDMMCDEVNAME(sc))); 175 CLR(sc->sc_flags, SMF_SD_MODE); 176 goto mmc_mode; 177 } 178 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 179 DPRINTF(("%s: couldn't read memory OCR\n", 180 SDMMCDEVNAME(sc))); 181 goto out; 182 } else { 183 /* Not a "combo" card. */ 184 CLR(sc->sc_flags, SMF_MEM_MODE); 185 error = 0; 186 goto out; 187 } 188 } 189 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 190 /* get card OCR */ 191 error = sdmmc_mem_spi_read_ocr(sc, ocr, &card_ocr); 192 if (error) { 193 DPRINTF(("%s: couldn't read SPI memory OCR\n", 194 SDMMCDEVNAME(sc))); 195 goto out; 196 } 197 } 198 199 /* Set the lowest voltage supported by the card and host. */ 200 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 201 error = sdmmc_set_bus_power(sc, host_ocr, card_ocr); 202 if (error) { 203 DPRINTF(("%s: couldn't supply voltage requested by card\n", 204 SDMMCDEVNAME(sc))); 205 goto out; 206 } 207 208 /* Tell the card(s) to enter the idle state (again). */ 209 sdmmc_go_idle_state(sc); 210 211 DPRINTF(("%s: host_ocr 0x%08x\n", SDMMCDEVNAME(sc), host_ocr)); 212 DPRINTF(("%s: card_ocr 0x%08x\n", SDMMCDEVNAME(sc), card_ocr)); 213 214 host_ocr &= card_ocr; /* only allow the common voltages */ 215 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 216 /* Check SD Ver.2 */ 217 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 218 if (error == 0 && card_ocr == 0x1aa) 219 SET(ocr, MMC_OCR_HCS); 220 221 if (sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch) & MMC_OCR_S18A) 222 SET(ocr, MMC_OCR_S18A); 223 } 224 host_ocr |= ocr; 225 226 /* Send the new OCR value until all cards are ready. */ 227 error = sdmmc_mem_send_op_cond(sc, host_ocr, &new_ocr); 228 if (error) { 229 DPRINTF(("%s: couldn't send memory OCR\n", SDMMCDEVNAME(sc))); 230 goto out; 231 } 232 233 if (ISSET(new_ocr, MMC_OCR_S18A) && sc->sc_sct->signal_voltage) { 234 /* 235 * Card and host support low voltage mode, begin switch 236 * sequence. 237 */ 238 struct sdmmc_command cmd; 239 memset(&cmd, 0, sizeof(cmd)); 240 cmd.c_arg = 0; 241 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 242 cmd.c_opcode = SD_VOLTAGE_SWITCH; 243 DPRINTF(("%s: switching card to 1.8V\n", SDMMCDEVNAME(sc))); 244 error = sdmmc_mmc_command(sc, &cmd); 245 if (error) { 246 DPRINTF(("%s: voltage switch command failed\n", 247 SDMMCDEVNAME(sc))); 248 goto out; 249 } 250 251 delay(1000); 252 253 /* 254 * Stop the clock 255 */ 256 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 257 SDMMC_SDCLK_OFF, false); 258 if (error) 259 goto out; 260 261 delay(1000); 262 263 /* 264 * Card switch command was successful, update host controller 265 * signal voltage setting. 266 */ 267 DPRINTF(("%s: switching host to 1.8V\n", SDMMCDEVNAME(sc))); 268 error = sdmmc_chip_signal_voltage(sc->sc_sct, 269 sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_180); 270 if (error) 271 goto out; 272 273 delay(5000); 274 275 /* 276 * Switch to SDR12 timing 277 */ 278 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 25000, 279 false); 280 if (error) 281 goto out; 282 283 delay(1000); 284 285 SET(sc->sc_flags, SMF_UHS_MODE); 286 } 287 288 out: 289 SDMMC_UNLOCK(sc); 290 291 if (error) 292 printf("%s: %s failed with error %d\n", SDMMCDEVNAME(sc), 293 __func__, error); 294 295 return error; 296 } 297 298 /* 299 * Read the CSD and CID from all cards and assign each card a unique 300 * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 301 */ 302 void 303 sdmmc_mem_scan(struct sdmmc_softc *sc) 304 { 305 sdmmc_response resp; 306 struct sdmmc_function *sf; 307 uint16_t next_rca; 308 int error; 309 int retry; 310 311 SDMMC_LOCK(sc); 312 313 /* 314 * CMD2 is a broadcast command understood by SD cards and MMC 315 * cards. All cards begin to respond to the command, but back 316 * off if another card drives the CMD line to a different level. 317 * Only one card will get its entire response through. That 318 * card remains silent once it has been assigned a RCA. 319 */ 320 for (retry = 0; retry < 100; retry++) { 321 error = sdmmc_mem_send_cid(sc, &resp); 322 if (error) { 323 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && 324 error == ETIMEDOUT) { 325 /* No more cards there. */ 326 break; 327 } 328 DPRINTF(("%s: couldn't read CID\n", SDMMCDEVNAME(sc))); 329 break; 330 } 331 332 /* In MMC mode, find the next available RCA. */ 333 next_rca = 1; 334 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 335 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) 336 next_rca++; 337 } 338 339 /* Allocate a sdmmc_function structure. */ 340 sf = sdmmc_function_alloc(sc); 341 sf->rca = next_rca; 342 343 /* 344 * Remember the CID returned in the CMD2 response for 345 * later decoding. 346 */ 347 memcpy(sf->raw_cid, resp, sizeof(sf->raw_cid)); 348 349 /* 350 * Silence the card by assigning it a unique RCA, or 351 * querying it for its RCA in the case of SD. 352 */ 353 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 354 if (sdmmc_set_relative_addr(sc, sf) != 0) { 355 aprint_error_dev(sc->sc_dev, 356 "couldn't set mem RCA\n"); 357 sdmmc_function_free(sf); 358 break; 359 } 360 } 361 362 /* 363 * If this is a memory-only card, the card responding 364 * first becomes an alias for SDIO function 0. 365 */ 366 if (sc->sc_fn0 == NULL) 367 sc->sc_fn0 = sf; 368 369 SIMPLEQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 370 371 /* only one function in SPI mode */ 372 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 373 break; 374 } 375 376 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 377 /* Go to Data Transfer Mode, if possible. */ 378 sdmmc_chip_bus_rod(sc->sc_sct, sc->sc_sch, 0); 379 380 /* 381 * All cards are either inactive or awaiting further commands. 382 * Read the CSDs and decode the raw CID for each card. 383 */ 384 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) { 385 error = sdmmc_mem_send_csd(sc, sf, &resp); 386 if (error) { 387 SET(sf->flags, SFF_ERROR); 388 continue; 389 } 390 391 if (sdmmc_decode_csd(sc, resp, sf) != 0 || 392 sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 393 SET(sf->flags, SFF_ERROR); 394 continue; 395 } 396 397 #ifdef SDMMC_DEBUG 398 printf("%s: CID: ", SDMMCDEVNAME(sc)); 399 sdmmc_print_cid(&sf->cid); 400 #endif 401 } 402 403 SDMMC_UNLOCK(sc); 404 } 405 406 int 407 sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 408 struct sdmmc_function *sf) 409 { 410 /* TRAN_SPEED(2:0): transfer rate exponent */ 411 static const int speed_exponent[8] = { 412 100 * 1, /* 100 Kbits/s */ 413 1 * 1000, /* 1 Mbits/s */ 414 10 * 1000, /* 10 Mbits/s */ 415 100 * 1000, /* 100 Mbits/s */ 416 0, 417 0, 418 0, 419 0, 420 }; 421 /* TRAN_SPEED(6:3): time mantissa */ 422 static const int speed_mantissa[16] = { 423 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 424 }; 425 struct sdmmc_csd *csd = &sf->csd; 426 int e, m; 427 428 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 429 /* 430 * CSD version 1.0 corresponds to SD system 431 * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 432 */ 433 csd->csdver = SD_CSD_CSDVER(resp); 434 switch (csd->csdver) { 435 case SD_CSD_CSDVER_2_0: 436 DPRINTF(("%s: SD Ver.2.0\n", SDMMCDEVNAME(sc))); 437 SET(sf->flags, SFF_SDHC); 438 csd->capacity = SD_CSD_V2_CAPACITY(resp); 439 csd->read_bl_len = SD_CSD_V2_BL_LEN; 440 break; 441 442 case SD_CSD_CSDVER_1_0: 443 DPRINTF(("%s: SD Ver.1.0\n", SDMMCDEVNAME(sc))); 444 csd->capacity = SD_CSD_CAPACITY(resp); 445 csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 446 break; 447 448 default: 449 aprint_error_dev(sc->sc_dev, 450 "unknown SD CSD structure version 0x%x\n", 451 csd->csdver); 452 return 1; 453 } 454 455 csd->mmcver = SD_CSD_MMCVER(resp); 456 csd->write_bl_len = SD_CSD_WRITE_BL_LEN(resp); 457 csd->r2w_factor = SD_CSD_R2W_FACTOR(resp); 458 e = SD_CSD_SPEED_EXP(resp); 459 m = SD_CSD_SPEED_MANT(resp); 460 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 461 csd->ccc = SD_CSD_CCC(resp); 462 } else { 463 csd->csdver = MMC_CSD_CSDVER(resp); 464 if (csd->csdver == MMC_CSD_CSDVER_1_0) { 465 aprint_error_dev(sc->sc_dev, 466 "unknown MMC CSD structure version 0x%x\n", 467 csd->csdver); 468 return 1; 469 } 470 471 csd->mmcver = MMC_CSD_MMCVER(resp); 472 csd->capacity = MMC_CSD_CAPACITY(resp); 473 csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 474 csd->write_bl_len = MMC_CSD_WRITE_BL_LEN(resp); 475 csd->r2w_factor = MMC_CSD_R2W_FACTOR(resp); 476 e = MMC_CSD_TRAN_SPEED_EXP(resp); 477 m = MMC_CSD_TRAN_SPEED_MANT(resp); 478 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 479 } 480 if ((1 << csd->read_bl_len) > SDMMC_SECTOR_SIZE) 481 csd->capacity *= (1 << csd->read_bl_len) / SDMMC_SECTOR_SIZE; 482 483 #ifdef SDMMC_DUMP_CSD 484 sdmmc_print_csd(resp, csd); 485 #endif 486 487 return 0; 488 } 489 490 int 491 sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 492 struct sdmmc_function *sf) 493 { 494 struct sdmmc_cid *cid = &sf->cid; 495 496 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 497 cid->mid = SD_CID_MID(resp); 498 cid->oid = SD_CID_OID(resp); 499 SD_CID_PNM_CPY(resp, cid->pnm); 500 cid->rev = SD_CID_REV(resp); 501 cid->psn = SD_CID_PSN(resp); 502 cid->mdt = SD_CID_MDT(resp); 503 } else { 504 switch(sf->csd.mmcver) { 505 case MMC_CSD_MMCVER_1_0: 506 case MMC_CSD_MMCVER_1_4: 507 cid->mid = MMC_CID_MID_V1(resp); 508 MMC_CID_PNM_V1_CPY(resp, cid->pnm); 509 cid->rev = MMC_CID_REV_V1(resp); 510 cid->psn = MMC_CID_PSN_V1(resp); 511 cid->mdt = MMC_CID_MDT_V1(resp); 512 break; 513 case MMC_CSD_MMCVER_2_0: 514 case MMC_CSD_MMCVER_3_1: 515 case MMC_CSD_MMCVER_4_0: 516 cid->mid = MMC_CID_MID_V2(resp); 517 cid->oid = MMC_CID_OID_V2(resp); 518 MMC_CID_PNM_V2_CPY(resp, cid->pnm); 519 cid->psn = MMC_CID_PSN_V2(resp); 520 break; 521 default: 522 aprint_error_dev(sc->sc_dev, "unknown MMC version %d\n", 523 sf->csd.mmcver); 524 return 1; 525 } 526 } 527 return 0; 528 } 529 530 void 531 sdmmc_print_cid(struct sdmmc_cid *cid) 532 { 533 534 printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 535 " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 536 cid->mdt); 537 } 538 539 #ifdef SDMMC_DUMP_CSD 540 void 541 sdmmc_print_csd(sdmmc_response resp, struct sdmmc_csd *csd) 542 { 543 544 printf("csdver = %d\n", csd->csdver); 545 printf("mmcver = %d\n", csd->mmcver); 546 printf("capacity = 0x%08x\n", csd->capacity); 547 printf("read_bl_len = %d\n", csd->read_bl_len); 548 printf("write_bl_len = %d\n", csd->write_bl_len); 549 printf("r2w_factor = %d\n", csd->r2w_factor); 550 printf("tran_speed = %d\n", csd->tran_speed); 551 printf("ccc = 0x%x\n", csd->ccc); 552 } 553 #endif 554 555 /* 556 * Initialize a SD/MMC memory card. 557 */ 558 int 559 sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 560 { 561 int error = 0; 562 563 SDMMC_LOCK(sc); 564 565 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 566 error = sdmmc_select_card(sc, sf); 567 if (error) 568 goto out; 569 } 570 571 error = sdmmc_mem_set_blocklen(sc, sf, SDMMC_SECTOR_SIZE); 572 if (error) 573 goto out; 574 575 if (ISSET(sc->sc_flags, SMF_SD_MODE)) 576 error = sdmmc_mem_sd_init(sc, sf); 577 else 578 error = sdmmc_mem_mmc_init(sc, sf); 579 580 out: 581 SDMMC_UNLOCK(sc); 582 583 return error; 584 } 585 586 /* 587 * Get or set the card's memory OCR value (SD or MMC). 588 */ 589 int 590 sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 591 { 592 struct sdmmc_command cmd; 593 int error; 594 int retry; 595 596 /* Don't lock */ 597 598 DPRINTF(("%s: sdmmc_mem_send_op_cond: ocr=%#x\n", 599 SDMMCDEVNAME(sc), ocr)); 600 601 /* 602 * If we change the OCR value, retry the command until the OCR 603 * we receive in response has the "CARD BUSY" bit set, meaning 604 * that all cards are ready for identification. 605 */ 606 for (retry = 0; retry < 100; retry++) { 607 memset(&cmd, 0, sizeof(cmd)); 608 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? 609 ocr : (ocr & MMC_OCR_HCS); 610 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3 | SCF_RSP_SPI_R1; 611 612 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 613 cmd.c_opcode = SD_APP_OP_COND; 614 error = sdmmc_app_command(sc, NULL, &cmd); 615 } else { 616 cmd.c_opcode = MMC_SEND_OP_COND; 617 error = sdmmc_mmc_command(sc, &cmd); 618 } 619 if (error) 620 break; 621 622 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 623 if (!ISSET(MMC_SPI_R1(cmd.c_resp), R1_SPI_IDLE)) 624 break; 625 } else { 626 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 627 ocr == 0) 628 break; 629 } 630 631 error = ETIMEDOUT; 632 sdmmc_delay(10000); 633 } 634 if (error == 0 && 635 ocrp != NULL && 636 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 637 *ocrp = MMC_R3(cmd.c_resp); 638 DPRINTF(("%s: sdmmc_mem_send_op_cond: error=%d, ocr=%#x\n", 639 SDMMCDEVNAME(sc), error, MMC_R3(cmd.c_resp))); 640 return error; 641 } 642 643 int 644 sdmmc_mem_send_if_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 645 { 646 struct sdmmc_command cmd; 647 int error; 648 649 /* Don't lock */ 650 651 memset(&cmd, 0, sizeof(cmd)); 652 cmd.c_arg = ocr; 653 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R7 | SCF_RSP_SPI_R7; 654 cmd.c_opcode = SD_SEND_IF_COND; 655 656 error = sdmmc_mmc_command(sc, &cmd); 657 if (error == 0 && ocrp != NULL) { 658 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 659 *ocrp = MMC_SPI_R7(cmd.c_resp); 660 } else { 661 *ocrp = MMC_R7(cmd.c_resp); 662 } 663 DPRINTF(("%s: sdmmc_mem_send_if_cond: error=%d, ocr=%#x\n", 664 SDMMCDEVNAME(sc), error, *ocrp)); 665 } 666 return error; 667 } 668 669 /* 670 * Set the read block length appropriately for this card, according to 671 * the card CSD register value. 672 */ 673 int 674 sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf, 675 int block_len) 676 { 677 struct sdmmc_command cmd; 678 int error; 679 680 /* Don't lock */ 681 682 memset(&cmd, 0, sizeof(cmd)); 683 cmd.c_opcode = MMC_SET_BLOCKLEN; 684 cmd.c_arg = block_len; 685 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1; 686 687 error = sdmmc_mmc_command(sc, &cmd); 688 689 DPRINTF(("%s: sdmmc_mem_set_blocklen: read_bl_len=%d sector_size=%d\n", 690 SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, block_len)); 691 692 return error; 693 } 694 695 /* make 512-bit BE quantity __bitfield()-compatible */ 696 static void 697 sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) { 698 size_t i; 699 uint32_t tmp0, tmp1; 700 const size_t bitswords = __arraycount(buf->_bits); 701 for (i = 0; i < bitswords/2; i++) { 702 tmp0 = buf->_bits[i]; 703 tmp1 = buf->_bits[bitswords - 1 - i]; 704 buf->_bits[i] = be32toh(tmp1); 705 buf->_bits[bitswords - 1 - i] = be32toh(tmp0); 706 } 707 } 708 709 static int 710 sdmmc_mem_select_transfer_mode(struct sdmmc_softc *sc, int support_func) 711 { 712 if (ISSET(sc->sc_flags, SMF_UHS_MODE)) { 713 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR104) && 714 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR104)) { 715 return SD_ACCESS_MODE_SDR104; 716 } 717 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_DDR50) && 718 ISSET(support_func, 1 << SD_ACCESS_MODE_DDR50)) { 719 return SD_ACCESS_MODE_DDR50; 720 } 721 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR50) && 722 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR50)) { 723 return SD_ACCESS_MODE_SDR50; 724 } 725 } 726 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) && 727 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR25)) { 728 return SD_ACCESS_MODE_SDR25; 729 } 730 return SD_ACCESS_MODE_SDR12; 731 } 732 733 static int 734 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 735 { 736 int support_func, best_func, bus_clock, error, i; 737 sdmmc_bitfield512_t status; /* Switch Function Status */ 738 bool ddr = false; 739 740 /* change bus clock */ 741 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 742 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock, false); 743 if (error) { 744 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 745 return error; 746 } 747 748 error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr); 749 if (error) { 750 aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n"); 751 return error; 752 } 753 error = sdmmc_mem_decode_scr(sc, sf); 754 if (error) 755 return error; 756 757 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 758 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 759 DPRINTF(("%s: change bus width\n", SDMMCDEVNAME(sc))); 760 error = sdmmc_set_bus_width(sf, 4); 761 if (error) { 762 aprint_error_dev(sc->sc_dev, 763 "can't change bus width (%d bit)\n", 4); 764 return error; 765 } 766 sf->width = 4; 767 } 768 769 best_func = 0; 770 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 771 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 772 DPRINTF(("%s: switch func mode 0\n", SDMMCDEVNAME(sc))); 773 error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status); 774 if (error) { 775 aprint_error_dev(sc->sc_dev, 776 "switch func mode 0 failed\n"); 777 return error; 778 } 779 780 support_func = SFUNC_STATUS_GROUP(&status, 1); 781 782 for (i = 0; i < __arraycount(switch_group0_functions); i++) { 783 if (!(support_func & (1 << i))) 784 continue; 785 DPRINTF(("%s: card supports mode %s\n", 786 SDMMCDEVNAME(sc), 787 switch_group0_functions[i].name)); 788 } 789 790 best_func = sdmmc_mem_select_transfer_mode(sc, support_func); 791 792 DPRINTF(("%s: using mode %s\n", SDMMCDEVNAME(sc), 793 switch_group0_functions[best_func].name)); 794 795 if (best_func != 0) { 796 DPRINTF(("%s: switch func mode 1(func=%d)\n", 797 SDMMCDEVNAME(sc), best_func)); 798 error = 799 sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status); 800 if (error) { 801 aprint_error_dev(sc->sc_dev, 802 "switch func mode 1 failed:" 803 " group 1 function %d(0x%2x)\n", 804 best_func, support_func); 805 return error; 806 } 807 sf->csd.tran_speed = 808 switch_group0_functions[best_func].freq; 809 810 if (best_func == SD_ACCESS_MODE_DDR50) 811 ddr = true; 812 813 /* Wait 400KHz x 8 clock (2.5us * 8 + slop) */ 814 delay(25); 815 } 816 } 817 818 /* update bus clock */ 819 if (sc->sc_busclk > sf->csd.tran_speed) 820 sc->sc_busclk = sf->csd.tran_speed; 821 if (sc->sc_busclk == bus_clock && sc->sc_busddr == ddr) 822 return 0; 823 824 /* change bus clock */ 825 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk, 826 ddr); 827 if (error) { 828 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 829 return error; 830 } 831 832 sc->sc_transfer_mode = switch_group0_functions[best_func].name; 833 sc->sc_busddr = ddr; 834 835 return 0; 836 } 837 838 static int 839 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 840 { 841 int width, value, hs_timing, bus_clock, error; 842 char ext_csd[512]; 843 uint32_t sectors = 0; 844 845 sc->sc_transfer_mode = NULL; 846 847 /* change bus clock */ 848 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 849 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock, false); 850 if (error) { 851 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 852 return error; 853 } 854 855 if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 856 error = sdmmc_mem_send_cxd_data(sc, 857 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 858 if (error) { 859 aprint_error_dev(sc->sc_dev, 860 "can't read EXT_CSD (error=%d)\n", error); 861 return error; 862 } 863 if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) && 864 (ext_csd[EXT_CSD_STRUCTURE] > EXT_CSD_STRUCTURE_VER_1_2)) { 865 aprint_error_dev(sc->sc_dev, 866 "unrecognised future version (%d)\n", 867 ext_csd[EXT_CSD_STRUCTURE]); 868 return ENOTSUP; 869 } 870 871 sc->sc_transfer_mode = NULL; 872 if (ISSET(sc->sc_caps, SMC_CAPS_MMC_HS200) && 873 ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_HS200_1_8V) { 874 sf->csd.tran_speed = 200000; /* 200MHz SDR */ 875 hs_timing = 2; 876 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_52M) { 877 sf->csd.tran_speed = 52000; /* 52MHz */ 878 hs_timing = 1; 879 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_26M) { 880 sf->csd.tran_speed = 26000; /* 26MHz */ 881 hs_timing = 0; 882 } else { 883 aprint_error_dev(sc->sc_dev, 884 "unknown CARD_TYPE: 0x%x\n", 885 ext_csd[EXT_CSD_CARD_TYPE]); 886 return ENOTSUP; 887 } 888 889 if (hs_timing == 2) { 890 error = sdmmc_chip_signal_voltage(sc->sc_sct, 891 sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_180); 892 if (error) 893 hs_timing = 1; 894 } 895 896 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 897 width = 8; 898 value = EXT_CSD_BUS_WIDTH_8; 899 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 900 width = 4; 901 value = EXT_CSD_BUS_WIDTH_4; 902 } else { 903 width = 1; 904 value = EXT_CSD_BUS_WIDTH_1; 905 } 906 907 if (width != 1) { 908 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 909 EXT_CSD_BUS_WIDTH, value); 910 if (error == 0) 911 error = sdmmc_chip_bus_width(sc->sc_sct, 912 sc->sc_sch, width); 913 else { 914 DPRINTF(("%s: can't change bus width" 915 " (%d bit)\n", SDMMCDEVNAME(sc), width)); 916 return error; 917 } 918 919 /* XXXX: need bus test? (using by CMD14 & CMD19) */ 920 } 921 sf->width = width; 922 923 if (hs_timing == 1 && 924 !ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 925 hs_timing = 0; 926 } 927 if (hs_timing) { 928 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 929 EXT_CSD_HS_TIMING, hs_timing); 930 if (error) { 931 aprint_error_dev(sc->sc_dev, 932 "can't change high speed\n"); 933 return error; 934 } 935 } 936 937 if (sc->sc_busclk > sf->csd.tran_speed) 938 sc->sc_busclk = sf->csd.tran_speed; 939 if (sc->sc_busclk != bus_clock) { 940 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 941 sc->sc_busclk, false); 942 if (error) { 943 aprint_error_dev(sc->sc_dev, 944 "can't change bus clock\n"); 945 return error; 946 } 947 } 948 949 if (hs_timing) { 950 error = sdmmc_mem_send_cxd_data(sc, 951 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 952 if (error) { 953 aprint_error_dev(sc->sc_dev, 954 "can't re-read EXT_CSD\n"); 955 return error; 956 } 957 if (ext_csd[EXT_CSD_HS_TIMING] != hs_timing) { 958 aprint_error_dev(sc->sc_dev, 959 "HS_TIMING set failed\n"); 960 return EINVAL; 961 } 962 } 963 964 sectors = ext_csd[EXT_CSD_SEC_COUNT + 0] << 0 | 965 ext_csd[EXT_CSD_SEC_COUNT + 1] << 8 | 966 ext_csd[EXT_CSD_SEC_COUNT + 2] << 16 | 967 ext_csd[EXT_CSD_SEC_COUNT + 3] << 24; 968 if (sectors > (2u * 1024 * 1024 * 1024) / 512) { 969 SET(sf->flags, SFF_SDHC); 970 sf->csd.capacity = sectors; 971 } 972 973 if (hs_timing == 2) { 974 sc->sc_transfer_mode = "HS200"; 975 } else { 976 sc->sc_transfer_mode = NULL; 977 } 978 } else { 979 if (sc->sc_busclk > sf->csd.tran_speed) 980 sc->sc_busclk = sf->csd.tran_speed; 981 if (sc->sc_busclk != bus_clock) { 982 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 983 sc->sc_busclk, false); 984 if (error) { 985 aprint_error_dev(sc->sc_dev, 986 "can't change bus clock\n"); 987 return error; 988 } 989 } 990 } 991 992 return 0; 993 } 994 995 static int 996 sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp) 997 { 998 struct sdmmc_command cmd; 999 int error; 1000 1001 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1002 memset(&cmd, 0, sizeof cmd); 1003 cmd.c_opcode = MMC_ALL_SEND_CID; 1004 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 1005 1006 error = sdmmc_mmc_command(sc, &cmd); 1007 } else { 1008 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CID, &cmd.c_resp, 1009 sizeof(cmd.c_resp)); 1010 } 1011 1012 #ifdef SDMMC_DEBUG 1013 if (error == 0) 1014 sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp)); 1015 #endif 1016 if (error == 0 && resp != NULL) 1017 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 1018 return error; 1019 } 1020 1021 static int 1022 sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf, 1023 sdmmc_response *resp) 1024 { 1025 struct sdmmc_command cmd; 1026 int error; 1027 1028 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1029 memset(&cmd, 0, sizeof cmd); 1030 cmd.c_opcode = MMC_SEND_CSD; 1031 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1032 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 1033 1034 error = sdmmc_mmc_command(sc, &cmd); 1035 } else { 1036 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CSD, &cmd.c_resp, 1037 sizeof(cmd.c_resp)); 1038 } 1039 1040 #ifdef SDMMC_DEBUG 1041 if (error == 0) 1042 sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp)); 1043 #endif 1044 if (error == 0 && resp != NULL) 1045 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 1046 return error; 1047 } 1048 1049 static int 1050 sdmmc_mem_send_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf, 1051 uint32_t *scr) 1052 { 1053 struct sdmmc_command cmd; 1054 bus_dma_segment_t ds[1]; 1055 void *ptr = NULL; 1056 int datalen = 8; 1057 int rseg; 1058 int error = 0; 1059 1060 /* Don't lock */ 1061 1062 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1063 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, 1064 ds, 1, &rseg, BUS_DMA_NOWAIT); 1065 if (error) 1066 goto out; 1067 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1068 BUS_DMA_NOWAIT); 1069 if (error) 1070 goto dmamem_free; 1071 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1072 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1073 if (error) 1074 goto dmamem_unmap; 1075 1076 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1077 BUS_DMASYNC_PREREAD); 1078 } else { 1079 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1080 if (ptr == NULL) 1081 goto out; 1082 } 1083 1084 memset(&cmd, 0, sizeof(cmd)); 1085 cmd.c_data = ptr; 1086 cmd.c_datalen = datalen; 1087 cmd.c_blklen = datalen; 1088 cmd.c_arg = 0; 1089 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1090 cmd.c_opcode = SD_APP_SEND_SCR; 1091 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1092 cmd.c_dmamap = sc->sc_dmap; 1093 1094 error = sdmmc_app_command(sc, sf, &cmd); 1095 if (error == 0) { 1096 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1097 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1098 BUS_DMASYNC_POSTREAD); 1099 } 1100 memcpy(scr, ptr, datalen); 1101 } 1102 1103 out: 1104 if (ptr != NULL) { 1105 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1106 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1107 dmamem_unmap: 1108 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1109 dmamem_free: 1110 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1111 } else { 1112 free(ptr, M_DEVBUF); 1113 } 1114 } 1115 DPRINTF(("%s: sdmem_mem_send_scr: error = %d\n", SDMMCDEVNAME(sc), 1116 error)); 1117 1118 #ifdef SDMMC_DEBUG 1119 if (error == 0) 1120 sdmmc_dump_data("SCR", scr, datalen); 1121 #endif 1122 return error; 1123 } 1124 1125 static int 1126 sdmmc_mem_decode_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf) 1127 { 1128 sdmmc_response resp; 1129 int ver; 1130 1131 memset(resp, 0, sizeof(resp)); 1132 /* 1133 * Change the raw-scr received from the DMA stream to resp. 1134 */ 1135 resp[0] = be32toh(sf->raw_scr[1]) >> 8; // LSW 1136 resp[1] = be32toh(sf->raw_scr[0]); // MSW 1137 resp[0] |= (resp[1] & 0xff) << 24; 1138 resp[1] >>= 8; 1139 1140 ver = SCR_STRUCTURE(resp); 1141 sf->scr.sd_spec = SCR_SD_SPEC(resp); 1142 sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 1143 1144 DPRINTF(("%s: sdmmc_mem_decode_scr: %08x%08x ver=%d, spec=%d, bus width=%d\n", 1145 SDMMCDEVNAME(sc), resp[1], resp[0], 1146 ver, sf->scr.sd_spec, sf->scr.bus_width)); 1147 1148 if (ver != 0 && ver != 1) { 1149 DPRINTF(("%s: unknown structure version: %d\n", 1150 SDMMCDEVNAME(sc), ver)); 1151 return EINVAL; 1152 } 1153 return 0; 1154 } 1155 1156 static int 1157 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 1158 size_t datalen) 1159 { 1160 struct sdmmc_command cmd; 1161 bus_dma_segment_t ds[1]; 1162 void *ptr = NULL; 1163 int rseg; 1164 int error = 0; 1165 1166 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1167 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, ds, 1168 1, &rseg, BUS_DMA_NOWAIT); 1169 if (error) 1170 goto out; 1171 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1172 BUS_DMA_NOWAIT); 1173 if (error) 1174 goto dmamem_free; 1175 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1176 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1177 if (error) 1178 goto dmamem_unmap; 1179 1180 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1181 BUS_DMASYNC_PREREAD); 1182 } else { 1183 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1184 if (ptr == NULL) 1185 goto out; 1186 } 1187 1188 memset(&cmd, 0, sizeof(cmd)); 1189 cmd.c_data = ptr; 1190 cmd.c_datalen = datalen; 1191 cmd.c_blklen = datalen; 1192 cmd.c_opcode = opcode; 1193 cmd.c_arg = 0; 1194 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_SPI_R1; 1195 if (opcode == MMC_SEND_EXT_CSD) 1196 SET(cmd.c_flags, SCF_RSP_R1); 1197 else 1198 SET(cmd.c_flags, SCF_RSP_R2); 1199 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1200 cmd.c_dmamap = sc->sc_dmap; 1201 1202 error = sdmmc_mmc_command(sc, &cmd); 1203 if (error == 0) { 1204 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1205 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1206 BUS_DMASYNC_POSTREAD); 1207 } 1208 memcpy(data, ptr, datalen); 1209 #ifdef SDMMC_DEBUG 1210 sdmmc_dump_data("CXD", data, datalen); 1211 #endif 1212 } 1213 1214 out: 1215 if (ptr != NULL) { 1216 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1217 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1218 dmamem_unmap: 1219 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1220 dmamem_free: 1221 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1222 } else { 1223 free(ptr, M_DEVBUF); 1224 } 1225 } 1226 return error; 1227 } 1228 1229 static int 1230 sdmmc_set_bus_width(struct sdmmc_function *sf, int width) 1231 { 1232 struct sdmmc_softc *sc = sf->sc; 1233 struct sdmmc_command cmd; 1234 int error; 1235 1236 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1237 return ENODEV; 1238 1239 memset(&cmd, 0, sizeof(cmd)); 1240 cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 1241 cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 1242 1243 switch (width) { 1244 case 1: 1245 cmd.c_arg = SD_ARG_BUS_WIDTH_1; 1246 break; 1247 1248 case 4: 1249 cmd.c_arg = SD_ARG_BUS_WIDTH_4; 1250 break; 1251 1252 default: 1253 return EINVAL; 1254 } 1255 1256 error = sdmmc_app_command(sc, sf, &cmd); 1257 if (error == 0) 1258 error = sdmmc_chip_bus_width(sc->sc_sct, sc->sc_sch, width); 1259 return error; 1260 } 1261 1262 static int 1263 sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 1264 int function, sdmmc_bitfield512_t *status) 1265 { 1266 struct sdmmc_softc *sc = sf->sc; 1267 struct sdmmc_command cmd; 1268 bus_dma_segment_t ds[1]; 1269 void *ptr = NULL; 1270 int gsft, rseg, error = 0; 1271 const int statlen = 64; 1272 1273 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 1274 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 1275 return EINVAL; 1276 1277 if (group <= 0 || group > 6 || 1278 function < 0 || function > 15) 1279 return EINVAL; 1280 1281 gsft = (group - 1) << 2; 1282 1283 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1284 error = bus_dmamem_alloc(sc->sc_dmat, statlen, PAGE_SIZE, 0, ds, 1285 1, &rseg, BUS_DMA_NOWAIT); 1286 if (error) 1287 goto out; 1288 error = bus_dmamem_map(sc->sc_dmat, ds, 1, statlen, &ptr, 1289 BUS_DMA_NOWAIT); 1290 if (error) 1291 goto dmamem_free; 1292 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, statlen, 1293 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1294 if (error) 1295 goto dmamem_unmap; 1296 1297 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1298 BUS_DMASYNC_PREREAD); 1299 } else { 1300 ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 1301 if (ptr == NULL) 1302 goto out; 1303 } 1304 1305 memset(&cmd, 0, sizeof(cmd)); 1306 cmd.c_data = ptr; 1307 cmd.c_datalen = statlen; 1308 cmd.c_blklen = statlen; 1309 cmd.c_opcode = SD_SEND_SWITCH_FUNC; 1310 cmd.c_arg = 1311 (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 1312 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1313 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1314 cmd.c_dmamap = sc->sc_dmap; 1315 1316 error = sdmmc_mmc_command(sc, &cmd); 1317 if (error == 0) { 1318 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1319 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1320 BUS_DMASYNC_POSTREAD); 1321 } 1322 memcpy(status, ptr, statlen); 1323 } 1324 1325 out: 1326 if (ptr != NULL) { 1327 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1328 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1329 dmamem_unmap: 1330 bus_dmamem_unmap(sc->sc_dmat, ptr, statlen); 1331 dmamem_free: 1332 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1333 } else { 1334 free(ptr, M_DEVBUF); 1335 } 1336 } 1337 1338 if (error == 0) 1339 sdmmc_be512_to_bitfield512(status); 1340 1341 return error; 1342 } 1343 1344 static int 1345 sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 1346 uint8_t value) 1347 { 1348 struct sdmmc_softc *sc = sf->sc; 1349 struct sdmmc_command cmd; 1350 1351 memset(&cmd, 0, sizeof(cmd)); 1352 cmd.c_opcode = MMC_SWITCH; 1353 cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 1354 (index << 16) | (value << 8) | set; 1355 cmd.c_flags = SCF_RSP_SPI_R1B | SCF_RSP_R1B | SCF_CMD_AC; 1356 1357 return sdmmc_mmc_command(sc, &cmd); 1358 } 1359 1360 /* 1361 * SPI mode function 1362 */ 1363 static int 1364 sdmmc_mem_spi_read_ocr(struct sdmmc_softc *sc, uint32_t hcs, uint32_t *card_ocr) 1365 { 1366 struct sdmmc_command cmd; 1367 int error; 1368 1369 memset(&cmd, 0, sizeof(cmd)); 1370 cmd.c_opcode = MMC_READ_OCR; 1371 cmd.c_arg = hcs ? MMC_OCR_HCS : 0; 1372 cmd.c_flags = SCF_RSP_SPI_R3; 1373 1374 error = sdmmc_mmc_command(sc, &cmd); 1375 if (error == 0 && card_ocr != NULL) 1376 *card_ocr = cmd.c_resp[1]; 1377 DPRINTF(("%s: sdmmc_mem_spi_read_ocr: error=%d, ocr=%#x\n", 1378 SDMMCDEVNAME(sc), error, cmd.c_resp[1])); 1379 return error; 1380 } 1381 1382 /* 1383 * read/write function 1384 */ 1385 /* read */ 1386 static int 1387 sdmmc_mem_single_read_block(struct sdmmc_function *sf, uint32_t blkno, 1388 u_char *data, size_t datalen) 1389 { 1390 struct sdmmc_softc *sc = sf->sc; 1391 int error = 0; 1392 int i; 1393 1394 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1395 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1396 1397 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1398 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno + i, 1399 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1400 if (error) 1401 break; 1402 } 1403 return error; 1404 } 1405 1406 /* 1407 * Simulate multi-segment dma transfer. 1408 */ 1409 static int 1410 sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *sf, 1411 uint32_t blkno, u_char *data, size_t datalen) 1412 { 1413 struct sdmmc_softc *sc = sf->sc; 1414 bool use_bbuf = false; 1415 int error = 0; 1416 int i; 1417 1418 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1419 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1420 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1421 use_bbuf = true; 1422 break; 1423 } 1424 } 1425 if (use_bbuf) { 1426 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1427 BUS_DMASYNC_PREREAD); 1428 1429 error = sdmmc_mem_read_block_subr(sf, sf->bbuf_dmap, 1430 blkno, data, datalen); 1431 if (error) { 1432 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1433 return error; 1434 } 1435 1436 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1437 BUS_DMASYNC_POSTREAD); 1438 1439 /* Copy from bounce buffer */ 1440 memcpy(data, sf->bbuf, datalen); 1441 1442 return 0; 1443 } 1444 1445 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1446 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1447 1448 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1449 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_READ); 1450 if (error) 1451 return error; 1452 1453 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1454 BUS_DMASYNC_PREREAD); 1455 1456 error = sdmmc_mem_read_block_subr(sf, sf->sseg_dmap, 1457 blkno, data, len); 1458 if (error) { 1459 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1460 return error; 1461 } 1462 1463 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1464 BUS_DMASYNC_POSTREAD); 1465 1466 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1467 1468 blkno += len / SDMMC_SECTOR_SIZE; 1469 data += len; 1470 } 1471 return 0; 1472 } 1473 1474 static int 1475 sdmmc_mem_read_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1476 uint32_t blkno, u_char *data, size_t datalen) 1477 { 1478 struct sdmmc_softc *sc = sf->sc; 1479 struct sdmmc_command cmd; 1480 int error; 1481 1482 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1483 error = sdmmc_select_card(sc, sf); 1484 if (error) 1485 goto out; 1486 } 1487 1488 memset(&cmd, 0, sizeof(cmd)); 1489 cmd.c_data = data; 1490 cmd.c_datalen = datalen; 1491 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1492 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1493 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1494 cmd.c_arg = blkno; 1495 if (!ISSET(sf->flags, SFF_SDHC)) 1496 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1497 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1498 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1499 cmd.c_dmamap = dmap; 1500 1501 error = sdmmc_mmc_command(sc, &cmd); 1502 if (error) 1503 goto out; 1504 1505 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1506 if (cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 1507 memset(&cmd, 0, sizeof cmd); 1508 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1509 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1510 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1511 error = sdmmc_mmc_command(sc, &cmd); 1512 if (error) 1513 goto out; 1514 } 1515 } 1516 1517 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1518 do { 1519 memset(&cmd, 0, sizeof(cmd)); 1520 cmd.c_opcode = MMC_SEND_STATUS; 1521 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1522 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1523 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1524 error = sdmmc_mmc_command(sc, &cmd); 1525 if (error) 1526 break; 1527 /* XXX time out */ 1528 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1529 } 1530 1531 out: 1532 return error; 1533 } 1534 1535 int 1536 sdmmc_mem_read_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1537 size_t datalen) 1538 { 1539 struct sdmmc_softc *sc = sf->sc; 1540 int error; 1541 1542 SDMMC_LOCK(sc); 1543 mutex_enter(&sc->sc_mtx); 1544 1545 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1546 error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 1547 goto out; 1548 } 1549 1550 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1551 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1552 datalen); 1553 goto out; 1554 } 1555 1556 /* DMA transfer */ 1557 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1558 BUS_DMA_NOWAIT|BUS_DMA_READ); 1559 if (error) 1560 goto out; 1561 1562 #ifdef SDMMC_DEBUG 1563 printf("data=%p, datalen=%zu\n", data, datalen); 1564 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1565 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1566 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1567 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1568 } 1569 #endif 1570 1571 if (sc->sc_dmap->dm_nsegs > 1 1572 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1573 error = sdmmc_mem_single_segment_dma_read_block(sf, blkno, 1574 data, datalen); 1575 goto unload; 1576 } 1577 1578 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1579 BUS_DMASYNC_PREREAD); 1580 1581 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1582 datalen); 1583 if (error) 1584 goto unload; 1585 1586 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1587 BUS_DMASYNC_POSTREAD); 1588 unload: 1589 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1590 1591 out: 1592 mutex_exit(&sc->sc_mtx); 1593 SDMMC_UNLOCK(sc); 1594 1595 return error; 1596 } 1597 1598 /* write */ 1599 static int 1600 sdmmc_mem_single_write_block(struct sdmmc_function *sf, uint32_t blkno, 1601 u_char *data, size_t datalen) 1602 { 1603 struct sdmmc_softc *sc = sf->sc; 1604 int error = 0; 1605 int i; 1606 1607 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1608 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1609 1610 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1611 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno + i, 1612 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1613 if (error) 1614 break; 1615 } 1616 return error; 1617 } 1618 1619 /* 1620 * Simulate multi-segment dma transfer. 1621 */ 1622 static int 1623 sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *sf, 1624 uint32_t blkno, u_char *data, size_t datalen) 1625 { 1626 struct sdmmc_softc *sc = sf->sc; 1627 bool use_bbuf = false; 1628 int error = 0; 1629 int i; 1630 1631 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1632 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1633 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1634 use_bbuf = true; 1635 break; 1636 } 1637 } 1638 if (use_bbuf) { 1639 /* Copy to bounce buffer */ 1640 memcpy(sf->bbuf, data, datalen); 1641 1642 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1643 BUS_DMASYNC_PREWRITE); 1644 1645 error = sdmmc_mem_write_block_subr(sf, sf->bbuf_dmap, 1646 blkno, data, datalen); 1647 if (error) { 1648 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1649 return error; 1650 } 1651 1652 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1653 BUS_DMASYNC_POSTWRITE); 1654 1655 return 0; 1656 } 1657 1658 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1659 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1660 1661 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1662 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1663 if (error) 1664 return error; 1665 1666 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1667 BUS_DMASYNC_PREWRITE); 1668 1669 error = sdmmc_mem_write_block_subr(sf, sf->sseg_dmap, 1670 blkno, data, len); 1671 if (error) { 1672 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1673 return error; 1674 } 1675 1676 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1677 BUS_DMASYNC_POSTWRITE); 1678 1679 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1680 1681 blkno += len / SDMMC_SECTOR_SIZE; 1682 data += len; 1683 } 1684 1685 return error; 1686 } 1687 1688 static int 1689 sdmmc_mem_write_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1690 uint32_t blkno, u_char *data, size_t datalen) 1691 { 1692 struct sdmmc_softc *sc = sf->sc; 1693 struct sdmmc_command cmd; 1694 int error; 1695 1696 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1697 error = sdmmc_select_card(sc, sf); 1698 if (error) 1699 goto out; 1700 } 1701 1702 memset(&cmd, 0, sizeof(cmd)); 1703 cmd.c_data = data; 1704 cmd.c_datalen = datalen; 1705 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1706 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1707 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1708 cmd.c_arg = blkno; 1709 if (!ISSET(sf->flags, SFF_SDHC)) 1710 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1711 cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 1712 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1713 cmd.c_dmamap = dmap; 1714 1715 error = sdmmc_mmc_command(sc, &cmd); 1716 if (error) 1717 goto out; 1718 1719 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1720 if (cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1721 memset(&cmd, 0, sizeof(cmd)); 1722 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1723 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1724 error = sdmmc_mmc_command(sc, &cmd); 1725 if (error) 1726 goto out; 1727 } 1728 } 1729 1730 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1731 do { 1732 memset(&cmd, 0, sizeof(cmd)); 1733 cmd.c_opcode = MMC_SEND_STATUS; 1734 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1735 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1736 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1737 error = sdmmc_mmc_command(sc, &cmd); 1738 if (error) 1739 break; 1740 /* XXX time out */ 1741 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1742 } 1743 1744 out: 1745 return error; 1746 } 1747 1748 int 1749 sdmmc_mem_write_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1750 size_t datalen) 1751 { 1752 struct sdmmc_softc *sc = sf->sc; 1753 int error; 1754 1755 SDMMC_LOCK(sc); 1756 mutex_enter(&sc->sc_mtx); 1757 1758 if (sdmmc_chip_write_protect(sc->sc_sct, sc->sc_sch)) { 1759 aprint_normal_dev(sc->sc_dev, "write-protected\n"); 1760 error = EIO; 1761 goto out; 1762 } 1763 1764 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1765 error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1766 goto out; 1767 } 1768 1769 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1770 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1771 datalen); 1772 goto out; 1773 } 1774 1775 /* DMA transfer */ 1776 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1777 BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1778 if (error) 1779 goto out; 1780 1781 #ifdef SDMMC_DEBUG 1782 aprint_normal_dev(sc->sc_dev, "%s: data=%p, datalen=%zu\n", 1783 __func__, data, datalen); 1784 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1785 aprint_normal_dev(sc->sc_dev, 1786 "%s: seg#%d: addr=%#lx, size=%#lx\n", __func__, i, 1787 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1788 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1789 } 1790 #endif 1791 1792 if (sc->sc_dmap->dm_nsegs > 1 1793 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1794 error = sdmmc_mem_single_segment_dma_write_block(sf, blkno, 1795 data, datalen); 1796 goto unload; 1797 } 1798 1799 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1800 BUS_DMASYNC_PREWRITE); 1801 1802 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1803 datalen); 1804 if (error) 1805 goto unload; 1806 1807 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1808 BUS_DMASYNC_POSTWRITE); 1809 unload: 1810 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1811 1812 out: 1813 mutex_exit(&sc->sc_mtx); 1814 SDMMC_UNLOCK(sc); 1815 1816 return error; 1817 } 1818
Indexes created Tue Sep 23 14:10:03 GMT 2025