sdmmc_mem.c revision 1.44
1 /* $NetBSD: sdmmc_mem.c,v 1.44 2015/08/04 01:21:55 jmcneill Exp $ */ 2 /* $OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2007, 2008, 2009, 2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 /* Routines for SD/MMC memory cards. */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.44 2015/08/04 01:21:55 jmcneill Exp $"); 49 50 #ifdef _KERNEL_OPT 51 #include "opt_sdmmc.h" 52 #endif 53 54 #include <sys/param.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 60 #include <dev/sdmmc/sdmmcchip.h> 61 #include <dev/sdmmc/sdmmcreg.h> 62 #include <dev/sdmmc/sdmmcvar.h> 63 64 #ifdef SDMMC_DEBUG 65 #define DPRINTF(s) do { printf s; } while (/*CONSTCOND*/0) 66 #else 67 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 68 #endif 69 70 typedef struct { uint32_t _bits[512/32]; } __packed __aligned(4) sdmmc_bitfield512_t; 71 72 static int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 73 static int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 74 static int sdmmc_mem_send_cid(struct sdmmc_softc *, sdmmc_response *); 75 static int sdmmc_mem_send_csd(struct sdmmc_softc *, struct sdmmc_function *, 76 sdmmc_response *); 77 static int sdmmc_mem_send_scr(struct sdmmc_softc *, struct sdmmc_function *, 78 uint32_t *scr); 79 static int sdmmc_mem_decode_scr(struct sdmmc_softc *, struct sdmmc_function *); 80 static int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 81 static int sdmmc_set_bus_width(struct sdmmc_function *, int); 82 static int sdmmc_mem_sd_switch(struct sdmmc_function *, int, int, int, sdmmc_bitfield512_t *); 83 static int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, 84 uint8_t); 85 static int sdmmc_mem_signal_voltage(struct sdmmc_softc *, int); 86 static int sdmmc_mem_spi_read_ocr(struct sdmmc_softc *, uint32_t, uint32_t *); 87 static int sdmmc_mem_single_read_block(struct sdmmc_function *, uint32_t, 88 u_char *, size_t); 89 static int sdmmc_mem_single_write_block(struct sdmmc_function *, uint32_t, 90 u_char *, size_t); 91 static int sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *, 92 uint32_t, u_char *, size_t); 93 static int sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *, 94 uint32_t, u_char *, size_t); 95 static int sdmmc_mem_read_block_subr(struct sdmmc_function *, bus_dmamap_t, 96 uint32_t, u_char *, size_t); 97 static int sdmmc_mem_write_block_subr(struct sdmmc_function *, bus_dmamap_t, 98 uint32_t, u_char *, size_t); 99 100 static const struct { 101 const char *name; 102 int v; 103 int freq; 104 } switch_group0_functions[] = { 105 /* Default/SDR12 */ 106 { "Default/SDR12", 0, 25000 }, 107 108 /* High-Speed/SDR25 */ 109 { "High-Speed/SDR25", SMC_CAPS_SD_HIGHSPEED, 50000 }, 110 111 /* SDR50 */ 112 { "SDR50", SMC_CAPS_UHS_SDR50, 100000 }, 113 114 /* SDR104 */ 115 { "SDR104", SMC_CAPS_UHS_SDR104, 208000 }, 116 117 /* DDR50 */ 118 { "DDR50", SMC_CAPS_UHS_DDR50, 50000 }, 119 }; 120 121 /* 122 * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 123 */ 124 int 125 sdmmc_mem_enable(struct sdmmc_softc *sc) 126 { 127 uint32_t host_ocr; 128 uint32_t card_ocr; 129 uint32_t new_ocr; 130 uint32_t ocr = 0; 131 int error; 132 133 SDMMC_LOCK(sc); 134 135 /* Set host mode to SD "combo" card or SD memory-only. */ 136 CLR(sc->sc_flags, SMF_UHS_MODE); 137 SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 138 139 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 140 sdmmc_spi_chip_initialize(sc->sc_spi_sct, sc->sc_sch); 141 142 /* Reset memory (*must* do that before CMD55 or CMD1). */ 143 sdmmc_go_idle_state(sc); 144 145 /* Set 3.3V signaling */ 146 if (sc->sc_sct->signal_voltage) { 147 error = sdmmc_mem_signal_voltage(sc, SDMMC_SIGNAL_VOLTAGE_330); 148 if (error) 149 goto out; 150 } 151 152 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 153 /* Check SD Ver.2 */ 154 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 155 if (error == 0 && card_ocr == 0x1aa) 156 SET(ocr, MMC_OCR_HCS); 157 } 158 159 /* 160 * Read the SD/MMC memory OCR value by issuing CMD55 followed 161 * by ACMD41 to read the OCR value from memory-only SD cards. 162 * MMC cards will not respond to CMD55 or ACMD41 and this is 163 * how we distinguish them from SD cards. 164 */ 165 mmc_mode: 166 error = sdmmc_mem_send_op_cond(sc, 167 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr); 168 if (error) { 169 if (ISSET(sc->sc_flags, SMF_SD_MODE) && 170 !ISSET(sc->sc_flags, SMF_IO_MODE)) { 171 /* Not a SD card, switch to MMC mode. */ 172 DPRINTF(("%s: switch to MMC mode\n", SDMMCDEVNAME(sc))); 173 CLR(sc->sc_flags, SMF_SD_MODE); 174 goto mmc_mode; 175 } 176 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 177 DPRINTF(("%s: couldn't read memory OCR\n", 178 SDMMCDEVNAME(sc))); 179 goto out; 180 } else { 181 /* Not a "combo" card. */ 182 CLR(sc->sc_flags, SMF_MEM_MODE); 183 error = 0; 184 goto out; 185 } 186 } 187 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 188 /* get card OCR */ 189 error = sdmmc_mem_spi_read_ocr(sc, ocr, &card_ocr); 190 if (error) { 191 DPRINTF(("%s: couldn't read SPI memory OCR\n", 192 SDMMCDEVNAME(sc))); 193 goto out; 194 } 195 } 196 197 /* Set the lowest voltage supported by the card and host. */ 198 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 199 error = sdmmc_set_bus_power(sc, host_ocr, card_ocr); 200 if (error) { 201 DPRINTF(("%s: couldn't supply voltage requested by card\n", 202 SDMMCDEVNAME(sc))); 203 goto out; 204 } 205 206 /* Tell the card(s) to enter the idle state (again). */ 207 sdmmc_go_idle_state(sc); 208 209 DPRINTF(("%s: host_ocr 0x%08x\n", SDMMCDEVNAME(sc), host_ocr)); 210 DPRINTF(("%s: card_ocr 0x%08x\n", SDMMCDEVNAME(sc), card_ocr)); 211 212 host_ocr &= card_ocr; /* only allow the common voltages */ 213 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 214 /* Check SD Ver.2 */ 215 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 216 if (error == 0 && card_ocr == 0x1aa) 217 SET(ocr, MMC_OCR_HCS); 218 219 if (sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch) & MMC_OCR_S18A) 220 SET(ocr, MMC_OCR_S18A); 221 } 222 host_ocr |= ocr; 223 224 /* Send the new OCR value until all cards are ready. */ 225 error = sdmmc_mem_send_op_cond(sc, host_ocr, &new_ocr); 226 if (error) { 227 DPRINTF(("%s: couldn't send memory OCR\n", SDMMCDEVNAME(sc))); 228 goto out; 229 } 230 231 if (ISSET(new_ocr, MMC_OCR_S18A) && sc->sc_sct->signal_voltage) { 232 /* 233 * Card and host support low voltage mode, begin switch 234 * sequence. 235 */ 236 struct sdmmc_command cmd; 237 memset(&cmd, 0, sizeof(cmd)); 238 cmd.c_arg = 0; 239 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 240 cmd.c_opcode = SD_VOLTAGE_SWITCH; 241 DPRINTF(("%s: switching card to 1.8V\n", SDMMCDEVNAME(sc))); 242 error = sdmmc_mmc_command(sc, &cmd); 243 if (error) { 244 DPRINTF(("%s: voltage switch command failed\n", 245 SDMMCDEVNAME(sc))); 246 goto out; 247 } 248 249 error = sdmmc_mem_signal_voltage(sc, SDMMC_SIGNAL_VOLTAGE_180); 250 if (error) 251 goto out; 252 253 SET(sc->sc_flags, SMF_UHS_MODE); 254 } 255 256 out: 257 SDMMC_UNLOCK(sc); 258 259 if (error) 260 printf("%s: %s failed with error %d\n", SDMMCDEVNAME(sc), 261 __func__, error); 262 263 return error; 264 } 265 266 static int 267 sdmmc_mem_signal_voltage(struct sdmmc_softc *sc, int signal_voltage) 268 { 269 int error; 270 271 /* 272 * Stop the clock 273 */ 274 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 275 SDMMC_SDCLK_OFF, false); 276 if (error) 277 goto out; 278 279 delay(1000); 280 281 /* 282 * Card switch command was successful, update host controller 283 * signal voltage setting. 284 */ 285 DPRINTF(("%s: switching host to %s\n", SDMMCDEVNAME(sc), 286 signal_voltage == SDMMC_SIGNAL_VOLTAGE_180 ? "1.8V" : "3.3V")); 287 error = sdmmc_chip_signal_voltage(sc->sc_sct, 288 sc->sc_sch, signal_voltage); 289 if (error) 290 goto out; 291 292 delay(5000); 293 294 /* 295 * Switch to SDR12 timing 296 */ 297 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 25000, 298 false); 299 if (error) 300 goto out; 301 302 delay(1000); 303 304 out: 305 return error; 306 } 307 308 /* 309 * Read the CSD and CID from all cards and assign each card a unique 310 * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 311 */ 312 void 313 sdmmc_mem_scan(struct sdmmc_softc *sc) 314 { 315 sdmmc_response resp; 316 struct sdmmc_function *sf; 317 uint16_t next_rca; 318 int error; 319 int retry; 320 321 SDMMC_LOCK(sc); 322 323 /* 324 * CMD2 is a broadcast command understood by SD cards and MMC 325 * cards. All cards begin to respond to the command, but back 326 * off if another card drives the CMD line to a different level. 327 * Only one card will get its entire response through. That 328 * card remains silent once it has been assigned a RCA. 329 */ 330 for (retry = 0; retry < 100; retry++) { 331 error = sdmmc_mem_send_cid(sc, &resp); 332 if (error) { 333 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && 334 error == ETIMEDOUT) { 335 /* No more cards there. */ 336 break; 337 } 338 DPRINTF(("%s: couldn't read CID\n", SDMMCDEVNAME(sc))); 339 break; 340 } 341 342 /* In MMC mode, find the next available RCA. */ 343 next_rca = 1; 344 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 345 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) 346 next_rca++; 347 } 348 349 /* Allocate a sdmmc_function structure. */ 350 sf = sdmmc_function_alloc(sc); 351 sf->rca = next_rca; 352 353 /* 354 * Remember the CID returned in the CMD2 response for 355 * later decoding. 356 */ 357 memcpy(sf->raw_cid, resp, sizeof(sf->raw_cid)); 358 359 /* 360 * Silence the card by assigning it a unique RCA, or 361 * querying it for its RCA in the case of SD. 362 */ 363 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 364 if (sdmmc_set_relative_addr(sc, sf) != 0) { 365 aprint_error_dev(sc->sc_dev, 366 "couldn't set mem RCA\n"); 367 sdmmc_function_free(sf); 368 break; 369 } 370 } 371 372 /* 373 * If this is a memory-only card, the card responding 374 * first becomes an alias for SDIO function 0. 375 */ 376 if (sc->sc_fn0 == NULL) 377 sc->sc_fn0 = sf; 378 379 SIMPLEQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 380 381 /* only one function in SPI mode */ 382 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 383 break; 384 } 385 386 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 387 /* Go to Data Transfer Mode, if possible. */ 388 sdmmc_chip_bus_rod(sc->sc_sct, sc->sc_sch, 0); 389 390 /* 391 * All cards are either inactive or awaiting further commands. 392 * Read the CSDs and decode the raw CID for each card. 393 */ 394 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) { 395 error = sdmmc_mem_send_csd(sc, sf, &resp); 396 if (error) { 397 SET(sf->flags, SFF_ERROR); 398 continue; 399 } 400 401 if (sdmmc_decode_csd(sc, resp, sf) != 0 || 402 sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 403 SET(sf->flags, SFF_ERROR); 404 continue; 405 } 406 407 #ifdef SDMMC_DEBUG 408 printf("%s: CID: ", SDMMCDEVNAME(sc)); 409 sdmmc_print_cid(&sf->cid); 410 #endif 411 } 412 413 SDMMC_UNLOCK(sc); 414 } 415 416 int 417 sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 418 struct sdmmc_function *sf) 419 { 420 /* TRAN_SPEED(2:0): transfer rate exponent */ 421 static const int speed_exponent[8] = { 422 100 * 1, /* 100 Kbits/s */ 423 1 * 1000, /* 1 Mbits/s */ 424 10 * 1000, /* 10 Mbits/s */ 425 100 * 1000, /* 100 Mbits/s */ 426 0, 427 0, 428 0, 429 0, 430 }; 431 /* TRAN_SPEED(6:3): time mantissa */ 432 static const int speed_mantissa[16] = { 433 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 434 }; 435 struct sdmmc_csd *csd = &sf->csd; 436 int e, m; 437 438 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 439 /* 440 * CSD version 1.0 corresponds to SD system 441 * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 442 */ 443 csd->csdver = SD_CSD_CSDVER(resp); 444 switch (csd->csdver) { 445 case SD_CSD_CSDVER_2_0: 446 DPRINTF(("%s: SD Ver.2.0\n", SDMMCDEVNAME(sc))); 447 SET(sf->flags, SFF_SDHC); 448 csd->capacity = SD_CSD_V2_CAPACITY(resp); 449 csd->read_bl_len = SD_CSD_V2_BL_LEN; 450 break; 451 452 case SD_CSD_CSDVER_1_0: 453 DPRINTF(("%s: SD Ver.1.0\n", SDMMCDEVNAME(sc))); 454 csd->capacity = SD_CSD_CAPACITY(resp); 455 csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 456 break; 457 458 default: 459 aprint_error_dev(sc->sc_dev, 460 "unknown SD CSD structure version 0x%x\n", 461 csd->csdver); 462 return 1; 463 } 464 465 csd->mmcver = SD_CSD_MMCVER(resp); 466 csd->write_bl_len = SD_CSD_WRITE_BL_LEN(resp); 467 csd->r2w_factor = SD_CSD_R2W_FACTOR(resp); 468 e = SD_CSD_SPEED_EXP(resp); 469 m = SD_CSD_SPEED_MANT(resp); 470 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 471 csd->ccc = SD_CSD_CCC(resp); 472 } else { 473 csd->csdver = MMC_CSD_CSDVER(resp); 474 if (csd->csdver == MMC_CSD_CSDVER_1_0) { 475 aprint_error_dev(sc->sc_dev, 476 "unknown MMC CSD structure version 0x%x\n", 477 csd->csdver); 478 return 1; 479 } 480 481 csd->mmcver = MMC_CSD_MMCVER(resp); 482 csd->capacity = MMC_CSD_CAPACITY(resp); 483 csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 484 csd->write_bl_len = MMC_CSD_WRITE_BL_LEN(resp); 485 csd->r2w_factor = MMC_CSD_R2W_FACTOR(resp); 486 e = MMC_CSD_TRAN_SPEED_EXP(resp); 487 m = MMC_CSD_TRAN_SPEED_MANT(resp); 488 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 489 } 490 if ((1 << csd->read_bl_len) > SDMMC_SECTOR_SIZE) 491 csd->capacity *= (1 << csd->read_bl_len) / SDMMC_SECTOR_SIZE; 492 493 #ifdef SDMMC_DUMP_CSD 494 sdmmc_print_csd(resp, csd); 495 #endif 496 497 return 0; 498 } 499 500 int 501 sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 502 struct sdmmc_function *sf) 503 { 504 struct sdmmc_cid *cid = &sf->cid; 505 506 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 507 cid->mid = SD_CID_MID(resp); 508 cid->oid = SD_CID_OID(resp); 509 SD_CID_PNM_CPY(resp, cid->pnm); 510 cid->rev = SD_CID_REV(resp); 511 cid->psn = SD_CID_PSN(resp); 512 cid->mdt = SD_CID_MDT(resp); 513 } else { 514 switch(sf->csd.mmcver) { 515 case MMC_CSD_MMCVER_1_0: 516 case MMC_CSD_MMCVER_1_4: 517 cid->mid = MMC_CID_MID_V1(resp); 518 MMC_CID_PNM_V1_CPY(resp, cid->pnm); 519 cid->rev = MMC_CID_REV_V1(resp); 520 cid->psn = MMC_CID_PSN_V1(resp); 521 cid->mdt = MMC_CID_MDT_V1(resp); 522 break; 523 case MMC_CSD_MMCVER_2_0: 524 case MMC_CSD_MMCVER_3_1: 525 case MMC_CSD_MMCVER_4_0: 526 cid->mid = MMC_CID_MID_V2(resp); 527 cid->oid = MMC_CID_OID_V2(resp); 528 MMC_CID_PNM_V2_CPY(resp, cid->pnm); 529 cid->psn = MMC_CID_PSN_V2(resp); 530 break; 531 default: 532 aprint_error_dev(sc->sc_dev, "unknown MMC version %d\n", 533 sf->csd.mmcver); 534 return 1; 535 } 536 } 537 return 0; 538 } 539 540 void 541 sdmmc_print_cid(struct sdmmc_cid *cid) 542 { 543 544 printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 545 " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 546 cid->mdt); 547 } 548 549 #ifdef SDMMC_DUMP_CSD 550 void 551 sdmmc_print_csd(sdmmc_response resp, struct sdmmc_csd *csd) 552 { 553 554 printf("csdver = %d\n", csd->csdver); 555 printf("mmcver = %d\n", csd->mmcver); 556 printf("capacity = 0x%08x\n", csd->capacity); 557 printf("read_bl_len = %d\n", csd->read_bl_len); 558 printf("write_bl_len = %d\n", csd->write_bl_len); 559 printf("r2w_factor = %d\n", csd->r2w_factor); 560 printf("tran_speed = %d\n", csd->tran_speed); 561 printf("ccc = 0x%x\n", csd->ccc); 562 } 563 #endif 564 565 /* 566 * Initialize a SD/MMC memory card. 567 */ 568 int 569 sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 570 { 571 int error = 0; 572 573 SDMMC_LOCK(sc); 574 575 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 576 error = sdmmc_select_card(sc, sf); 577 if (error) 578 goto out; 579 } 580 581 error = sdmmc_mem_set_blocklen(sc, sf, SDMMC_SECTOR_SIZE); 582 if (error) 583 goto out; 584 585 if (ISSET(sc->sc_flags, SMF_SD_MODE)) 586 error = sdmmc_mem_sd_init(sc, sf); 587 else 588 error = sdmmc_mem_mmc_init(sc, sf); 589 590 out: 591 SDMMC_UNLOCK(sc); 592 593 return error; 594 } 595 596 /* 597 * Get or set the card's memory OCR value (SD or MMC). 598 */ 599 int 600 sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 601 { 602 struct sdmmc_command cmd; 603 int error; 604 int retry; 605 606 /* Don't lock */ 607 608 DPRINTF(("%s: sdmmc_mem_send_op_cond: ocr=%#x\n", 609 SDMMCDEVNAME(sc), ocr)); 610 611 /* 612 * If we change the OCR value, retry the command until the OCR 613 * we receive in response has the "CARD BUSY" bit set, meaning 614 * that all cards are ready for identification. 615 */ 616 for (retry = 0; retry < 100; retry++) { 617 memset(&cmd, 0, sizeof(cmd)); 618 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? 619 ocr : (ocr & MMC_OCR_HCS); 620 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3 | SCF_RSP_SPI_R1; 621 622 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 623 cmd.c_opcode = SD_APP_OP_COND; 624 error = sdmmc_app_command(sc, NULL, &cmd); 625 } else { 626 cmd.c_opcode = MMC_SEND_OP_COND; 627 error = sdmmc_mmc_command(sc, &cmd); 628 } 629 if (error) 630 break; 631 632 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 633 if (!ISSET(MMC_SPI_R1(cmd.c_resp), R1_SPI_IDLE)) 634 break; 635 } else { 636 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 637 ocr == 0) 638 break; 639 } 640 641 error = ETIMEDOUT; 642 sdmmc_delay(10000); 643 } 644 if (error == 0 && 645 ocrp != NULL && 646 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 647 *ocrp = MMC_R3(cmd.c_resp); 648 DPRINTF(("%s: sdmmc_mem_send_op_cond: error=%d, ocr=%#x\n", 649 SDMMCDEVNAME(sc), error, MMC_R3(cmd.c_resp))); 650 return error; 651 } 652 653 int 654 sdmmc_mem_send_if_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 655 { 656 struct sdmmc_command cmd; 657 int error; 658 659 /* Don't lock */ 660 661 memset(&cmd, 0, sizeof(cmd)); 662 cmd.c_arg = ocr; 663 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R7 | SCF_RSP_SPI_R7; 664 cmd.c_opcode = SD_SEND_IF_COND; 665 666 error = sdmmc_mmc_command(sc, &cmd); 667 if (error == 0 && ocrp != NULL) { 668 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 669 *ocrp = MMC_SPI_R7(cmd.c_resp); 670 } else { 671 *ocrp = MMC_R7(cmd.c_resp); 672 } 673 DPRINTF(("%s: sdmmc_mem_send_if_cond: error=%d, ocr=%#x\n", 674 SDMMCDEVNAME(sc), error, *ocrp)); 675 } 676 return error; 677 } 678 679 /* 680 * Set the read block length appropriately for this card, according to 681 * the card CSD register value. 682 */ 683 int 684 sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf, 685 int block_len) 686 { 687 struct sdmmc_command cmd; 688 int error; 689 690 /* Don't lock */ 691 692 memset(&cmd, 0, sizeof(cmd)); 693 cmd.c_opcode = MMC_SET_BLOCKLEN; 694 cmd.c_arg = block_len; 695 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1; 696 697 error = sdmmc_mmc_command(sc, &cmd); 698 699 DPRINTF(("%s: sdmmc_mem_set_blocklen: read_bl_len=%d sector_size=%d\n", 700 SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, block_len)); 701 702 return error; 703 } 704 705 /* make 512-bit BE quantity __bitfield()-compatible */ 706 static void 707 sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) { 708 size_t i; 709 uint32_t tmp0, tmp1; 710 const size_t bitswords = __arraycount(buf->_bits); 711 for (i = 0; i < bitswords/2; i++) { 712 tmp0 = buf->_bits[i]; 713 tmp1 = buf->_bits[bitswords - 1 - i]; 714 buf->_bits[i] = be32toh(tmp1); 715 buf->_bits[bitswords - 1 - i] = be32toh(tmp0); 716 } 717 } 718 719 static int 720 sdmmc_mem_select_transfer_mode(struct sdmmc_softc *sc, int support_func) 721 { 722 if (ISSET(sc->sc_flags, SMF_UHS_MODE)) { 723 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR104) && 724 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR104)) { 725 return SD_ACCESS_MODE_SDR104; 726 } 727 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_DDR50) && 728 ISSET(support_func, 1 << SD_ACCESS_MODE_DDR50)) { 729 return SD_ACCESS_MODE_DDR50; 730 } 731 if (ISSET(sc->sc_caps, SMC_CAPS_UHS_SDR50) && 732 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR50)) { 733 return SD_ACCESS_MODE_SDR50; 734 } 735 } 736 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) && 737 ISSET(support_func, 1 << SD_ACCESS_MODE_SDR25)) { 738 return SD_ACCESS_MODE_SDR25; 739 } 740 return SD_ACCESS_MODE_SDR12; 741 } 742 743 static int 744 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 745 { 746 int support_func, best_func, bus_clock, error, i; 747 sdmmc_bitfield512_t status; /* Switch Function Status */ 748 bool ddr = false; 749 750 /* change bus clock */ 751 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 752 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock, false); 753 if (error) { 754 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 755 return error; 756 } 757 758 error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr); 759 if (error) { 760 aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n"); 761 return error; 762 } 763 error = sdmmc_mem_decode_scr(sc, sf); 764 if (error) 765 return error; 766 767 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 768 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 769 DPRINTF(("%s: change bus width\n", SDMMCDEVNAME(sc))); 770 error = sdmmc_set_bus_width(sf, 4); 771 if (error) { 772 aprint_error_dev(sc->sc_dev, 773 "can't change bus width (%d bit)\n", 4); 774 return error; 775 } 776 sf->width = 4; 777 } 778 779 best_func = 0; 780 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 781 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 782 DPRINTF(("%s: switch func mode 0\n", SDMMCDEVNAME(sc))); 783 error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status); 784 if (error) { 785 aprint_error_dev(sc->sc_dev, 786 "switch func mode 0 failed\n"); 787 return error; 788 } 789 790 support_func = SFUNC_STATUS_GROUP(&status, 1); 791 792 if (!ISSET(sc->sc_flags, SMF_UHS_MODE) && support_func & 0x1c) { 793 /* XXX UHS-I card started in 1.8V mode, switch now */ 794 error = sdmmc_mem_signal_voltage(sc, 795 SDMMC_SIGNAL_VOLTAGE_180); 796 if (error) { 797 aprint_error_dev(sc->sc_dev, 798 "failed to recover UHS card\n"); 799 return error; 800 } 801 SET(sc->sc_flags, SMF_UHS_MODE); 802 } 803 804 for (i = 0; i < __arraycount(switch_group0_functions); i++) { 805 if (!(support_func & (1 << i))) 806 continue; 807 DPRINTF(("%s: card supports mode %s\n", 808 SDMMCDEVNAME(sc), 809 switch_group0_functions[i].name)); 810 } 811 812 best_func = sdmmc_mem_select_transfer_mode(sc, support_func); 813 814 DPRINTF(("%s: using mode %s\n", SDMMCDEVNAME(sc), 815 switch_group0_functions[best_func].name)); 816 817 if (best_func != 0) { 818 DPRINTF(("%s: switch func mode 1(func=%d)\n", 819 SDMMCDEVNAME(sc), best_func)); 820 error = 821 sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status); 822 if (error) { 823 aprint_error_dev(sc->sc_dev, 824 "switch func mode 1 failed:" 825 " group 1 function %d(0x%2x)\n", 826 best_func, support_func); 827 return error; 828 } 829 sf->csd.tran_speed = 830 switch_group0_functions[best_func].freq; 831 832 if (best_func == SD_ACCESS_MODE_DDR50) 833 ddr = true; 834 835 /* Wait 400KHz x 8 clock (2.5us * 8 + slop) */ 836 delay(25); 837 } 838 } 839 840 /* update bus clock */ 841 if (sc->sc_busclk > sf->csd.tran_speed) 842 sc->sc_busclk = sf->csd.tran_speed; 843 if (sc->sc_busclk == bus_clock && sc->sc_busddr == ddr) 844 return 0; 845 846 /* change bus clock */ 847 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk, 848 ddr); 849 if (error) { 850 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 851 return error; 852 } 853 854 sc->sc_transfer_mode = switch_group0_functions[best_func].name; 855 sc->sc_busddr = ddr; 856 857 return 0; 858 } 859 860 static int 861 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 862 { 863 int width, value, hs_timing, bus_clock, error; 864 char ext_csd[512]; 865 uint32_t sectors = 0; 866 867 sc->sc_transfer_mode = NULL; 868 869 /* change bus clock */ 870 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 871 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock, false); 872 if (error) { 873 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 874 return error; 875 } 876 877 if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 878 error = sdmmc_mem_send_cxd_data(sc, 879 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 880 if (error) { 881 aprint_error_dev(sc->sc_dev, 882 "can't read EXT_CSD (error=%d)\n", error); 883 return error; 884 } 885 if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) && 886 (ext_csd[EXT_CSD_STRUCTURE] > EXT_CSD_STRUCTURE_VER_1_2)) { 887 aprint_error_dev(sc->sc_dev, 888 "unrecognised future version (%d)\n", 889 ext_csd[EXT_CSD_STRUCTURE]); 890 return ENOTSUP; 891 } 892 893 sc->sc_transfer_mode = NULL; 894 if (ISSET(sc->sc_caps, SMC_CAPS_MMC_HS200) && 895 ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_HS200_1_8V) { 896 sf->csd.tran_speed = 200000; /* 200MHz SDR */ 897 hs_timing = 2; 898 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_52M) { 899 sf->csd.tran_speed = 52000; /* 52MHz */ 900 hs_timing = 1; 901 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_26M) { 902 sf->csd.tran_speed = 26000; /* 26MHz */ 903 hs_timing = 0; 904 } else { 905 aprint_error_dev(sc->sc_dev, 906 "unknown CARD_TYPE: 0x%x\n", 907 ext_csd[EXT_CSD_CARD_TYPE]); 908 return ENOTSUP; 909 } 910 911 if (hs_timing == 2) { 912 error = sdmmc_chip_signal_voltage(sc->sc_sct, 913 sc->sc_sch, SDMMC_SIGNAL_VOLTAGE_180); 914 if (error) 915 hs_timing = 1; 916 } 917 918 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 919 width = 8; 920 value = EXT_CSD_BUS_WIDTH_8; 921 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 922 width = 4; 923 value = EXT_CSD_BUS_WIDTH_4; 924 } else { 925 width = 1; 926 value = EXT_CSD_BUS_WIDTH_1; 927 } 928 929 if (width != 1) { 930 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 931 EXT_CSD_BUS_WIDTH, value); 932 if (error == 0) 933 error = sdmmc_chip_bus_width(sc->sc_sct, 934 sc->sc_sch, width); 935 else { 936 DPRINTF(("%s: can't change bus width" 937 " (%d bit)\n", SDMMCDEVNAME(sc), width)); 938 return error; 939 } 940 941 /* XXXX: need bus test? (using by CMD14 & CMD19) */ 942 } 943 sf->width = width; 944 945 if (hs_timing == 1 && 946 !ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 947 hs_timing = 0; 948 } 949 if (hs_timing) { 950 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 951 EXT_CSD_HS_TIMING, hs_timing); 952 if (error) { 953 aprint_error_dev(sc->sc_dev, 954 "can't change high speed\n"); 955 return error; 956 } 957 } 958 959 if (sc->sc_busclk > sf->csd.tran_speed) 960 sc->sc_busclk = sf->csd.tran_speed; 961 if (sc->sc_busclk != bus_clock) { 962 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 963 sc->sc_busclk, false); 964 if (error) { 965 aprint_error_dev(sc->sc_dev, 966 "can't change bus clock\n"); 967 return error; 968 } 969 } 970 971 if (hs_timing) { 972 error = sdmmc_mem_send_cxd_data(sc, 973 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 974 if (error) { 975 aprint_error_dev(sc->sc_dev, 976 "can't re-read EXT_CSD\n"); 977 return error; 978 } 979 if (ext_csd[EXT_CSD_HS_TIMING] != hs_timing) { 980 aprint_error_dev(sc->sc_dev, 981 "HS_TIMING set failed\n"); 982 return EINVAL; 983 } 984 } 985 986 sectors = ext_csd[EXT_CSD_SEC_COUNT + 0] << 0 | 987 ext_csd[EXT_CSD_SEC_COUNT + 1] << 8 | 988 ext_csd[EXT_CSD_SEC_COUNT + 2] << 16 | 989 ext_csd[EXT_CSD_SEC_COUNT + 3] << 24; 990 if (sectors > (2u * 1024 * 1024 * 1024) / 512) { 991 SET(sf->flags, SFF_SDHC); 992 sf->csd.capacity = sectors; 993 } 994 995 if (hs_timing == 2) { 996 sc->sc_transfer_mode = "HS200"; 997 } else { 998 sc->sc_transfer_mode = NULL; 999 } 1000 } else { 1001 if (sc->sc_busclk > sf->csd.tran_speed) 1002 sc->sc_busclk = sf->csd.tran_speed; 1003 if (sc->sc_busclk != bus_clock) { 1004 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 1005 sc->sc_busclk, false); 1006 if (error) { 1007 aprint_error_dev(sc->sc_dev, 1008 "can't change bus clock\n"); 1009 return error; 1010 } 1011 } 1012 } 1013 1014 return 0; 1015 } 1016 1017 static int 1018 sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp) 1019 { 1020 struct sdmmc_command cmd; 1021 int error; 1022 1023 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1024 memset(&cmd, 0, sizeof cmd); 1025 cmd.c_opcode = MMC_ALL_SEND_CID; 1026 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 1027 1028 error = sdmmc_mmc_command(sc, &cmd); 1029 } else { 1030 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CID, &cmd.c_resp, 1031 sizeof(cmd.c_resp)); 1032 } 1033 1034 #ifdef SDMMC_DEBUG 1035 if (error == 0) 1036 sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp)); 1037 #endif 1038 if (error == 0 && resp != NULL) 1039 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 1040 return error; 1041 } 1042 1043 static int 1044 sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf, 1045 sdmmc_response *resp) 1046 { 1047 struct sdmmc_command cmd; 1048 int error; 1049 1050 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1051 memset(&cmd, 0, sizeof cmd); 1052 cmd.c_opcode = MMC_SEND_CSD; 1053 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1054 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 1055 1056 error = sdmmc_mmc_command(sc, &cmd); 1057 } else { 1058 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CSD, &cmd.c_resp, 1059 sizeof(cmd.c_resp)); 1060 } 1061 1062 #ifdef SDMMC_DEBUG 1063 if (error == 0) 1064 sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp)); 1065 #endif 1066 if (error == 0 && resp != NULL) 1067 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 1068 return error; 1069 } 1070 1071 static int 1072 sdmmc_mem_send_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf, 1073 uint32_t *scr) 1074 { 1075 struct sdmmc_command cmd; 1076 bus_dma_segment_t ds[1]; 1077 void *ptr = NULL; 1078 int datalen = 8; 1079 int rseg; 1080 int error = 0; 1081 1082 /* Don't lock */ 1083 1084 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1085 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, 1086 ds, 1, &rseg, BUS_DMA_NOWAIT); 1087 if (error) 1088 goto out; 1089 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1090 BUS_DMA_NOWAIT); 1091 if (error) 1092 goto dmamem_free; 1093 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1094 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1095 if (error) 1096 goto dmamem_unmap; 1097 1098 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1099 BUS_DMASYNC_PREREAD); 1100 } else { 1101 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1102 if (ptr == NULL) 1103 goto out; 1104 } 1105 1106 memset(&cmd, 0, sizeof(cmd)); 1107 cmd.c_data = ptr; 1108 cmd.c_datalen = datalen; 1109 cmd.c_blklen = datalen; 1110 cmd.c_arg = 0; 1111 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1112 cmd.c_opcode = SD_APP_SEND_SCR; 1113 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1114 cmd.c_dmamap = sc->sc_dmap; 1115 1116 error = sdmmc_app_command(sc, sf, &cmd); 1117 if (error == 0) { 1118 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1119 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1120 BUS_DMASYNC_POSTREAD); 1121 } 1122 memcpy(scr, ptr, datalen); 1123 } 1124 1125 out: 1126 if (ptr != NULL) { 1127 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1128 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1129 dmamem_unmap: 1130 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1131 dmamem_free: 1132 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1133 } else { 1134 free(ptr, M_DEVBUF); 1135 } 1136 } 1137 DPRINTF(("%s: sdmem_mem_send_scr: error = %d\n", SDMMCDEVNAME(sc), 1138 error)); 1139 1140 #ifdef SDMMC_DEBUG 1141 if (error == 0) 1142 sdmmc_dump_data("SCR", scr, datalen); 1143 #endif 1144 return error; 1145 } 1146 1147 static int 1148 sdmmc_mem_decode_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf) 1149 { 1150 sdmmc_response resp; 1151 int ver; 1152 1153 memset(resp, 0, sizeof(resp)); 1154 /* 1155 * Change the raw-scr received from the DMA stream to resp. 1156 */ 1157 resp[0] = be32toh(sf->raw_scr[1]) >> 8; // LSW 1158 resp[1] = be32toh(sf->raw_scr[0]); // MSW 1159 resp[0] |= (resp[1] & 0xff) << 24; 1160 resp[1] >>= 8; 1161 1162 ver = SCR_STRUCTURE(resp); 1163 sf->scr.sd_spec = SCR_SD_SPEC(resp); 1164 sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 1165 1166 DPRINTF(("%s: sdmmc_mem_decode_scr: %08x%08x ver=%d, spec=%d, bus width=%d\n", 1167 SDMMCDEVNAME(sc), resp[1], resp[0], 1168 ver, sf->scr.sd_spec, sf->scr.bus_width)); 1169 1170 if (ver != 0 && ver != 1) { 1171 DPRINTF(("%s: unknown structure version: %d\n", 1172 SDMMCDEVNAME(sc), ver)); 1173 return EINVAL; 1174 } 1175 return 0; 1176 } 1177 1178 static int 1179 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 1180 size_t datalen) 1181 { 1182 struct sdmmc_command cmd; 1183 bus_dma_segment_t ds[1]; 1184 void *ptr = NULL; 1185 int rseg; 1186 int error = 0; 1187 1188 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1189 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, ds, 1190 1, &rseg, BUS_DMA_NOWAIT); 1191 if (error) 1192 goto out; 1193 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1194 BUS_DMA_NOWAIT); 1195 if (error) 1196 goto dmamem_free; 1197 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1198 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1199 if (error) 1200 goto dmamem_unmap; 1201 1202 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1203 BUS_DMASYNC_PREREAD); 1204 } else { 1205 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1206 if (ptr == NULL) 1207 goto out; 1208 } 1209 1210 memset(&cmd, 0, sizeof(cmd)); 1211 cmd.c_data = ptr; 1212 cmd.c_datalen = datalen; 1213 cmd.c_blklen = datalen; 1214 cmd.c_opcode = opcode; 1215 cmd.c_arg = 0; 1216 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_SPI_R1; 1217 if (opcode == MMC_SEND_EXT_CSD) 1218 SET(cmd.c_flags, SCF_RSP_R1); 1219 else 1220 SET(cmd.c_flags, SCF_RSP_R2); 1221 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1222 cmd.c_dmamap = sc->sc_dmap; 1223 1224 error = sdmmc_mmc_command(sc, &cmd); 1225 if (error == 0) { 1226 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1227 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1228 BUS_DMASYNC_POSTREAD); 1229 } 1230 memcpy(data, ptr, datalen); 1231 #ifdef SDMMC_DEBUG 1232 sdmmc_dump_data("CXD", data, datalen); 1233 #endif 1234 } 1235 1236 out: 1237 if (ptr != NULL) { 1238 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1239 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1240 dmamem_unmap: 1241 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1242 dmamem_free: 1243 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1244 } else { 1245 free(ptr, M_DEVBUF); 1246 } 1247 } 1248 return error; 1249 } 1250 1251 static int 1252 sdmmc_set_bus_width(struct sdmmc_function *sf, int width) 1253 { 1254 struct sdmmc_softc *sc = sf->sc; 1255 struct sdmmc_command cmd; 1256 int error; 1257 1258 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1259 return ENODEV; 1260 1261 memset(&cmd, 0, sizeof(cmd)); 1262 cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 1263 cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 1264 1265 switch (width) { 1266 case 1: 1267 cmd.c_arg = SD_ARG_BUS_WIDTH_1; 1268 break; 1269 1270 case 4: 1271 cmd.c_arg = SD_ARG_BUS_WIDTH_4; 1272 break; 1273 1274 default: 1275 return EINVAL; 1276 } 1277 1278 error = sdmmc_app_command(sc, sf, &cmd); 1279 if (error == 0) 1280 error = sdmmc_chip_bus_width(sc->sc_sct, sc->sc_sch, width); 1281 return error; 1282 } 1283 1284 static int 1285 sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 1286 int function, sdmmc_bitfield512_t *status) 1287 { 1288 struct sdmmc_softc *sc = sf->sc; 1289 struct sdmmc_command cmd; 1290 bus_dma_segment_t ds[1]; 1291 void *ptr = NULL; 1292 int gsft, rseg, error = 0; 1293 const int statlen = 64; 1294 1295 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 1296 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 1297 return EINVAL; 1298 1299 if (group <= 0 || group > 6 || 1300 function < 0 || function > 15) 1301 return EINVAL; 1302 1303 gsft = (group - 1) << 2; 1304 1305 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1306 error = bus_dmamem_alloc(sc->sc_dmat, statlen, PAGE_SIZE, 0, ds, 1307 1, &rseg, BUS_DMA_NOWAIT); 1308 if (error) 1309 goto out; 1310 error = bus_dmamem_map(sc->sc_dmat, ds, 1, statlen, &ptr, 1311 BUS_DMA_NOWAIT); 1312 if (error) 1313 goto dmamem_free; 1314 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, statlen, 1315 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1316 if (error) 1317 goto dmamem_unmap; 1318 1319 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1320 BUS_DMASYNC_PREREAD); 1321 } else { 1322 ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 1323 if (ptr == NULL) 1324 goto out; 1325 } 1326 1327 memset(&cmd, 0, sizeof(cmd)); 1328 cmd.c_data = ptr; 1329 cmd.c_datalen = statlen; 1330 cmd.c_blklen = statlen; 1331 cmd.c_opcode = SD_SEND_SWITCH_FUNC; 1332 cmd.c_arg = 1333 (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 1334 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1335 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1336 cmd.c_dmamap = sc->sc_dmap; 1337 1338 error = sdmmc_mmc_command(sc, &cmd); 1339 if (error == 0) { 1340 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1341 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1342 BUS_DMASYNC_POSTREAD); 1343 } 1344 memcpy(status, ptr, statlen); 1345 } 1346 1347 out: 1348 if (ptr != NULL) { 1349 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1350 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1351 dmamem_unmap: 1352 bus_dmamem_unmap(sc->sc_dmat, ptr, statlen); 1353 dmamem_free: 1354 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1355 } else { 1356 free(ptr, M_DEVBUF); 1357 } 1358 } 1359 1360 if (error == 0) 1361 sdmmc_be512_to_bitfield512(status); 1362 1363 return error; 1364 } 1365 1366 static int 1367 sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 1368 uint8_t value) 1369 { 1370 struct sdmmc_softc *sc = sf->sc; 1371 struct sdmmc_command cmd; 1372 1373 memset(&cmd, 0, sizeof(cmd)); 1374 cmd.c_opcode = MMC_SWITCH; 1375 cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 1376 (index << 16) | (value << 8) | set; 1377 cmd.c_flags = SCF_RSP_SPI_R1B | SCF_RSP_R1B | SCF_CMD_AC; 1378 1379 return sdmmc_mmc_command(sc, &cmd); 1380 } 1381 1382 /* 1383 * SPI mode function 1384 */ 1385 static int 1386 sdmmc_mem_spi_read_ocr(struct sdmmc_softc *sc, uint32_t hcs, uint32_t *card_ocr) 1387 { 1388 struct sdmmc_command cmd; 1389 int error; 1390 1391 memset(&cmd, 0, sizeof(cmd)); 1392 cmd.c_opcode = MMC_READ_OCR; 1393 cmd.c_arg = hcs ? MMC_OCR_HCS : 0; 1394 cmd.c_flags = SCF_RSP_SPI_R3; 1395 1396 error = sdmmc_mmc_command(sc, &cmd); 1397 if (error == 0 && card_ocr != NULL) 1398 *card_ocr = cmd.c_resp[1]; 1399 DPRINTF(("%s: sdmmc_mem_spi_read_ocr: error=%d, ocr=%#x\n", 1400 SDMMCDEVNAME(sc), error, cmd.c_resp[1])); 1401 return error; 1402 } 1403 1404 /* 1405 * read/write function 1406 */ 1407 /* read */ 1408 static int 1409 sdmmc_mem_single_read_block(struct sdmmc_function *sf, uint32_t blkno, 1410 u_char *data, size_t datalen) 1411 { 1412 struct sdmmc_softc *sc = sf->sc; 1413 int error = 0; 1414 int i; 1415 1416 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1417 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1418 1419 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1420 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno + i, 1421 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1422 if (error) 1423 break; 1424 } 1425 return error; 1426 } 1427 1428 /* 1429 * Simulate multi-segment dma transfer. 1430 */ 1431 static int 1432 sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *sf, 1433 uint32_t blkno, u_char *data, size_t datalen) 1434 { 1435 struct sdmmc_softc *sc = sf->sc; 1436 bool use_bbuf = false; 1437 int error = 0; 1438 int i; 1439 1440 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1441 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1442 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1443 use_bbuf = true; 1444 break; 1445 } 1446 } 1447 if (use_bbuf) { 1448 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1449 BUS_DMASYNC_PREREAD); 1450 1451 error = sdmmc_mem_read_block_subr(sf, sf->bbuf_dmap, 1452 blkno, data, datalen); 1453 if (error) { 1454 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1455 return error; 1456 } 1457 1458 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1459 BUS_DMASYNC_POSTREAD); 1460 1461 /* Copy from bounce buffer */ 1462 memcpy(data, sf->bbuf, datalen); 1463 1464 return 0; 1465 } 1466 1467 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1468 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1469 1470 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1471 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_READ); 1472 if (error) 1473 return error; 1474 1475 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1476 BUS_DMASYNC_PREREAD); 1477 1478 error = sdmmc_mem_read_block_subr(sf, sf->sseg_dmap, 1479 blkno, data, len); 1480 if (error) { 1481 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1482 return error; 1483 } 1484 1485 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1486 BUS_DMASYNC_POSTREAD); 1487 1488 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1489 1490 blkno += len / SDMMC_SECTOR_SIZE; 1491 data += len; 1492 } 1493 return 0; 1494 } 1495 1496 static int 1497 sdmmc_mem_read_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1498 uint32_t blkno, u_char *data, size_t datalen) 1499 { 1500 struct sdmmc_softc *sc = sf->sc; 1501 struct sdmmc_command cmd; 1502 int error; 1503 1504 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1505 error = sdmmc_select_card(sc, sf); 1506 if (error) 1507 goto out; 1508 } 1509 1510 memset(&cmd, 0, sizeof(cmd)); 1511 cmd.c_data = data; 1512 cmd.c_datalen = datalen; 1513 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1514 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1515 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1516 cmd.c_arg = blkno; 1517 if (!ISSET(sf->flags, SFF_SDHC)) 1518 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1519 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1520 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1521 cmd.c_dmamap = dmap; 1522 1523 error = sdmmc_mmc_command(sc, &cmd); 1524 if (error) 1525 goto out; 1526 1527 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1528 if (cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 1529 memset(&cmd, 0, sizeof cmd); 1530 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1531 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1532 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1533 error = sdmmc_mmc_command(sc, &cmd); 1534 if (error) 1535 goto out; 1536 } 1537 } 1538 1539 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1540 do { 1541 memset(&cmd, 0, sizeof(cmd)); 1542 cmd.c_opcode = MMC_SEND_STATUS; 1543 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1544 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1545 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1546 error = sdmmc_mmc_command(sc, &cmd); 1547 if (error) 1548 break; 1549 /* XXX time out */ 1550 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1551 } 1552 1553 out: 1554 return error; 1555 } 1556 1557 int 1558 sdmmc_mem_read_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1559 size_t datalen) 1560 { 1561 struct sdmmc_softc *sc = sf->sc; 1562 int error; 1563 1564 SDMMC_LOCK(sc); 1565 mutex_enter(&sc->sc_mtx); 1566 1567 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1568 error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 1569 goto out; 1570 } 1571 1572 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1573 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1574 datalen); 1575 goto out; 1576 } 1577 1578 /* DMA transfer */ 1579 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1580 BUS_DMA_NOWAIT|BUS_DMA_READ); 1581 if (error) 1582 goto out; 1583 1584 #ifdef SDMMC_DEBUG 1585 printf("data=%p, datalen=%zu\n", data, datalen); 1586 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1587 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1588 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1589 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1590 } 1591 #endif 1592 1593 if (sc->sc_dmap->dm_nsegs > 1 1594 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1595 error = sdmmc_mem_single_segment_dma_read_block(sf, blkno, 1596 data, datalen); 1597 goto unload; 1598 } 1599 1600 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1601 BUS_DMASYNC_PREREAD); 1602 1603 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1604 datalen); 1605 if (error) 1606 goto unload; 1607 1608 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1609 BUS_DMASYNC_POSTREAD); 1610 unload: 1611 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1612 1613 out: 1614 mutex_exit(&sc->sc_mtx); 1615 SDMMC_UNLOCK(sc); 1616 1617 return error; 1618 } 1619 1620 /* write */ 1621 static int 1622 sdmmc_mem_single_write_block(struct sdmmc_function *sf, uint32_t blkno, 1623 u_char *data, size_t datalen) 1624 { 1625 struct sdmmc_softc *sc = sf->sc; 1626 int error = 0; 1627 int i; 1628 1629 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1630 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1631 1632 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1633 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno + i, 1634 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1635 if (error) 1636 break; 1637 } 1638 return error; 1639 } 1640 1641 /* 1642 * Simulate multi-segment dma transfer. 1643 */ 1644 static int 1645 sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *sf, 1646 uint32_t blkno, u_char *data, size_t datalen) 1647 { 1648 struct sdmmc_softc *sc = sf->sc; 1649 bool use_bbuf = false; 1650 int error = 0; 1651 int i; 1652 1653 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1654 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1655 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1656 use_bbuf = true; 1657 break; 1658 } 1659 } 1660 if (use_bbuf) { 1661 /* Copy to bounce buffer */ 1662 memcpy(sf->bbuf, data, datalen); 1663 1664 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1665 BUS_DMASYNC_PREWRITE); 1666 1667 error = sdmmc_mem_write_block_subr(sf, sf->bbuf_dmap, 1668 blkno, data, datalen); 1669 if (error) { 1670 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1671 return error; 1672 } 1673 1674 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1675 BUS_DMASYNC_POSTWRITE); 1676 1677 return 0; 1678 } 1679 1680 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1681 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1682 1683 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1684 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1685 if (error) 1686 return error; 1687 1688 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1689 BUS_DMASYNC_PREWRITE); 1690 1691 error = sdmmc_mem_write_block_subr(sf, sf->sseg_dmap, 1692 blkno, data, len); 1693 if (error) { 1694 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1695 return error; 1696 } 1697 1698 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1699 BUS_DMASYNC_POSTWRITE); 1700 1701 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1702 1703 blkno += len / SDMMC_SECTOR_SIZE; 1704 data += len; 1705 } 1706 1707 return error; 1708 } 1709 1710 static int 1711 sdmmc_mem_write_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1712 uint32_t blkno, u_char *data, size_t datalen) 1713 { 1714 struct sdmmc_softc *sc = sf->sc; 1715 struct sdmmc_command cmd; 1716 int error; 1717 1718 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1719 error = sdmmc_select_card(sc, sf); 1720 if (error) 1721 goto out; 1722 } 1723 1724 memset(&cmd, 0, sizeof(cmd)); 1725 cmd.c_data = data; 1726 cmd.c_datalen = datalen; 1727 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1728 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1729 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1730 cmd.c_arg = blkno; 1731 if (!ISSET(sf->flags, SFF_SDHC)) 1732 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1733 cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 1734 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1735 cmd.c_dmamap = dmap; 1736 1737 error = sdmmc_mmc_command(sc, &cmd); 1738 if (error) 1739 goto out; 1740 1741 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1742 if (cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1743 memset(&cmd, 0, sizeof(cmd)); 1744 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1745 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1746 error = sdmmc_mmc_command(sc, &cmd); 1747 if (error) 1748 goto out; 1749 } 1750 } 1751 1752 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1753 do { 1754 memset(&cmd, 0, sizeof(cmd)); 1755 cmd.c_opcode = MMC_SEND_STATUS; 1756 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1757 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1758 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1759 error = sdmmc_mmc_command(sc, &cmd); 1760 if (error) 1761 break; 1762 /* XXX time out */ 1763 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1764 } 1765 1766 out: 1767 return error; 1768 } 1769 1770 int 1771 sdmmc_mem_write_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1772 size_t datalen) 1773 { 1774 struct sdmmc_softc *sc = sf->sc; 1775 int error; 1776 1777 SDMMC_LOCK(sc); 1778 mutex_enter(&sc->sc_mtx); 1779 1780 if (sdmmc_chip_write_protect(sc->sc_sct, sc->sc_sch)) { 1781 aprint_normal_dev(sc->sc_dev, "write-protected\n"); 1782 error = EIO; 1783 goto out; 1784 } 1785 1786 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1787 error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1788 goto out; 1789 } 1790 1791 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1792 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1793 datalen); 1794 goto out; 1795 } 1796 1797 /* DMA transfer */ 1798 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1799 BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1800 if (error) 1801 goto out; 1802 1803 #ifdef SDMMC_DEBUG 1804 aprint_normal_dev(sc->sc_dev, "%s: data=%p, datalen=%zu\n", 1805 __func__, data, datalen); 1806 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1807 aprint_normal_dev(sc->sc_dev, 1808 "%s: seg#%d: addr=%#lx, size=%#lx\n", __func__, i, 1809 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1810 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1811 } 1812 #endif 1813 1814 if (sc->sc_dmap->dm_nsegs > 1 1815 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1816 error = sdmmc_mem_single_segment_dma_write_block(sf, blkno, 1817 data, datalen); 1818 goto unload; 1819 } 1820 1821 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1822 BUS_DMASYNC_PREWRITE); 1823 1824 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1825 datalen); 1826 if (error) 1827 goto unload; 1828 1829 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1830 BUS_DMASYNC_POSTWRITE); 1831 unload: 1832 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1833 1834 out: 1835 mutex_exit(&sc->sc_mtx); 1836 SDMMC_UNLOCK(sc); 1837 1838 return error; 1839 } 1840
Indexes created Wed Sep 24 05:09:52 GMT 2025