sdmmcvar.h revision 1.30.4.2
1 /* $NetBSD: sdmmcvar.h,v 1.30.4.2 2020/08/09 14:03:07 martin Exp $ */ 2 /* $OpenBSD: sdmmcvar.h,v 1.13 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _SDMMCVAR_H_ 21 #define _SDMMCVAR_H_ 22 23 #ifdef _KERNEL_OPT 24 #include "opt_sdmmc.h" 25 #endif 26 27 #include <sys/queue.h> 28 #include <sys/mutex.h> 29 #include <sys/callout.h> 30 #include <sys/evcnt.h> 31 32 #include <sys/bus.h> 33 34 #include <dev/sdmmc/sdmmcchip.h> 35 #include <dev/sdmmc/sdmmcreg.h> 36 37 #define SDMMC_SECTOR_SIZE_SB 9 38 #define SDMMC_SECTOR_SIZE (1 << SDMMC_SECTOR_SIZE_SB) /* =512 */ 39 40 struct sdmmc_csd { 41 int csdver; /* CSD structure format */ 42 u_int mmcver; /* MMC version (for CID format) */ 43 int capacity; /* total number of sectors */ 44 int read_bl_len; /* block length for reads */ 45 int write_bl_len; /* block length for writes */ 46 int r2w_factor; 47 int tran_speed; /* transfer speed (kbit/s) */ 48 int ccc; /* Card Command Class for SD */ 49 /* ... */ 50 }; 51 52 struct sdmmc_ext_csd { 53 uint8_t rev; 54 uint8_t rst_n_function; /* RST_n_FUNCTION */ 55 uint32_t cache_size; 56 }; 57 58 struct sdmmc_cid { 59 int mid; /* manufacturer identification number */ 60 int oid; /* OEM/product identification number */ 61 char pnm[8]; /* product name (MMC v1 has the longest) */ 62 int rev; /* product revision */ 63 int psn; /* product serial number */ 64 int mdt; /* manufacturing date */ 65 }; 66 67 struct sdmmc_scr { 68 int sd_spec; 69 int bus_width; 70 }; 71 72 typedef uint32_t sdmmc_response[4]; 73 74 struct sdmmc_softc; 75 76 struct sdmmc_task { 77 void (*func)(void *arg); 78 void *arg; 79 int onqueue; 80 struct sdmmc_softc *sc; 81 TAILQ_ENTRY(sdmmc_task) next; 82 }; 83 84 #define sdmmc_init_task(xtask, xfunc, xarg) \ 85 do { \ 86 (xtask)->func = (xfunc); \ 87 (xtask)->arg = (xarg); \ 88 (xtask)->onqueue = 0; \ 89 (xtask)->sc = NULL; \ 90 } while (/*CONSTCOND*/0) 91 92 struct sdmmc_command { 93 struct sdmmc_task c_task; /* task queue entry */ 94 uint16_t c_opcode; /* SD or MMC command index */ 95 uint32_t c_arg; /* SD/MMC command argument */ 96 sdmmc_response c_resp; /* response buffer */ 97 bus_dmamap_t c_dmamap; 98 int c_dmaseg; /* DMA segment number */ 99 int c_dmaoff; /* offset in DMA segment */ 100 void *c_data; /* buffer to send or read into */ 101 int c_datalen; /* length of data buffer */ 102 int c_blklen; /* block length */ 103 int c_flags; /* see below */ 104 #define SCF_ITSDONE (1U << 0) /* command is complete */ 105 #define SCF_RSP_PRESENT (1U << 1) 106 #define SCF_RSP_BSY (1U << 2) 107 #define SCF_RSP_136 (1U << 3) 108 #define SCF_RSP_CRC (1U << 4) 109 #define SCF_RSP_IDX (1U << 5) 110 #define SCF_CMD_READ (1U << 6) /* read command (data expected) */ 111 /* non SPI */ 112 #define SCF_CMD_AC (0U << 8) 113 #define SCF_CMD_ADTC (1U << 8) 114 #define SCF_CMD_BC (2U << 8) 115 #define SCF_CMD_BCR (3U << 8) 116 #define SCF_CMD_MASK (3U << 8) 117 /* SPI */ 118 #define SCF_RSP_SPI_S1 (1U << 10) 119 #define SCF_RSP_SPI_S2 (1U << 11) 120 #define SCF_RSP_SPI_B4 (1U << 12) 121 #define SCF_RSP_SPI_BSY (1U << 13) 122 /* Probing */ 123 #define SCF_TOUT_OK (1U << 14) /* command timeout expected */ 124 /* Command hints */ 125 #define SCF_XFER_SDHC (1U << 15) /* card is SDHC */ 126 #define SCF_POLL (1U << 16) /* polling required */ 127 #define SCF_NEED_BOUNCE (1U << 17) /* (driver) transfer requires bounce buffer */ 128 /* response types */ 129 #define SCF_RSP_R0 0 /* none */ 130 #define SCF_RSP_R1 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 131 #define SCF_RSP_R1B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) 132 #define SCF_RSP_R2 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_136) 133 #define SCF_RSP_R3 (SCF_RSP_PRESENT) 134 #define SCF_RSP_R4 (SCF_RSP_PRESENT) 135 #define SCF_RSP_R5 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 136 #define SCF_RSP_R5B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) 137 #define SCF_RSP_R6 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 138 #define SCF_RSP_R7 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 139 #define SCF_RSP_MASK (0x1f << 1) 140 /* SPI */ 141 #define SCF_RSP_SPI_R1 (SCF_RSP_SPI_S1) 142 #define SCF_RSP_SPI_R1B (SCF_RSP_SPI_S1|SCF_RSP_SPI_BSY) 143 #define SCF_RSP_SPI_R2 (SCF_RSP_SPI_S1|SCF_RSP_SPI_S2) 144 #define SCF_RSP_SPI_R3 (SCF_RSP_SPI_S1|SCF_RSP_SPI_B4) 145 #define SCF_RSP_SPI_R4 (SCF_RSP_SPI_S1|SCF_RSP_SPI_B4) 146 #define SCF_RSP_SPI_R5 (SCF_RSP_SPI_S1|SCF_RSP_SPI_S2) 147 #define SCF_RSP_SPI_R7 (SCF_RSP_SPI_S1|SCF_RSP_SPI_B4) 148 #define SCF_RSP_SPI_MASK (0xf << 10) 149 int c_error; /* errno value on completion */ 150 151 /* Host controller owned fields for data xfer in progress */ 152 int c_resid; /* remaining I/O */ 153 u_char *c_buf; /* remaining data */ 154 }; 155 156 /* 157 * Decoded PC Card 16 based Card Information Structure (CIS), 158 * per card (function 0) and per function (1 and greater). 159 */ 160 struct sdmmc_cis { 161 uint16_t manufacturer; 162 #define SDMMC_VENDOR_INVALID 0xffff 163 uint16_t product; 164 #define SDMMC_PRODUCT_INVALID 0xffff 165 uint8_t function; 166 #define SDMMC_FUNCTION_INVALID 0xff 167 u_char cis1_major; 168 u_char cis1_minor; 169 char cis1_info_buf[256]; 170 char *cis1_info[4]; 171 }; 172 173 /* 174 * Structure describing either an SD card I/O function or a SD/MMC 175 * memory card from a "stack of cards" that responded to CMD2. For a 176 * combo card with one I/O function and one memory card, there will be 177 * two of these structures allocated. Each card slot has such a list 178 * of sdmmc_function structures. 179 */ 180 struct sdmmc_function { 181 /* common members */ 182 struct sdmmc_softc *sc; /* card slot softc */ 183 uint16_t rca; /* relative card address */ 184 int interface; /* SD/MMC:0, SDIO:standard interface */ 185 int width; /* bus width */ 186 u_int blklen; /* block length */ 187 int flags; 188 #define SFF_ERROR 0x0001 /* function is poo; ignore it */ 189 #define SFF_SDHC 0x0002 /* SD High Capacity card */ 190 #define SFF_CACHE_ENABLED 0x0004 /* cache enabled */ 191 SIMPLEQ_ENTRY(sdmmc_function) sf_list; 192 /* SD card I/O function members */ 193 int number; /* I/O function number or -1 */ 194 device_t child; /* function driver */ 195 struct sdmmc_cis cis; /* decoded CIS */ 196 /* SD/MMC memory card members */ 197 struct sdmmc_csd csd; /* decoded CSD value */ 198 struct sdmmc_ext_csd ext_csd; /* decoded EXT_CSD value */ 199 struct sdmmc_cid cid; /* decoded CID value */ 200 sdmmc_response raw_cid; /* temp. storage for decoding */ 201 uint32_t raw_scr[2]; 202 struct sdmmc_scr scr; /* decoded SCR value */ 203 204 void *bbuf; /* bounce buffer */ 205 bus_dmamap_t bbuf_dmap; /* DMA map for bounce buffer */ 206 bus_dmamap_t sseg_dmap; /* DMA map for single segment */ 207 }; 208 209 /* 210 * Structure describing a single SD/MMC/SDIO card slot. 211 */ 212 struct sdmmc_softc { 213 device_t sc_dev; /* base device */ 214 #define SDMMCDEVNAME(sc) (device_xname(sc->sc_dev)) 215 216 sdmmc_chipset_tag_t sc_sct; /* host controller chipset tag */ 217 sdmmc_spi_chipset_tag_t sc_spi_sct; 218 sdmmc_chipset_handle_t sc_sch; /* host controller chipset handle */ 219 bus_dma_tag_t sc_dmat; 220 bus_dmamap_t sc_dmap; 221 #define SDMMC_MAXNSEGS ((MAXPHYS / PAGE_SIZE) + 1) 222 223 struct kmutex sc_mtx; /* lock around host controller */ 224 int sc_dying; /* bus driver is shutting down */ 225 226 uint32_t sc_flags; 227 #define SMF_INITED 0x0001 228 #define SMF_SD_MODE 0x0002 /* host in SD mode (MMC otherwise) */ 229 #define SMF_IO_MODE 0x0004 /* host in I/O mode (SD mode only) */ 230 #define SMF_MEM_MODE 0x0008 /* host in memory mode (SD or MMC) */ 231 #define SMF_CARD_PRESENT 0x4000 /* card presence noticed */ 232 #define SMF_CARD_ATTACHED 0x8000 /* card driver(s) attached */ 233 #define SMF_UHS_MODE 0x10000 /* host in UHS mode */ 234 235 uint32_t sc_caps; /* host capability */ 236 #define SMC_CAPS_AUTO_STOP __BIT(0) /* send CMD12 automagically by host */ 237 #define SMC_CAPS_4BIT_MODE __BIT(1) /* 4-bits data bus width */ 238 #define SMC_CAPS_DMA __BIT(2) /* DMA transfer */ 239 #define SMC_CAPS_SPI_MODE __BIT(3) /* SPI mode */ 240 #define SMC_CAPS_POLL_CARD_DET __BIT(4) /* Polling card detect */ 241 #define SMC_CAPS_SINGLE_ONLY __BIT(5) /* only single read/write */ 242 #define SMC_CAPS_8BIT_MODE __BIT(6) /* 8-bits data bus width */ 243 #define SMC_CAPS_MULTI_SEG_DMA __BIT(7) /* multiple segment DMA transfer */ 244 #define SMC_CAPS_SD_HIGHSPEED __BIT(8) /* SD high-speed timing */ 245 #define SMC_CAPS_MMC_HIGHSPEED __BIT(9) /* MMC high-speed timing */ 246 #define SMC_CAPS_MMC_DDR52 __BIT(10) /* MMC HS DDR52 timing */ 247 /* __BIT(11) */ 248 #define SMC_CAPS_UHS_SDR50 __BIT(12) /* UHS SDR50 timing */ 249 #define SMC_CAPS_UHS_SDR104 __BIT(13) /* UHS SDR104 timing */ 250 #define SMC_CAPS_UHS_DDR50 __BIT(14) /* UHS DDR50 timing */ 251 #define SMC_CAPS_UHS_MASK (SMC_CAPS_UHS_SDR50 \ 252 | SMC_CAPS_UHS_SDR104 \ 253 | SMC_CAPS_UHS_DDR50) 254 #define SMC_CAPS_MMC_HS200 __BIT(15) /* eMMC HS200 timing */ 255 #define SMC_CAPS_POLLING __BIT(30) /* driver supports cmd polling */ 256 257 /* function */ 258 int sc_function_count; /* number of I/O functions (SDIO) */ 259 struct sdmmc_function *sc_card; /* selected card */ 260 struct sdmmc_function *sc_fn0; /* function 0, the card itself */ 261 SIMPLEQ_HEAD(, sdmmc_function) sf_head; /* list of card functions */ 262 263 /* task queue */ 264 struct lwp *sc_tskq_lwp; /* asynchronous tasks */ 265 TAILQ_HEAD(, sdmmc_task) sc_tskq; /* task thread work queue */ 266 struct kmutex sc_tskq_mtx; 267 struct kcondvar sc_tskq_cv; 268 struct sdmmc_task *sc_curtask; 269 270 /* discover task */ 271 struct sdmmc_task sc_discover_task; /* card attach/detach task */ 272 struct kmutex sc_discover_task_mtx; 273 274 /* interrupt task */ 275 struct sdmmc_task sc_intr_task; /* card interrupt task */ 276 TAILQ_HEAD(, sdmmc_intr_handler) sc_intrq; /* interrupt handlers */ 277 278 u_int sc_clkmin; /* host min bus clock */ 279 u_int sc_clkmax; /* host max bus clock */ 280 u_int sc_busclk; /* host bus clock */ 281 bool sc_busddr; /* host bus clock is in DDR mode */ 282 int sc_buswidth; /* host bus width */ 283 const char *sc_transfer_mode; /* current transfer mode */ 284 285 callout_t sc_card_detect_ch; /* polling card insert/remove */ 286 287 /* event counters */ 288 struct evcnt sc_ev_xfer; /* xfer count */ 289 struct evcnt sc_ev_xfer_aligned[8]; /* aligned xfer counts */ 290 struct evcnt sc_ev_xfer_unaligned; /* unaligned xfer count */ 291 struct evcnt sc_ev_xfer_error; /* error xfer count */ 292 }; 293 294 /* 295 * Attach devices at the sdmmc bus. 296 */ 297 struct sdmmc_attach_args { 298 uint16_t manufacturer; 299 uint16_t product; 300 int interface; 301 struct sdmmc_function *sf; 302 }; 303 304 struct sdmmc_product { 305 uint16_t pp_vendor; 306 uint16_t pp_product; 307 const char *pp_cisinfo[4]; 308 }; 309 310 #ifndef IPL_SDMMC 311 #define IPL_SDMMC IPL_BIO 312 #endif 313 314 #ifndef splsdmmc 315 #define splsdmmc() splbio() 316 #endif 317 318 #define SDMMC_LOCK(sc) 319 #define SDMMC_UNLOCK(sc) 320 321 #ifdef SDMMC_DEBUG 322 extern int sdmmcdebug; 323 #endif 324 325 void sdmmc_add_task(struct sdmmc_softc *, struct sdmmc_task *); 326 bool sdmmc_del_task(struct sdmmc_softc *, struct sdmmc_task *, kmutex_t *); 327 328 struct sdmmc_function *sdmmc_function_alloc(struct sdmmc_softc *); 329 void sdmmc_function_free(struct sdmmc_function *); 330 int sdmmc_set_bus_power(struct sdmmc_softc *, uint32_t, uint32_t); 331 int sdmmc_mmc_command(struct sdmmc_softc *, struct sdmmc_command *); 332 int sdmmc_app_command(struct sdmmc_softc *, struct sdmmc_function *, 333 struct sdmmc_command *); 334 void sdmmc_stop_transmission(struct sdmmc_softc *); 335 void sdmmc_go_idle_state(struct sdmmc_softc *); 336 int sdmmc_select_card(struct sdmmc_softc *, struct sdmmc_function *); 337 int sdmmc_set_relative_addr(struct sdmmc_softc *, struct sdmmc_function *); 338 339 void sdmmc_intr_enable(struct sdmmc_function *); 340 void sdmmc_intr_disable(struct sdmmc_function *); 341 void *sdmmc_intr_establish(device_t, int (*)(void *), void *, const char *); 342 void sdmmc_intr_disestablish(void *); 343 void sdmmc_intr_task(void *); 344 345 int sdmmc_decode_csd(struct sdmmc_softc *, sdmmc_response, 346 struct sdmmc_function *); 347 int sdmmc_decode_cid(struct sdmmc_softc *, sdmmc_response, 348 struct sdmmc_function *); 349 void sdmmc_print_cid(struct sdmmc_cid *); 350 #ifdef SDMMC_DUMP_CSD 351 void sdmmc_print_csd(sdmmc_response, struct sdmmc_csd *); 352 #endif 353 void sdmmc_dump_data(const char *, void *, size_t); 354 355 int sdmmc_io_enable(struct sdmmc_softc *); 356 void sdmmc_io_scan(struct sdmmc_softc *); 357 int sdmmc_io_init(struct sdmmc_softc *, struct sdmmc_function *); 358 int sdmmc_io_set_blocklen(struct sdmmc_function *, int); 359 uint8_t sdmmc_io_read_1(struct sdmmc_function *, int); 360 uint16_t sdmmc_io_read_2(struct sdmmc_function *, int); 361 uint32_t sdmmc_io_read_4(struct sdmmc_function *, int); 362 int sdmmc_io_read_multi_1(struct sdmmc_function *, int, u_char *, int); 363 int sdmmc_io_read_region_1(struct sdmmc_function *, int, u_char *, int); 364 void sdmmc_io_write_1(struct sdmmc_function *, int, uint8_t); 365 void sdmmc_io_write_2(struct sdmmc_function *, int, uint16_t); 366 void sdmmc_io_write_4(struct sdmmc_function *, int, uint32_t); 367 int sdmmc_io_write_multi_1(struct sdmmc_function *, int, u_char *, int); 368 int sdmmc_io_write_region_1(struct sdmmc_function *, int, u_char *, int); 369 int sdmmc_io_function_enable(struct sdmmc_function *); 370 void sdmmc_io_function_disable(struct sdmmc_function *); 371 int sdmmc_io_function_abort(struct sdmmc_function *); 372 373 int sdmmc_read_cis(struct sdmmc_function *, struct sdmmc_cis *); 374 void sdmmc_print_cis(struct sdmmc_function *); 375 void sdmmc_check_cis_quirks(struct sdmmc_function *); 376 377 int sdmmc_mem_enable(struct sdmmc_softc *); 378 void sdmmc_mem_scan(struct sdmmc_softc *); 379 int sdmmc_mem_init(struct sdmmc_softc *, struct sdmmc_function *); 380 int sdmmc_mem_send_op_cond(struct sdmmc_softc *, uint32_t, uint32_t *); 381 int sdmmc_mem_send_if_cond(struct sdmmc_softc *, uint32_t, uint32_t *); 382 int sdmmc_mem_set_blocklen(struct sdmmc_softc *, struct sdmmc_function *, 383 int); 384 int sdmmc_mem_read_block(struct sdmmc_function *, uint32_t, u_char *, 385 size_t); 386 int sdmmc_mem_write_block(struct sdmmc_function *, uint32_t, u_char *, 387 size_t); 388 int sdmmc_mem_discard(struct sdmmc_function *, uint32_t, uint32_t); 389 int sdmmc_mem_flush_cache(struct sdmmc_function *, bool); 390 391 void sdmmc_pause(u_int, kmutex_t *); 392 393 #endif /* _SDMMCVAR_H_ */ 394
Indexes created Mon Oct 20 20:10:13 GMT 2025