sdmmcvar.h revision 1.38
1 /* $NetBSD: sdmmcvar.h,v 1.38 2025/01/17 11:54:50 jmcneill Exp $ */ 2 /* $OpenBSD: sdmmcvar.h,v 1.13 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _SDMMCVAR_H_ 21 #define _SDMMCVAR_H_ 22 23 #ifdef _KERNEL_OPT 24 #include "opt_sdmmc.h" 25 #endif 26 27 #include <sys/queue.h> 28 #include <sys/mutex.h> 29 #include <sys/callout.h> 30 #include <sys/evcnt.h> 31 32 #include <sys/bus.h> 33 34 #include <dev/sdmmc/sdmmcchip.h> 35 #include <dev/sdmmc/sdmmcreg.h> 36 37 #define SDMMC_SECTOR_SIZE_SB 9 38 #define SDMMC_SECTOR_SIZE (1 << SDMMC_SECTOR_SIZE_SB) /* =512 */ 39 40 struct sdmmc_csd { 41 int csdver; /* CSD structure format */ 42 u_int mmcver; /* MMC version (for CID format) */ 43 int capacity; /* total number of sectors */ 44 int read_bl_len; /* block length for reads */ 45 int write_bl_len; /* block length for writes */ 46 int r2w_factor; 47 int tran_speed; /* transfer speed (kbit/s) */ 48 int ccc; /* Card Command Class for SD */ 49 /* ... */ 50 }; 51 52 struct sdmmc_ext_csd { 53 uint8_t rev; 54 uint8_t rst_n_function; /* RST_n_FUNCTION */ 55 uint32_t cache_size; 56 }; 57 58 struct sdmmc_cid { 59 int mid; /* manufacturer identification number */ 60 int oid; /* OEM/product identification number */ 61 char pnm[8]; /* product name (MMC v1 has the longest) */ 62 int rev; /* product revision */ 63 int psn; /* product serial number */ 64 int mdt; /* manufacturing date */ 65 }; 66 67 struct sdmmc_scr { 68 int sd_spec; 69 int sd_spec3; 70 int sd_spec4; 71 int bus_width; 72 bool support_cmd48; 73 }; 74 75 struct sdmmc_ssr { 76 bool cache; /* cache supported */ 77 }; 78 79 struct sdmmc_ext_regset { 80 bool valid; 81 uint8_t fno; 82 uint32_t start_addr; 83 }; 84 85 struct sdmmc_ext_sd { 86 struct sdmmc_ext_regset pef; /* Performance Enhancement */ 87 }; 88 89 90 typedef uint32_t sdmmc_response[4]; 91 92 struct sdmmc_softc; 93 94 struct sdmmc_task { 95 void (*func)(void *arg); 96 void *arg; 97 int onqueue; 98 struct sdmmc_softc *sc; 99 TAILQ_ENTRY(sdmmc_task) next; 100 }; 101 102 #define sdmmc_init_task(xtask, xfunc, xarg) \ 103 do { \ 104 (xtask)->func = (xfunc); \ 105 (xtask)->arg = (xarg); \ 106 (xtask)->onqueue = 0; \ 107 (xtask)->sc = NULL; \ 108 } while (/*CONSTCOND*/0) 109 110 struct sdmmc_command { 111 struct sdmmc_task c_task; /* task queue entry */ 112 uint16_t c_opcode; /* SD or MMC command index */ 113 uint32_t c_arg; /* SD/MMC command argument */ 114 sdmmc_response c_resp; /* response buffer */ 115 bus_dmamap_t c_dmamap; 116 int c_dmaseg; /* DMA segment number */ 117 int c_dmaoff; /* offset in DMA segment */ 118 void *c_data; /* buffer to send or read into */ 119 int c_datalen; /* length of data buffer */ 120 int c_blklen; /* block length */ 121 int c_flags; /* see below */ 122 #define SCF_ITSDONE (1U << 0) /* command is complete */ 123 #define SCF_RSP_PRESENT (1U << 1) 124 #define SCF_RSP_BSY (1U << 2) 125 #define SCF_RSP_136 (1U << 3) 126 #define SCF_RSP_CRC (1U << 4) 127 #define SCF_RSP_IDX (1U << 5) 128 #define SCF_CMD_READ (1U << 6) /* read command (data expected) */ 129 /* non SPI */ 130 #define SCF_CMD_AC (0U << 8) 131 #define SCF_CMD_ADTC (1U << 8) 132 #define SCF_CMD_BC (2U << 8) 133 #define SCF_CMD_BCR (3U << 8) 134 #define SCF_CMD_MASK (3U << 8) 135 /* SPI */ 136 #define SCF_RSP_SPI_S1 (1U << 10) 137 #define SCF_RSP_SPI_S2 (1U << 11) 138 #define SCF_RSP_SPI_B4 (1U << 12) 139 #define SCF_RSP_SPI_BSY (1U << 13) 140 /* Probing */ 141 #define SCF_TOUT_OK (1U << 14) /* command timeout expected */ 142 /* Command hints */ 143 #define SCF_XFER_SDHC (1U << 15) /* card is SDHC */ 144 #define SCF_POLL (1U << 16) /* polling required */ 145 #define SCF_NEED_BOUNCE (1U << 17) /* (driver) transfer requires bounce buffer */ 146 #define SCF_NO_STOP (1U << 18) /* don't enable automatic stop CMD12 */ 147 /* response types */ 148 #define SCF_RSP_R0 0 /* none */ 149 #define SCF_RSP_R1 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 150 #define SCF_RSP_R1B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) 151 #define SCF_RSP_R2 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_136) 152 #define SCF_RSP_R3 (SCF_RSP_PRESENT) 153 #define SCF_RSP_R4 (SCF_RSP_PRESENT) 154 #define SCF_RSP_R5 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 155 #define SCF_RSP_R5B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) 156 #define SCF_RSP_R6 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 157 #define SCF_RSP_R7 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 158 #define SCF_RSP_MASK (0x1f << 1) 159 /* SPI */ 160 #define SCF_RSP_SPI_R1 (SCF_RSP_SPI_S1) 161 #define SCF_RSP_SPI_R1B (SCF_RSP_SPI_S1|SCF_RSP_SPI_BSY) 162 #define SCF_RSP_SPI_R2 (SCF_RSP_SPI_S1|SCF_RSP_SPI_S2) 163 #define SCF_RSP_SPI_R3 (SCF_RSP_SPI_S1|SCF_RSP_SPI_B4) 164 #define SCF_RSP_SPI_R4 (SCF_RSP_SPI_S1|SCF_RSP_SPI_B4) 165 #define SCF_RSP_SPI_R5 (SCF_RSP_SPI_S1|SCF_RSP_SPI_S2) 166 #define SCF_RSP_SPI_R7 (SCF_RSP_SPI_S1|SCF_RSP_SPI_B4) 167 #define SCF_RSP_SPI_MASK (0xf << 10) 168 int c_error; /* errno value on completion */ 169 170 /* Host controller owned fields for data xfer in progress */ 171 int c_resid; /* remaining I/O */ 172 u_char *c_buf; /* remaining data */ 173 }; 174 175 /* 176 * Decoded PC Card 16 based Card Information Structure (CIS), 177 * per card (function 0) and per function (1 and greater). 178 */ 179 struct sdmmc_cis { 180 uint16_t manufacturer; 181 #define SDMMC_VENDOR_INVALID 0xffff 182 uint16_t product; 183 #define SDMMC_PRODUCT_INVALID 0xffff 184 uint8_t function; 185 #define SDMMC_FUNCTION_INVALID 0xff 186 u_char cis1_major; 187 u_char cis1_minor; 188 char cis1_info_buf[256]; 189 char *cis1_info[4]; 190 uint8_t lan_nid[6]; 191 }; 192 193 /* 194 * Structure describing either an SD card I/O function or a SD/MMC 195 * memory card from a "stack of cards" that responded to CMD2. For a 196 * combo card with one I/O function and one memory card, there will be 197 * two of these structures allocated. Each card slot has such a list 198 * of sdmmc_function structures. 199 */ 200 struct sdmmc_function { 201 /* common members */ 202 struct sdmmc_softc *sc; /* card slot softc */ 203 uint16_t rca; /* relative card address */ 204 int interface; /* SD/MMC:0, SDIO:standard interface */ 205 int width; /* bus width */ 206 u_int blklen; /* block length */ 207 int flags; 208 #define SFF_ERROR 0x0001 /* function is poo; ignore it */ 209 #define SFF_SDHC 0x0002 /* SD High Capacity card */ 210 #define SFF_CACHE_ENABLED 0x0004 /* cache enabled */ 211 SIMPLEQ_ENTRY(sdmmc_function) sf_list; 212 /* SD card I/O function members */ 213 int number; /* I/O function number or -1 */ 214 device_t child; /* function driver */ 215 struct sdmmc_cis cis; /* decoded CIS */ 216 /* SD/MMC memory card members */ 217 struct sdmmc_csd csd; /* decoded CSD value */ 218 struct sdmmc_ext_csd ext_csd; /* decoded EXT_CSD value */ 219 struct sdmmc_cid cid; /* decoded CID value */ 220 sdmmc_response raw_cid; /* temp. storage for decoding */ 221 uint32_t raw_scr[2]; 222 struct sdmmc_scr scr; /* decoded SCR value */ 223 struct sdmmc_ssr ssr; /* decoded SSR value */ 224 struct sdmmc_ext_sd ext_sd; /* decoded SD extension value */ 225 226 void *bbuf; /* bounce buffer */ 227 bus_dmamap_t bbuf_dmap; /* DMA map for bounce buffer */ 228 bus_dmamap_t sseg_dmap; /* DMA map for single segment */ 229 }; 230 231 /* 232 * Structure describing a single SD/MMC/SDIO card slot. 233 */ 234 struct sdmmc_softc { 235 device_t sc_dev; /* base device */ 236 #define SDMMCDEVNAME(sc) (device_xname(sc->sc_dev)) 237 238 sdmmc_chipset_tag_t sc_sct; /* host controller chipset tag */ 239 sdmmc_spi_chipset_tag_t sc_spi_sct; 240 sdmmc_chipset_handle_t sc_sch; /* host controller chipset handle */ 241 bus_dma_tag_t sc_dmat; 242 bus_dmamap_t sc_dmap; 243 #define SDMMC_MAXNSEGS ((MAXPHYS / PAGE_SIZE) + 1) 244 245 struct kmutex sc_mtx; /* lock around host controller */ 246 int sc_dying; /* bus driver is shutting down */ 247 248 uint32_t sc_flags; 249 #define SMF_INITED 0x0001 250 #define SMF_SD_MODE 0x0002 /* host in SD mode (MMC otherwise) */ 251 #define SMF_IO_MODE 0x0004 /* host in I/O mode (SD mode only) */ 252 #define SMF_MEM_MODE 0x0008 /* host in memory mode (SD or MMC) */ 253 #define SMF_CARD_PRESENT 0x4000 /* card presence noticed */ 254 #define SMF_CARD_ATTACHED 0x8000 /* card driver(s) attached */ 255 #define SMF_UHS_MODE 0x10000 /* host in UHS mode */ 256 257 uint32_t sc_caps; /* host capability */ 258 #define SMC_CAPS_AUTO_STOP __BIT(0) /* send CMD12 automagically by host */ 259 #define SMC_CAPS_4BIT_MODE __BIT(1) /* 4-bits data bus width */ 260 #define SMC_CAPS_DMA __BIT(2) /* DMA transfer */ 261 #define SMC_CAPS_SPI_MODE __BIT(3) /* SPI mode */ 262 #define SMC_CAPS_POLL_CARD_DET __BIT(4) /* Polling card detect */ 263 #define SMC_CAPS_SINGLE_ONLY __BIT(5) /* only single read/write */ 264 #define SMC_CAPS_8BIT_MODE __BIT(6) /* 8-bits data bus width */ 265 #define SMC_CAPS_MULTI_SEG_DMA __BIT(7) /* multiple segment DMA transfer */ 266 #define SMC_CAPS_SD_HIGHSPEED __BIT(8) /* SD high-speed timing */ 267 #define SMC_CAPS_MMC_HIGHSPEED __BIT(9) /* MMC high-speed timing */ 268 #define SMC_CAPS_MMC_DDR52 __BIT(10) /* MMC HS DDR52 timing */ 269 /* __BIT(11) */ 270 #define SMC_CAPS_UHS_SDR50 __BIT(12) /* UHS SDR50 timing */ 271 #define SMC_CAPS_UHS_SDR104 __BIT(13) /* UHS SDR104 timing */ 272 #define SMC_CAPS_UHS_DDR50 __BIT(14) /* UHS DDR50 timing */ 273 #define SMC_CAPS_UHS_MASK (SMC_CAPS_UHS_SDR50 \ 274 | SMC_CAPS_UHS_SDR104 \ 275 | SMC_CAPS_UHS_DDR50) 276 #define SMC_CAPS_MMC_HS200 __BIT(15) /* eMMC HS200 timing */ 277 #define SMC_CAPS_POLLING __BIT(30) /* driver supports cmd polling */ 278 279 /* function */ 280 int sc_function_count; /* number of I/O functions (SDIO) */ 281 struct sdmmc_function *sc_card; /* selected card */ 282 struct sdmmc_function *sc_fn0; /* function 0, the card itself */ 283 SIMPLEQ_HEAD(, sdmmc_function) sf_head; /* list of card functions */ 284 285 /* task queue */ 286 struct lwp *sc_tskq_lwp; /* asynchronous tasks */ 287 TAILQ_HEAD(, sdmmc_task) sc_tskq; /* task thread work queue */ 288 struct kmutex sc_tskq_mtx; 289 struct kcondvar sc_tskq_cv; 290 struct sdmmc_task *sc_curtask; 291 292 /* discover task */ 293 struct sdmmc_task sc_discover_task; /* card attach/detach task */ 294 struct kmutex sc_discover_task_mtx; 295 296 /* interrupt task */ 297 struct sdmmc_task sc_intr_task; /* card interrupt task */ 298 TAILQ_HEAD(, sdmmc_intr_handler) sc_intrq; /* interrupt handlers */ 299 300 u_int sc_clkmin; /* host min bus clock */ 301 u_int sc_clkmax; /* host max bus clock */ 302 u_int sc_busclk; /* host bus clock */ 303 bool sc_busddr; /* host bus clock is in DDR mode */ 304 int sc_buswidth; /* host bus width */ 305 const char *sc_transfer_mode; /* current transfer mode */ 306 307 callout_t sc_card_detect_ch; /* polling card insert/remove */ 308 309 /* event counters */ 310 struct evcnt sc_ev_xfer; /* xfer count */ 311 struct evcnt sc_ev_xfer_aligned[8]; /* aligned xfer counts */ 312 struct evcnt sc_ev_xfer_unaligned; /* unaligned xfer count */ 313 struct evcnt sc_ev_xfer_error; /* error xfer count */ 314 315 uint32_t sc_max_seg; /* maximum segment size */ 316 }; 317 318 /* 319 * Attach devices at the sdmmc bus. 320 */ 321 struct sdmmc_attach_args { 322 uint16_t manufacturer; 323 uint16_t product; 324 int interface; 325 struct sdmmc_function *sf; 326 }; 327 328 struct sdmmc_product { 329 uint16_t pp_vendor; 330 uint16_t pp_product; 331 const char *pp_cisinfo[4]; 332 }; 333 334 #ifndef IPL_SDMMC 335 #define IPL_SDMMC IPL_BIO 336 #endif 337 338 #ifndef splsdmmc 339 #define splsdmmc() splbio() 340 #endif 341 342 #define SDMMC_LOCK(sc) 343 #define SDMMC_UNLOCK(sc) 344 345 #ifdef SDMMC_DEBUG 346 extern int sdmmcdebug; 347 #endif 348 349 void sdmmc_add_task(struct sdmmc_softc *, struct sdmmc_task *); 350 bool sdmmc_del_task(struct sdmmc_softc *, struct sdmmc_task *, kmutex_t *); 351 352 struct sdmmc_function *sdmmc_function_alloc(struct sdmmc_softc *); 353 void sdmmc_function_free(struct sdmmc_function *); 354 int sdmmc_set_bus_power(struct sdmmc_softc *, uint32_t, uint32_t); 355 int sdmmc_mmc_command(struct sdmmc_softc *, struct sdmmc_command *); 356 int sdmmc_app_command(struct sdmmc_softc *, struct sdmmc_function *, 357 struct sdmmc_command *); 358 void sdmmc_stop_transmission(struct sdmmc_softc *); 359 void sdmmc_go_idle_state(struct sdmmc_softc *); 360 int sdmmc_select_card(struct sdmmc_softc *, struct sdmmc_function *); 361 int sdmmc_set_relative_addr(struct sdmmc_softc *, struct sdmmc_function *); 362 363 void sdmmc_intr_enable(struct sdmmc_function *); 364 void sdmmc_intr_disable(struct sdmmc_function *); 365 void *sdmmc_intr_establish(device_t, int (*)(void *), void *, const char *); 366 void sdmmc_intr_disestablish(void *); 367 void sdmmc_intr_task(void *); 368 369 int sdmmc_decode_csd(struct sdmmc_softc *, sdmmc_response, 370 struct sdmmc_function *); 371 int sdmmc_decode_cid(struct sdmmc_softc *, sdmmc_response, 372 struct sdmmc_function *); 373 void sdmmc_print_cid(struct sdmmc_cid *); 374 #ifdef SDMMC_DUMP_CSD 375 void sdmmc_print_csd(sdmmc_response, struct sdmmc_csd *); 376 #endif 377 void sdmmc_dump_data(const char *, void *, size_t); 378 379 int sdmmc_io_enable(struct sdmmc_softc *); 380 void sdmmc_io_scan(struct sdmmc_softc *); 381 int sdmmc_io_init(struct sdmmc_softc *, struct sdmmc_function *); 382 int sdmmc_io_set_blocklen(struct sdmmc_function *, int); 383 uint8_t sdmmc_io_read_1(struct sdmmc_function *, int); 384 uint16_t sdmmc_io_read_2(struct sdmmc_function *, int); 385 uint32_t sdmmc_io_read_4(struct sdmmc_function *, int); 386 int sdmmc_io_read_multi_1(struct sdmmc_function *, int, u_char *, int); 387 int sdmmc_io_read_region_1(struct sdmmc_function *, int, u_char *, int); 388 void sdmmc_io_write_1(struct sdmmc_function *, int, uint8_t); 389 void sdmmc_io_write_2(struct sdmmc_function *, int, uint16_t); 390 void sdmmc_io_write_4(struct sdmmc_function *, int, uint32_t); 391 int sdmmc_io_write_multi_1(struct sdmmc_function *, int, u_char *, int); 392 int sdmmc_io_write_region_1(struct sdmmc_function *, int, u_char *, int); 393 int sdmmc_io_function_enable(struct sdmmc_function *); 394 void sdmmc_io_function_disable(struct sdmmc_function *); 395 int sdmmc_io_function_abort(struct sdmmc_function *); 396 397 uint32_t sdmmc_cisptr(struct sdmmc_function *); 398 int sdmmc_read_cis(struct sdmmc_function *, struct sdmmc_cis *); 399 void sdmmc_print_cis(struct sdmmc_function *); 400 void sdmmc_check_cis_quirks(struct sdmmc_function *); 401 402 int sdmmc_mem_enable(struct sdmmc_softc *); 403 void sdmmc_mem_scan(struct sdmmc_softc *); 404 int sdmmc_mem_init(struct sdmmc_softc *, struct sdmmc_function *); 405 int sdmmc_mem_send_op_cond(struct sdmmc_softc *, uint32_t, uint32_t *); 406 int sdmmc_mem_send_if_cond(struct sdmmc_softc *, uint32_t, uint32_t *); 407 int sdmmc_mem_set_blocklen(struct sdmmc_softc *, struct sdmmc_function *, 408 int); 409 int sdmmc_mem_read_block(struct sdmmc_function *, uint32_t, u_char *, 410 size_t); 411 int sdmmc_mem_write_block(struct sdmmc_function *, uint32_t, u_char *, 412 size_t); 413 int sdmmc_mem_discard(struct sdmmc_function *, uint32_t, uint32_t); 414 int sdmmc_mem_flush_cache(struct sdmmc_function *, bool); 415 416 void sdmmc_pause(u_int, kmutex_t *); 417 418 #endif /* _SDMMCVAR_H_ */ 419
Indexes created Fri Oct 17 23:09:53 GMT 2025