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      1  1.1  simonb /* $NetBSD: x1241reg.h,v 1.1 2002/11/12 01:00:59 simonb Exp $ */
      2  1.1  simonb 
      3  1.1  simonb /*
      4  1.1  simonb  * Copyright 2002 Wasabi Systems, Inc.
      5  1.1  simonb  * All rights reserved.
      6  1.1  simonb  *
      7  1.1  simonb  * Written by Simon Burge for Wasabi Systems, Inc.
      8  1.1  simonb  *
      9  1.1  simonb  * Redistribution and use in source and binary forms, with or without
     10  1.1  simonb  * modification, are permitted provided that the following conditions
     11  1.1  simonb  * are met:
     12  1.1  simonb  * 1. Redistributions of source code must retain the above copyright
     13  1.1  simonb  *    notice, this list of conditions and the following disclaimer.
     14  1.1  simonb  * 2. Redistributions in binary form must reproduce the above copyright
     15  1.1  simonb  *    notice, this list of conditions and the following disclaimer in the
     16  1.1  simonb  *    documentation and/or other materials provided with the distribution.
     17  1.1  simonb  * 3. All advertising materials mentioning features or use of this software
     18  1.1  simonb  *    must display the following acknowledgement:
     19  1.1  simonb  *      This product includes software developed for the NetBSD Project by
     20  1.1  simonb  *      Wasabi Systems, Inc.
     21  1.1  simonb  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  1.1  simonb  *    or promote products derived from this software without specific prior
     23  1.1  simonb  *    written permission.
     24  1.1  simonb  *
     25  1.1  simonb  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  1.1  simonb  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  1.1  simonb  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  1.1  simonb  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  1.1  simonb  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  1.1  simonb  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  1.1  simonb  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  1.1  simonb  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  1.1  simonb  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  1.1  simonb  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  1.1  simonb  * POSSIBILITY OF SUCH DAMAGE.
     36  1.1  simonb  */
     37  1.1  simonb 
     38  1.1  simonb #ifndef _DEV_SMBUS_X1241REG_H_
     39  1.1  simonb #define	_DEV_SMBUS_X1241REG_H_
     40  1.1  simonb 
     41  1.1  simonb /*
     42  1.1  simonb  * The X1241 appears at two fixed addresses on the SMBus, one each for
     43  1.1  simonb  * the EEPROM array and the real time clock.
     44  1.1  simonb  */
     45  1.1  simonb #define	X1241_ARRAY_SLAVEADDR	0x57
     46  1.1  simonb #define	X1241_RTC_SLAVEADDR	0x6f
     47  1.1  simonb 
     48  1.1  simonb #define	X1241REG_BL		0x10	/* Control register */
     49  1.1  simonb #define	X1241REG_SC		0x30	/* Seconds */
     50  1.1  simonb #define	X1241REG_MN		0x31	/* Minutes */
     51  1.1  simonb #define	X1241REG_HR		0x32	/* Hours */
     52  1.1  simonb #define	X1241REG_DT		0x33	/* Day of month */
     53  1.1  simonb #define	X1241REG_MO		0x34	/* Month */
     54  1.1  simonb #define	X1241REG_YR		0x35	/* Year */
     55  1.1  simonb #define	X1241REG_DW		0x36	/* Day of Week */
     56  1.1  simonb #define	X1241REG_Y2K		0x37	/* Year 2K */
     57  1.1  simonb #define	X1241REG_SR		0x3f	/* Status register */
     58  1.1  simonb 
     59  1.1  simonb /* Register bits for the status register */
     60  1.1  simonb #define	X1241REG_SR_BAT		0x80	/* currently on battery power */
     61  1.1  simonb #define	X1241REG_SR_RWEL	0x04	/* r/w latch is enabled, can write RTC */
     62  1.1  simonb #define	X1241REG_SR_WEL		0x02	/* r/w latch is unlocked, can enable r/w now */
     63  1.1  simonb #define	X1241REG_SR_RTCF	0x01	/* clock failed */
     64  1.1  simonb 
     65  1.1  simonb /* Register bits for the block protect register */
     66  1.1  simonb #define	X1241REG_BL_BP2		0x80	/* block protect 2 */
     67  1.1  simonb #define	X1241REG_BL_BP1		0x40	/* block protect 1 */
     68  1.1  simonb #define	X1241REG_BL_BP0		0x20	/* block protect 0 */
     69  1.1  simonb #define	X1241REG_BL_WD1		0x10	/* watchdog timeout 0 */
     70  1.1  simonb #define	X1241REG_BL_WD0		0x08	/* watchdog timeout 1 */
     71  1.1  simonb 
     72  1.1  simonb /* Register bits for the hours register */
     73  1.1  simonb #define	X1241REG_HR_MIL		0x80	/* military time format */
     74  1.1  simonb 
     75  1.1  simonb #endif /* _DEV_SMBUS_X1241REG_H_ */
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