scmdspi.c revision 1.6
1 2 /* $NetBSD: scmdspi.c,v 1.6 2025/09/12 13:48:26 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 2021 Brad Spencer <brad (at) anduin.eldar.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __KERNEL_RCSID(0, "$NetBSD: scmdspi.c,v 1.6 2025/09/12 13:48:26 thorpej Exp $"); 22 23 /* 24 * SPI driver for the Sparkfun Serial motor controller. 25 * Uses the common scmd driver to do the real work. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/kernel.h> 31 #include <sys/device.h> 32 #include <sys/module.h> 33 #include <sys/conf.h> 34 #include <sys/sysctl.h> 35 #include <sys/mutex.h> 36 #include <sys/condvar.h> 37 #include <sys/pool.h> 38 #include <sys/kmem.h> 39 40 #include <dev/i2c/i2cvar.h> 41 #include <dev/spi/spivar.h> 42 #include <dev/ic/scmdreg.h> 43 #include <dev/ic/scmdvar.h> 44 45 static const struct device_compatible_entry compat_data[] = { 46 { .compat = "sparkfun,scmd-motor-driver" }, 47 48 DEVICE_COMPAT_EOL 49 }; 50 51 extern void scmd_attach(struct scmd_sc *); 52 53 static int scmdspi_match(device_t, cfdata_t, void *); 54 static void scmdspi_attach(device_t, device_t, void *); 55 static int scmdspi_detach(device_t, int); 56 static int scmdspi_activate(device_t, enum devact); 57 58 #define SCMD_DEBUG 59 #ifdef SCMD_DEBUG 60 #define DPRINTF(s, l, x) \ 61 do { \ 62 if (l <= s->sc_scmddebug) \ 63 printf x; \ 64 } while (/*CONSTCOND*/0) 65 #else 66 #define DPRINTF(s, l, x) 67 #endif 68 69 CFATTACH_DECL_NEW(scmdspi, sizeof(struct scmd_sc), 70 scmdspi_match, scmdspi_attach, scmdspi_detach, scmdspi_activate); 71 72 /* For the SPI interface on this device, the reads are done in an odd 73 * manner. The first part is normal enough, you send the register binary 74 * or'ed with 0x80 and then the receive the data. However, you MUST also 75 * then receive a dummy value, otherwise everything gets out of sync and 76 * no further reads appear to work unless you do a SPI receive all by itself. 77 * This is documented in the data sheet for this device. 78 * 79 * Please note that the Ardunio code does this a little differently. What is 80 * below works on a Raspberry PI 3 without any apparent problems. 81 * 82 * The delays are also mentioned in the datasheet as being 20us, however, the 83 * Ardunio code does 50us, so do likewise. 84 */ 85 static int 86 scmdspi_read_reg_direct(struct spi_handle *sh, uint8_t reg, 87 uint8_t *buf) 88 { 89 int err; 90 uint8_t b; 91 uint8_t rreg = reg | 0x80; 92 93 err = spi_send(sh, 1, &rreg); 94 if (err) 95 return err; 96 97 delay(50); 98 99 b = SCMD_HOLE_VALUE; 100 err = spi_recv(sh, 1, &b); 101 if (err) 102 return err; 103 104 *buf = b; 105 106 delay(50); 107 108 b = SCMD_HOLE_VALUE; 109 err = spi_recv(sh, 1, &b); 110 delay(50); 111 112 return err; 113 } 114 115 static int 116 scmdspi_read_reg(struct scmd_sc *sc, uint8_t reg, uint8_t *buf) 117 { 118 return scmdspi_read_reg_direct(sc->sc_sh, reg, buf); 119 } 120 121 /* SPI writes to this device are normal enough. You send the register 122 * you want making sure that the high bit, 0x80, is clear and then the 123 * data. 124 * 125 * The rule about waiting between operations appears to not apply, however. 126 * This does more or less what the Ardunio code does. 127 */ 128 static int 129 scmdspi_write_reg_direct(struct spi_handle *sh, uint8_t reg, 130 uint8_t buf) 131 { 132 uint8_t rreg = reg & 0x7F; 133 int err; 134 135 err = spi_send(sh, 1, &rreg); 136 if (err) 137 return err; 138 139 err = spi_send(sh, 1, &buf); 140 if (err) 141 return err; 142 143 delay(50); 144 145 return err; 146 } 147 148 static int 149 scmdspi_write_reg(struct scmd_sc *sc, uint8_t reg, uint8_t buf) 150 { 151 return scmdspi_write_reg_direct(sc->sc_sh, reg, buf); 152 } 153 154 /* These are to satisfy the common code */ 155 static int 156 scmdspi_acquire_bus(struct scmd_sc *sc) 157 { 158 return 0; 159 } 160 161 static void 162 scmdspi_release_bus(struct scmd_sc *sc) 163 { 164 return; 165 } 166 167 /* Nothing more is done here. It would be nice if the device was 168 * actually checked to make sure it was there, but at least on the 169 * Raspberry PI 3 the SPI pins were not set up in ALT0 mode yet and 170 * everything acts like it succeeds. No errors are ever produced while 171 * in that state. 172 */ 173 static int 174 scmdspi_match(device_t parent, cfdata_t match, void *aux) 175 { 176 struct spi_attach_args *sa = aux; 177 int match_result; 178 179 if (spi_use_direct_match(sa, compat_data, &match_result)) { 180 return match_result; 181 } 182 183 return SPI_MATCH_DEFAULT; 184 } 185 186 static void 187 scmdspi_attach(device_t parent, device_t self, void *aux) 188 { 189 struct scmd_sc *sc; 190 struct spi_attach_args *sa; 191 int error; 192 193 sa = aux; 194 sc = device_private(self); 195 196 sc->sc_dev = self; 197 sc->sc_sh = sa->sa_handle; 198 sc->sc_scmddebug = 0; 199 sc->sc_topaddr = 0xff; 200 sc->sc_opened = false; 201 sc->sc_dying = false; 202 sc->sc_func_acquire_bus = &scmdspi_acquire_bus; 203 sc->sc_func_release_bus = &scmdspi_release_bus; 204 sc->sc_func_read_register = &scmdspi_read_reg; 205 sc->sc_func_write_register = &scmdspi_write_reg; 206 207 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_NONE); 208 mutex_init(&sc->sc_condmutex, MUTEX_DEFAULT, IPL_NONE); 209 mutex_init(&sc->sc_dying_mutex, MUTEX_DEFAULT, IPL_NONE); 210 cv_init(&sc->sc_condvar, "scmdspicv"); 211 cv_init(&sc->sc_cond_dying, "scmdspidc"); 212 213 /* configure for 1MHz and SPI mode 0 according to the data sheet */ 214 error = spi_configure(self, sa->sa_handle, SPI_MODE_0, SPI_FREQ_MHz(1)); 215 if (error) { 216 return; 217 } 218 219 /* Please note that if the pins are not set up for SPI, the attachment 220 * will work, but it will not figure out that there are slave modules. 221 * It is likely required that a re-enumeration be performed after the pins 222 * are set. This can be done from userland later. 223 */ 224 scmd_attach(sc); 225 226 return; 227 } 228 229 /* These really do not do a whole lot, as SPI devices do not seem to work 230 * as modules. 231 */ 232 static int 233 scmdspi_detach(device_t self, int flags) 234 { 235 struct scmd_sc *sc; 236 237 sc = device_private(self); 238 239 mutex_enter(&sc->sc_mutex); 240 sc->sc_dying = true; 241 /* If this is true we are still open, destroy the condvar */ 242 if (sc->sc_opened) { 243 mutex_enter(&sc->sc_dying_mutex); 244 DPRINTF(sc, 2, ("%s: Will wait for anything to exit\n", 245 device_xname(sc->sc_dev))); 246 /* In the worst case this will time out after 5 seconds. 247 * It really should not take that long for the drain / whatever 248 * to happen 249 */ 250 cv_timedwait_sig(&sc->sc_cond_dying, 251 &sc->sc_dying_mutex, mstohz(5000)); 252 mutex_exit(&sc->sc_dying_mutex); 253 cv_destroy(&sc->sc_cond_dying); 254 } 255 cv_destroy(&sc->sc_condvar); 256 mutex_exit(&sc->sc_mutex); 257 258 mutex_destroy(&sc->sc_mutex); 259 mutex_destroy(&sc->sc_condmutex); 260 261 return 0; 262 } 263 264 int 265 scmdspi_activate(device_t self, enum devact act) 266 { 267 struct scmd_sc *sc = device_private(self); 268 269 switch (act) { 270 case DVACT_DEACTIVATE: 271 sc->sc_dying = true; 272 return 0; 273 default: 274 return EOPNOTSUPP; 275 } 276 } 277
Indexes created Tue Sep 30 10:09:55 GMT 2025