ssdfb_spi.c revision 1.7 1 1.7 tnn /* $NetBSD: ssdfb_spi.c,v 1.7 2021/08/03 11:30:25 tnn Exp $ */
2 1.1 tnn
3 1.1 tnn /*
4 1.1 tnn * Copyright (c) 2019 The NetBSD Foundation, Inc.
5 1.1 tnn * All rights reserved.
6 1.1 tnn *
7 1.1 tnn * This code is derived from software contributed to The NetBSD Foundation
8 1.1 tnn * by Tobias Nygren.
9 1.1 tnn *
10 1.1 tnn * Redistribution and use in source and binary forms, with or without
11 1.1 tnn * modification, are permitted provided that the following conditions
12 1.1 tnn * are met:
13 1.1 tnn * 1. Redistributions of source code must retain the above copyright
14 1.1 tnn * notice, this list of conditions and the following disclaimer.
15 1.1 tnn * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 tnn * notice, this list of conditions and the following disclaimer in the
17 1.1 tnn * documentation and/or other materials provided with the distribution.
18 1.1 tnn *
19 1.1 tnn * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 tnn * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 tnn * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 tnn * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 tnn * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 tnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 tnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 tnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 tnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 tnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 tnn * POSSIBILITY OF SUCH DAMAGE.
30 1.1 tnn */
31 1.1 tnn
32 1.1 tnn #include <sys/cdefs.h>
33 1.7 tnn __KERNEL_RCSID(0, "$NetBSD: ssdfb_spi.c,v 1.7 2021/08/03 11:30:25 tnn Exp $");
34 1.1 tnn
35 1.1 tnn #include <sys/param.h>
36 1.1 tnn #include <sys/device.h>
37 1.1 tnn #include <sys/kernel.h>
38 1.1 tnn #include <dev/wscons/wsdisplayvar.h>
39 1.1 tnn #include <dev/rasops/rasops.h>
40 1.1 tnn #include <dev/spi/spivar.h>
41 1.1 tnn #include <dev/ic/ssdfbvar.h>
42 1.6 tnn #include "opt_fdt.h"
43 1.6 tnn #ifdef FDT
44 1.6 tnn #include <dev/fdt/fdtvar.h>
45 1.6 tnn #endif
46 1.1 tnn
47 1.1 tnn struct bs_state {
48 1.1 tnn uint8_t *base;
49 1.1 tnn uint8_t *cur;
50 1.1 tnn uint8_t mask;
51 1.1 tnn };
52 1.1 tnn
53 1.1 tnn struct ssdfb_spi_softc {
54 1.1 tnn struct ssdfb_softc sc;
55 1.1 tnn struct spi_handle *sc_sh;
56 1.6 tnn #ifdef FDT
57 1.6 tnn struct fdtbus_gpio_pin *sc_gpio_dc;
58 1.7 tnn struct fdtbus_gpio_pin *sc_gpio_res;
59 1.6 tnn #endif
60 1.1 tnn bool sc_3wiremode;
61 1.1 tnn };
62 1.1 tnn
63 1.1 tnn static int ssdfb_spi_match(device_t, cfdata_t, void *);
64 1.1 tnn static void ssdfb_spi_attach(device_t, device_t, void *);
65 1.1 tnn
66 1.1 tnn static int ssdfb_spi_cmd_3wire(void *, uint8_t *, size_t, bool);
67 1.1 tnn static int ssdfb_spi_xfer_rect_3wire_ssd1322(void *, uint8_t, uint8_t,
68 1.1 tnn uint8_t, uint8_t, uint8_t *, size_t, bool);
69 1.1 tnn
70 1.1 tnn static int ssdfb_spi_cmd_4wire(void *, uint8_t *, size_t, bool);
71 1.1 tnn static int ssdfb_spi_xfer_rect_4wire_ssd1322(void *, uint8_t, uint8_t,
72 1.1 tnn uint8_t, uint8_t, uint8_t *, size_t, bool);
73 1.1 tnn
74 1.1 tnn static void ssdfb_bitstream_init(struct bs_state *, uint8_t *);
75 1.1 tnn static void ssdfb_bitstream_append(struct bs_state *, uint8_t, uint8_t);
76 1.1 tnn static void ssdfb_bitstream_append_cmd(struct bs_state *, uint8_t);
77 1.1 tnn static void ssdfb_bitstream_append_data(struct bs_state *, uint8_t *,
78 1.1 tnn size_t);
79 1.1 tnn static void ssdfb_bitstream_final(struct bs_state *);
80 1.1 tnn
81 1.1 tnn CFATTACH_DECL_NEW(ssdfb_spi, sizeof(struct ssdfb_spi_softc),
82 1.1 tnn ssdfb_spi_match, ssdfb_spi_attach, NULL, NULL);
83 1.1 tnn
84 1.3 tnn static const struct device_compatible_entry compat_data[] = {
85 1.6 tnn { .compat = "solomon,ssd1306", .value = SSDFB_PRODUCT_SSD1306_GENERIC },
86 1.6 tnn { .compat = "solomon,ssd1322", .value = SSDFB_PRODUCT_SSD1322_GENERIC },
87 1.5 thorpej DEVICE_COMPAT_EOL
88 1.3 tnn };
89 1.3 tnn
90 1.1 tnn static int
91 1.1 tnn ssdfb_spi_match(device_t parent, cfdata_t match, void *aux)
92 1.1 tnn {
93 1.1 tnn struct spi_attach_args *sa = aux;
94 1.3 tnn int res;
95 1.3 tnn
96 1.3 tnn res = spi_compatible_match(sa, match, compat_data);
97 1.3 tnn if (!res)
98 1.3 tnn return res;
99 1.1 tnn
100 1.1 tnn /*
101 1.1 tnn * SSD1306 and SSD1322 data sheets specify 100ns cycle time.
102 1.1 tnn */
103 1.1 tnn if (spi_configure(sa->sa_handle, SPI_MODE_0, 10000000))
104 1.3 tnn res = 0;
105 1.1 tnn
106 1.3 tnn return res;
107 1.1 tnn }
108 1.1 tnn
109 1.1 tnn static void
110 1.1 tnn ssdfb_spi_attach(device_t parent, device_t self, void *aux)
111 1.1 tnn {
112 1.1 tnn struct ssdfb_spi_softc *sc = device_private(self);
113 1.1 tnn struct cfdata *cf = device_cfdata(self);
114 1.1 tnn struct spi_attach_args *sa = aux;
115 1.1 tnn int flags = cf->cf_flags;
116 1.1 tnn
117 1.1 tnn sc->sc.sc_dev = self;
118 1.1 tnn sc->sc_sh = sa->sa_handle;
119 1.1 tnn sc->sc.sc_cookie = (void *)sc;
120 1.6 tnn if ((flags & SSDFB_ATTACH_FLAG_PRODUCT_MASK) == SSDFB_PRODUCT_UNKNOWN) {
121 1.6 tnn const struct device_compatible_entry *dce =
122 1.6 tnn device_compatible_lookup(sa->sa_compat, sa->sa_ncompat, compat_data);
123 1.6 tnn if (dce)
124 1.6 tnn flags |= (int)dce->value;
125 1.6 tnn else
126 1.6 tnn flags |= SSDFB_PRODUCT_SSD1322_GENERIC;
127 1.6 tnn }
128 1.1 tnn /*
129 1.1 tnn * Note on interface modes.
130 1.1 tnn *
131 1.1 tnn * 3 wire mode sends 9 bit sequences over the MOSI, MSB contains
132 1.1 tnn * the bit that determines if the lower 8 bits are command or data.
133 1.1 tnn *
134 1.1 tnn * 4 wire mode sends 8 bit sequences and requires an auxiliary GPIO
135 1.6 tnn * pin for the command/data bit.
136 1.1 tnn */
137 1.6 tnn #ifdef FDT
138 1.6 tnn const int phandle = sa->sa_cookie;
139 1.7 tnn sc->sc_gpio_dc =
140 1.7 tnn fdtbus_gpio_acquire(phandle, "dc-gpio", GPIO_PIN_OUTPUT);
141 1.6 tnn if (!sc->sc_gpio_dc)
142 1.7 tnn sc->sc_gpio_dc =
143 1.7 tnn fdtbus_gpio_acquire(phandle, "cd-gpio", GPIO_PIN_OUTPUT);
144 1.6 tnn sc->sc_3wiremode = (sc->sc_gpio_dc == NULL);
145 1.7 tnn sc->sc_gpio_res =
146 1.7 tnn fdtbus_gpio_acquire(phandle, "res-gpio", GPIO_PIN_OUTPUT);
147 1.7 tnn if (sc->sc_gpio_res) {
148 1.7 tnn fdtbus_gpio_write_raw(sc->sc_gpio_res, 0);
149 1.7 tnn DELAY(100);
150 1.7 tnn fdtbus_gpio_write_raw(sc->sc_gpio_res, 1);
151 1.7 tnn DELAY(100);
152 1.7 tnn }
153 1.6 tnn #else
154 1.6 tnn sc->sc_3wiremode = true;
155 1.6 tnn #endif
156 1.1 tnn
157 1.1 tnn switch (flags & SSDFB_ATTACH_FLAG_PRODUCT_MASK) {
158 1.1 tnn case SSDFB_PRODUCT_SSD1322_GENERIC:
159 1.1 tnn if (sc->sc_3wiremode) {
160 1.1 tnn sc->sc.sc_transfer_rect =
161 1.1 tnn ssdfb_spi_xfer_rect_3wire_ssd1322;
162 1.1 tnn } else {
163 1.1 tnn sc->sc.sc_transfer_rect =
164 1.1 tnn ssdfb_spi_xfer_rect_4wire_ssd1322;
165 1.1 tnn }
166 1.1 tnn break;
167 1.1 tnn default:
168 1.1 tnn panic("ssdfb_spi_attach: product not implemented");
169 1.1 tnn }
170 1.1 tnn if (sc->sc_3wiremode) {
171 1.1 tnn sc->sc.sc_cmd = ssdfb_spi_cmd_3wire;
172 1.1 tnn } else {
173 1.1 tnn sc->sc.sc_cmd = ssdfb_spi_cmd_4wire;
174 1.1 tnn }
175 1.6 tnn
176 1.1 tnn ssdfb_attach(&sc->sc, flags);
177 1.1 tnn
178 1.1 tnn device_printf(sc->sc.sc_dev, "%d-wire SPI interface\n",
179 1.1 tnn sc->sc_3wiremode == true ? 3 : 4);
180 1.1 tnn }
181 1.1 tnn
182 1.1 tnn static int
183 1.1 tnn ssdfb_spi_cmd_3wire(void *cookie, uint8_t *cmd, size_t len, bool usepoll)
184 1.1 tnn {
185 1.1 tnn struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie;
186 1.1 tnn uint8_t bitstream[16 * 9 / 8];
187 1.1 tnn struct bs_state s;
188 1.1 tnn
189 1.1 tnn KASSERT(len > 0 && len <= 16);
190 1.1 tnn ssdfb_bitstream_init(&s, bitstream);
191 1.1 tnn ssdfb_bitstream_append_cmd(&s, *cmd);
192 1.1 tnn cmd++;
193 1.1 tnn len--;
194 1.1 tnn ssdfb_bitstream_append_data(&s, cmd, len);
195 1.1 tnn ssdfb_bitstream_final(&s);
196 1.1 tnn
197 1.1 tnn return spi_send(sc->sc_sh, s.cur - s.base, bitstream);
198 1.1 tnn }
199 1.1 tnn
200 1.1 tnn static int
201 1.1 tnn ssdfb_spi_xfer_rect_3wire_ssd1322(void *cookie, uint8_t fromcol, uint8_t tocol,
202 1.1 tnn uint8_t fromrow, uint8_t torow, uint8_t *p, size_t stride, bool usepoll)
203 1.1 tnn {
204 1.1 tnn struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie;
205 1.1 tnn uint8_t bitstream[128 * 9 / 8];
206 1.1 tnn struct bs_state s;
207 1.1 tnn uint8_t row;
208 1.1 tnn size_t rlen = (tocol + 1 - fromcol) * 2;
209 1.1 tnn int error;
210 1.1 tnn
211 1.1 tnn /*
212 1.1 tnn * Unlike iic(4), there is no way to force spi(4) to use polling.
213 1.1 tnn */
214 1.2 tnn if (usepoll && !cold)
215 1.1 tnn return 0;
216 1.1 tnn
217 1.1 tnn ssdfb_bitstream_init(&s, bitstream);
218 1.1 tnn ssdfb_bitstream_append_cmd(&s, SSD1322_CMD_SET_ROW_ADDRESS);
219 1.1 tnn ssdfb_bitstream_append_data(&s, &fromrow, 1);
220 1.1 tnn ssdfb_bitstream_append_data(&s, &torow, 1);
221 1.1 tnn ssdfb_bitstream_append_cmd(&s, SSD1322_CMD_SET_COLUMN_ADDRESS);
222 1.1 tnn ssdfb_bitstream_append_data(&s, &fromcol, 1);
223 1.1 tnn ssdfb_bitstream_append_data(&s, &tocol, 1);
224 1.1 tnn ssdfb_bitstream_append_cmd(&s, SSD1322_CMD_WRITE_RAM);
225 1.1 tnn ssdfb_bitstream_final(&s);
226 1.1 tnn error = spi_send(sc->sc_sh, s.cur - s.base, bitstream);
227 1.1 tnn if (error)
228 1.1 tnn return error;
229 1.1 tnn
230 1.1 tnn KASSERT(rlen <= 128);
231 1.1 tnn for (row = fromrow; row <= torow; row++) {
232 1.1 tnn ssdfb_bitstream_init(&s, bitstream);
233 1.1 tnn ssdfb_bitstream_append_data(&s, p, rlen);
234 1.1 tnn ssdfb_bitstream_final(&s);
235 1.1 tnn error = spi_send(sc->sc_sh, s.cur - s.base, bitstream);
236 1.1 tnn if (error)
237 1.1 tnn return error;
238 1.1 tnn p += stride;
239 1.1 tnn }
240 1.1 tnn
241 1.1 tnn return 0;
242 1.1 tnn }
243 1.1 tnn
244 1.1 tnn static void
245 1.1 tnn ssdfb_bitstream_init(struct bs_state *s, uint8_t *dst)
246 1.1 tnn {
247 1.1 tnn s->base = s->cur = dst;
248 1.1 tnn s->mask = 0x80;
249 1.1 tnn }
250 1.1 tnn
251 1.1 tnn static void
252 1.1 tnn ssdfb_bitstream_append(struct bs_state *s, uint8_t b, uint8_t srcmask)
253 1.1 tnn {
254 1.1 tnn while(srcmask) {
255 1.1 tnn if (b & srcmask)
256 1.1 tnn *s->cur |= s->mask;
257 1.1 tnn else
258 1.1 tnn *s->cur &= ~s->mask;
259 1.1 tnn srcmask >>= 1;
260 1.1 tnn s->mask >>= 1;
261 1.1 tnn if (!s->mask) {
262 1.1 tnn s->mask = 0x80;
263 1.1 tnn s->cur++;
264 1.1 tnn }
265 1.1 tnn }
266 1.1 tnn }
267 1.1 tnn
268 1.1 tnn static void
269 1.1 tnn ssdfb_bitstream_append_cmd(struct bs_state *s, uint8_t cmd)
270 1.1 tnn {
271 1.1 tnn ssdfb_bitstream_append(s, 0, 1);
272 1.1 tnn ssdfb_bitstream_append(s, cmd, 0x80);
273 1.1 tnn }
274 1.1 tnn
275 1.1 tnn static void
276 1.1 tnn ssdfb_bitstream_append_data(struct bs_state *s, uint8_t *data, size_t len)
277 1.1 tnn {
278 1.1 tnn while(len--) {
279 1.1 tnn ssdfb_bitstream_append(s, 1, 1);
280 1.1 tnn ssdfb_bitstream_append(s, *data++, 0x80);
281 1.1 tnn }
282 1.1 tnn }
283 1.1 tnn
284 1.1 tnn static void
285 1.1 tnn ssdfb_bitstream_final(struct bs_state *s)
286 1.1 tnn {
287 1.1 tnn uint8_t padding_cmd = SSD1322_CMD_WRITE_RAM;
288 1.1 tnn /* padding_cmd = SSDFB_NOP_CMD; */
289 1.1 tnn
290 1.1 tnn while (s->mask != 0x80) {
291 1.1 tnn ssdfb_bitstream_append_cmd(s, padding_cmd);
292 1.1 tnn }
293 1.1 tnn }
294 1.1 tnn
295 1.1 tnn static void
296 1.1 tnn ssdfb_spi_4wire_set_dc(struct ssdfb_spi_softc *sc, int value)
297 1.1 tnn {
298 1.6 tnn #ifdef FDT
299 1.6 tnn fdtbus_gpio_write_raw(sc->sc_gpio_dc, value);
300 1.6 tnn #else
301 1.1 tnn panic("ssdfb_spi_4wire_set_dc");
302 1.6 tnn #endif
303 1.1 tnn }
304 1.1 tnn
305 1.1 tnn static int
306 1.1 tnn ssdfb_spi_cmd_4wire(void *cookie, uint8_t *cmd, size_t len, bool usepoll)
307 1.1 tnn {
308 1.1 tnn struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie;
309 1.1 tnn int error;
310 1.1 tnn
311 1.1 tnn ssdfb_spi_4wire_set_dc(sc, 0);
312 1.1 tnn error = spi_send(sc->sc_sh, 1, cmd);
313 1.1 tnn if (error)
314 1.1 tnn return error;
315 1.1 tnn if (len > 1) {
316 1.1 tnn ssdfb_spi_4wire_set_dc(sc, 1);
317 1.1 tnn len--;
318 1.1 tnn cmd++;
319 1.1 tnn error = spi_send(sc->sc_sh, len, cmd);
320 1.1 tnn if (error)
321 1.1 tnn return error;
322 1.1 tnn }
323 1.1 tnn
324 1.1 tnn return 0;
325 1.1 tnn }
326 1.1 tnn
327 1.1 tnn static int
328 1.1 tnn ssdfb_spi_xfer_rect_4wire_ssd1322(void *cookie, uint8_t fromcol, uint8_t tocol,
329 1.1 tnn uint8_t fromrow, uint8_t torow, uint8_t *p, size_t stride, bool usepoll)
330 1.1 tnn {
331 1.1 tnn struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie;
332 1.1 tnn uint8_t row;
333 1.1 tnn size_t rlen = (tocol + 1 - fromcol) * 2;
334 1.1 tnn int error;
335 1.1 tnn uint8_t cmd;
336 1.1 tnn uint8_t data[2];
337 1.1 tnn
338 1.1 tnn /*
339 1.1 tnn * Unlike iic(4), there is no way to force spi(4) to use polling.
340 1.1 tnn */
341 1.2 tnn if (usepoll && !cold)
342 1.1 tnn return 0;
343 1.1 tnn
344 1.1 tnn ssdfb_spi_4wire_set_dc(sc, 0);
345 1.1 tnn cmd = SSD1322_CMD_SET_ROW_ADDRESS;
346 1.1 tnn error = spi_send(sc->sc_sh, sizeof(cmd), &cmd);
347 1.1 tnn if (error)
348 1.1 tnn return error;
349 1.1 tnn ssdfb_spi_4wire_set_dc(sc, 1);
350 1.1 tnn data[0] = fromrow;
351 1.1 tnn data[1] = torow;
352 1.1 tnn error = spi_send(sc->sc_sh, sizeof(data), data);
353 1.1 tnn if (error)
354 1.1 tnn return error;
355 1.1 tnn
356 1.1 tnn ssdfb_spi_4wire_set_dc(sc, 0);
357 1.1 tnn cmd = SSD1322_CMD_SET_COLUMN_ADDRESS;
358 1.1 tnn error = spi_send(sc->sc_sh, sizeof(cmd), &cmd);
359 1.1 tnn if (error)
360 1.1 tnn return error;
361 1.1 tnn ssdfb_spi_4wire_set_dc(sc, 1);
362 1.1 tnn data[0] = fromcol;
363 1.1 tnn data[1] = tocol;
364 1.1 tnn error = spi_send(sc->sc_sh, sizeof(data), data);
365 1.1 tnn if (error)
366 1.1 tnn return error;
367 1.1 tnn
368 1.1 tnn ssdfb_spi_4wire_set_dc(sc, 0);
369 1.1 tnn cmd = SSD1322_CMD_WRITE_RAM;
370 1.1 tnn error = spi_send(sc->sc_sh, sizeof(cmd), &cmd);
371 1.1 tnn if (error)
372 1.1 tnn return error;
373 1.1 tnn
374 1.1 tnn ssdfb_spi_4wire_set_dc(sc, 1);
375 1.1 tnn for (row = fromrow; row <= torow; row++) {
376 1.1 tnn error = spi_send(sc->sc_sh, rlen, p);
377 1.1 tnn if (error)
378 1.1 tnn return error;
379 1.1 tnn p += stride;
380 1.1 tnn }
381 1.1 tnn
382 1.1 tnn return 0;
383 1.1 tnn }
384