ssdfb_spi.c revision 1.2
1 /* $NetBSD: ssdfb_spi.c,v 1.2 2019/11/02 17:13:20 tnn Exp $ */ 2 3 /* 4 * Copyright (c) 2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tobias Nygren. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ssdfb_spi.c,v 1.2 2019/11/02 17:13:20 tnn Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/kernel.h> 38 #include <dev/wscons/wsdisplayvar.h> 39 #include <dev/rasops/rasops.h> 40 #include <dev/spi/spivar.h> 41 #include <dev/ic/ssdfbvar.h> 42 43 struct bs_state { 44 uint8_t *base; 45 uint8_t *cur; 46 uint8_t mask; 47 }; 48 49 struct ssdfb_spi_softc { 50 struct ssdfb_softc sc; 51 struct spi_handle *sc_sh; 52 bool sc_3wiremode; 53 }; 54 55 static int ssdfb_spi_match(device_t, cfdata_t, void *); 56 static void ssdfb_spi_attach(device_t, device_t, void *); 57 58 static int ssdfb_spi_cmd_3wire(void *, uint8_t *, size_t, bool); 59 static int ssdfb_spi_xfer_rect_3wire_ssd1322(void *, uint8_t, uint8_t, 60 uint8_t, uint8_t, uint8_t *, size_t, bool); 61 62 static int ssdfb_spi_cmd_4wire(void *, uint8_t *, size_t, bool); 63 static int ssdfb_spi_xfer_rect_4wire_ssd1322(void *, uint8_t, uint8_t, 64 uint8_t, uint8_t, uint8_t *, size_t, bool); 65 66 static void ssdfb_bitstream_init(struct bs_state *, uint8_t *); 67 static void ssdfb_bitstream_append(struct bs_state *, uint8_t, uint8_t); 68 static void ssdfb_bitstream_append_cmd(struct bs_state *, uint8_t); 69 static void ssdfb_bitstream_append_data(struct bs_state *, uint8_t *, 70 size_t); 71 static void ssdfb_bitstream_final(struct bs_state *); 72 73 CFATTACH_DECL_NEW(ssdfb_spi, sizeof(struct ssdfb_spi_softc), 74 ssdfb_spi_match, ssdfb_spi_attach, NULL, NULL); 75 76 static int 77 ssdfb_spi_match(device_t parent, cfdata_t match, void *aux) 78 { 79 struct spi_attach_args *sa = aux; 80 81 /* 82 * SSD1306 and SSD1322 data sheets specify 100ns cycle time. 83 */ 84 if (spi_configure(sa->sa_handle, SPI_MODE_0, 10000000)) 85 return 0; 86 87 return 1; 88 } 89 90 static void 91 ssdfb_spi_attach(device_t parent, device_t self, void *aux) 92 { 93 struct ssdfb_spi_softc *sc = device_private(self); 94 struct cfdata *cf = device_cfdata(self); 95 struct spi_attach_args *sa = aux; 96 int flags = cf->cf_flags; 97 98 sc->sc.sc_dev = self; 99 sc->sc_sh = sa->sa_handle; 100 sc->sc.sc_cookie = (void *)sc; 101 if ((flags & SSDFB_ATTACH_FLAG_PRODUCT_MASK) == SSDFB_PRODUCT_UNKNOWN) 102 flags |= SSDFB_PRODUCT_SSD1322_GENERIC; 103 /* 104 * Note on interface modes. 105 * 106 * 3 wire mode sends 9 bit sequences over the MOSI, MSB contains 107 * the bit that determines if the lower 8 bits are command or data. 108 * 109 * 4 wire mode sends 8 bit sequences and requires an auxiliary GPIO 110 * pin for the command/data bit. But in other to allocate a GPIO pin 111 * we need to use fdt, so only support 3 wire mode in this frontend, 112 * at least for now. 113 */ 114 sc->sc_3wiremode = true; 115 116 switch (flags & SSDFB_ATTACH_FLAG_PRODUCT_MASK) { 117 case SSDFB_PRODUCT_SSD1322_GENERIC: 118 if (sc->sc_3wiremode) { 119 sc->sc.sc_transfer_rect = 120 ssdfb_spi_xfer_rect_3wire_ssd1322; 121 } else { 122 sc->sc.sc_transfer_rect = 123 ssdfb_spi_xfer_rect_4wire_ssd1322; 124 } 125 break; 126 default: 127 panic("ssdfb_spi_attach: product not implemented"); 128 } 129 if (sc->sc_3wiremode) { 130 sc->sc.sc_cmd = ssdfb_spi_cmd_3wire; 131 } else { 132 sc->sc.sc_cmd = ssdfb_spi_cmd_4wire; 133 } 134 135 ssdfb_attach(&sc->sc, flags); 136 137 device_printf(sc->sc.sc_dev, "%d-wire SPI interface\n", 138 sc->sc_3wiremode == true ? 3 : 4); 139 } 140 141 static int 142 ssdfb_spi_cmd_3wire(void *cookie, uint8_t *cmd, size_t len, bool usepoll) 143 { 144 struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie; 145 uint8_t bitstream[16 * 9 / 8]; 146 struct bs_state s; 147 148 KASSERT(len > 0 && len <= 16); 149 ssdfb_bitstream_init(&s, bitstream); 150 ssdfb_bitstream_append_cmd(&s, *cmd); 151 cmd++; 152 len--; 153 ssdfb_bitstream_append_data(&s, cmd, len); 154 ssdfb_bitstream_final(&s); 155 156 return spi_send(sc->sc_sh, s.cur - s.base, bitstream); 157 } 158 159 static int 160 ssdfb_spi_xfer_rect_3wire_ssd1322(void *cookie, uint8_t fromcol, uint8_t tocol, 161 uint8_t fromrow, uint8_t torow, uint8_t *p, size_t stride, bool usepoll) 162 { 163 struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie; 164 uint8_t bitstream[128 * 9 / 8]; 165 struct bs_state s; 166 uint8_t row; 167 size_t rlen = (tocol + 1 - fromcol) * 2; 168 int error; 169 170 /* 171 * Unlike iic(4), there is no way to force spi(4) to use polling. 172 */ 173 if (usepoll && !cold) 174 return 0; 175 176 ssdfb_bitstream_init(&s, bitstream); 177 ssdfb_bitstream_append_cmd(&s, SSD1322_CMD_SET_ROW_ADDRESS); 178 ssdfb_bitstream_append_data(&s, &fromrow, 1); 179 ssdfb_bitstream_append_data(&s, &torow, 1); 180 ssdfb_bitstream_append_cmd(&s, SSD1322_CMD_SET_COLUMN_ADDRESS); 181 ssdfb_bitstream_append_data(&s, &fromcol, 1); 182 ssdfb_bitstream_append_data(&s, &tocol, 1); 183 ssdfb_bitstream_append_cmd(&s, SSD1322_CMD_WRITE_RAM); 184 ssdfb_bitstream_final(&s); 185 error = spi_send(sc->sc_sh, s.cur - s.base, bitstream); 186 if (error) 187 return error; 188 189 KASSERT(rlen <= 128); 190 for (row = fromrow; row <= torow; row++) { 191 ssdfb_bitstream_init(&s, bitstream); 192 ssdfb_bitstream_append_data(&s, p, rlen); 193 ssdfb_bitstream_final(&s); 194 error = spi_send(sc->sc_sh, s.cur - s.base, bitstream); 195 if (error) 196 return error; 197 p += stride; 198 } 199 200 return 0; 201 } 202 203 static void 204 ssdfb_bitstream_init(struct bs_state *s, uint8_t *dst) 205 { 206 s->base = s->cur = dst; 207 s->mask = 0x80; 208 } 209 210 static void 211 ssdfb_bitstream_append(struct bs_state *s, uint8_t b, uint8_t srcmask) 212 { 213 while(srcmask) { 214 if (b & srcmask) 215 *s->cur |= s->mask; 216 else 217 *s->cur &= ~s->mask; 218 srcmask >>= 1; 219 s->mask >>= 1; 220 if (!s->mask) { 221 s->mask = 0x80; 222 s->cur++; 223 } 224 } 225 } 226 227 static void 228 ssdfb_bitstream_append_cmd(struct bs_state *s, uint8_t cmd) 229 { 230 ssdfb_bitstream_append(s, 0, 1); 231 ssdfb_bitstream_append(s, cmd, 0x80); 232 } 233 234 static void 235 ssdfb_bitstream_append_data(struct bs_state *s, uint8_t *data, size_t len) 236 { 237 while(len--) { 238 ssdfb_bitstream_append(s, 1, 1); 239 ssdfb_bitstream_append(s, *data++, 0x80); 240 } 241 } 242 243 static void 244 ssdfb_bitstream_final(struct bs_state *s) 245 { 246 uint8_t padding_cmd = SSD1322_CMD_WRITE_RAM; 247 /* padding_cmd = SSDFB_NOP_CMD; */ 248 249 while (s->mask != 0x80) { 250 ssdfb_bitstream_append_cmd(s, padding_cmd); 251 } 252 } 253 254 static void 255 ssdfb_spi_4wire_set_dc(struct ssdfb_spi_softc *sc, int value) 256 { 257 /* TODO: this should toggle an auxilliary GPIO pin */ 258 panic("ssdfb_spi_4wire_set_dc"); 259 } 260 261 static int 262 ssdfb_spi_cmd_4wire(void *cookie, uint8_t *cmd, size_t len, bool usepoll) 263 { 264 struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie; 265 int error; 266 267 ssdfb_spi_4wire_set_dc(sc, 0); 268 error = spi_send(sc->sc_sh, 1, cmd); 269 if (error) 270 return error; 271 if (len > 1) { 272 ssdfb_spi_4wire_set_dc(sc, 1); 273 len--; 274 cmd++; 275 error = spi_send(sc->sc_sh, len, cmd); 276 if (error) 277 return error; 278 } 279 280 return 0; 281 } 282 283 static int 284 ssdfb_spi_xfer_rect_4wire_ssd1322(void *cookie, uint8_t fromcol, uint8_t tocol, 285 uint8_t fromrow, uint8_t torow, uint8_t *p, size_t stride, bool usepoll) 286 { 287 struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie; 288 uint8_t row; 289 size_t rlen = (tocol + 1 - fromcol) * 2; 290 int error; 291 uint8_t cmd; 292 uint8_t data[2]; 293 294 /* 295 * Unlike iic(4), there is no way to force spi(4) to use polling. 296 */ 297 if (usepoll && !cold) 298 return 0; 299 300 ssdfb_spi_4wire_set_dc(sc, 0); 301 cmd = SSD1322_CMD_SET_ROW_ADDRESS; 302 error = spi_send(sc->sc_sh, sizeof(cmd), &cmd); 303 if (error) 304 return error; 305 ssdfb_spi_4wire_set_dc(sc, 1); 306 data[0] = fromrow; 307 data[1] = torow; 308 error = spi_send(sc->sc_sh, sizeof(data), data); 309 if (error) 310 return error; 311 312 ssdfb_spi_4wire_set_dc(sc, 0); 313 cmd = SSD1322_CMD_SET_COLUMN_ADDRESS; 314 error = spi_send(sc->sc_sh, sizeof(cmd), &cmd); 315 if (error) 316 return error; 317 ssdfb_spi_4wire_set_dc(sc, 1); 318 data[0] = fromcol; 319 data[1] = tocol; 320 error = spi_send(sc->sc_sh, sizeof(data), data); 321 if (error) 322 return error; 323 324 ssdfb_spi_4wire_set_dc(sc, 0); 325 cmd = SSD1322_CMD_WRITE_RAM; 326 error = spi_send(sc->sc_sh, sizeof(cmd), &cmd); 327 if (error) 328 return error; 329 330 ssdfb_spi_4wire_set_dc(sc, 1); 331 for (row = fromrow; row <= torow; row++) { 332 error = spi_send(sc->sc_sh, rlen, p); 333 if (error) 334 return error; 335 p += stride; 336 } 337 338 return 0; 339 } 340
Indexes created Sun Sep 21 20:09:37 GMT 2025