ssdfb_spi.c revision 1.7
1 /* $NetBSD: ssdfb_spi.c,v 1.7 2021/08/03 11:30:25 tnn Exp $ */ 2 3 /* 4 * Copyright (c) 2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tobias Nygren. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ssdfb_spi.c,v 1.7 2021/08/03 11:30:25 tnn Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/kernel.h> 38 #include <dev/wscons/wsdisplayvar.h> 39 #include <dev/rasops/rasops.h> 40 #include <dev/spi/spivar.h> 41 #include <dev/ic/ssdfbvar.h> 42 #include "opt_fdt.h" 43 #ifdef FDT 44 #include <dev/fdt/fdtvar.h> 45 #endif 46 47 struct bs_state { 48 uint8_t *base; 49 uint8_t *cur; 50 uint8_t mask; 51 }; 52 53 struct ssdfb_spi_softc { 54 struct ssdfb_softc sc; 55 struct spi_handle *sc_sh; 56 #ifdef FDT 57 struct fdtbus_gpio_pin *sc_gpio_dc; 58 struct fdtbus_gpio_pin *sc_gpio_res; 59 #endif 60 bool sc_3wiremode; 61 }; 62 63 static int ssdfb_spi_match(device_t, cfdata_t, void *); 64 static void ssdfb_spi_attach(device_t, device_t, void *); 65 66 static int ssdfb_spi_cmd_3wire(void *, uint8_t *, size_t, bool); 67 static int ssdfb_spi_xfer_rect_3wire_ssd1322(void *, uint8_t, uint8_t, 68 uint8_t, uint8_t, uint8_t *, size_t, bool); 69 70 static int ssdfb_spi_cmd_4wire(void *, uint8_t *, size_t, bool); 71 static int ssdfb_spi_xfer_rect_4wire_ssd1322(void *, uint8_t, uint8_t, 72 uint8_t, uint8_t, uint8_t *, size_t, bool); 73 74 static void ssdfb_bitstream_init(struct bs_state *, uint8_t *); 75 static void ssdfb_bitstream_append(struct bs_state *, uint8_t, uint8_t); 76 static void ssdfb_bitstream_append_cmd(struct bs_state *, uint8_t); 77 static void ssdfb_bitstream_append_data(struct bs_state *, uint8_t *, 78 size_t); 79 static void ssdfb_bitstream_final(struct bs_state *); 80 81 CFATTACH_DECL_NEW(ssdfb_spi, sizeof(struct ssdfb_spi_softc), 82 ssdfb_spi_match, ssdfb_spi_attach, NULL, NULL); 83 84 static const struct device_compatible_entry compat_data[] = { 85 { .compat = "solomon,ssd1306", .value = SSDFB_PRODUCT_SSD1306_GENERIC }, 86 { .compat = "solomon,ssd1322", .value = SSDFB_PRODUCT_SSD1322_GENERIC }, 87 DEVICE_COMPAT_EOL 88 }; 89 90 static int 91 ssdfb_spi_match(device_t parent, cfdata_t match, void *aux) 92 { 93 struct spi_attach_args *sa = aux; 94 int res; 95 96 res = spi_compatible_match(sa, match, compat_data); 97 if (!res) 98 return res; 99 100 /* 101 * SSD1306 and SSD1322 data sheets specify 100ns cycle time. 102 */ 103 if (spi_configure(sa->sa_handle, SPI_MODE_0, 10000000)) 104 res = 0; 105 106 return res; 107 } 108 109 static void 110 ssdfb_spi_attach(device_t parent, device_t self, void *aux) 111 { 112 struct ssdfb_spi_softc *sc = device_private(self); 113 struct cfdata *cf = device_cfdata(self); 114 struct spi_attach_args *sa = aux; 115 int flags = cf->cf_flags; 116 117 sc->sc.sc_dev = self; 118 sc->sc_sh = sa->sa_handle; 119 sc->sc.sc_cookie = (void *)sc; 120 if ((flags & SSDFB_ATTACH_FLAG_PRODUCT_MASK) == SSDFB_PRODUCT_UNKNOWN) { 121 const struct device_compatible_entry *dce = 122 device_compatible_lookup(sa->sa_compat, sa->sa_ncompat, compat_data); 123 if (dce) 124 flags |= (int)dce->value; 125 else 126 flags |= SSDFB_PRODUCT_SSD1322_GENERIC; 127 } 128 /* 129 * Note on interface modes. 130 * 131 * 3 wire mode sends 9 bit sequences over the MOSI, MSB contains 132 * the bit that determines if the lower 8 bits are command or data. 133 * 134 * 4 wire mode sends 8 bit sequences and requires an auxiliary GPIO 135 * pin for the command/data bit. 136 */ 137 #ifdef FDT 138 const int phandle = sa->sa_cookie; 139 sc->sc_gpio_dc = 140 fdtbus_gpio_acquire(phandle, "dc-gpio", GPIO_PIN_OUTPUT); 141 if (!sc->sc_gpio_dc) 142 sc->sc_gpio_dc = 143 fdtbus_gpio_acquire(phandle, "cd-gpio", GPIO_PIN_OUTPUT); 144 sc->sc_3wiremode = (sc->sc_gpio_dc == NULL); 145 sc->sc_gpio_res = 146 fdtbus_gpio_acquire(phandle, "res-gpio", GPIO_PIN_OUTPUT); 147 if (sc->sc_gpio_res) { 148 fdtbus_gpio_write_raw(sc->sc_gpio_res, 0); 149 DELAY(100); 150 fdtbus_gpio_write_raw(sc->sc_gpio_res, 1); 151 DELAY(100); 152 } 153 #else 154 sc->sc_3wiremode = true; 155 #endif 156 157 switch (flags & SSDFB_ATTACH_FLAG_PRODUCT_MASK) { 158 case SSDFB_PRODUCT_SSD1322_GENERIC: 159 if (sc->sc_3wiremode) { 160 sc->sc.sc_transfer_rect = 161 ssdfb_spi_xfer_rect_3wire_ssd1322; 162 } else { 163 sc->sc.sc_transfer_rect = 164 ssdfb_spi_xfer_rect_4wire_ssd1322; 165 } 166 break; 167 default: 168 panic("ssdfb_spi_attach: product not implemented"); 169 } 170 if (sc->sc_3wiremode) { 171 sc->sc.sc_cmd = ssdfb_spi_cmd_3wire; 172 } else { 173 sc->sc.sc_cmd = ssdfb_spi_cmd_4wire; 174 } 175 176 ssdfb_attach(&sc->sc, flags); 177 178 device_printf(sc->sc.sc_dev, "%d-wire SPI interface\n", 179 sc->sc_3wiremode == true ? 3 : 4); 180 } 181 182 static int 183 ssdfb_spi_cmd_3wire(void *cookie, uint8_t *cmd, size_t len, bool usepoll) 184 { 185 struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie; 186 uint8_t bitstream[16 * 9 / 8]; 187 struct bs_state s; 188 189 KASSERT(len > 0 && len <= 16); 190 ssdfb_bitstream_init(&s, bitstream); 191 ssdfb_bitstream_append_cmd(&s, *cmd); 192 cmd++; 193 len--; 194 ssdfb_bitstream_append_data(&s, cmd, len); 195 ssdfb_bitstream_final(&s); 196 197 return spi_send(sc->sc_sh, s.cur - s.base, bitstream); 198 } 199 200 static int 201 ssdfb_spi_xfer_rect_3wire_ssd1322(void *cookie, uint8_t fromcol, uint8_t tocol, 202 uint8_t fromrow, uint8_t torow, uint8_t *p, size_t stride, bool usepoll) 203 { 204 struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie; 205 uint8_t bitstream[128 * 9 / 8]; 206 struct bs_state s; 207 uint8_t row; 208 size_t rlen = (tocol + 1 - fromcol) * 2; 209 int error; 210 211 /* 212 * Unlike iic(4), there is no way to force spi(4) to use polling. 213 */ 214 if (usepoll && !cold) 215 return 0; 216 217 ssdfb_bitstream_init(&s, bitstream); 218 ssdfb_bitstream_append_cmd(&s, SSD1322_CMD_SET_ROW_ADDRESS); 219 ssdfb_bitstream_append_data(&s, &fromrow, 1); 220 ssdfb_bitstream_append_data(&s, &torow, 1); 221 ssdfb_bitstream_append_cmd(&s, SSD1322_CMD_SET_COLUMN_ADDRESS); 222 ssdfb_bitstream_append_data(&s, &fromcol, 1); 223 ssdfb_bitstream_append_data(&s, &tocol, 1); 224 ssdfb_bitstream_append_cmd(&s, SSD1322_CMD_WRITE_RAM); 225 ssdfb_bitstream_final(&s); 226 error = spi_send(sc->sc_sh, s.cur - s.base, bitstream); 227 if (error) 228 return error; 229 230 KASSERT(rlen <= 128); 231 for (row = fromrow; row <= torow; row++) { 232 ssdfb_bitstream_init(&s, bitstream); 233 ssdfb_bitstream_append_data(&s, p, rlen); 234 ssdfb_bitstream_final(&s); 235 error = spi_send(sc->sc_sh, s.cur - s.base, bitstream); 236 if (error) 237 return error; 238 p += stride; 239 } 240 241 return 0; 242 } 243 244 static void 245 ssdfb_bitstream_init(struct bs_state *s, uint8_t *dst) 246 { 247 s->base = s->cur = dst; 248 s->mask = 0x80; 249 } 250 251 static void 252 ssdfb_bitstream_append(struct bs_state *s, uint8_t b, uint8_t srcmask) 253 { 254 while(srcmask) { 255 if (b & srcmask) 256 *s->cur |= s->mask; 257 else 258 *s->cur &= ~s->mask; 259 srcmask >>= 1; 260 s->mask >>= 1; 261 if (!s->mask) { 262 s->mask = 0x80; 263 s->cur++; 264 } 265 } 266 } 267 268 static void 269 ssdfb_bitstream_append_cmd(struct bs_state *s, uint8_t cmd) 270 { 271 ssdfb_bitstream_append(s, 0, 1); 272 ssdfb_bitstream_append(s, cmd, 0x80); 273 } 274 275 static void 276 ssdfb_bitstream_append_data(struct bs_state *s, uint8_t *data, size_t len) 277 { 278 while(len--) { 279 ssdfb_bitstream_append(s, 1, 1); 280 ssdfb_bitstream_append(s, *data++, 0x80); 281 } 282 } 283 284 static void 285 ssdfb_bitstream_final(struct bs_state *s) 286 { 287 uint8_t padding_cmd = SSD1322_CMD_WRITE_RAM; 288 /* padding_cmd = SSDFB_NOP_CMD; */ 289 290 while (s->mask != 0x80) { 291 ssdfb_bitstream_append_cmd(s, padding_cmd); 292 } 293 } 294 295 static void 296 ssdfb_spi_4wire_set_dc(struct ssdfb_spi_softc *sc, int value) 297 { 298 #ifdef FDT 299 fdtbus_gpio_write_raw(sc->sc_gpio_dc, value); 300 #else 301 panic("ssdfb_spi_4wire_set_dc"); 302 #endif 303 } 304 305 static int 306 ssdfb_spi_cmd_4wire(void *cookie, uint8_t *cmd, size_t len, bool usepoll) 307 { 308 struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie; 309 int error; 310 311 ssdfb_spi_4wire_set_dc(sc, 0); 312 error = spi_send(sc->sc_sh, 1, cmd); 313 if (error) 314 return error; 315 if (len > 1) { 316 ssdfb_spi_4wire_set_dc(sc, 1); 317 len--; 318 cmd++; 319 error = spi_send(sc->sc_sh, len, cmd); 320 if (error) 321 return error; 322 } 323 324 return 0; 325 } 326 327 static int 328 ssdfb_spi_xfer_rect_4wire_ssd1322(void *cookie, uint8_t fromcol, uint8_t tocol, 329 uint8_t fromrow, uint8_t torow, uint8_t *p, size_t stride, bool usepoll) 330 { 331 struct ssdfb_spi_softc *sc = (struct ssdfb_spi_softc *)cookie; 332 uint8_t row; 333 size_t rlen = (tocol + 1 - fromcol) * 2; 334 int error; 335 uint8_t cmd; 336 uint8_t data[2]; 337 338 /* 339 * Unlike iic(4), there is no way to force spi(4) to use polling. 340 */ 341 if (usepoll && !cold) 342 return 0; 343 344 ssdfb_spi_4wire_set_dc(sc, 0); 345 cmd = SSD1322_CMD_SET_ROW_ADDRESS; 346 error = spi_send(sc->sc_sh, sizeof(cmd), &cmd); 347 if (error) 348 return error; 349 ssdfb_spi_4wire_set_dc(sc, 1); 350 data[0] = fromrow; 351 data[1] = torow; 352 error = spi_send(sc->sc_sh, sizeof(data), data); 353 if (error) 354 return error; 355 356 ssdfb_spi_4wire_set_dc(sc, 0); 357 cmd = SSD1322_CMD_SET_COLUMN_ADDRESS; 358 error = spi_send(sc->sc_sh, sizeof(cmd), &cmd); 359 if (error) 360 return error; 361 ssdfb_spi_4wire_set_dc(sc, 1); 362 data[0] = fromcol; 363 data[1] = tocol; 364 error = spi_send(sc->sc_sh, sizeof(data), data); 365 if (error) 366 return error; 367 368 ssdfb_spi_4wire_set_dc(sc, 0); 369 cmd = SSD1322_CMD_WRITE_RAM; 370 error = spi_send(sc->sc_sh, sizeof(cmd), &cmd); 371 if (error) 372 return error; 373 374 ssdfb_spi_4wire_set_dc(sc, 1); 375 for (row = fromrow; row <= torow; row++) { 376 error = spi_send(sc->sc_sh, rlen, p); 377 if (error) 378 return error; 379 p += stride; 380 } 381 382 return 0; 383 } 384
Indexes created Tue Sep 23 07:09:52 GMT 2025