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cgsixreg.h revision 1.9.2.1
      1  1.9.2.1       tls /*	$NetBSD: cgsixreg.h,v 1.9.2.1 2013/06/23 06:20:22 tls Exp $ */
      2      1.1        pk 
      3      1.1        pk /*
      4      1.1        pk  * Copyright (c) 1993
      5      1.1        pk  *	The Regents of the University of California.  All rights reserved.
      6      1.1        pk  *
      7      1.1        pk  * This software was developed by the Computer Systems Engineering group
      8      1.1        pk  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
      9      1.1        pk  * contributed to Berkeley.
     10      1.1        pk  *
     11      1.1        pk  * All advertising materials mentioning features or use of this software
     12      1.1        pk  * must display the following acknowledgement:
     13      1.1        pk  *	This product includes software developed by the University of
     14      1.1        pk  *	California, Lawrence Berkeley Laboratory.
     15      1.1        pk  *
     16      1.1        pk  * Redistribution and use in source and binary forms, with or without
     17      1.1        pk  * modification, are permitted provided that the following conditions
     18      1.1        pk  * are met:
     19      1.1        pk  * 1. Redistributions of source code must retain the above copyright
     20      1.1        pk  *    notice, this list of conditions and the following disclaimer.
     21      1.1        pk  * 2. Redistributions in binary form must reproduce the above copyright
     22      1.1        pk  *    notice, this list of conditions and the following disclaimer in the
     23      1.1        pk  *    documentation and/or other materials provided with the distribution.
     24      1.5       agc  * 3. Neither the name of the University nor the names of its contributors
     25      1.1        pk  *    may be used to endorse or promote products derived from this software
     26      1.1        pk  *    without specific prior written permission.
     27      1.1        pk  *
     28      1.1        pk  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     29      1.1        pk  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     30      1.1        pk  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     31      1.1        pk  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     32      1.1        pk  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     33      1.1        pk  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     34      1.1        pk  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     35      1.1        pk  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     36      1.1        pk  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     37      1.1        pk  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     38      1.1        pk  * SUCH DAMAGE.
     39      1.1        pk  *
     40      1.1        pk  *	@(#)cgsixreg.h	8.4 (Berkeley) 1/21/94
     41      1.1        pk  */
     42      1.1        pk 
     43      1.1        pk /*
     44      1.1        pk  * CG6 display registers.  (Note, I got tired of writing `cgsix' about
     45      1.1        pk  * halfway through and changed everything to cg6, but I probably missed
     46      1.1        pk  * some.  Unfortunately, the way config works, we need to spell out `six'
     47      1.1        pk  * in some places anyway.)
     48      1.1        pk  *
     49      1.1        pk  * The cg6 is a complicated beastie.  We have been unable to extract any
     50      1.1        pk  * documentation and most of the following are guesses based on a limited
     51      1.1        pk  * amount of reverse engineering.
     52      1.1        pk  *
     53      1.1        pk  * A cg6 is composed of numerous groups of control registers, all with TLAs:
     54      1.1        pk  *	FBC - frame buffer control?
     55      1.1        pk  *	FHC - fbc hardware configuration / control? register (32 bits)
     56      1.1        pk  *	DHC - ???
     57      1.1        pk  *	TEC - transform engine control?
     58      1.1        pk  *	THC - TEC Hardware Configuration
     59      1.1        pk  *	ROM - a 64Kbyte ROM with who knows what in it.
     60      1.1        pk  *	colormap - see below
     61      1.1        pk  *	frame buffer memory (video RAM)
     62      1.1        pk  *	possible other stuff
     63      1.1        pk  *
     64      1.1        pk  * Like the cg3, the cg6 uses a Brooktree Video DAC (see btreg.h).
     65      1.1        pk  *
     66      1.1        pk  * Various revisions of the cgsix have various hardware bugs.  So far,
     67      1.1        pk  * we have only seen rev 1 & 2.
     68      1.1        pk  */
     69      1.1        pk 
     70      1.1        pk /* Control register banks offsets */
     71      1.1        pk #define CGSIX_ROM_OFFSET	0x000000
     72      1.1        pk #define CGSIX_BT_OFFSET		0x200000
     73      1.1        pk #define CGSIX_DHC_OFFSET	0x240000
     74      1.1        pk #define CGSIX_ALT_OFFSET	0x280000
     75      1.1        pk #define CGSIX_FHC_OFFSET	0x300000
     76      1.1        pk #define CGSIX_THC_OFFSET	0x301000
     77      1.1        pk #define CGSIX_FBC_OFFSET	0x700000
     78      1.1        pk #define CGSIX_TEC_OFFSET	0x701000
     79      1.1        pk #define CGSIX_RAM_OFFSET	0x800000
     80      1.1        pk 
     81      1.1        pk /* bits in FHC register */
     82      1.1        pk #define	FHC_FBID_MASK	0xff000000	/* bits 24..31 are frame buffer ID */
     83      1.1        pk #define	FHC_FBID_SHIFT	24
     84      1.1        pk #define	FHC_REV_MASK	0x00f00000	/* bits 20..23 are revision */
     85      1.1        pk #define	FHC_REV_SHIFT	20
     86  1.9.2.1       tls #define	FHC_FROP_DISABLE 0x00080000	/* disable fast rasterops */
     87  1.9.2.1       tls #define	FHC_ROW_DISABLE	0x00040000	/* disable row cache */
     88  1.9.2.1       tls #define	FHC_SRC_DISABLE	0x00020000	/* disable source cache */
     89      1.1        pk #define	FHC_DST_DISABLE	0x00010000	/* disable destination cache */
     90  1.9.2.1       tls #define	FHC_RESET	0x00008000	/* reset FBC */
     91  1.9.2.1       tls #define	FHC_XXX0	0x00004000	/* unused */
     92  1.9.2.1       tls #define	FHC_LEBO	0x00002000	/* set little endian byte order */
     93      1.1        pk #define	FHC_RES_MASK	0x00001800	/* bits 11&12 are resolution */
     94      1.1        pk #define	FHC_RES_1024	 0x00000000		/* res = 1024x768 */
     95      1.1        pk #define	FHC_RES_1152	 0x00000800		/* res = 1152x900 */
     96      1.1        pk #define	FHC_RES_1280	 0x00001000		/* res = 1280x1024 */
     97      1.1        pk #define	FHC_RES_1600	 0x00001800		/* res = 1600x1200 */
     98      1.1        pk #define	FHC_CPU_MASK	0x00000600	/* bits 9&10 are cpu type */
     99      1.1        pk #define	FHC_CPU_SPARC	 0x00000000		/* cpu = sparc */
    100      1.1        pk #define	FHC_CPU_68020	 0x00000200		/* cpu = 68020 */
    101      1.1        pk #define	FHC_CPU_386	 0x00000400		/* cpu = 80386 */
    102  1.9.2.1       tls #define	FHC_CPU_XXX	 0x00000600		/* unused */
    103  1.9.2.1       tls #define	FHC_TEST	0x00000100	/* modify TESTX and TESTY */
    104      1.1        pk #define	FHC_TESTX_MASK	0x000000f0	/* bits 4..7 are test window X */
    105      1.1        pk #define	FHC_TESTX_SHIFT	4
    106      1.1        pk #define	FHC_TESTY_MASK	0x0000000f	/* bits 0..3 are test window Y */
    107      1.1        pk #define	FHC_TESTY_SHIFT	0
    108      1.1        pk 
    109      1.1        pk /*
    110      1.1        pk  * The layout of the THC.
    111      1.1        pk  */
    112      1.1        pk struct cg6_thc {
    113      1.1        pk 	u_int32_t	thc_xxx0[512];	/* ??? */
    114      1.1        pk 	u_int32_t	thc_hsync1;	/* horizontal sync timing */
    115      1.1        pk 	u_int32_t	thc_hsync2;	/* more hsync timing */
    116      1.1        pk 	u_int32_t	thc_hsync3;	/* yet more hsync timing */
    117      1.1        pk 	u_int32_t	thc_vsync1;	/* vertical sync timing */
    118      1.1        pk 	u_int32_t	thc_vsync2;	/* only two of these */
    119      1.1        pk 	u_int32_t	thc_refresh;	/* refresh counter */
    120      1.1        pk 	u_int32_t	thc_misc;	/* miscellaneous control & status */
    121      1.1        pk 	u_int32_t	thc_xxx1[56];	/* ??? */
    122      1.1        pk 	u_int32_t	thc_cursxy;	/* cursor x,y position (16 bits each) */
    123      1.1        pk 	u_int32_t	thc_cursmask[32];/* cursor mask bits */
    124      1.1        pk 	u_int32_t	thc_cursbits[32];/* what to show where mask enabled */
    125      1.1        pk };
    126      1.1        pk 
    127      1.1        pk /* bits in thc_misc */
    128      1.1        pk #define	THC_MISC_XXX0		0xfff00000	/* unused */
    129      1.1        pk #define	THC_MISC_REVMASK	0x000f0000	/* cg6 revision? */
    130      1.1        pk #define	THC_MISC_REVSHIFT	16
    131      1.1        pk #define	THC_MISC_XXX1		0x0000e000	/* unused */
    132      1.1        pk #define	THC_MISC_RESET		0x00001000	/* ??? */
    133      1.1        pk #define	THC_MISC_XXX2		0x00000800	/* unused */
    134      1.1        pk #define	THC_MISC_VIDEN		0x00000400	/* video enable */
    135  1.9.2.1       tls #define	THC_MISC_SYNC		0x00000200	/* sync status */
    136  1.9.2.1       tls #define	THC_MISC_VSYNC		0x00000100	/* vsync status */
    137      1.1        pk #define	THC_MISC_SYNCEN		0x00000080	/* sync enable */
    138      1.1        pk #define	THC_MISC_CURSRES	0x00000040	/* cursor resolution */
    139      1.1        pk #define	THC_MISC_INTEN		0x00000020	/* v.retrace intr enable */
    140      1.1        pk #define	THC_MISC_INTR		0x00000010	/* intr pending / ack bit */
    141      1.1        pk #define	THC_MISC_XXX		0x0000000f	/* ??? */
    142      1.1        pk 
    143      1.1        pk /* cursor x / y position value for `off' */
    144      1.1        pk #define	THC_CURSOFF	(65536-32)	/* i.e., USHRT_MAX+1-32 */
    145      1.1        pk 
    146      1.1        pk /*
    147      1.1        pk  * Partial description of TEC (needed to get around FHC rev 1 bugs).
    148      1.1        pk  */
    149      1.1        pk struct cg6_tec_xxx {
    150      1.1        pk 	u_int32_t	tec_mv;		/* matrix stuff */
    151      1.1        pk 	u_int32_t	tec_clip;	/* clipping stuff */
    152      1.1        pk 	u_int32_t	tec_vdc;	/* ??? */
    153      1.1        pk };
    154      1.1        pk 
    155      1.1        pk /*
    156      1.1        pk  * Partial description of FBC
    157      1.1        pk  *
    158      1.1        pk  * Most of this we don't care about; here are only the portions
    159      1.1        pk  * we need, most notably the blitter.  Comments are merely my
    160      1.1        pk  * best guesses as to register functions, based largely on the
    161      1.1        pk  * X11R6.4 sunGX code.  Some of these are here only so we can
    162      1.1        pk  * stuff canned values in them (eg, offx).
    163      1.1        pk  */
    164      1.1        pk struct cg6_fbc {
    165  1.9.2.1       tls 	u_int32_t fbc_config;		/* r/o CONFIG register */
    166  1.9.2.1       tls 	volatile u_int32_t fbc_mode;	/* mode setting */
    167  1.9.2.1       tls 	u_int32_t fbc_clip;		/* TEC clip check */
    168      1.1        pk 	u_int32_t fbc_pad2[1];
    169      1.1        pk 	u_int32_t fbc_s;		/* global status */
    170      1.1        pk 	u_int32_t fbc_draw;		/* drawing pipeline status */
    171      1.1        pk 	u_int32_t fbc_blit;		/* blitter status */
    172      1.6  macallan 	u_int32_t fbc_font;		/* pixel transfer register */
    173      1.6  macallan 	u_int32_t fbc_pad3[24];
    174      1.1        pk 	u_int32_t fbc_x0;		/* blitter, src llx */
    175      1.1        pk 	u_int32_t fbc_y0;		/* blitter, src lly */
    176      1.1        pk 	u_int32_t fbc_pad4[2];
    177      1.1        pk 	u_int32_t fbc_x1;		/* blitter, src urx */
    178      1.1        pk 	u_int32_t fbc_y1;		/* blitter, src ury */
    179      1.1        pk 	u_int32_t fbc_pad5[2];
    180      1.1        pk 	u_int32_t fbc_x2;		/* blitter, dst llx */
    181      1.1        pk 	u_int32_t fbc_y2;		/* blitter, dst lly */
    182      1.1        pk 	u_int32_t fbc_pad6[2];
    183      1.1        pk 	u_int32_t fbc_x3;		/* blitter, dst urx */
    184      1.1        pk 	u_int32_t fbc_y3;		/* blitter, dst ury */
    185      1.1        pk 	u_int32_t fbc_pad7[2];
    186      1.1        pk 	u_int32_t fbc_offx;		/* x offset for drawing */
    187      1.1        pk 	u_int32_t fbc_offy;		/* y offset for drawing */
    188      1.6  macallan 	u_int32_t fbc_pad8[2];
    189      1.6  macallan 	u_int32_t fbc_incx;		/* x offset for drawing */
    190      1.6  macallan 	u_int32_t fbc_incy;		/* y offset for drawing */
    191      1.6  macallan 	u_int32_t fbc_pad81[2];
    192      1.1        pk 	u_int32_t fbc_clipminx;		/* clip rectangle llx */
    193      1.1        pk 	u_int32_t fbc_clipminy;		/* clip rectangle lly */
    194      1.1        pk 	u_int32_t fbc_pad9[2];
    195      1.1        pk 	u_int32_t fbc_clipmaxx;		/* clip rectangle urx */
    196      1.1        pk 	u_int32_t fbc_clipmaxy;		/* clip rectangle ury */
    197      1.1        pk 	u_int32_t fbc_pad10[2];
    198      1.1        pk 	u_int32_t fbc_fg;		/* fg value for rop */
    199      1.6  macallan 	u_int32_t fbc_bg;
    200      1.1        pk 	u_int32_t fbc_alu;		/* operation to be performed */
    201      1.1        pk 	u_int32_t fbc_pad12[509];
    202      1.1        pk 	u_int32_t fbc_arectx;		/* rectangle drawing, x coord */
    203      1.1        pk 	u_int32_t fbc_arecty;		/* rectangle drawing, y coord */
    204      1.1        pk 	/* actually much more, but nothing more we need */
    205      1.1        pk };
    206      1.1        pk 
    207      1.8  macallan /* FBC mode definitions (from XFree86) */
    208      1.8  macallan #define CG6_FBC_BLIT_IGNORE		0x00000000
    209      1.8  macallan #define CG6_FBC_BLIT_NOSRC		0x00100000
    210      1.8  macallan #define CG6_FBC_BLIT_SRC		0x00200000
    211      1.8  macallan #define CG6_FBC_BLIT_ILLEGAL		0x00300000
    212      1.8  macallan #define CG6_FBC_BLIT_MASK		0x00300000
    213      1.8  macallan 
    214      1.8  macallan #define CG6_FBC_VBLANK			0x00080000
    215      1.8  macallan 
    216      1.8  macallan #define CG6_FBC_MODE_IGNORE		0x00000000
    217      1.8  macallan #define CG6_FBC_MODE_COLOR8		0x00020000
    218      1.8  macallan #define CG6_FBC_MODE_COLOR1		0x00040000
    219      1.8  macallan #define CG6_FBC_MODE_HRMONO		0x00060000
    220      1.8  macallan #define CG6_FBC_MODE_MASK		0x00060000
    221      1.8  macallan 
    222      1.8  macallan #define CG6_FBC_DRAW_IGNORE		0x00000000
    223      1.8  macallan #define CG6_FBC_DRAW_RENDER		0x00008000
    224      1.8  macallan #define CG6_FBC_DRAW_PICK		0x00010000
    225      1.8  macallan #define CG6_FBC_DRAW_ILLEGAL		0x00018000
    226      1.8  macallan #define CG6_FBC_DRAW_MASK		0x00018000
    227      1.8  macallan 
    228      1.8  macallan #define CG6_FBC_BWRITE0_IGNORE		0x00000000
    229      1.8  macallan #define CG6_FBC_BWRITE0_ENABLE		0x00002000
    230      1.8  macallan #define CG6_FBC_BWRITE0_DISABLE		0x00004000
    231      1.8  macallan #define CG6_FBC_BWRITE0_ILLEGAL		0x00006000
    232      1.8  macallan #define CG6_FBC_BWRITE0_MASK		0x00006000
    233      1.8  macallan 
    234      1.8  macallan #define CG6_FBC_BWRITE1_IGNORE		0x00000000
    235      1.8  macallan #define CG6_FBC_BWRITE1_ENABLE		0x00000800
    236      1.8  macallan #define CG6_FBC_BWRITE1_DISABLE		0x00001000
    237      1.8  macallan #define CG6_FBC_BWRITE1_ILLEGAL		0x00001800
    238      1.8  macallan #define CG6_FBC_BWRITE1_MASK		0x00001800
    239      1.8  macallan 
    240      1.8  macallan #define CG6_FBC_BREAD_IGNORE		0x00000000
    241      1.8  macallan #define CG6_FBC_BREAD_0			0x00000200
    242      1.8  macallan #define CG6_FBC_BREAD_1			0x00000400
    243      1.8  macallan #define CG6_FBC_BREAD_ILLEGAL		0x00000600
    244      1.8  macallan #define CG6_FBC_BREAD_MASK		0x00000600
    245      1.8  macallan 
    246      1.8  macallan #define CG6_FBC_BDISP_IGNORE		0x00000000
    247      1.8  macallan #define CG6_FBC_BDISP_0			0x00000080
    248      1.8  macallan #define CG6_FBC_BDISP_1			0x00000100
    249      1.8  macallan #define CG6_FBC_BDISP_ILLEGAL		0x00000180
    250      1.8  macallan #define CG6_FBC_BDISP_MASK		0x00000180
    251      1.8  macallan 
    252      1.8  macallan #define CG6_FBC_INDEX_MOD		0x00000040
    253      1.8  macallan #define CG6_FBC_INDEX_MASK		0x00000030
    254      1.8  macallan 
    255      1.9  macallan /* rasterops */
    256      1.9  macallan #define GX_ROP_CLEAR        0x0
    257      1.9  macallan #define GX_ROP_INVERT       0x1
    258      1.9  macallan #define GX_ROP_NOOP         0x2
    259      1.9  macallan #define GX_ROP_SET          0x3
    260      1.9  macallan 
    261      1.9  macallan #define GX_ROP_00_0(rop)    ((rop) << 0)
    262      1.9  macallan #define GX_ROP_00_1(rop)    ((rop) << 2)
    263      1.9  macallan #define GX_ROP_01_0(rop)    ((rop) << 4)
    264      1.9  macallan #define GX_ROP_01_1(rop)    ((rop) << 6)
    265      1.9  macallan #define GX_ROP_10_0(rop)    ((rop) << 8)
    266      1.9  macallan #define GX_ROP_10_1(rop)    ((rop) << 10)
    267      1.9  macallan #define GX_ROP_11_0(rop)    ((rop) << 12)
    268      1.9  macallan #define GX_ROP_11_1(rop)    ((rop) << 14)
    269      1.9  macallan #define GX_PLOT_PLOT        0x00000000
    270      1.9  macallan #define GX_PLOT_UNPLOT      0x00020000
    271      1.9  macallan #define GX_RAST_BOOL        0x00000000
    272      1.9  macallan #define GX_RAST_LINEAR      0x00040000
    273      1.9  macallan #define GX_ATTR_UNSUPP      0x00400000
    274      1.9  macallan #define GX_ATTR_SUPP        0x00800000
    275      1.9  macallan #define GX_POLYG_OVERLAP    0x01000000
    276      1.9  macallan #define GX_POLYG_NONOVERLAP 0x02000000
    277      1.9  macallan #define GX_PATTERN_ZEROS    0x04000000
    278      1.9  macallan #define GX_PATTERN_ONES     0x08000000
    279      1.9  macallan #define GX_PATTERN_MASK     0x0c000000
    280      1.9  macallan #define GX_PIXEL_ZEROS      0x10000000
    281      1.9  macallan #define GX_PIXEL_ONES       0x20000000
    282      1.9  macallan #define GX_PIXEL_MASK       0x30000000
    283      1.9  macallan #define GX_PLANE_ZEROS      0x40000000
    284      1.9  macallan #define GX_PLANE_ONES       0x80000000
    285      1.9  macallan #define GX_PLANE_MASK       0xc0000000
    286      1.9  macallan /* rops for bit blit / copy area
    287      1.9  macallan    with:
    288      1.9  macallan        Plane Mask - use plane mask reg.
    289      1.9  macallan        Pixel Mask - use all ones.
    290      1.9  macallan        Patt  Mask - use all ones.
    291      1.9  macallan */
    292      1.9  macallan 
    293      1.9  macallan #define POLY_O          GX_POLYG_OVERLAP
    294      1.9  macallan #define POLY_N          GX_POLYG_NONOVERLAP
    295      1.9  macallan 
    296      1.9  macallan #define ROP_STANDARD    (GX_PLANE_MASK |\
    297      1.9  macallan                         GX_PIXEL_ONES |\
    298      1.9  macallan                         GX_ATTR_SUPP |\
    299      1.9  macallan                         GX_RAST_BOOL |\
    300      1.9  macallan                         GX_PLOT_PLOT)
    301      1.9  macallan 
    302      1.9  macallan /* fg = don't care  bg = don't care */
    303      1.9  macallan 
    304      1.9  macallan #define ROP_BLIT(O,I)   (ROP_STANDARD | \
    305      1.9  macallan                         GX_PATTERN_ONES |\
    306      1.9  macallan                         GX_ROP_11_1(I) |\
    307      1.9  macallan                         GX_ROP_11_0(O) |\
    308      1.9  macallan                         GX_ROP_10_1(I) |\
    309      1.9  macallan                         GX_ROP_10_0(O) |\
    310      1.9  macallan                         GX_ROP_01_1(I) |\
    311      1.9  macallan                         GX_ROP_01_0(O) |\
    312      1.9  macallan                         GX_ROP_00_1(I) |\
    313      1.9  macallan                         GX_ROP_00_0(O))
    314      1.9  macallan 
    315      1.9  macallan /* fg = fgPixel     bg = don't care */
    316      1.9  macallan 
    317      1.9  macallan #define ROP_FILL(O,I)   (ROP_STANDARD | \
    318      1.9  macallan                         GX_PATTERN_ONES |\
    319      1.9  macallan                         GX_ROP_11_1(I) |\
    320      1.9  macallan                         GX_ROP_11_0(I) |\
    321      1.9  macallan                         GX_ROP_10_1(I) |\
    322      1.9  macallan                         GX_ROP_10_0(I) | \
    323      1.9  macallan                         GX_ROP_01_1(O) |\
    324      1.9  macallan                         GX_ROP_01_0(O) |\
    325      1.9  macallan                         GX_ROP_00_1(O) |\
    326      1.9  macallan                         GX_ROP_00_0(O))
    327      1.9  macallan 
    328      1.9  macallan /* fg = fgPixel     bg = don't care */
    329      1.9  macallan 
    330      1.9  macallan #define ROP_STIP(O,I)   (ROP_STANDARD |\
    331      1.9  macallan                         GX_ROP_11_1(I) |\
    332      1.9  macallan                         GX_ROP_11_0(GX_ROP_NOOP) |\
    333      1.9  macallan                         GX_ROP_10_1(I) |\
    334      1.9  macallan                         GX_ROP_10_0(GX_ROP_NOOP) | \
    335      1.9  macallan                         GX_ROP_01_1(O) |\
    336      1.9  macallan                         GX_ROP_01_0(GX_ROP_NOOP) |\
    337      1.9  macallan                         GX_ROP_00_1(O) |\
    338      1.9  macallan                         GX_ROP_00_0(GX_ROP_NOOP))
    339      1.9  macallan 
    340      1.9  macallan /* fg = fgPixel     bg = bgPixel */
    341      1.9  macallan 
    342      1.9  macallan #define ROP_OSTP(O,I)   (ROP_STANDARD |\
    343      1.9  macallan                         GX_ROP_11_1(I) |\
    344      1.9  macallan                         GX_ROP_11_0(I) |\
    345      1.9  macallan                         GX_ROP_10_1(I) |\
    346      1.9  macallan                         GX_ROP_10_0(O) |\
    347      1.9  macallan                         GX_ROP_01_1(O) |\
    348      1.9  macallan                         GX_ROP_01_0(I) |\
    349      1.9  macallan                         GX_ROP_00_1(O) |\
    350      1.9  macallan                         GX_ROP_00_0(O))
    351      1.9  macallan 
    352      1.9  macallan #define GX_ROP_USE_PIXELMASK    0x30000000
    353      1.9  macallan 
    354      1.9  macallan #define GX_BLT_INPROGRESS       0x20000000
    355      1.9  macallan 
    356  1.9.2.1       tls /* status register(s) */
    357  1.9.2.1       tls #define GX_EXCEPTION		0x80000000
    358  1.9.2.1       tls #define GX_TEC_EXCEPTION	0x40000000
    359      1.9  macallan #define GX_FULL                 0x20000000
    360  1.9.2.1       tls #define GX_INPROGRESS           0x10000000
    361  1.9.2.1       tls #define GX_UNSUPPORTED_ATTR	0x02000000
    362  1.9.2.1       tls #define GX_HRMONO		0x01000000
    363  1.9.2.1       tls #define GX_OVERFLOW		0x00200000
    364  1.9.2.1       tls #define GX_PICK			0x00100000
    365  1.9.2.1       tls #define GX_TEC_HIDDEN		0x00040000
    366  1.9.2.1       tls #define GX_TEC_INTERSECT	0x00020000
    367  1.9.2.1       tls #define GX_TEC_VISIBLE		0x00010000
    368  1.9.2.1       tls #define GX_BLIT_HARDWARE	0x00008000	/* hardware can blit this */
    369  1.9.2.1       tls #define GX_BLIT_SOFTWARE	0x00004000	/* software must blit this */
    370  1.9.2.1       tls #define GX_BLIT_SRC_HIDDEN	0x00002000
    371  1.9.2.1       tls #define GX_BLIT_SRC_INTERSECT	0x00001000
    372  1.9.2.1       tls #define GX_BLIT_SRC_VISIBLE	0x00000800
    373  1.9.2.1       tls #define GX_BLIT_DST_HIDDEN	0x00000400
    374  1.9.2.1       tls #define GX_BLIT_DST_INTERSECT	0x00000200
    375  1.9.2.1       tls #define GX_BLIT_DST_VISIBLE	0x00000100
    376  1.9.2.1       tls #define GX_DRAW_HARDWARE	0x00000010	/* hardware can draw this */
    377  1.9.2.1       tls #define GX_DRAW_SOFTAWRE	0x00000008	/* software must draw this */
    378  1.9.2.1       tls #define GX_DRAW_HIDDEN		0x00000004
    379  1.9.2.1       tls #define GX_DRAW_INTERSECT	0x00000002
    380  1.9.2.1       tls #define GX_DRAW_VISIBLE		0x00000001
    381      1.9  macallan 
    382  1.9.2.1       tls /* MISC register */
    383      1.9  macallan #define GX_INDEX(n)         ((n) << 4)
    384      1.9  macallan #define GX_INDEX_ALL        0x00000030
    385      1.9  macallan #define GX_INDEX_MOD        0x00000040
    386      1.9  macallan #define GX_BDISP_0          0x00000080
    387      1.9  macallan #define GX_BDISP_1          0x00000100
    388      1.9  macallan #define GX_BDISP_ALL        0x00000180
    389      1.9  macallan #define GX_BREAD_0          0x00000200
    390      1.9  macallan #define GX_BREAD_1          0x00000400
    391      1.9  macallan #define GX_BREAD_ALL        0x00000600
    392      1.9  macallan #define GX_BWRITE1_ENABLE   0x00000800
    393      1.9  macallan #define GX_BWRITE1_DISABLE  0x00001000
    394      1.9  macallan #define GX_BWRITE1_ALL      0x00001800
    395      1.9  macallan #define GX_BWRITE0_ENABLE   0x00002000
    396      1.9  macallan #define GX_BWRITE0_DISABLE  0x00004000
    397      1.9  macallan #define GX_BWRITE0_ALL      0x00006000
    398      1.9  macallan #define GX_DRAW_RENDER      0x00008000
    399      1.9  macallan #define GX_DRAW_PICK        0x00010000
    400      1.9  macallan #define GX_DRAW_ALL         0x00018000
    401      1.9  macallan #define GX_MODE_COLOR8      0x00020000
    402      1.9  macallan #define GX_MODE_COLOR1      0x00040000
    403      1.9  macallan #define GX_MODE_HRMONO      0x00060000
    404      1.9  macallan #define GX_MODE_ALL         0x00060000
    405      1.9  macallan #define GX_VBLANK           0x00080000
    406      1.9  macallan #define GX_BLIT_NOSRC       0x00100000
    407      1.9  macallan #define GX_BLIT_SRC         0x00200000
    408      1.9  macallan #define GX_BLIT_ALL         0x00300000
    409      1.9  macallan 
    410      1.1        pk #if _CG6_LAYOUT_NOT_USED_ANYMORE
    411      1.1        pk /*
    412      1.1        pk  * This structure exists only to compute the layout of the CG6
    413      1.1        pk  * hardware.  Each of the individual substructures lives on a
    414      1.1        pk  * separate `page' (where a `page' is at least 4K), and many are
    415      1.1        pk  * very far apart.  We avoid large offsets (which make for lousy
    416      1.1        pk  * code) by using pointers to the individual interesting pieces,
    417      1.1        pk  * and map them in independently (to avoid using up PTEs unnecessarily).
    418      1.1        pk  */
    419      1.1        pk struct cg6_layout {
    420      1.1        pk 	/* ROM at 0 */
    421      1.1        pk 	union {
    422      1.2       eeh 		int un_id;		/* ID = ?? */
    423      1.1        pk 		char un_rom[65536];	/* 64K rom */
    424      1.1        pk 		char un_pad[0x200000];
    425      1.1        pk 	} cg6_rom_un;
    426      1.1        pk 
    427      1.1        pk 	/* Brooktree DAC at 0x200000 */
    428      1.1        pk 	union {
    429      1.1        pk 		struct bt_regs un_btregs;
    430      1.1        pk 		char un_pad[0x040000];
    431      1.1        pk 	} cg6_bt_un;
    432      1.1        pk 
    433      1.1        pk 	/* DHC, whatever that is, at 0x240000 */
    434      1.1        pk 	union {
    435      1.1        pk 		char un_pad[0x40000];
    436      1.1        pk 	} cg6_dhc_un;
    437      1.1        pk 
    438      1.1        pk 	/* ALT, whatever that is, at 0x280000 */
    439      1.1        pk 	union {
    440      1.1        pk 		char un_pad[0x80000];
    441      1.1        pk 	} cg6_alt_un;
    442      1.1        pk 
    443      1.1        pk 	/* FHC register at 0x300000 */
    444      1.1        pk 	union {
    445      1.1        pk 		int un_fhc;
    446      1.1        pk 		char un_pad[0x1000];
    447      1.1        pk 	} cg6_fhc_un;
    448      1.1        pk 
    449      1.1        pk 	/* THC at 0x301000 */
    450      1.1        pk 	union {
    451      1.1        pk 		struct cg6_thc un_thc;
    452      1.1        pk 		char un_pad[0x400000 - 0x1000];
    453      1.1        pk 	} cg6_thc_un;
    454      1.1        pk 
    455      1.1        pk 	/* FBC at 0x700000 */
    456      1.1        pk 	union {
    457      1.1        pk 		char un_pad[0x1000];
    458      1.1        pk 	} cg6_fbc_un;
    459      1.1        pk 
    460      1.1        pk 	/* TEC at 0x701000 */
    461      1.1        pk 	union {
    462      1.1        pk 		char un_pad[0x100000 - 0x1000];
    463      1.1        pk 		struct cg6_tec_xxx un_tec;
    464      1.1        pk 	} cg6_tec_un;
    465      1.1        pk 
    466      1.1        pk 	/* Video RAM at 0x800000 */
    467      1.1        pk 	char	cg6_ram[1024 * 1024];	/* approx.? */
    468      1.1        pk };
    469      1.1        pk #endif
    470