asc_tc.c revision 1.14.8.2
1 /* $NetBSD: asc_tc.c,v 1.14.8.2 2002/01/10 19:58:37 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: asc_tc.c,v 1.14.8.2 2002/01/10 19:58:37 thorpej Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/buf.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 #include <dev/scsipi/scsi_message.h> 51 52 #include <machine/bus.h> 53 54 #include <dev/ic/ncr53c9xreg.h> 55 #include <dev/ic/ncr53c9xvar.h> 56 57 #include <dev/tc/tcvar.h> 58 59 struct asc_softc { 60 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 61 bus_space_tag_t sc_bst; 62 bus_space_handle_t sc_bsh; 63 bus_dma_tag_t sc_dmat; 64 bus_dmamap_t sc_dmamap; 65 caddr_t *sc_dmaaddr; 66 size_t *sc_dmalen; 67 size_t sc_dmasize; 68 int sc_active; /* DMA active ? */ 69 int sc_ispullup; /* DMA into main memory? */ 70 71 /* XXX XXX XXX */ 72 caddr_t sc_base, sc_bounce, sc_target; 73 }; 74 75 static int asc_tc_match __P((struct device *, struct cfdata *, void *)); 76 static void asc_tc_attach __P((struct device *, struct device *, void *)); 77 78 struct cfattach asc_tc_ca = { 79 sizeof(struct asc_softc), asc_tc_match, asc_tc_attach 80 }; 81 82 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 83 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 84 static int asc_dma_isintr __P((struct ncr53c9x_softc *)); 85 static void asc_tc_reset __P((struct ncr53c9x_softc *)); 86 static int asc_tc_intr __P((struct ncr53c9x_softc *)); 87 static int asc_tc_setup __P((struct ncr53c9x_softc *, caddr_t *, 88 size_t *, int, size_t *)); 89 static void asc_tc_go __P((struct ncr53c9x_softc *)); 90 static void asc_tc_stop __P((struct ncr53c9x_softc *)); 91 static int asc_dma_isactive __P((struct ncr53c9x_softc *)); 92 static void asc_clear_latched_intr __P((struct ncr53c9x_softc *)); 93 94 static struct ncr53c9x_glue asc_tc_glue = { 95 asc_read_reg, 96 asc_write_reg, 97 asc_dma_isintr, 98 asc_tc_reset, 99 asc_tc_intr, 100 asc_tc_setup, 101 asc_tc_go, 102 asc_tc_stop, 103 asc_dma_isactive, 104 asc_clear_latched_intr, 105 }; 106 107 /* 108 * Parameters specific to PMAZ-A TC option card. 109 */ 110 #define PMAZ_OFFSET_53C94 0x0 /* from module base */ 111 #define PMAZ_OFFSET_DMAR 0x40000 /* DMA Address Register */ 112 #define PMAZ_OFFSET_RAM 0x80000 /* 128KB SRAM buffer */ 113 #define PMAZ_OFFSET_ROM 0xc0000 /* diagnostic ROM */ 114 115 #define PMAZ_RAM_SIZE 0x20000 /* 128k (32k*32) */ 116 #define PER_TGT_DMA_SIZE ((PMAZ_RAM_SIZE/7) & ~(sizeof(int)-1)) 117 118 #define PMAZ_DMAR_WRITE 0x80000000 /* DMA direction bit */ 119 #define PMAZ_DMAR_MASK 0x1ffff /* 17 bits, 128k */ 120 #define PMAZ_DMA_ADDR(x) ((unsigned long)(x) & PMAZ_DMAR_MASK) 121 122 static int 123 asc_tc_match(parent, cfdata, aux) 124 struct device *parent; 125 struct cfdata *cfdata; 126 void *aux; 127 { 128 struct tc_attach_args *d = aux; 129 130 if (strncmp("PMAZ-AA ", d->ta_modname, TC_ROM_LLEN)) 131 return (0); 132 133 return (1); 134 } 135 136 static void 137 asc_tc_attach(parent, self, aux) 138 struct device *parent, *self; 139 void *aux; 140 { 141 struct tc_attach_args *ta = aux; 142 struct asc_softc *asc = (struct asc_softc *)self; 143 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 144 145 /* 146 * Set up glue for MI code early; we use some of it here. 147 */ 148 sc->sc_glue = &asc_tc_glue; 149 asc->sc_bst = ta->ta_memt; 150 asc->sc_dmat = ta->ta_dmat; 151 if (bus_space_map(asc->sc_bst, ta->ta_addr, 152 PMAZ_OFFSET_RAM + PMAZ_RAM_SIZE, 0, &asc->sc_bsh)) { 153 printf("%s: unable to map device\n", sc->sc_dev.dv_xname); 154 return; 155 } 156 asc->sc_base = (caddr_t)ta->ta_addr; /* XXX XXX XXX */ 157 158 tc_intr_establish(parent, ta->ta_cookie, IPL_BIO, ncr53c9x_intr, sc); 159 160 sc->sc_id = 7; 161 sc->sc_freq = (ta->ta_busspeed) ? 25000000 : 12500000; 162 163 /* gimme Mhz */ 164 sc->sc_freq /= 1000000; 165 166 /* 167 * XXX More of this should be in ncr53c9x_attach(), but 168 * XXX should we really poke around the chip that much in 169 * XXX the MI code? Think about this more... 170 */ 171 172 /* 173 * Set up static configuration info. 174 */ 175 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 176 sc->sc_cfg2 = NCRCFG2_SCSI2; 177 sc->sc_cfg3 = 0; 178 sc->sc_rev = NCR_VARIANT_NCR53C94; 179 180 /* 181 * XXX minsync and maxxfer _should_ be set up in MI code, 182 * XXX but it appears to have some dependency on what sort 183 * XXX of DMA we're hooked up to, etc. 184 */ 185 186 /* 187 * This is the value used to start sync negotiations 188 * Note that the NCR register "SYNCTP" is programmed 189 * in "clocks per byte", and has a minimum value of 4. 190 * The SCSI period used in negotiation is one-fourth 191 * of the time (in nanoseconds) needed to transfer one byte. 192 * Since the chip's clock is given in MHz, we have the following 193 * formula: 4 * period = (1000 / freq) * 4 194 */ 195 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 196 197 sc->sc_maxxfer = 64 * 1024; 198 199 /* Do the common parts of attachment. */ 200 sc->sc_adapter.adapt_minphys = minphys; 201 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 202 ncr53c9x_attach(sc); 203 } 204 205 static void 206 asc_tc_reset(sc) 207 struct ncr53c9x_softc *sc; 208 { 209 struct asc_softc *asc = (struct asc_softc *)sc; 210 211 asc->sc_active = 0; 212 } 213 214 static int 215 asc_tc_intr(sc) 216 struct ncr53c9x_softc *sc; 217 { 218 struct asc_softc *asc = (struct asc_softc *)sc; 219 int trans, resid; 220 221 resid = 0; 222 if (!asc->sc_ispullup && 223 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 224 NCR_DMA(("asc_tc_intr: empty FIFO of %d ", resid)); 225 DELAY(1); 226 } 227 228 resid += NCR_READ_REG(sc, NCR_TCL); 229 resid += NCR_READ_REG(sc, NCR_TCM) << 8; 230 231 trans = asc->sc_dmasize - resid; 232 233 if (asc->sc_ispullup) 234 memcpy(asc->sc_target, asc->sc_bounce, trans); 235 *asc->sc_dmalen -= trans; 236 *asc->sc_dmaaddr += trans; 237 asc->sc_active = 0; 238 239 return (0); 240 } 241 242 static int 243 asc_tc_setup(sc, addr, len, datain, dmasize) 244 struct ncr53c9x_softc *sc; 245 caddr_t *addr; 246 size_t *len; 247 int datain; 248 size_t *dmasize; 249 { 250 struct asc_softc *asc = (struct asc_softc *)sc; 251 u_int32_t tc_dmar; 252 size_t size; 253 254 asc->sc_dmaaddr = addr; 255 asc->sc_dmalen = len; 256 asc->sc_ispullup = datain; 257 258 NCR_DMA(("asc_tc_setup: start %ld@%p, %s\n", (long)*asc->sc_dmalen, 259 *asc->sc_dmaaddr, datain ? "IN" : "OUT")); 260 261 size = *dmasize; 262 if (size > PER_TGT_DMA_SIZE) 263 size = PER_TGT_DMA_SIZE; 264 *dmasize = asc->sc_dmasize = size; 265 266 NCR_DMA(("asc_tc_setup: dmasize = %ld\n", (long)asc->sc_dmasize)); 267 268 asc->sc_bounce = asc->sc_base + PMAZ_OFFSET_RAM; 269 asc->sc_bounce += PER_TGT_DMA_SIZE * 270 sc->sc_nexus->xs->xs_periph->periph_target; 271 asc->sc_target = *addr; 272 273 if (!asc->sc_ispullup) 274 memcpy(asc->sc_bounce, asc->sc_target, size); 275 276 #if 1 277 if (asc->sc_ispullup) 278 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 279 else 280 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 281 bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar); 282 asc->sc_active = 1; 283 #endif 284 return (0); 285 } 286 287 static void 288 asc_tc_go(sc) 289 struct ncr53c9x_softc *sc; 290 { 291 #if 0 292 struct asc_softc *asc = (struct asc_softc *)sc; 293 u_int32_t tc_dmar; 294 295 if (asc->sc_ispullup) 296 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 297 else 298 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 299 bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar); 300 asc->sc_active = 1; 301 #endif 302 } 303 304 /* NEVER CALLED BY MI 53C9x ENGINE INDEED */ 305 static void 306 asc_tc_stop(sc) 307 struct ncr53c9x_softc *sc; 308 { 309 #if 0 310 struct asc_softc *asc = (struct asc_softc *)sc; 311 312 if (asc->sc_ispullup) 313 memcpy(asc->sc_target, asc->sc_bounce, asc->sc_dmasize); 314 asc->sc_active = 0; 315 #endif 316 } 317 318 /* 319 * Glue functions. 320 */ 321 static u_char 322 asc_read_reg(sc, reg) 323 struct ncr53c9x_softc *sc; 324 int reg; 325 { 326 struct asc_softc *asc = (struct asc_softc *)sc; 327 u_char v; 328 329 v = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 330 reg * sizeof(u_int32_t)) & 0xff; 331 332 return (v); 333 } 334 335 static void 336 asc_write_reg(sc, reg, val) 337 struct ncr53c9x_softc *sc; 338 int reg; 339 u_char val; 340 { 341 struct asc_softc *asc = (struct asc_softc *)sc; 342 343 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 344 reg * sizeof(u_int32_t), val); 345 } 346 347 static int 348 asc_dma_isintr(sc) 349 struct ncr53c9x_softc *sc; 350 { 351 return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT); 352 } 353 354 static int 355 asc_dma_isactive(sc) 356 struct ncr53c9x_softc *sc; 357 { 358 struct asc_softc *asc = (struct asc_softc *)sc; 359 360 return (asc->sc_active); 361 } 362 363 static void 364 asc_clear_latched_intr(sc) 365 struct ncr53c9x_softc *sc; 366 { 367 } 368
Indexes created Sun Oct 12 05:10:08 GMT 2025