asc_tc.c revision 1.17
1 /* $NetBSD: asc_tc.c,v 1.17 2001/10/01 10:19:09 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 40 __KERNEL_RCSID(0, "$NetBSD: asc_tc.c,v 1.17 2001/10/01 10:19:09 simonb Exp $"); 41 42 #include <sys/types.h> 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 55 #include <dev/ic/ncr53c9xreg.h> 56 #include <dev/ic/ncr53c9xvar.h> 57 58 #include <dev/tc/tcvar.h> 59 60 struct asc_softc { 61 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 62 bus_space_tag_t sc_bst; 63 bus_space_handle_t sc_bsh; 64 bus_dma_tag_t sc_dmat; 65 bus_dmamap_t sc_dmamap; 66 caddr_t *sc_dmaaddr; 67 size_t *sc_dmalen; 68 size_t sc_dmasize; 69 int sc_active; /* DMA active ? */ 70 int sc_ispullup; /* DMA into main memory? */ 71 72 /* XXX XXX XXX */ 73 caddr_t sc_base, sc_bounce, sc_target; 74 }; 75 76 static int asc_tc_match __P((struct device *, struct cfdata *, void *)); 77 static void asc_tc_attach __P((struct device *, struct device *, void *)); 78 79 struct cfattach asc_tc_ca = { 80 sizeof(struct asc_softc), asc_tc_match, asc_tc_attach 81 }; 82 83 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 84 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 85 static int asc_dma_isintr __P((struct ncr53c9x_softc *)); 86 static void asc_tc_reset __P((struct ncr53c9x_softc *)); 87 static int asc_tc_intr __P((struct ncr53c9x_softc *)); 88 static int asc_tc_setup __P((struct ncr53c9x_softc *, caddr_t *, 89 size_t *, int, size_t *)); 90 static void asc_tc_go __P((struct ncr53c9x_softc *)); 91 static void asc_tc_stop __P((struct ncr53c9x_softc *)); 92 static int asc_dma_isactive __P((struct ncr53c9x_softc *)); 93 static void asc_clear_latched_intr __P((struct ncr53c9x_softc *)); 94 95 static struct ncr53c9x_glue asc_tc_glue = { 96 asc_read_reg, 97 asc_write_reg, 98 asc_dma_isintr, 99 asc_tc_reset, 100 asc_tc_intr, 101 asc_tc_setup, 102 asc_tc_go, 103 asc_tc_stop, 104 asc_dma_isactive, 105 asc_clear_latched_intr, 106 }; 107 108 /* 109 * Parameters specific to PMAZ-A TC option card. 110 */ 111 #define PMAZ_OFFSET_53C94 0x0 /* from module base */ 112 #define PMAZ_OFFSET_DMAR 0x40000 /* DMA Address Register */ 113 #define PMAZ_OFFSET_RAM 0x80000 /* 128KB SRAM buffer */ 114 #define PMAZ_OFFSET_ROM 0xc0000 /* diagnostic ROM */ 115 116 #define PMAZ_RAM_SIZE 0x20000 /* 128k (32k*32) */ 117 #define PER_TGT_DMA_SIZE ((PMAZ_RAM_SIZE/7) & ~(sizeof(int)-1)) 118 119 #define PMAZ_DMAR_WRITE 0x80000000 /* DMA direction bit */ 120 #define PMAZ_DMAR_MASK 0x1ffff /* 17 bits, 128k */ 121 #define PMAZ_DMA_ADDR(x) ((unsigned long)(x) & PMAZ_DMAR_MASK) 122 123 static int 124 asc_tc_match(parent, cfdata, aux) 125 struct device *parent; 126 struct cfdata *cfdata; 127 void *aux; 128 { 129 struct tc_attach_args *d = aux; 130 131 if (strncmp("PMAZ-AA ", d->ta_modname, TC_ROM_LLEN)) 132 return (0); 133 134 return (1); 135 } 136 137 static void 138 asc_tc_attach(parent, self, aux) 139 struct device *parent, *self; 140 void *aux; 141 { 142 struct tc_attach_args *ta = aux; 143 struct asc_softc *asc = (struct asc_softc *)self; 144 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 145 146 /* 147 * Set up glue for MI code early; we use some of it here. 148 */ 149 sc->sc_glue = &asc_tc_glue; 150 asc->sc_bst = ta->ta_memt; 151 asc->sc_dmat = ta->ta_dmat; 152 if (bus_space_map(asc->sc_bst, ta->ta_addr, 153 PMAZ_OFFSET_RAM + PMAZ_RAM_SIZE, 0, &asc->sc_bsh)) { 154 printf("%s: unable to map device\n", sc->sc_dev.dv_xname); 155 return; 156 } 157 asc->sc_base = (caddr_t)ta->ta_addr; /* XXX XXX XXX */ 158 159 tc_intr_establish(parent, ta->ta_cookie, IPL_BIO, ncr53c9x_intr, sc); 160 161 sc->sc_id = 7; 162 sc->sc_freq = (ta->ta_busspeed) ? 25000000 : 12500000; 163 164 /* gimme Mhz */ 165 sc->sc_freq /= 1000000; 166 167 /* 168 * XXX More of this should be in ncr53c9x_attach(), but 169 * XXX should we really poke around the chip that much in 170 * XXX the MI code? Think about this more... 171 */ 172 173 /* 174 * Set up static configuration info. 175 */ 176 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 177 sc->sc_cfg2 = NCRCFG2_SCSI2; 178 sc->sc_cfg3 = 0; 179 sc->sc_rev = NCR_VARIANT_NCR53C94; 180 181 /* 182 * XXX minsync and maxxfer _should_ be set up in MI code, 183 * XXX but it appears to have some dependency on what sort 184 * XXX of DMA we're hooked up to, etc. 185 */ 186 187 /* 188 * This is the value used to start sync negotiations 189 * Note that the NCR register "SYNCTP" is programmed 190 * in "clocks per byte", and has a minimum value of 4. 191 * The SCSI period used in negotiation is one-fourth 192 * of the time (in nanoseconds) needed to transfer one byte. 193 * Since the chip's clock is given in MHz, we have the following 194 * formula: 4 * period = (1000 / freq) * 4 195 */ 196 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 197 198 sc->sc_maxxfer = 64 * 1024; 199 200 /* Do the common parts of attachment. */ 201 sc->sc_adapter.adapt_minphys = minphys; 202 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 203 ncr53c9x_attach(sc); 204 } 205 206 static void 207 asc_tc_reset(sc) 208 struct ncr53c9x_softc *sc; 209 { 210 struct asc_softc *asc = (struct asc_softc *)sc; 211 212 asc->sc_active = 0; 213 } 214 215 static int 216 asc_tc_intr(sc) 217 struct ncr53c9x_softc *sc; 218 { 219 struct asc_softc *asc = (struct asc_softc *)sc; 220 int trans, resid; 221 222 resid = 0; 223 if (!asc->sc_ispullup && 224 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 225 NCR_DMA(("asc_tc_intr: empty FIFO of %d ", resid)); 226 DELAY(1); 227 } 228 229 resid += NCR_READ_REG(sc, NCR_TCL); 230 resid += NCR_READ_REG(sc, NCR_TCM) << 8; 231 232 trans = asc->sc_dmasize - resid; 233 234 if (asc->sc_ispullup) 235 memcpy(asc->sc_target, asc->sc_bounce, trans); 236 *asc->sc_dmalen -= trans; 237 *asc->sc_dmaaddr += trans; 238 asc->sc_active = 0; 239 240 return (0); 241 } 242 243 static int 244 asc_tc_setup(sc, addr, len, datain, dmasize) 245 struct ncr53c9x_softc *sc; 246 caddr_t *addr; 247 size_t *len; 248 int datain; 249 size_t *dmasize; 250 { 251 struct asc_softc *asc = (struct asc_softc *)sc; 252 u_int32_t tc_dmar; 253 size_t size; 254 255 asc->sc_dmaaddr = addr; 256 asc->sc_dmalen = len; 257 asc->sc_ispullup = datain; 258 259 NCR_DMA(("asc_tc_setup: start %ld@%p, %s\n", (long)*asc->sc_dmalen, 260 *asc->sc_dmaaddr, datain ? "IN" : "OUT")); 261 262 size = *dmasize; 263 if (size > PER_TGT_DMA_SIZE) 264 size = PER_TGT_DMA_SIZE; 265 *dmasize = asc->sc_dmasize = size; 266 267 NCR_DMA(("asc_tc_setup: dmasize = %ld\n", (long)asc->sc_dmasize)); 268 269 asc->sc_bounce = asc->sc_base + PMAZ_OFFSET_RAM; 270 asc->sc_bounce += PER_TGT_DMA_SIZE * 271 sc->sc_nexus->xs->xs_periph->periph_target; 272 asc->sc_target = *addr; 273 274 if (!asc->sc_ispullup) 275 memcpy(asc->sc_bounce, asc->sc_target, size); 276 277 #if 1 278 if (asc->sc_ispullup) 279 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 280 else 281 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 282 bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar); 283 asc->sc_active = 1; 284 #endif 285 return (0); 286 } 287 288 static void 289 asc_tc_go(sc) 290 struct ncr53c9x_softc *sc; 291 { 292 #if 0 293 struct asc_softc *asc = (struct asc_softc *)sc; 294 u_int32_t tc_dmar; 295 296 if (asc->sc_ispullup) 297 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 298 else 299 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 300 bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar); 301 asc->sc_active = 1; 302 #endif 303 } 304 305 /* NEVER CALLED BY MI 53C9x ENGINE INDEED */ 306 static void 307 asc_tc_stop(sc) 308 struct ncr53c9x_softc *sc; 309 { 310 #if 0 311 struct asc_softc *asc = (struct asc_softc *)sc; 312 313 if (asc->sc_ispullup) 314 memcpy(asc->sc_target, asc->sc_bounce, asc->sc_dmasize); 315 asc->sc_active = 0; 316 #endif 317 } 318 319 /* 320 * Glue functions. 321 */ 322 static u_char 323 asc_read_reg(sc, reg) 324 struct ncr53c9x_softc *sc; 325 int reg; 326 { 327 struct asc_softc *asc = (struct asc_softc *)sc; 328 u_char v; 329 330 v = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 331 reg * sizeof(u_int32_t)) & 0xff; 332 333 return (v); 334 } 335 336 static void 337 asc_write_reg(sc, reg, val) 338 struct ncr53c9x_softc *sc; 339 int reg; 340 u_char val; 341 { 342 struct asc_softc *asc = (struct asc_softc *)sc; 343 344 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 345 reg * sizeof(u_int32_t), val); 346 } 347 348 static int 349 asc_dma_isintr(sc) 350 struct ncr53c9x_softc *sc; 351 { 352 return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT); 353 } 354 355 static int 356 asc_dma_isactive(sc) 357 struct ncr53c9x_softc *sc; 358 { 359 struct asc_softc *asc = (struct asc_softc *)sc; 360 361 return (asc->sc_active); 362 } 363 364 static void 365 asc_clear_latched_intr(sc) 366 struct ncr53c9x_softc *sc; 367 { 368 } 369
Indexes created Mon Sep 22 05:09:51 GMT 2025