asc_tc.c revision 1.24
1 /* $NetBSD: asc_tc.c,v 1.24 2005/02/04 02:10:48 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: asc_tc.c,v 1.24 2005/02/04 02:10:48 perry Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/buf.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 #include <dev/scsipi/scsi_message.h> 51 52 #include <machine/bus.h> 53 54 #include <dev/ic/ncr53c9xreg.h> 55 #include <dev/ic/ncr53c9xvar.h> 56 57 #include <dev/tc/tcvar.h> 58 59 struct asc_softc { 60 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 61 bus_space_tag_t sc_bst; 62 bus_space_handle_t sc_bsh; 63 bus_dma_tag_t sc_dmat; 64 bus_dmamap_t sc_dmamap; 65 caddr_t *sc_dmaaddr; 66 size_t *sc_dmalen; 67 size_t sc_dmasize; 68 int sc_active; /* DMA active ? */ 69 int sc_ispullup; /* DMA into main memory? */ 70 71 /* XXX XXX XXX */ 72 caddr_t sc_base, sc_bounce, sc_target; 73 }; 74 75 static int asc_tc_match(struct device *, struct cfdata *, void *); 76 static void asc_tc_attach(struct device *, struct device *, void *); 77 78 CFATTACH_DECL(asc_tc, sizeof(struct asc_softc), 79 asc_tc_match, asc_tc_attach, NULL, NULL); 80 81 static u_char asc_read_reg(struct ncr53c9x_softc *, int); 82 static void asc_write_reg(struct ncr53c9x_softc *, int, u_char); 83 static int asc_dma_isintr(struct ncr53c9x_softc *); 84 static void asc_tc_reset(struct ncr53c9x_softc *); 85 static int asc_tc_intr(struct ncr53c9x_softc *); 86 static int asc_tc_setup(struct ncr53c9x_softc *, caddr_t *, 87 size_t *, int, size_t *); 88 static void asc_tc_go(struct ncr53c9x_softc *); 89 static void asc_tc_stop(struct ncr53c9x_softc *); 90 static int asc_dma_isactive(struct ncr53c9x_softc *); 91 static void asc_clear_latched_intr(struct ncr53c9x_softc *); 92 93 static struct ncr53c9x_glue asc_tc_glue = { 94 asc_read_reg, 95 asc_write_reg, 96 asc_dma_isintr, 97 asc_tc_reset, 98 asc_tc_intr, 99 asc_tc_setup, 100 asc_tc_go, 101 asc_tc_stop, 102 asc_dma_isactive, 103 asc_clear_latched_intr, 104 }; 105 106 /* 107 * Parameters specific to PMAZ-A TC option card. 108 */ 109 #define PMAZ_OFFSET_53C94 0x0 /* from module base */ 110 #define PMAZ_OFFSET_DMAR 0x40000 /* DMA Address Register */ 111 #define PMAZ_OFFSET_RAM 0x80000 /* 128KB SRAM buffer */ 112 #define PMAZ_OFFSET_ROM 0xc0000 /* diagnostic ROM */ 113 114 #define PMAZ_RAM_SIZE 0x20000 /* 128k (32k*32) */ 115 #define PER_TGT_DMA_SIZE ((PMAZ_RAM_SIZE/7) & ~(sizeof(int)-1)) 116 117 #define PMAZ_DMAR_WRITE 0x80000000 /* DMA direction bit */ 118 #define PMAZ_DMAR_MASK 0x1ffff /* 17 bits, 128k */ 119 #define PMAZ_DMA_ADDR(x) ((unsigned long)(x) & PMAZ_DMAR_MASK) 120 121 static int 122 asc_tc_match(parent, cfdata, aux) 123 struct device *parent; 124 struct cfdata *cfdata; 125 void *aux; 126 { 127 struct tc_attach_args *d = aux; 128 129 if (strncmp("PMAZ-AA ", d->ta_modname, TC_ROM_LLEN)) 130 return (0); 131 132 return (1); 133 } 134 135 static void 136 asc_tc_attach(parent, self, aux) 137 struct device *parent, *self; 138 void *aux; 139 { 140 struct tc_attach_args *ta = aux; 141 struct asc_softc *asc = (struct asc_softc *)self; 142 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 143 144 /* 145 * Set up glue for MI code early; we use some of it here. 146 */ 147 sc->sc_glue = &asc_tc_glue; 148 asc->sc_bst = ta->ta_memt; 149 asc->sc_dmat = ta->ta_dmat; 150 if (bus_space_map(asc->sc_bst, ta->ta_addr, 151 PMAZ_OFFSET_RAM + PMAZ_RAM_SIZE, 0, &asc->sc_bsh)) { 152 printf("%s: unable to map device\n", sc->sc_dev.dv_xname); 153 return; 154 } 155 asc->sc_base = (caddr_t)ta->ta_addr; /* XXX XXX XXX */ 156 157 tc_intr_establish(parent, ta->ta_cookie, IPL_BIO, ncr53c9x_intr, sc); 158 159 sc->sc_id = 7; 160 sc->sc_freq = (ta->ta_busspeed) ? 25000000 : 12500000; 161 162 /* gimme MHz */ 163 sc->sc_freq /= 1000000; 164 165 /* 166 * XXX More of this should be in ncr53c9x_attach(), but 167 * XXX should we really poke around the chip that much in 168 * XXX the MI code? Think about this more... 169 */ 170 171 /* 172 * Set up static configuration info. 173 */ 174 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 175 sc->sc_cfg2 = NCRCFG2_SCSI2; 176 sc->sc_cfg3 = 0; 177 sc->sc_rev = NCR_VARIANT_NCR53C94; 178 179 /* 180 * XXX minsync and maxxfer _should_ be set up in MI code, 181 * XXX but it appears to have some dependency on what sort 182 * XXX of DMA we're hooked up to, etc. 183 */ 184 185 /* 186 * This is the value used to start sync negotiations 187 * Note that the NCR register "SYNCTP" is programmed 188 * in "clocks per byte", and has a minimum value of 4. 189 * The SCSI period used in negotiation is one-fourth 190 * of the time (in nanoseconds) needed to transfer one byte. 191 * Since the chip's clock is given in MHz, we have the following 192 * formula: 4 * period = (1000 / freq) * 4 193 */ 194 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 195 196 sc->sc_maxxfer = 64 * 1024; 197 198 /* Do the common parts of attachment. */ 199 sc->sc_adapter.adapt_minphys = minphys; 200 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 201 ncr53c9x_attach(sc); 202 } 203 204 static void 205 asc_tc_reset(sc) 206 struct ncr53c9x_softc *sc; 207 { 208 struct asc_softc *asc = (struct asc_softc *)sc; 209 210 asc->sc_active = 0; 211 } 212 213 static int 214 asc_tc_intr(sc) 215 struct ncr53c9x_softc *sc; 216 { 217 struct asc_softc *asc = (struct asc_softc *)sc; 218 int trans, resid; 219 220 resid = 0; 221 if (!asc->sc_ispullup && 222 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 223 NCR_DMA(("asc_tc_intr: empty FIFO of %d ", resid)); 224 DELAY(1); 225 } 226 227 resid += NCR_READ_REG(sc, NCR_TCL); 228 resid += NCR_READ_REG(sc, NCR_TCM) << 8; 229 230 trans = asc->sc_dmasize - resid; 231 232 if (asc->sc_ispullup) 233 memcpy(asc->sc_target, asc->sc_bounce, trans); 234 *asc->sc_dmalen -= trans; 235 *asc->sc_dmaaddr += trans; 236 asc->sc_active = 0; 237 238 return (0); 239 } 240 241 static int 242 asc_tc_setup(sc, addr, len, datain, dmasize) 243 struct ncr53c9x_softc *sc; 244 caddr_t *addr; 245 size_t *len; 246 int datain; 247 size_t *dmasize; 248 { 249 struct asc_softc *asc = (struct asc_softc *)sc; 250 u_int32_t tc_dmar; 251 size_t size; 252 253 asc->sc_dmaaddr = addr; 254 asc->sc_dmalen = len; 255 asc->sc_ispullup = datain; 256 257 NCR_DMA(("asc_tc_setup: start %ld@%p, %s\n", (long)*asc->sc_dmalen, 258 *asc->sc_dmaaddr, datain ? "IN" : "OUT")); 259 260 size = *dmasize; 261 if (size > PER_TGT_DMA_SIZE) 262 size = PER_TGT_DMA_SIZE; 263 *dmasize = asc->sc_dmasize = size; 264 265 NCR_DMA(("asc_tc_setup: dmasize = %ld\n", (long)asc->sc_dmasize)); 266 267 asc->sc_bounce = asc->sc_base + PMAZ_OFFSET_RAM; 268 asc->sc_bounce += PER_TGT_DMA_SIZE * 269 sc->sc_nexus->xs->xs_periph->periph_target; 270 asc->sc_target = *addr; 271 272 if (!asc->sc_ispullup) 273 memcpy(asc->sc_bounce, asc->sc_target, size); 274 275 #if 1 276 if (asc->sc_ispullup) 277 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 278 else 279 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 280 bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar); 281 asc->sc_active = 1; 282 #endif 283 return (0); 284 } 285 286 static void 287 asc_tc_go(sc) 288 struct ncr53c9x_softc *sc; 289 { 290 #if 0 291 struct asc_softc *asc = (struct asc_softc *)sc; 292 u_int32_t tc_dmar; 293 294 if (asc->sc_ispullup) 295 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 296 else 297 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 298 bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar); 299 asc->sc_active = 1; 300 #endif 301 } 302 303 /* NEVER CALLED BY MI 53C9x ENGINE INDEED */ 304 static void 305 asc_tc_stop(sc) 306 struct ncr53c9x_softc *sc; 307 { 308 #if 0 309 struct asc_softc *asc = (struct asc_softc *)sc; 310 311 if (asc->sc_ispullup) 312 memcpy(asc->sc_target, asc->sc_bounce, asc->sc_dmasize); 313 asc->sc_active = 0; 314 #endif 315 } 316 317 /* 318 * Glue functions. 319 */ 320 static u_char 321 asc_read_reg(sc, reg) 322 struct ncr53c9x_softc *sc; 323 int reg; 324 { 325 struct asc_softc *asc = (struct asc_softc *)sc; 326 u_char v; 327 328 v = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 329 reg * sizeof(u_int32_t)) & 0xff; 330 331 return (v); 332 } 333 334 static void 335 asc_write_reg(sc, reg, val) 336 struct ncr53c9x_softc *sc; 337 int reg; 338 u_char val; 339 { 340 struct asc_softc *asc = (struct asc_softc *)sc; 341 342 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 343 reg * sizeof(u_int32_t), val); 344 } 345 346 static int 347 asc_dma_isintr(sc) 348 struct ncr53c9x_softc *sc; 349 { 350 return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT); 351 } 352 353 static int 354 asc_dma_isactive(sc) 355 struct ncr53c9x_softc *sc; 356 { 357 struct asc_softc *asc = (struct asc_softc *)sc; 358 359 return (asc->sc_active); 360 } 361 362 static void 363 asc_clear_latched_intr(sc) 364 struct ncr53c9x_softc *sc; 365 { 366 } 367
Indexes created Mon Sep 22 05:09:51 GMT 2025