asc_tc.c revision 1.30
1 /* $NetBSD: asc_tc.c,v 1.30 2007/03/04 15:17:06 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: asc_tc.c,v 1.30 2007/03/04 15:17:06 yamt Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/buf.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 #include <dev/scsipi/scsi_message.h> 51 52 #include <machine/bus.h> 53 54 #include <dev/ic/ncr53c9xreg.h> 55 #include <dev/ic/ncr53c9xvar.h> 56 57 #include <dev/tc/tcvar.h> 58 59 struct asc_softc { 60 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 61 bus_space_tag_t sc_bst; 62 bus_space_handle_t sc_bsh; 63 bus_dma_tag_t sc_dmat; 64 bus_dmamap_t sc_dmamap; 65 char **sc_dmaaddr; 66 size_t *sc_dmalen; 67 size_t sc_dmasize; 68 int sc_active; /* DMA active ? */ 69 int sc_ispullup; /* DMA into main memory? */ 70 71 /* XXX XXX XXX */ 72 char *sc_base, *sc_bounce, *sc_target; 73 }; 74 75 static int asc_tc_match(struct device *, struct cfdata *, void *); 76 static void asc_tc_attach(struct device *, struct device *, void *); 77 78 CFATTACH_DECL(asc_tc, sizeof(struct asc_softc), 79 asc_tc_match, asc_tc_attach, NULL, NULL); 80 81 static u_char asc_read_reg(struct ncr53c9x_softc *, int); 82 static void asc_write_reg(struct ncr53c9x_softc *, int, u_char); 83 static int asc_dma_isintr(struct ncr53c9x_softc *); 84 static void asc_tc_reset(struct ncr53c9x_softc *); 85 static int asc_tc_intr(struct ncr53c9x_softc *); 86 static int asc_tc_setup(struct ncr53c9x_softc *, void **, 87 size_t *, int, size_t *); 88 static void asc_tc_go(struct ncr53c9x_softc *); 89 static void asc_tc_stop(struct ncr53c9x_softc *); 90 static int asc_dma_isactive(struct ncr53c9x_softc *); 91 static void asc_clear_latched_intr(struct ncr53c9x_softc *); 92 93 static struct ncr53c9x_glue asc_tc_glue = { 94 asc_read_reg, 95 asc_write_reg, 96 asc_dma_isintr, 97 asc_tc_reset, 98 asc_tc_intr, 99 asc_tc_setup, 100 asc_tc_go, 101 asc_tc_stop, 102 asc_dma_isactive, 103 asc_clear_latched_intr, 104 }; 105 106 /* 107 * Parameters specific to PMAZ-A TC option card. 108 */ 109 #define PMAZ_OFFSET_53C94 0x0 /* from module base */ 110 #define PMAZ_OFFSET_DMAR 0x40000 /* DMA Address Register */ 111 #define PMAZ_OFFSET_RAM 0x80000 /* 128KB SRAM buffer */ 112 #define PMAZ_OFFSET_ROM 0xc0000 /* diagnostic ROM */ 113 114 #define PMAZ_RAM_SIZE 0x20000 /* 128k (32k*32) */ 115 #define PER_TGT_DMA_SIZE ((PMAZ_RAM_SIZE/7) & ~(sizeof(int)-1)) 116 117 #define PMAZ_DMAR_WRITE 0x80000000 /* DMA direction bit */ 118 #define PMAZ_DMAR_MASK 0x1ffff /* 17 bits, 128k */ 119 #define PMAZ_DMA_ADDR(x) ((unsigned long)(x) & PMAZ_DMAR_MASK) 120 121 static int 122 asc_tc_match(struct device *parent, struct cfdata *cfdata, void *aux) 123 { 124 struct tc_attach_args *d = aux; 125 126 if (strncmp("PMAZ-AA ", d->ta_modname, TC_ROM_LLEN)) 127 return (0); 128 129 return (1); 130 } 131 132 static void 133 asc_tc_attach(struct device *parent, struct device *self, void *aux) 134 { 135 struct tc_attach_args *ta = aux; 136 struct asc_softc *asc = device_private(self); 137 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 138 139 /* 140 * Set up glue for MI code early; we use some of it here. 141 */ 142 sc->sc_glue = &asc_tc_glue; 143 asc->sc_bst = ta->ta_memt; 144 asc->sc_dmat = ta->ta_dmat; 145 if (bus_space_map(asc->sc_bst, ta->ta_addr, 146 PMAZ_OFFSET_RAM + PMAZ_RAM_SIZE, 0, &asc->sc_bsh)) { 147 printf("%s: unable to map device\n", sc->sc_dev.dv_xname); 148 return; 149 } 150 asc->sc_base = (void *)ta->ta_addr; /* XXX XXX XXX */ 151 152 tc_intr_establish(parent, ta->ta_cookie, IPL_BIO, ncr53c9x_intr, sc); 153 154 sc->sc_id = 7; 155 sc->sc_freq = (ta->ta_busspeed) ? 25000000 : 12500000; 156 157 /* gimme MHz */ 158 sc->sc_freq /= 1000000; 159 160 /* 161 * XXX More of this should be in ncr53c9x_attach(), but 162 * XXX should we really poke around the chip that much in 163 * XXX the MI code? Think about this more... 164 */ 165 166 /* 167 * Set up static configuration info. 168 */ 169 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 170 sc->sc_cfg2 = NCRCFG2_SCSI2; 171 sc->sc_cfg3 = 0; 172 sc->sc_rev = NCR_VARIANT_NCR53C94; 173 174 /* 175 * XXX minsync and maxxfer _should_ be set up in MI code, 176 * XXX but it appears to have some dependency on what sort 177 * XXX of DMA we're hooked up to, etc. 178 */ 179 180 /* 181 * This is the value used to start sync negotiations 182 * Note that the NCR register "SYNCTP" is programmed 183 * in "clocks per byte", and has a minimum value of 4. 184 * The SCSI period used in negotiation is one-fourth 185 * of the time (in nanoseconds) needed to transfer one byte. 186 * Since the chip's clock is given in MHz, we have the following 187 * formula: 4 * period = (1000 / freq) * 4 188 */ 189 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 190 191 sc->sc_maxxfer = 64 * 1024; 192 193 /* Do the common parts of attachment. */ 194 sc->sc_adapter.adapt_minphys = minphys; 195 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 196 ncr53c9x_attach(sc); 197 } 198 199 static void 200 asc_tc_reset(struct ncr53c9x_softc *sc) 201 { 202 struct asc_softc *asc = (struct asc_softc *)sc; 203 204 asc->sc_active = 0; 205 } 206 207 static int 208 asc_tc_intr(struct ncr53c9x_softc *sc) 209 { 210 struct asc_softc *asc = (struct asc_softc *)sc; 211 int trans, resid; 212 213 resid = 0; 214 if (!asc->sc_ispullup && 215 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 216 NCR_DMA(("asc_tc_intr: empty FIFO of %d ", resid)); 217 DELAY(1); 218 } 219 220 resid += NCR_READ_REG(sc, NCR_TCL); 221 resid += NCR_READ_REG(sc, NCR_TCM) << 8; 222 223 trans = asc->sc_dmasize - resid; 224 225 if (asc->sc_ispullup) 226 memcpy(asc->sc_target, asc->sc_bounce, trans); 227 *asc->sc_dmalen -= trans; 228 *asc->sc_dmaaddr += trans; 229 asc->sc_active = 0; 230 231 return (0); 232 } 233 234 static int 235 asc_tc_setup(struct ncr53c9x_softc *sc, void **addr, size_t *len, 236 int datain, size_t *dmasize) 237 { 238 struct asc_softc *asc = (struct asc_softc *)sc; 239 u_int32_t tc_dmar; 240 size_t size; 241 242 asc->sc_dmaaddr = (char **)addr; 243 asc->sc_dmalen = len; 244 asc->sc_ispullup = datain; 245 246 NCR_DMA(("asc_tc_setup: start %ld@%p, %s\n", (long)*asc->sc_dmalen, 247 *asc->sc_dmaaddr, datain ? "IN" : "OUT")); 248 249 size = *dmasize; 250 if (size > PER_TGT_DMA_SIZE) 251 size = PER_TGT_DMA_SIZE; 252 *dmasize = asc->sc_dmasize = size; 253 254 NCR_DMA(("asc_tc_setup: dmasize = %ld\n", (long)asc->sc_dmasize)); 255 256 asc->sc_bounce = asc->sc_base + PMAZ_OFFSET_RAM; 257 asc->sc_bounce += PER_TGT_DMA_SIZE * 258 sc->sc_nexus->xs->xs_periph->periph_target; 259 asc->sc_target = *addr; 260 261 if (!asc->sc_ispullup) 262 memcpy(asc->sc_bounce, asc->sc_target, size); 263 264 #if 1 265 if (asc->sc_ispullup) 266 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 267 else 268 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 269 bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar); 270 asc->sc_active = 1; 271 #endif 272 return (0); 273 } 274 275 static void 276 asc_tc_go(struct ncr53c9x_softc *sc) 277 { 278 #if 0 279 struct asc_softc *asc = (struct asc_softc *)sc; 280 u_int32_t tc_dmar; 281 282 if (asc->sc_ispullup) 283 tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); 284 else 285 tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); 286 bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar); 287 asc->sc_active = 1; 288 #endif 289 } 290 291 /* NEVER CALLED BY MI 53C9x ENGINE INDEED */ 292 static void 293 asc_tc_stop(struct ncr53c9x_softc *sc) 294 { 295 #if 0 296 struct asc_softc *asc = (struct asc_softc *)sc; 297 298 if (asc->sc_ispullup) 299 memcpy(asc->sc_target, asc->sc_bounce, asc->sc_dmasize); 300 asc->sc_active = 0; 301 #endif 302 } 303 304 /* 305 * Glue functions. 306 */ 307 static u_char 308 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 309 { 310 struct asc_softc *asc = (struct asc_softc *)sc; 311 u_char v; 312 313 v = bus_space_read_4(asc->sc_bst, asc->sc_bsh, 314 reg * sizeof(u_int32_t)) & 0xff; 315 316 return (v); 317 } 318 319 static void 320 asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 321 { 322 struct asc_softc *asc = (struct asc_softc *)sc; 323 324 bus_space_write_4(asc->sc_bst, asc->sc_bsh, 325 reg * sizeof(u_int32_t), val); 326 } 327 328 static int 329 asc_dma_isintr(struct ncr53c9x_softc *sc) 330 { 331 return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT); 332 } 333 334 static int 335 asc_dma_isactive(struct ncr53c9x_softc *sc) 336 { 337 struct asc_softc *asc = (struct asc_softc *)sc; 338 339 return (asc->sc_active); 340 } 341 342 static void 343 asc_clear_latched_intr(struct ncr53c9x_softc *sc) 344 { 345 } 346
Indexes created Mon Sep 22 13:09:51 GMT 2025