asc_tcds.c revision 1.1
1 /* $NetBSD: asc_tcds.c,v 1.1 2000/07/04 02:22:19 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Peter Galbavy. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 70 71 __KERNEL_RCSID(0, "$NetBSD: asc_tcds.c,v 1.1 2000/07/04 02:22:19 nisimura Exp $"); 72 73 #include <sys/types.h> 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 78 #include <dev/scsipi/scsi_all.h> 79 #include <dev/scsipi/scsipi_all.h> 80 #include <dev/scsipi/scsiconf.h> 81 82 #include <dev/ic/ncr53c9xreg.h> 83 #include <dev/ic/ncr53c9xvar.h> 84 85 #include <machine/bus.h> 86 87 #include <dev/tc/tcvar.h> 88 #include <dev/tc/tcdsreg.h> 89 #include <dev/tc/tcdsvar.h> 90 91 struct asc_softc { 92 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 93 bus_space_tag_t sc_bst; /* bus space tag */ 94 bus_space_handle_t sc_scsi_bsh; /* ASC register handle */ 95 bus_dma_tag_t sc_dmat; /* bus dma tag */ 96 bus_dmamap_t sc_dmamap; /* bus dmamap */ 97 caddr_t *sc_dmaaddr; 98 size_t *sc_dmalen; 99 size_t sc_dmasize; 100 unsigned sc_flags; 101 #define ASC_ISPULLUP 0x01 102 #define ASC_DMAACTIVE 0x02 103 #define ASC_MAPLOADED 0x04 104 struct tcds_slotconfig *sc_tcds; /* DMA/slot info lives here */ 105 }; 106 107 static int asc_tcds_match __P((struct device *, struct cfdata *, void *)); 108 static void asc_tcds_attach __P((struct device *, struct device *, void *)); 109 110 /* Linkup to the rest of the kernel */ 111 struct cfattach asc_tcds_ca = { 112 sizeof(struct asc_softc), asc_tcds_match, asc_tcds_attach 113 }; 114 115 /* 116 * Functions and the switch for the MI code. 117 */ 118 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 119 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 120 static int tcds_dma_isintr __P((struct ncr53c9x_softc *)); 121 static void tcds_dma_reset __P((struct ncr53c9x_softc *)); 122 static int tcds_dma_intr __P((struct ncr53c9x_softc *)); 123 static int tcds_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 124 size_t *, int, size_t *)); 125 static void tcds_dma_go __P((struct ncr53c9x_softc *)); 126 static void tcds_dma_stop __P((struct ncr53c9x_softc *)); 127 static int tcds_dma_isactive __P((struct ncr53c9x_softc *)); 128 static void tcds_clear_latched_intr __P((struct ncr53c9x_softc *)); 129 130 static struct ncr53c9x_glue asc_tcds_glue = { 131 asc_read_reg, 132 asc_write_reg, 133 tcds_dma_isintr, 134 tcds_dma_reset, 135 tcds_dma_intr, 136 tcds_dma_setup, 137 tcds_dma_go, 138 tcds_dma_stop, 139 tcds_dma_isactive, 140 tcds_clear_latched_intr, 141 }; 142 143 static int 144 asc_tcds_match(parent, cf, aux) 145 struct device *parent; 146 struct cfdata *cf; 147 void *aux; 148 { 149 150 /* We always exist. */ 151 return 1; 152 } 153 154 #define DMAMAX(a) (NBPG - ((a) & (NBPG - 1))) 155 156 /* 157 * Attach this instance, and then all the sub-devices 158 */ 159 static void 160 asc_tcds_attach(parent, self, aux) 161 struct device *parent, *self; 162 void *aux; 163 { 164 struct tcdsdev_attach_args *tcdsdev = aux; 165 struct asc_softc *asc = (struct asc_softc *)self; 166 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 167 int error; 168 169 /* 170 * Set up glue for MI code early; we use some of it here. 171 */ 172 sc->sc_glue = &asc_tcds_glue; 173 174 asc->sc_bst = tcdsdev->tcdsda_bst; 175 asc->sc_scsi_bsh = tcdsdev->tcdsda_bsh; 176 asc->sc_tcds = tcdsdev->tcdsda_sc; 177 178 /* 179 * The TCDS ASIC cannot DMA across 8k boundaries, and this 180 * driver is written such that each DMA segment gets a new 181 * call to tcds_dma_setup(). Thus, the DMA map only needs 182 * to support 8k transfers. 183 */ 184 asc->sc_dmat = tcdsdev->tcdsda_dmat; 185 if ((error = bus_dmamap_create(asc->sc_dmat, NBPG, 1, NBPG, 186 NBPG, BUS_DMA_NOWAIT, &asc->sc_dmamap)) < 0) { 187 printf("failed to create dma map, error = %d\n", error); 188 } 189 190 sc->sc_id = tcdsdev->tcdsda_id; 191 sc->sc_freq = tcdsdev->tcdsda_freq; 192 193 /* gimme Mhz */ 194 sc->sc_freq /= 1000000; 195 196 tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc); 197 198 /* 199 * XXX More of this should be in ncr53c9x_attach(), but 200 * XXX should we really poke around the chip that much in 201 * XXX the MI code? Think about this more... 202 */ 203 204 /* 205 * Set up static configuration info. 206 */ 207 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 208 sc->sc_cfg2 = NCRCFG2_SCSI2; 209 sc->sc_cfg3 = NCRCFG3_CDB; 210 if (sc->sc_freq > 25) 211 sc->sc_cfg3 |= NCRF9XCFG3_FCLK; 212 sc->sc_rev = tcdsdev->tcdsda_variant; 213 if (tcdsdev->tcdsda_fast) { 214 sc->sc_features |= NCR_F_FASTSCSI; 215 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 216 } 217 218 /* 219 * XXX minsync and maxxfer _should_ be set up in MI code, 220 * XXX but it appears to have some dependency on what sort 221 * XXX of DMA we're hooked up to, etc. 222 */ 223 224 /* 225 * This is the value used to start sync negotiations 226 * Note that the NCR register "SYNCTP" is programmed 227 * in "clocks per byte", and has a minimum value of 4. 228 * The SCSI period used in negotiation is one-fourth 229 * of the time (in nanoseconds) needed to transfer one byte. 230 * Since the chip's clock is given in MHz, we have the following 231 * formula: 4 * period = (1000 / freq) * 4 232 */ 233 sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4; 234 235 sc->sc_maxxfer = 64 * 1024; 236 237 /* Do the common parts of attachment. */ 238 ncr53c9x_attach(sc, NULL, NULL); 239 } 240 241 static void 242 tcds_dma_reset(sc) 243 struct ncr53c9x_softc *sc; 244 { 245 struct asc_softc *asc = (struct asc_softc *)sc; 246 247 /* TCDS SCSI disable/reset/enable. */ 248 tcds_scsi_reset(asc->sc_tcds); /* XXX */ 249 250 if (asc->sc_flags & ASC_MAPLOADED) 251 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 252 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 253 } 254 255 /* 256 * start a dma transfer or keep it going 257 */ 258 int 259 tcds_dma_setup(sc, addr, len, ispullup, dmasize) 260 struct ncr53c9x_softc *sc; 261 caddr_t *addr; 262 size_t *len, *dmasize; 263 int ispullup; /* DMA into main memory */ 264 { 265 struct asc_softc *asc = (struct asc_softc *)sc; 266 struct tcds_slotconfig *tcds = asc->sc_tcds; 267 size_t size; 268 u_int32_t dic; 269 270 NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot, 271 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, 272 (ispullup) ? "IN" : "OUT")); 273 274 /* 275 * the rules say we cannot transfer more than the limit 276 * of this DMA chip (64k) and we cannot cross a 8k boundary. 277 */ 278 size = min(*dmasize, DMAMAX((size_t)*addr)); 279 asc->sc_dmaaddr = addr; 280 asc->sc_dmalen = len; 281 asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 282 *dmasize = asc->sc_dmasize = size; 283 284 NCR_DMA(("dma_start: dmasize = %d\n", (int)size)); 285 286 if (size == 0) 287 return 0; 288 289 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, size, 290 NULL, BUS_DMA_NOWAIT)) { 291 /* 292 * XXX Should return an error, here, but the upper-layer 293 * XXX doesn't check the return value! 294 */ 295 panic("tcds_dma_setup: dmamap load failed"); 296 } 297 298 /* synchronize dmamap contents with memory image */ 299 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 0, size, 300 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 301 302 /* load address, set/clear unaligned transfer and read/write bits. */ 303 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda, 304 asc->sc_dmamap->dm_segs[0].ds_addr >> 2); 305 dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic); 306 dic &= ~TCDS_DIC_ADDRMASK; 307 dic |= asc->sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK; 308 if (ispullup) 309 dic |= TCDS_DIC_WRITE; 310 else 311 dic &= ~TCDS_DIC_WRITE; 312 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic); 313 314 asc->sc_flags |= ASC_MAPLOADED; 315 return 0; 316 } 317 318 static void 319 tcds_dma_go(sc) 320 struct ncr53c9x_softc *sc; 321 { 322 struct asc_softc *asc = (struct asc_softc *)sc; 323 324 /* mark unit as DMA-active */ 325 asc->sc_flags |= ASC_DMAACTIVE; 326 327 /* start DMA */ 328 tcds_dma_enable(asc->sc_tcds, 1); 329 } 330 331 static void 332 tcds_dma_stop(sc) 333 struct ncr53c9x_softc *sc; 334 { 335 #if 0 336 struct asc_softc *asc = (struct asc_softc *)sc; 337 #endif 338 339 /* 340 * XXX STOP DMA HERE! 341 */ 342 } 343 344 /* 345 * Pseudo (chained) interrupt from the asc driver to kick the 346 * current running DMA transfer. Called from ncr53c9x_intr() 347 * for now. 348 * 349 * return 1 if it was a DMA continue. 350 */ 351 static int 352 tcds_dma_intr(sc) 353 struct ncr53c9x_softc *sc; 354 { 355 struct asc_softc *asc = (struct asc_softc *)sc; 356 struct tcds_slotconfig *tcds = asc->sc_tcds; 357 int trans, resid; 358 u_int32_t tcl, tcm; 359 u_int32_t dud, dudmask, *addr; 360 bus_addr_t pa; 361 362 NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot)); 363 364 if (tcds_scsi_iserr(tcds)) 365 return 0; 366 367 /* This is an "assertion" :) */ 368 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 369 panic("tcds_dma_intr: DMA wasn't active"); 370 371 /* DMA has stopped */ 372 tcds_dma_enable(tcds, 0); 373 asc->sc_flags &= ~ASC_DMAACTIVE; 374 375 if (asc->sc_dmasize == 0) { 376 /* A "Transfer Pad" operation completed */ 377 tcl = NCR_READ_REG(sc, NCR_TCL); 378 tcm = NCR_READ_REG(sc, NCR_TCM); 379 NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 380 tcl | (tcm << 8), tcl, tcm)); 381 return 0; 382 } 383 384 resid = 0; 385 if ((asc->sc_flags & ASC_ISPULLUP) == 0 && 386 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 387 NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid)); 388 DELAY(1); 389 } 390 391 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 392 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 393 394 trans = asc->sc_dmasize - resid; 395 if (trans < 0) { /* transferred < 0 ? */ 396 printf("tcds_dma %d: xfer (%d) > req (%d)\n", 397 tcds->sc_slot, trans, (int)asc->sc_dmasize); 398 trans = asc->sc_dmasize; 399 } 400 401 NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 402 tcl, tcm, trans, resid)); 403 404 *asc->sc_dmalen -= trans; 405 *asc->sc_dmaaddr += trans; 406 407 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 408 0, asc->sc_dmamap->dm_mapsize, 409 (sc->sc_flags & ASC_ISPULLUP) 410 ? BUS_DMASYNC_POSTREAD 411 : BUS_DMASYNC_POSTWRITE); 412 413 /* 414 * Clean up unaligned DMAs into main memory. 415 */ 416 if (asc->sc_flags & ASC_ISPULLUP) { 417 /* Handle unaligned starting address, length. */ 418 dud = bus_space_read_4(tcds->sc_bst, 419 tcds->sc_bsh, tcds->sc_dud0); 420 if ((dud & TCDS_DUD0_VALIDBITS) != 0) { 421 addr = (u_int32_t *) 422 ((paddr_t)*asc->sc_dmaaddr & ~0x3); 423 dudmask = 0; 424 if (dud & TCDS_DUD0_VALID00) 425 panic("tcds_dma: dud0 byte 0 valid"); 426 if (dud & TCDS_DUD0_VALID01) 427 dudmask |= TCDS_DUD_BYTE01; 428 if (dud & TCDS_DUD0_VALID10) 429 dudmask |= TCDS_DUD_BYTE10; 430 #ifdef DIAGNOSTIC 431 if (dud & TCDS_DUD0_VALID11) 432 dudmask |= TCDS_DUD_BYTE11; 433 #endif 434 NCR_DMA(("dud0 at 0x%p dudmask 0x%x\n", 435 addr, dudmask)); 436 *addr = (*addr & ~dudmask) | (dud & dudmask); 437 } 438 dud = bus_space_read_4(tcds->sc_bst, 439 tcds->sc_bsh, tcds->sc_dud1); 440 if ((dud & TCDS_DUD1_VALIDBITS) != 0) { 441 pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, 442 tcds->sc_sda) << 2; 443 dudmask = 0; 444 if (dud & TCDS_DUD1_VALID00) 445 dudmask |= TCDS_DUD_BYTE00; 446 if (dud & TCDS_DUD1_VALID01) 447 dudmask |= TCDS_DUD_BYTE01; 448 if (dud & TCDS_DUD1_VALID10) 449 dudmask |= TCDS_DUD_BYTE10; 450 #ifdef DIAGNOSTIC 451 if (dud & TCDS_DUD1_VALID11) 452 panic("tcds_dma: dud1 byte 3 valid"); 453 #endif 454 NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n", 455 pa, dudmask)); 456 /* XXX Fix TC_PHYS_TO_UNCACHED() */ 457 #if defined(__alpha__) 458 addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG(pa); 459 #elif defined(__mips__) 460 addr = (u_int32_t *)MIPS_PHYS_TO_KSEG1(pa); 461 #else 462 #error TURBOchannel only exists on DECs, folks... 463 #endif 464 *addr = (*addr & ~dudmask) | (dud & dudmask); 465 } 466 /* XXX deal with saved residual byte? */ 467 } 468 469 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 470 asc->sc_flags &= ~ASC_MAPLOADED; 471 472 return 0; 473 } 474 475 /* 476 * Glue functions. 477 */ 478 static u_char 479 asc_read_reg(sc, reg) 480 struct ncr53c9x_softc *sc; 481 int reg; 482 { 483 struct asc_softc *asc = (struct asc_softc *)sc; 484 u_int32_t v; 485 486 v = bus_space_read_4(asc->sc_bst, asc->sc_scsi_bsh, 487 reg * sizeof(u_int32_t)); 488 489 return v & 0xff; 490 } 491 492 static void 493 asc_write_reg(sc, reg, val) 494 struct ncr53c9x_softc *sc; 495 int reg; 496 u_char val; 497 { 498 struct asc_softc *asc = (struct asc_softc *)sc; 499 500 bus_space_write_4(asc->sc_bst, asc->sc_scsi_bsh, 501 reg * sizeof(u_int32_t), val); 502 } 503 504 static int 505 tcds_dma_isintr(sc) 506 struct ncr53c9x_softc *sc; 507 { 508 struct asc_softc *asc = (struct asc_softc *)sc; 509 int x; 510 511 x = tcds_scsi_isintr(asc->sc_tcds, 1); 512 513 /* XXX */ 514 return x; 515 } 516 517 static int 518 tcds_dma_isactive(sc) 519 struct ncr53c9x_softc *sc; 520 { 521 struct asc_softc *asc = (struct asc_softc *)sc; 522 523 return !!(asc->sc_flags & ASC_DMAACTIVE); 524 } 525 526 static void 527 tcds_clear_latched_intr(sc) 528 struct ncr53c9x_softc *sc; 529 { 530 struct asc_softc *asc = (struct asc_softc *)sc; 531 532 /* Clear the TCDS interrupt bit. */ 533 (void)tcds_scsi_isintr(asc->sc_tcds, 1); 534 } 535
Indexes created Tue Sep 30 20:09:53 GMT 2025