asc_tcds.c revision 1.23
1 /* $NetBSD: asc_tcds.c,v 1.23 2008/04/13 04:55:54 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Peter Galbavy. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: asc_tcds.c,v 1.23 2008/04/13 04:55:54 tsutsui Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/device.h> 75 #include <sys/buf.h> 76 77 #include <uvm/uvm_extern.h> 78 79 #include <dev/scsipi/scsi_all.h> 80 #include <dev/scsipi/scsipi_all.h> 81 #include <dev/scsipi/scsiconf.h> 82 83 #include <dev/ic/ncr53c9xreg.h> 84 #include <dev/ic/ncr53c9xvar.h> 85 86 #include <sys/bus.h> 87 88 #include <dev/tc/tcvar.h> 89 #include <dev/tc/tcdsreg.h> 90 #include <dev/tc/tcdsvar.h> 91 92 struct asc_softc { 93 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 94 bus_space_tag_t sc_bst; /* bus space tag */ 95 bus_space_handle_t sc_scsi_bsh; /* ASC register handle */ 96 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 97 bus_dmamap_t sc_dmamap; /* bus dmamap */ 98 uint8_t **sc_dmaaddr; 99 size_t *sc_dmalen; 100 size_t sc_dmasize; 101 unsigned sc_flags; 102 #define ASC_ISPULLUP 0x01 103 #define ASC_DMAACTIVE 0x02 104 #define ASC_MAPLOADED 0x04 105 struct tcds_slotconfig *sc_tcds; /* DMA/slot info lives here */ 106 }; 107 108 static int asc_tcds_match(device_t, cfdata_t, void *); 109 static void asc_tcds_attach(device_t, device_t, void *); 110 111 CFATTACH_DECL_NEW(asc_tcds, sizeof(struct asc_softc), 112 asc_tcds_match, asc_tcds_attach, NULL, NULL); 113 114 /* 115 * Functions and the switch for the MI code. 116 */ 117 static uint8_t asc_read_reg(struct ncr53c9x_softc *, int); 118 static void asc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 119 static int tcds_dma_isintr(struct ncr53c9x_softc *); 120 static void tcds_dma_reset(struct ncr53c9x_softc *); 121 static int tcds_dma_intr(struct ncr53c9x_softc *); 122 static int tcds_dma_setup(struct ncr53c9x_softc *, uint8_t **, 123 size_t *, int, size_t *); 124 static void tcds_dma_go(struct ncr53c9x_softc *); 125 static void tcds_dma_stop(struct ncr53c9x_softc *); 126 static int tcds_dma_isactive(struct ncr53c9x_softc *); 127 static void tcds_clear_latched_intr(struct ncr53c9x_softc *); 128 129 static struct ncr53c9x_glue asc_tcds_glue = { 130 asc_read_reg, 131 asc_write_reg, 132 tcds_dma_isintr, 133 tcds_dma_reset, 134 tcds_dma_intr, 135 tcds_dma_setup, 136 tcds_dma_go, 137 tcds_dma_stop, 138 tcds_dma_isactive, 139 tcds_clear_latched_intr, 140 }; 141 142 static int 143 asc_tcds_match(device_t parent, cfdata_t cf, void *aux) 144 { 145 146 /* We always exist. */ 147 return 1; 148 } 149 150 #define DMAMAX(a) (PAGE_SIZE - ((a) & (PAGE_SIZE - 1))) 151 152 /* 153 * Attach this instance, and then all the sub-devices 154 */ 155 static void 156 asc_tcds_attach(device_t parent, device_t self, void *aux) 157 { 158 struct asc_softc *asc = device_private(self); 159 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 160 struct tcdsdev_attach_args *tcdsdev = aux; 161 int error; 162 163 /* 164 * Set up glue for MI code early; we use some of it here. 165 */ 166 sc->sc_dev = self; 167 sc->sc_glue = &asc_tcds_glue; 168 169 asc->sc_bst = tcdsdev->tcdsda_bst; 170 asc->sc_scsi_bsh = tcdsdev->tcdsda_bsh; 171 asc->sc_tcds = tcdsdev->tcdsda_sc; 172 173 /* 174 * The TCDS ASIC cannot DMA across 8k boundaries, and this 175 * driver is written such that each DMA segment gets a new 176 * call to tcds_dma_setup(). Thus, the DMA map only needs 177 * to support 8k transfers. 178 */ 179 asc->sc_dmat = tcdsdev->tcdsda_dmat; 180 if ((error = bus_dmamap_create(asc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 181 PAGE_SIZE, BUS_DMA_NOWAIT, &asc->sc_dmamap)) < 0) { 182 aprint_error(": failed to create DMA map, error = %d\n", error); 183 return; 184 } 185 186 sc->sc_id = tcdsdev->tcdsda_id; 187 sc->sc_freq = tcdsdev->tcdsda_freq; 188 189 /* gimme MHz */ 190 sc->sc_freq /= 1000000; 191 192 tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc); 193 194 /* 195 * XXX More of this should be in ncr53c9x_attach(), but 196 * XXX should we really poke around the chip that much in 197 * XXX the MI code? Think about this more... 198 */ 199 200 /* 201 * Set up static configuration info. 202 */ 203 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 204 sc->sc_cfg2 = NCRCFG2_SCSI2; 205 sc->sc_cfg3 = NCRCFG3_CDB; 206 if (sc->sc_freq > 25) 207 sc->sc_cfg3 |= NCRF9XCFG3_FCLK; 208 sc->sc_rev = tcdsdev->tcdsda_variant; 209 if (tcdsdev->tcdsda_fast) { 210 sc->sc_features |= NCR_F_FASTSCSI; 211 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 212 } 213 214 /* 215 * XXX minsync and maxxfer _should_ be set up in MI code, 216 * XXX but it appears to have some dependency on what sort 217 * XXX of DMA we're hooked up to, etc. 218 */ 219 220 /* 221 * This is the value used to start sync negotiations 222 * Note that the NCR register "SYNCTP" is programmed 223 * in "clocks per byte", and has a minimum value of 4. 224 * The SCSI period used in negotiation is one-fourth 225 * of the time (in nanoseconds) needed to transfer one byte. 226 * Since the chip's clock is given in MHz, we have the following 227 * formula: 4 * period = (1000 / freq) * 4 228 */ 229 sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4; 230 231 sc->sc_maxxfer = 64 * 1024; 232 233 /* Do the common parts of attachment. */ 234 sc->sc_adapter.adapt_minphys = minphys; 235 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 236 ncr53c9x_attach(sc); 237 } 238 239 static void 240 tcds_dma_reset(struct ncr53c9x_softc *sc) 241 { 242 struct asc_softc *asc = (struct asc_softc *)sc; 243 244 /* TCDS SCSI disable/reset/enable. */ 245 tcds_scsi_reset(asc->sc_tcds); /* XXX */ 246 247 if (asc->sc_flags & ASC_MAPLOADED) 248 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 249 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 250 } 251 252 /* 253 * start a DMA transfer or keep it going 254 */ 255 int 256 tcds_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 257 int ispullup, size_t *dmasize) 258 { 259 struct asc_softc *asc = (struct asc_softc *)sc; 260 struct tcds_slotconfig *tcds = asc->sc_tcds; 261 size_t size; 262 uint32_t dic; 263 264 NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot, 265 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, 266 (ispullup) ? "IN" : "OUT")); 267 268 /* 269 * the rules say we cannot transfer more than the limit 270 * of this DMA chip (64k) and we cannot cross a 8k boundary. 271 */ 272 size = min(*dmasize, DMAMAX((size_t)*addr)); 273 asc->sc_dmaaddr = addr; 274 asc->sc_dmalen = len; 275 asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 276 *dmasize = asc->sc_dmasize = size; 277 278 NCR_DMA(("dma_start: dmasize = %d\n", (int)size)); 279 280 if (size == 0) 281 return 0; 282 283 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, size, 284 NULL, BUS_DMA_NOWAIT | (ispullup ? BUS_DMA_READ : BUS_DMA_WRITE))) { 285 /* 286 * XXX Should return an error, here, but the upper-layer 287 * XXX doesn't check the return value! 288 */ 289 panic("%s: dmamap load failed", __func__); 290 } 291 292 /* synchronize dmamap contents with memory image */ 293 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 0, size, 294 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 295 296 /* load address, set/clear unaligned transfer and read/write bits. */ 297 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda, 298 asc->sc_dmamap->dm_segs[0].ds_addr >> 2); 299 dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic); 300 dic &= ~TCDS_DIC_ADDRMASK; 301 dic |= asc->sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK; 302 if (ispullup) 303 dic |= TCDS_DIC_WRITE; 304 else 305 dic &= ~TCDS_DIC_WRITE; 306 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic); 307 308 asc->sc_flags |= ASC_MAPLOADED; 309 return 0; 310 } 311 312 static void 313 tcds_dma_go(struct ncr53c9x_softc *sc) 314 { 315 struct asc_softc *asc = (struct asc_softc *)sc; 316 317 /* mark unit as DMA-active */ 318 asc->sc_flags |= ASC_DMAACTIVE; 319 320 /* start DMA */ 321 tcds_dma_enable(asc->sc_tcds, 1); 322 } 323 324 static void 325 tcds_dma_stop(struct ncr53c9x_softc *sc) 326 { 327 #if 0 328 struct asc_softc *asc = (struct asc_softc *)sc; 329 #endif 330 331 /* 332 * XXX STOP DMA HERE! 333 */ 334 } 335 336 /* 337 * Pseudo (chained) interrupt from the asc driver to kick the 338 * current running DMA transfer. Called from ncr53c9x_intr() 339 * for now. 340 * 341 * return 1 if it was a DMA continue. 342 */ 343 static int 344 tcds_dma_intr(struct ncr53c9x_softc *sc) 345 { 346 struct asc_softc *asc = (struct asc_softc *)sc; 347 struct tcds_slotconfig *tcds = asc->sc_tcds; 348 int trans, resid; 349 uint32_t tcl, tcm; 350 uint32_t dud, dudmask, *addr; 351 bus_addr_t pa; 352 353 NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot)); 354 355 if (tcds_scsi_iserr(tcds)) 356 return 0; 357 358 /* This is an "assertion" :) */ 359 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 360 panic("%s: DMA wasn't active", __func__); 361 362 /* DMA has stopped */ 363 tcds_dma_enable(tcds, 0); 364 asc->sc_flags &= ~ASC_DMAACTIVE; 365 366 if (asc->sc_dmasize == 0) { 367 /* A "Transfer Pad" operation completed */ 368 tcl = NCR_READ_REG(sc, NCR_TCL); 369 tcm = NCR_READ_REG(sc, NCR_TCM); 370 NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 371 tcl | (tcm << 8), tcl, tcm)); 372 return 0; 373 } 374 375 resid = 0; 376 if ((asc->sc_flags & ASC_ISPULLUP) == 0 && 377 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 378 NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid)); 379 DELAY(1); 380 } 381 382 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 383 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 384 385 trans = asc->sc_dmasize - resid; 386 if (trans < 0) { /* transferred < 0 ? */ 387 printf("tcds_dma %d: xfer (%d) > req (%d)\n", 388 tcds->sc_slot, trans, (int)asc->sc_dmasize); 389 trans = asc->sc_dmasize; 390 } 391 392 NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 393 tcl, tcm, trans, resid)); 394 395 *asc->sc_dmalen -= trans; 396 *asc->sc_dmaaddr += trans; 397 398 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 399 0, asc->sc_dmamap->dm_mapsize, 400 (sc->sc_flags & ASC_ISPULLUP) ? 401 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 402 403 /* 404 * Clean up unaligned DMAs into main memory. 405 */ 406 if (asc->sc_flags & ASC_ISPULLUP) { 407 /* Handle unaligned starting address, length. */ 408 dud = bus_space_read_4(tcds->sc_bst, 409 tcds->sc_bsh, tcds->sc_dud0); 410 if ((dud & TCDS_DUD0_VALIDBITS) != 0) { 411 addr = (uint32_t *)((paddr_t)*asc->sc_dmaaddr & ~0x3); 412 dudmask = 0; 413 if (dud & TCDS_DUD0_VALID00) 414 panic("%s: dud0 byte 0 valid", __func__); 415 if (dud & TCDS_DUD0_VALID01) 416 dudmask |= TCDS_DUD_BYTE01; 417 if (dud & TCDS_DUD0_VALID10) 418 dudmask |= TCDS_DUD_BYTE10; 419 #ifdef DIAGNOSTIC 420 if (dud & TCDS_DUD0_VALID11) 421 dudmask |= TCDS_DUD_BYTE11; 422 #endif 423 NCR_DMA(("dud0 at %p dudmask 0x%x\n", 424 addr, dudmask)); 425 *addr = (*addr & ~dudmask) | (dud & dudmask); 426 } 427 dud = bus_space_read_4(tcds->sc_bst, 428 tcds->sc_bsh, tcds->sc_dud1); 429 if ((dud & TCDS_DUD1_VALIDBITS) != 0) { 430 pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, 431 tcds->sc_sda) << 2; 432 dudmask = 0; 433 if (dud & TCDS_DUD1_VALID00) 434 dudmask |= TCDS_DUD_BYTE00; 435 if (dud & TCDS_DUD1_VALID01) 436 dudmask |= TCDS_DUD_BYTE01; 437 if (dud & TCDS_DUD1_VALID10) 438 dudmask |= TCDS_DUD_BYTE10; 439 #ifdef DIAGNOSTIC 440 if (dud & TCDS_DUD1_VALID11) 441 panic("%s: dud1 byte 3 valid", __func__); 442 #endif 443 NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n", 444 pa, dudmask)); 445 /* XXX Fix TC_PHYS_TO_UNCACHED() */ 446 #if defined(__alpha__) 447 addr = (uint32_t *)ALPHA_PHYS_TO_K0SEG(pa); 448 #elif defined(__mips__) 449 addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(pa); 450 #elif defined(__vax__) 451 addr = (uint32_t *)VAX_PHYS_TO_S0(pa); 452 #else 453 #error TURBOchannel only exists on DECs, folks... 454 #endif 455 *addr = (*addr & ~dudmask) | (dud & dudmask); 456 } 457 /* XXX deal with saved residual byte? */ 458 } 459 460 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 461 asc->sc_flags &= ~ASC_MAPLOADED; 462 463 return 0; 464 } 465 466 /* 467 * Glue functions. 468 */ 469 static uint8_t 470 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 471 { 472 struct asc_softc *asc = (struct asc_softc *)sc; 473 uint32_t v; 474 475 v = bus_space_read_4(asc->sc_bst, asc->sc_scsi_bsh, 476 reg * sizeof(uint32_t)); 477 478 return v & 0xff; 479 } 480 481 static void 482 asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 483 { 484 struct asc_softc *asc = (struct asc_softc *)sc; 485 486 bus_space_write_4(asc->sc_bst, asc->sc_scsi_bsh, 487 reg * sizeof(uint32_t), val); 488 } 489 490 static int 491 tcds_dma_isintr(struct ncr53c9x_softc *sc) 492 { 493 struct asc_softc *asc = (struct asc_softc *)sc; 494 int x; 495 496 x = tcds_scsi_isintr(asc->sc_tcds, 1); 497 498 /* XXX */ 499 return x; 500 } 501 502 static int 503 tcds_dma_isactive(struct ncr53c9x_softc *sc) 504 { 505 struct asc_softc *asc = (struct asc_softc *)sc; 506 507 return (asc->sc_flags & ASC_DMAACTIVE) != 0; 508 } 509 510 static void 511 tcds_clear_latched_intr(struct ncr53c9x_softc *sc) 512 { 513 struct asc_softc *asc = (struct asc_softc *)sc; 514 515 /* Clear the TCDS interrupt bit. */ 516 (void)tcds_scsi_isintr(asc->sc_tcds, 1); 517 } 518
Indexes created Tue Sep 30 07:10:03 GMT 2025