asc_tcds.c revision 1.3
1 /* $NetBSD: asc_tcds.c,v 1.3 2001/07/19 16:43:44 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Peter Galbavy. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 70 71 __KERNEL_RCSID(0, "$NetBSD: asc_tcds.c,v 1.3 2001/07/19 16:43:44 thorpej Exp $"); 72 73 #include <sys/types.h> 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/buf.h> 78 79 #include <dev/scsipi/scsi_all.h> 80 #include <dev/scsipi/scsipi_all.h> 81 #include <dev/scsipi/scsiconf.h> 82 83 #include <dev/ic/ncr53c9xreg.h> 84 #include <dev/ic/ncr53c9xvar.h> 85 86 #include <machine/bus.h> 87 88 #include <dev/tc/tcvar.h> 89 #include <dev/tc/tcdsreg.h> 90 #include <dev/tc/tcdsvar.h> 91 92 struct asc_softc { 93 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 94 bus_space_tag_t sc_bst; /* bus space tag */ 95 bus_space_handle_t sc_scsi_bsh; /* ASC register handle */ 96 bus_dma_tag_t sc_dmat; /* bus dma tag */ 97 bus_dmamap_t sc_dmamap; /* bus dmamap */ 98 caddr_t *sc_dmaaddr; 99 size_t *sc_dmalen; 100 size_t sc_dmasize; 101 unsigned sc_flags; 102 #define ASC_ISPULLUP 0x01 103 #define ASC_DMAACTIVE 0x02 104 #define ASC_MAPLOADED 0x04 105 struct tcds_slotconfig *sc_tcds; /* DMA/slot info lives here */ 106 }; 107 108 static int asc_tcds_match __P((struct device *, struct cfdata *, void *)); 109 static void asc_tcds_attach __P((struct device *, struct device *, void *)); 110 111 /* Linkup to the rest of the kernel */ 112 struct cfattach asc_tcds_ca = { 113 sizeof(struct asc_softc), asc_tcds_match, asc_tcds_attach 114 }; 115 116 /* 117 * Functions and the switch for the MI code. 118 */ 119 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 120 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 121 static int tcds_dma_isintr __P((struct ncr53c9x_softc *)); 122 static void tcds_dma_reset __P((struct ncr53c9x_softc *)); 123 static int tcds_dma_intr __P((struct ncr53c9x_softc *)); 124 static int tcds_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 125 size_t *, int, size_t *)); 126 static void tcds_dma_go __P((struct ncr53c9x_softc *)); 127 static void tcds_dma_stop __P((struct ncr53c9x_softc *)); 128 static int tcds_dma_isactive __P((struct ncr53c9x_softc *)); 129 static void tcds_clear_latched_intr __P((struct ncr53c9x_softc *)); 130 131 static struct ncr53c9x_glue asc_tcds_glue = { 132 asc_read_reg, 133 asc_write_reg, 134 tcds_dma_isintr, 135 tcds_dma_reset, 136 tcds_dma_intr, 137 tcds_dma_setup, 138 tcds_dma_go, 139 tcds_dma_stop, 140 tcds_dma_isactive, 141 tcds_clear_latched_intr, 142 }; 143 144 static int 145 asc_tcds_match(parent, cf, aux) 146 struct device *parent; 147 struct cfdata *cf; 148 void *aux; 149 { 150 151 /* We always exist. */ 152 return 1; 153 } 154 155 #define DMAMAX(a) (NBPG - ((a) & (NBPG - 1))) 156 157 /* 158 * Attach this instance, and then all the sub-devices 159 */ 160 static void 161 asc_tcds_attach(parent, self, aux) 162 struct device *parent, *self; 163 void *aux; 164 { 165 struct tcdsdev_attach_args *tcdsdev = aux; 166 struct asc_softc *asc = (struct asc_softc *)self; 167 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 168 int error; 169 170 /* 171 * Set up glue for MI code early; we use some of it here. 172 */ 173 sc->sc_glue = &asc_tcds_glue; 174 175 asc->sc_bst = tcdsdev->tcdsda_bst; 176 asc->sc_scsi_bsh = tcdsdev->tcdsda_bsh; 177 asc->sc_tcds = tcdsdev->tcdsda_sc; 178 179 /* 180 * The TCDS ASIC cannot DMA across 8k boundaries, and this 181 * driver is written such that each DMA segment gets a new 182 * call to tcds_dma_setup(). Thus, the DMA map only needs 183 * to support 8k transfers. 184 */ 185 asc->sc_dmat = tcdsdev->tcdsda_dmat; 186 if ((error = bus_dmamap_create(asc->sc_dmat, NBPG, 1, NBPG, 187 NBPG, BUS_DMA_NOWAIT, &asc->sc_dmamap)) < 0) { 188 printf("failed to create dma map, error = %d\n", error); 189 } 190 191 sc->sc_id = tcdsdev->tcdsda_id; 192 sc->sc_freq = tcdsdev->tcdsda_freq; 193 194 /* gimme Mhz */ 195 sc->sc_freq /= 1000000; 196 197 tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc); 198 199 /* 200 * XXX More of this should be in ncr53c9x_attach(), but 201 * XXX should we really poke around the chip that much in 202 * XXX the MI code? Think about this more... 203 */ 204 205 /* 206 * Set up static configuration info. 207 */ 208 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 209 sc->sc_cfg2 = NCRCFG2_SCSI2; 210 sc->sc_cfg3 = NCRCFG3_CDB; 211 if (sc->sc_freq > 25) 212 sc->sc_cfg3 |= NCRF9XCFG3_FCLK; 213 sc->sc_rev = tcdsdev->tcdsda_variant; 214 if (tcdsdev->tcdsda_fast) { 215 sc->sc_features |= NCR_F_FASTSCSI; 216 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 217 } 218 219 /* 220 * XXX minsync and maxxfer _should_ be set up in MI code, 221 * XXX but it appears to have some dependency on what sort 222 * XXX of DMA we're hooked up to, etc. 223 */ 224 225 /* 226 * This is the value used to start sync negotiations 227 * Note that the NCR register "SYNCTP" is programmed 228 * in "clocks per byte", and has a minimum value of 4. 229 * The SCSI period used in negotiation is one-fourth 230 * of the time (in nanoseconds) needed to transfer one byte. 231 * Since the chip's clock is given in MHz, we have the following 232 * formula: 4 * period = (1000 / freq) * 4 233 */ 234 sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4; 235 236 sc->sc_maxxfer = 64 * 1024; 237 238 /* Do the common parts of attachment. */ 239 sc->sc_adapter.adapt_minphys = minphys; 240 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 241 ncr53c9x_attach(sc); 242 } 243 244 static void 245 tcds_dma_reset(sc) 246 struct ncr53c9x_softc *sc; 247 { 248 struct asc_softc *asc = (struct asc_softc *)sc; 249 250 /* TCDS SCSI disable/reset/enable. */ 251 tcds_scsi_reset(asc->sc_tcds); /* XXX */ 252 253 if (asc->sc_flags & ASC_MAPLOADED) 254 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 255 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 256 } 257 258 /* 259 * start a dma transfer or keep it going 260 */ 261 int 262 tcds_dma_setup(sc, addr, len, ispullup, dmasize) 263 struct ncr53c9x_softc *sc; 264 caddr_t *addr; 265 size_t *len, *dmasize; 266 int ispullup; /* DMA into main memory */ 267 { 268 struct asc_softc *asc = (struct asc_softc *)sc; 269 struct tcds_slotconfig *tcds = asc->sc_tcds; 270 size_t size; 271 u_int32_t dic; 272 273 NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot, 274 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, 275 (ispullup) ? "IN" : "OUT")); 276 277 /* 278 * the rules say we cannot transfer more than the limit 279 * of this DMA chip (64k) and we cannot cross a 8k boundary. 280 */ 281 size = min(*dmasize, DMAMAX((size_t)*addr)); 282 asc->sc_dmaaddr = addr; 283 asc->sc_dmalen = len; 284 asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 285 *dmasize = asc->sc_dmasize = size; 286 287 NCR_DMA(("dma_start: dmasize = %d\n", (int)size)); 288 289 if (size == 0) 290 return 0; 291 292 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, size, 293 NULL, BUS_DMA_NOWAIT | (ispullup ? BUS_DMA_READ : BUS_DMA_WRITE))) { 294 /* 295 * XXX Should return an error, here, but the upper-layer 296 * XXX doesn't check the return value! 297 */ 298 panic("tcds_dma_setup: dmamap load failed"); 299 } 300 301 /* synchronize dmamap contents with memory image */ 302 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 0, size, 303 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 304 305 /* load address, set/clear unaligned transfer and read/write bits. */ 306 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda, 307 asc->sc_dmamap->dm_segs[0].ds_addr >> 2); 308 dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic); 309 dic &= ~TCDS_DIC_ADDRMASK; 310 dic |= asc->sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK; 311 if (ispullup) 312 dic |= TCDS_DIC_WRITE; 313 else 314 dic &= ~TCDS_DIC_WRITE; 315 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic); 316 317 asc->sc_flags |= ASC_MAPLOADED; 318 return 0; 319 } 320 321 static void 322 tcds_dma_go(sc) 323 struct ncr53c9x_softc *sc; 324 { 325 struct asc_softc *asc = (struct asc_softc *)sc; 326 327 /* mark unit as DMA-active */ 328 asc->sc_flags |= ASC_DMAACTIVE; 329 330 /* start DMA */ 331 tcds_dma_enable(asc->sc_tcds, 1); 332 } 333 334 static void 335 tcds_dma_stop(sc) 336 struct ncr53c9x_softc *sc; 337 { 338 #if 0 339 struct asc_softc *asc = (struct asc_softc *)sc; 340 #endif 341 342 /* 343 * XXX STOP DMA HERE! 344 */ 345 } 346 347 /* 348 * Pseudo (chained) interrupt from the asc driver to kick the 349 * current running DMA transfer. Called from ncr53c9x_intr() 350 * for now. 351 * 352 * return 1 if it was a DMA continue. 353 */ 354 static int 355 tcds_dma_intr(sc) 356 struct ncr53c9x_softc *sc; 357 { 358 struct asc_softc *asc = (struct asc_softc *)sc; 359 struct tcds_slotconfig *tcds = asc->sc_tcds; 360 int trans, resid; 361 u_int32_t tcl, tcm; 362 u_int32_t dud, dudmask, *addr; 363 bus_addr_t pa; 364 365 NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot)); 366 367 if (tcds_scsi_iserr(tcds)) 368 return 0; 369 370 /* This is an "assertion" :) */ 371 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 372 panic("tcds_dma_intr: DMA wasn't active"); 373 374 /* DMA has stopped */ 375 tcds_dma_enable(tcds, 0); 376 asc->sc_flags &= ~ASC_DMAACTIVE; 377 378 if (asc->sc_dmasize == 0) { 379 /* A "Transfer Pad" operation completed */ 380 tcl = NCR_READ_REG(sc, NCR_TCL); 381 tcm = NCR_READ_REG(sc, NCR_TCM); 382 NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 383 tcl | (tcm << 8), tcl, tcm)); 384 return 0; 385 } 386 387 resid = 0; 388 if ((asc->sc_flags & ASC_ISPULLUP) == 0 && 389 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 390 NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid)); 391 DELAY(1); 392 } 393 394 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 395 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 396 397 trans = asc->sc_dmasize - resid; 398 if (trans < 0) { /* transferred < 0 ? */ 399 printf("tcds_dma %d: xfer (%d) > req (%d)\n", 400 tcds->sc_slot, trans, (int)asc->sc_dmasize); 401 trans = asc->sc_dmasize; 402 } 403 404 NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 405 tcl, tcm, trans, resid)); 406 407 *asc->sc_dmalen -= trans; 408 *asc->sc_dmaaddr += trans; 409 410 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 411 0, asc->sc_dmamap->dm_mapsize, 412 (sc->sc_flags & ASC_ISPULLUP) 413 ? BUS_DMASYNC_POSTREAD 414 : BUS_DMASYNC_POSTWRITE); 415 416 /* 417 * Clean up unaligned DMAs into main memory. 418 */ 419 if (asc->sc_flags & ASC_ISPULLUP) { 420 /* Handle unaligned starting address, length. */ 421 dud = bus_space_read_4(tcds->sc_bst, 422 tcds->sc_bsh, tcds->sc_dud0); 423 if ((dud & TCDS_DUD0_VALIDBITS) != 0) { 424 addr = (u_int32_t *) 425 ((paddr_t)*asc->sc_dmaaddr & ~0x3); 426 dudmask = 0; 427 if (dud & TCDS_DUD0_VALID00) 428 panic("tcds_dma: dud0 byte 0 valid"); 429 if (dud & TCDS_DUD0_VALID01) 430 dudmask |= TCDS_DUD_BYTE01; 431 if (dud & TCDS_DUD0_VALID10) 432 dudmask |= TCDS_DUD_BYTE10; 433 #ifdef DIAGNOSTIC 434 if (dud & TCDS_DUD0_VALID11) 435 dudmask |= TCDS_DUD_BYTE11; 436 #endif 437 NCR_DMA(("dud0 at 0x%p dudmask 0x%x\n", 438 addr, dudmask)); 439 *addr = (*addr & ~dudmask) | (dud & dudmask); 440 } 441 dud = bus_space_read_4(tcds->sc_bst, 442 tcds->sc_bsh, tcds->sc_dud1); 443 if ((dud & TCDS_DUD1_VALIDBITS) != 0) { 444 pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, 445 tcds->sc_sda) << 2; 446 dudmask = 0; 447 if (dud & TCDS_DUD1_VALID00) 448 dudmask |= TCDS_DUD_BYTE00; 449 if (dud & TCDS_DUD1_VALID01) 450 dudmask |= TCDS_DUD_BYTE01; 451 if (dud & TCDS_DUD1_VALID10) 452 dudmask |= TCDS_DUD_BYTE10; 453 #ifdef DIAGNOSTIC 454 if (dud & TCDS_DUD1_VALID11) 455 panic("tcds_dma: dud1 byte 3 valid"); 456 #endif 457 NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n", 458 pa, dudmask)); 459 /* XXX Fix TC_PHYS_TO_UNCACHED() */ 460 #if defined(__alpha__) 461 addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG(pa); 462 #elif defined(__mips__) 463 addr = (u_int32_t *)MIPS_PHYS_TO_KSEG1(pa); 464 #else 465 #error TURBOchannel only exists on DECs, folks... 466 #endif 467 *addr = (*addr & ~dudmask) | (dud & dudmask); 468 } 469 /* XXX deal with saved residual byte? */ 470 } 471 472 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 473 asc->sc_flags &= ~ASC_MAPLOADED; 474 475 return 0; 476 } 477 478 /* 479 * Glue functions. 480 */ 481 static u_char 482 asc_read_reg(sc, reg) 483 struct ncr53c9x_softc *sc; 484 int reg; 485 { 486 struct asc_softc *asc = (struct asc_softc *)sc; 487 u_int32_t v; 488 489 v = bus_space_read_4(asc->sc_bst, asc->sc_scsi_bsh, 490 reg * sizeof(u_int32_t)); 491 492 return v & 0xff; 493 } 494 495 static void 496 asc_write_reg(sc, reg, val) 497 struct ncr53c9x_softc *sc; 498 int reg; 499 u_char val; 500 { 501 struct asc_softc *asc = (struct asc_softc *)sc; 502 503 bus_space_write_4(asc->sc_bst, asc->sc_scsi_bsh, 504 reg * sizeof(u_int32_t), val); 505 } 506 507 static int 508 tcds_dma_isintr(sc) 509 struct ncr53c9x_softc *sc; 510 { 511 struct asc_softc *asc = (struct asc_softc *)sc; 512 int x; 513 514 x = tcds_scsi_isintr(asc->sc_tcds, 1); 515 516 /* XXX */ 517 return x; 518 } 519 520 static int 521 tcds_dma_isactive(sc) 522 struct ncr53c9x_softc *sc; 523 { 524 struct asc_softc *asc = (struct asc_softc *)sc; 525 526 return !!(asc->sc_flags & ASC_DMAACTIVE); 527 } 528 529 static void 530 tcds_clear_latched_intr(sc) 531 struct ncr53c9x_softc *sc; 532 { 533 struct asc_softc *asc = (struct asc_softc *)sc; 534 535 /* Clear the TCDS interrupt bit. */ 536 (void)tcds_scsi_isintr(asc->sc_tcds, 1); 537 } 538
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