asc_tcds.c revision 1.4
1 /* $NetBSD: asc_tcds.c,v 1.4 2001/11/13 06:26:09 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Peter Galbavy. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: asc_tcds.c,v 1.4 2001/11/13 06:26:09 lukem Exp $"); 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/device.h> 76 #include <sys/buf.h> 77 78 #include <dev/scsipi/scsi_all.h> 79 #include <dev/scsipi/scsipi_all.h> 80 #include <dev/scsipi/scsiconf.h> 81 82 #include <dev/ic/ncr53c9xreg.h> 83 #include <dev/ic/ncr53c9xvar.h> 84 85 #include <machine/bus.h> 86 87 #include <dev/tc/tcvar.h> 88 #include <dev/tc/tcdsreg.h> 89 #include <dev/tc/tcdsvar.h> 90 91 struct asc_softc { 92 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 93 bus_space_tag_t sc_bst; /* bus space tag */ 94 bus_space_handle_t sc_scsi_bsh; /* ASC register handle */ 95 bus_dma_tag_t sc_dmat; /* bus dma tag */ 96 bus_dmamap_t sc_dmamap; /* bus dmamap */ 97 caddr_t *sc_dmaaddr; 98 size_t *sc_dmalen; 99 size_t sc_dmasize; 100 unsigned sc_flags; 101 #define ASC_ISPULLUP 0x01 102 #define ASC_DMAACTIVE 0x02 103 #define ASC_MAPLOADED 0x04 104 struct tcds_slotconfig *sc_tcds; /* DMA/slot info lives here */ 105 }; 106 107 static int asc_tcds_match __P((struct device *, struct cfdata *, void *)); 108 static void asc_tcds_attach __P((struct device *, struct device *, void *)); 109 110 /* Linkup to the rest of the kernel */ 111 struct cfattach asc_tcds_ca = { 112 sizeof(struct asc_softc), asc_tcds_match, asc_tcds_attach 113 }; 114 115 /* 116 * Functions and the switch for the MI code. 117 */ 118 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 119 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 120 static int tcds_dma_isintr __P((struct ncr53c9x_softc *)); 121 static void tcds_dma_reset __P((struct ncr53c9x_softc *)); 122 static int tcds_dma_intr __P((struct ncr53c9x_softc *)); 123 static int tcds_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 124 size_t *, int, size_t *)); 125 static void tcds_dma_go __P((struct ncr53c9x_softc *)); 126 static void tcds_dma_stop __P((struct ncr53c9x_softc *)); 127 static int tcds_dma_isactive __P((struct ncr53c9x_softc *)); 128 static void tcds_clear_latched_intr __P((struct ncr53c9x_softc *)); 129 130 static struct ncr53c9x_glue asc_tcds_glue = { 131 asc_read_reg, 132 asc_write_reg, 133 tcds_dma_isintr, 134 tcds_dma_reset, 135 tcds_dma_intr, 136 tcds_dma_setup, 137 tcds_dma_go, 138 tcds_dma_stop, 139 tcds_dma_isactive, 140 tcds_clear_latched_intr, 141 }; 142 143 static int 144 asc_tcds_match(parent, cf, aux) 145 struct device *parent; 146 struct cfdata *cf; 147 void *aux; 148 { 149 150 /* We always exist. */ 151 return 1; 152 } 153 154 #define DMAMAX(a) (NBPG - ((a) & (NBPG - 1))) 155 156 /* 157 * Attach this instance, and then all the sub-devices 158 */ 159 static void 160 asc_tcds_attach(parent, self, aux) 161 struct device *parent, *self; 162 void *aux; 163 { 164 struct tcdsdev_attach_args *tcdsdev = aux; 165 struct asc_softc *asc = (struct asc_softc *)self; 166 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 167 int error; 168 169 /* 170 * Set up glue for MI code early; we use some of it here. 171 */ 172 sc->sc_glue = &asc_tcds_glue; 173 174 asc->sc_bst = tcdsdev->tcdsda_bst; 175 asc->sc_scsi_bsh = tcdsdev->tcdsda_bsh; 176 asc->sc_tcds = tcdsdev->tcdsda_sc; 177 178 /* 179 * The TCDS ASIC cannot DMA across 8k boundaries, and this 180 * driver is written such that each DMA segment gets a new 181 * call to tcds_dma_setup(). Thus, the DMA map only needs 182 * to support 8k transfers. 183 */ 184 asc->sc_dmat = tcdsdev->tcdsda_dmat; 185 if ((error = bus_dmamap_create(asc->sc_dmat, NBPG, 1, NBPG, 186 NBPG, BUS_DMA_NOWAIT, &asc->sc_dmamap)) < 0) { 187 printf("failed to create dma map, error = %d\n", error); 188 } 189 190 sc->sc_id = tcdsdev->tcdsda_id; 191 sc->sc_freq = tcdsdev->tcdsda_freq; 192 193 /* gimme Mhz */ 194 sc->sc_freq /= 1000000; 195 196 tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc); 197 198 /* 199 * XXX More of this should be in ncr53c9x_attach(), but 200 * XXX should we really poke around the chip that much in 201 * XXX the MI code? Think about this more... 202 */ 203 204 /* 205 * Set up static configuration info. 206 */ 207 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 208 sc->sc_cfg2 = NCRCFG2_SCSI2; 209 sc->sc_cfg3 = NCRCFG3_CDB; 210 if (sc->sc_freq > 25) 211 sc->sc_cfg3 |= NCRF9XCFG3_FCLK; 212 sc->sc_rev = tcdsdev->tcdsda_variant; 213 if (tcdsdev->tcdsda_fast) { 214 sc->sc_features |= NCR_F_FASTSCSI; 215 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 216 } 217 218 /* 219 * XXX minsync and maxxfer _should_ be set up in MI code, 220 * XXX but it appears to have some dependency on what sort 221 * XXX of DMA we're hooked up to, etc. 222 */ 223 224 /* 225 * This is the value used to start sync negotiations 226 * Note that the NCR register "SYNCTP" is programmed 227 * in "clocks per byte", and has a minimum value of 4. 228 * The SCSI period used in negotiation is one-fourth 229 * of the time (in nanoseconds) needed to transfer one byte. 230 * Since the chip's clock is given in MHz, we have the following 231 * formula: 4 * period = (1000 / freq) * 4 232 */ 233 sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4; 234 235 sc->sc_maxxfer = 64 * 1024; 236 237 /* Do the common parts of attachment. */ 238 sc->sc_adapter.adapt_minphys = minphys; 239 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 240 ncr53c9x_attach(sc); 241 } 242 243 static void 244 tcds_dma_reset(sc) 245 struct ncr53c9x_softc *sc; 246 { 247 struct asc_softc *asc = (struct asc_softc *)sc; 248 249 /* TCDS SCSI disable/reset/enable. */ 250 tcds_scsi_reset(asc->sc_tcds); /* XXX */ 251 252 if (asc->sc_flags & ASC_MAPLOADED) 253 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 254 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 255 } 256 257 /* 258 * start a dma transfer or keep it going 259 */ 260 int 261 tcds_dma_setup(sc, addr, len, ispullup, dmasize) 262 struct ncr53c9x_softc *sc; 263 caddr_t *addr; 264 size_t *len, *dmasize; 265 int ispullup; /* DMA into main memory */ 266 { 267 struct asc_softc *asc = (struct asc_softc *)sc; 268 struct tcds_slotconfig *tcds = asc->sc_tcds; 269 size_t size; 270 u_int32_t dic; 271 272 NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot, 273 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, 274 (ispullup) ? "IN" : "OUT")); 275 276 /* 277 * the rules say we cannot transfer more than the limit 278 * of this DMA chip (64k) and we cannot cross a 8k boundary. 279 */ 280 size = min(*dmasize, DMAMAX((size_t)*addr)); 281 asc->sc_dmaaddr = addr; 282 asc->sc_dmalen = len; 283 asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 284 *dmasize = asc->sc_dmasize = size; 285 286 NCR_DMA(("dma_start: dmasize = %d\n", (int)size)); 287 288 if (size == 0) 289 return 0; 290 291 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, size, 292 NULL, BUS_DMA_NOWAIT | (ispullup ? BUS_DMA_READ : BUS_DMA_WRITE))) { 293 /* 294 * XXX Should return an error, here, but the upper-layer 295 * XXX doesn't check the return value! 296 */ 297 panic("tcds_dma_setup: dmamap load failed"); 298 } 299 300 /* synchronize dmamap contents with memory image */ 301 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 0, size, 302 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 303 304 /* load address, set/clear unaligned transfer and read/write bits. */ 305 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda, 306 asc->sc_dmamap->dm_segs[0].ds_addr >> 2); 307 dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic); 308 dic &= ~TCDS_DIC_ADDRMASK; 309 dic |= asc->sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK; 310 if (ispullup) 311 dic |= TCDS_DIC_WRITE; 312 else 313 dic &= ~TCDS_DIC_WRITE; 314 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic); 315 316 asc->sc_flags |= ASC_MAPLOADED; 317 return 0; 318 } 319 320 static void 321 tcds_dma_go(sc) 322 struct ncr53c9x_softc *sc; 323 { 324 struct asc_softc *asc = (struct asc_softc *)sc; 325 326 /* mark unit as DMA-active */ 327 asc->sc_flags |= ASC_DMAACTIVE; 328 329 /* start DMA */ 330 tcds_dma_enable(asc->sc_tcds, 1); 331 } 332 333 static void 334 tcds_dma_stop(sc) 335 struct ncr53c9x_softc *sc; 336 { 337 #if 0 338 struct asc_softc *asc = (struct asc_softc *)sc; 339 #endif 340 341 /* 342 * XXX STOP DMA HERE! 343 */ 344 } 345 346 /* 347 * Pseudo (chained) interrupt from the asc driver to kick the 348 * current running DMA transfer. Called from ncr53c9x_intr() 349 * for now. 350 * 351 * return 1 if it was a DMA continue. 352 */ 353 static int 354 tcds_dma_intr(sc) 355 struct ncr53c9x_softc *sc; 356 { 357 struct asc_softc *asc = (struct asc_softc *)sc; 358 struct tcds_slotconfig *tcds = asc->sc_tcds; 359 int trans, resid; 360 u_int32_t tcl, tcm; 361 u_int32_t dud, dudmask, *addr; 362 bus_addr_t pa; 363 364 NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot)); 365 366 if (tcds_scsi_iserr(tcds)) 367 return 0; 368 369 /* This is an "assertion" :) */ 370 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 371 panic("tcds_dma_intr: DMA wasn't active"); 372 373 /* DMA has stopped */ 374 tcds_dma_enable(tcds, 0); 375 asc->sc_flags &= ~ASC_DMAACTIVE; 376 377 if (asc->sc_dmasize == 0) { 378 /* A "Transfer Pad" operation completed */ 379 tcl = NCR_READ_REG(sc, NCR_TCL); 380 tcm = NCR_READ_REG(sc, NCR_TCM); 381 NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 382 tcl | (tcm << 8), tcl, tcm)); 383 return 0; 384 } 385 386 resid = 0; 387 if ((asc->sc_flags & ASC_ISPULLUP) == 0 && 388 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 389 NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid)); 390 DELAY(1); 391 } 392 393 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 394 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 395 396 trans = asc->sc_dmasize - resid; 397 if (trans < 0) { /* transferred < 0 ? */ 398 printf("tcds_dma %d: xfer (%d) > req (%d)\n", 399 tcds->sc_slot, trans, (int)asc->sc_dmasize); 400 trans = asc->sc_dmasize; 401 } 402 403 NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 404 tcl, tcm, trans, resid)); 405 406 *asc->sc_dmalen -= trans; 407 *asc->sc_dmaaddr += trans; 408 409 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 410 0, asc->sc_dmamap->dm_mapsize, 411 (sc->sc_flags & ASC_ISPULLUP) 412 ? BUS_DMASYNC_POSTREAD 413 : BUS_DMASYNC_POSTWRITE); 414 415 /* 416 * Clean up unaligned DMAs into main memory. 417 */ 418 if (asc->sc_flags & ASC_ISPULLUP) { 419 /* Handle unaligned starting address, length. */ 420 dud = bus_space_read_4(tcds->sc_bst, 421 tcds->sc_bsh, tcds->sc_dud0); 422 if ((dud & TCDS_DUD0_VALIDBITS) != 0) { 423 addr = (u_int32_t *) 424 ((paddr_t)*asc->sc_dmaaddr & ~0x3); 425 dudmask = 0; 426 if (dud & TCDS_DUD0_VALID00) 427 panic("tcds_dma: dud0 byte 0 valid"); 428 if (dud & TCDS_DUD0_VALID01) 429 dudmask |= TCDS_DUD_BYTE01; 430 if (dud & TCDS_DUD0_VALID10) 431 dudmask |= TCDS_DUD_BYTE10; 432 #ifdef DIAGNOSTIC 433 if (dud & TCDS_DUD0_VALID11) 434 dudmask |= TCDS_DUD_BYTE11; 435 #endif 436 NCR_DMA(("dud0 at 0x%p dudmask 0x%x\n", 437 addr, dudmask)); 438 *addr = (*addr & ~dudmask) | (dud & dudmask); 439 } 440 dud = bus_space_read_4(tcds->sc_bst, 441 tcds->sc_bsh, tcds->sc_dud1); 442 if ((dud & TCDS_DUD1_VALIDBITS) != 0) { 443 pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, 444 tcds->sc_sda) << 2; 445 dudmask = 0; 446 if (dud & TCDS_DUD1_VALID00) 447 dudmask |= TCDS_DUD_BYTE00; 448 if (dud & TCDS_DUD1_VALID01) 449 dudmask |= TCDS_DUD_BYTE01; 450 if (dud & TCDS_DUD1_VALID10) 451 dudmask |= TCDS_DUD_BYTE10; 452 #ifdef DIAGNOSTIC 453 if (dud & TCDS_DUD1_VALID11) 454 panic("tcds_dma: dud1 byte 3 valid"); 455 #endif 456 NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n", 457 pa, dudmask)); 458 /* XXX Fix TC_PHYS_TO_UNCACHED() */ 459 #if defined(__alpha__) 460 addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG(pa); 461 #elif defined(__mips__) 462 addr = (u_int32_t *)MIPS_PHYS_TO_KSEG1(pa); 463 #else 464 #error TURBOchannel only exists on DECs, folks... 465 #endif 466 *addr = (*addr & ~dudmask) | (dud & dudmask); 467 } 468 /* XXX deal with saved residual byte? */ 469 } 470 471 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 472 asc->sc_flags &= ~ASC_MAPLOADED; 473 474 return 0; 475 } 476 477 /* 478 * Glue functions. 479 */ 480 static u_char 481 asc_read_reg(sc, reg) 482 struct ncr53c9x_softc *sc; 483 int reg; 484 { 485 struct asc_softc *asc = (struct asc_softc *)sc; 486 u_int32_t v; 487 488 v = bus_space_read_4(asc->sc_bst, asc->sc_scsi_bsh, 489 reg * sizeof(u_int32_t)); 490 491 return v & 0xff; 492 } 493 494 static void 495 asc_write_reg(sc, reg, val) 496 struct ncr53c9x_softc *sc; 497 int reg; 498 u_char val; 499 { 500 struct asc_softc *asc = (struct asc_softc *)sc; 501 502 bus_space_write_4(asc->sc_bst, asc->sc_scsi_bsh, 503 reg * sizeof(u_int32_t), val); 504 } 505 506 static int 507 tcds_dma_isintr(sc) 508 struct ncr53c9x_softc *sc; 509 { 510 struct asc_softc *asc = (struct asc_softc *)sc; 511 int x; 512 513 x = tcds_scsi_isintr(asc->sc_tcds, 1); 514 515 /* XXX */ 516 return x; 517 } 518 519 static int 520 tcds_dma_isactive(sc) 521 struct ncr53c9x_softc *sc; 522 { 523 struct asc_softc *asc = (struct asc_softc *)sc; 524 525 return !!(asc->sc_flags & ASC_DMAACTIVE); 526 } 527 528 static void 529 tcds_clear_latched_intr(sc) 530 struct ncr53c9x_softc *sc; 531 { 532 struct asc_softc *asc = (struct asc_softc *)sc; 533 534 /* Clear the TCDS interrupt bit. */ 535 (void)tcds_scsi_isintr(asc->sc_tcds, 1); 536 } 537
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