asc_tcds.c revision 1.8
1 /* $NetBSD: asc_tcds.c,v 1.8 2002/10/02 16:53:01 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Peter Galbavy. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: asc_tcds.c,v 1.8 2002/10/02 16:53:01 thorpej Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/device.h> 75 #include <sys/buf.h> 76 77 #include <dev/scsipi/scsi_all.h> 78 #include <dev/scsipi/scsipi_all.h> 79 #include <dev/scsipi/scsiconf.h> 80 81 #include <dev/ic/ncr53c9xreg.h> 82 #include <dev/ic/ncr53c9xvar.h> 83 84 #include <machine/bus.h> 85 86 #include <dev/tc/tcvar.h> 87 #include <dev/tc/tcdsreg.h> 88 #include <dev/tc/tcdsvar.h> 89 90 struct asc_softc { 91 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 92 bus_space_tag_t sc_bst; /* bus space tag */ 93 bus_space_handle_t sc_scsi_bsh; /* ASC register handle */ 94 bus_dma_tag_t sc_dmat; /* bus dma tag */ 95 bus_dmamap_t sc_dmamap; /* bus dmamap */ 96 caddr_t *sc_dmaaddr; 97 size_t *sc_dmalen; 98 size_t sc_dmasize; 99 unsigned sc_flags; 100 #define ASC_ISPULLUP 0x01 101 #define ASC_DMAACTIVE 0x02 102 #define ASC_MAPLOADED 0x04 103 struct tcds_slotconfig *sc_tcds; /* DMA/slot info lives here */ 104 }; 105 106 static int asc_tcds_match __P((struct device *, struct cfdata *, void *)); 107 static void asc_tcds_attach __P((struct device *, struct device *, void *)); 108 109 CFATTACH_DECL(asc_tcds, sizeof(struct asc_softc), 110 asc_tcds_match, asc_tcds_attach, NULL, NULL); 111 112 /* 113 * Functions and the switch for the MI code. 114 */ 115 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 116 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 117 static int tcds_dma_isintr __P((struct ncr53c9x_softc *)); 118 static void tcds_dma_reset __P((struct ncr53c9x_softc *)); 119 static int tcds_dma_intr __P((struct ncr53c9x_softc *)); 120 static int tcds_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 121 size_t *, int, size_t *)); 122 static void tcds_dma_go __P((struct ncr53c9x_softc *)); 123 static void tcds_dma_stop __P((struct ncr53c9x_softc *)); 124 static int tcds_dma_isactive __P((struct ncr53c9x_softc *)); 125 static void tcds_clear_latched_intr __P((struct ncr53c9x_softc *)); 126 127 static struct ncr53c9x_glue asc_tcds_glue = { 128 asc_read_reg, 129 asc_write_reg, 130 tcds_dma_isintr, 131 tcds_dma_reset, 132 tcds_dma_intr, 133 tcds_dma_setup, 134 tcds_dma_go, 135 tcds_dma_stop, 136 tcds_dma_isactive, 137 tcds_clear_latched_intr, 138 }; 139 140 static int 141 asc_tcds_match(parent, cf, aux) 142 struct device *parent; 143 struct cfdata *cf; 144 void *aux; 145 { 146 147 /* We always exist. */ 148 return 1; 149 } 150 151 #define DMAMAX(a) (NBPG - ((a) & (NBPG - 1))) 152 153 /* 154 * Attach this instance, and then all the sub-devices 155 */ 156 static void 157 asc_tcds_attach(parent, self, aux) 158 struct device *parent, *self; 159 void *aux; 160 { 161 struct tcdsdev_attach_args *tcdsdev = aux; 162 struct asc_softc *asc = (struct asc_softc *)self; 163 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 164 int error; 165 166 /* 167 * Set up glue for MI code early; we use some of it here. 168 */ 169 sc->sc_glue = &asc_tcds_glue; 170 171 asc->sc_bst = tcdsdev->tcdsda_bst; 172 asc->sc_scsi_bsh = tcdsdev->tcdsda_bsh; 173 asc->sc_tcds = tcdsdev->tcdsda_sc; 174 175 /* 176 * The TCDS ASIC cannot DMA across 8k boundaries, and this 177 * driver is written such that each DMA segment gets a new 178 * call to tcds_dma_setup(). Thus, the DMA map only needs 179 * to support 8k transfers. 180 */ 181 asc->sc_dmat = tcdsdev->tcdsda_dmat; 182 if ((error = bus_dmamap_create(asc->sc_dmat, NBPG, 1, NBPG, 183 NBPG, BUS_DMA_NOWAIT, &asc->sc_dmamap)) < 0) { 184 printf("failed to create dma map, error = %d\n", error); 185 } 186 187 sc->sc_id = tcdsdev->tcdsda_id; 188 sc->sc_freq = tcdsdev->tcdsda_freq; 189 190 /* gimme Mhz */ 191 sc->sc_freq /= 1000000; 192 193 tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc); 194 195 /* 196 * XXX More of this should be in ncr53c9x_attach(), but 197 * XXX should we really poke around the chip that much in 198 * XXX the MI code? Think about this more... 199 */ 200 201 /* 202 * Set up static configuration info. 203 */ 204 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 205 sc->sc_cfg2 = NCRCFG2_SCSI2; 206 sc->sc_cfg3 = NCRCFG3_CDB; 207 if (sc->sc_freq > 25) 208 sc->sc_cfg3 |= NCRF9XCFG3_FCLK; 209 sc->sc_rev = tcdsdev->tcdsda_variant; 210 if (tcdsdev->tcdsda_fast) { 211 sc->sc_features |= NCR_F_FASTSCSI; 212 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 213 } 214 215 /* 216 * XXX minsync and maxxfer _should_ be set up in MI code, 217 * XXX but it appears to have some dependency on what sort 218 * XXX of DMA we're hooked up to, etc. 219 */ 220 221 /* 222 * This is the value used to start sync negotiations 223 * Note that the NCR register "SYNCTP" is programmed 224 * in "clocks per byte", and has a minimum value of 4. 225 * The SCSI period used in negotiation is one-fourth 226 * of the time (in nanoseconds) needed to transfer one byte. 227 * Since the chip's clock is given in MHz, we have the following 228 * formula: 4 * period = (1000 / freq) * 4 229 */ 230 sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4; 231 232 sc->sc_maxxfer = 64 * 1024; 233 234 /* Do the common parts of attachment. */ 235 sc->sc_adapter.adapt_minphys = minphys; 236 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 237 ncr53c9x_attach(sc); 238 } 239 240 static void 241 tcds_dma_reset(sc) 242 struct ncr53c9x_softc *sc; 243 { 244 struct asc_softc *asc = (struct asc_softc *)sc; 245 246 /* TCDS SCSI disable/reset/enable. */ 247 tcds_scsi_reset(asc->sc_tcds); /* XXX */ 248 249 if (asc->sc_flags & ASC_MAPLOADED) 250 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 251 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 252 } 253 254 /* 255 * start a dma transfer or keep it going 256 */ 257 int 258 tcds_dma_setup(sc, addr, len, ispullup, dmasize) 259 struct ncr53c9x_softc *sc; 260 caddr_t *addr; 261 size_t *len, *dmasize; 262 int ispullup; /* DMA into main memory */ 263 { 264 struct asc_softc *asc = (struct asc_softc *)sc; 265 struct tcds_slotconfig *tcds = asc->sc_tcds; 266 size_t size; 267 u_int32_t dic; 268 269 NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot, 270 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, 271 (ispullup) ? "IN" : "OUT")); 272 273 /* 274 * the rules say we cannot transfer more than the limit 275 * of this DMA chip (64k) and we cannot cross a 8k boundary. 276 */ 277 size = min(*dmasize, DMAMAX((size_t)*addr)); 278 asc->sc_dmaaddr = addr; 279 asc->sc_dmalen = len; 280 asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 281 *dmasize = asc->sc_dmasize = size; 282 283 NCR_DMA(("dma_start: dmasize = %d\n", (int)size)); 284 285 if (size == 0) 286 return 0; 287 288 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, size, 289 NULL, BUS_DMA_NOWAIT | (ispullup ? BUS_DMA_READ : BUS_DMA_WRITE))) { 290 /* 291 * XXX Should return an error, here, but the upper-layer 292 * XXX doesn't check the return value! 293 */ 294 panic("tcds_dma_setup: dmamap load failed"); 295 } 296 297 /* synchronize dmamap contents with memory image */ 298 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 0, size, 299 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 300 301 /* load address, set/clear unaligned transfer and read/write bits. */ 302 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda, 303 asc->sc_dmamap->dm_segs[0].ds_addr >> 2); 304 dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic); 305 dic &= ~TCDS_DIC_ADDRMASK; 306 dic |= asc->sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK; 307 if (ispullup) 308 dic |= TCDS_DIC_WRITE; 309 else 310 dic &= ~TCDS_DIC_WRITE; 311 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic); 312 313 asc->sc_flags |= ASC_MAPLOADED; 314 return 0; 315 } 316 317 static void 318 tcds_dma_go(sc) 319 struct ncr53c9x_softc *sc; 320 { 321 struct asc_softc *asc = (struct asc_softc *)sc; 322 323 /* mark unit as DMA-active */ 324 asc->sc_flags |= ASC_DMAACTIVE; 325 326 /* start DMA */ 327 tcds_dma_enable(asc->sc_tcds, 1); 328 } 329 330 static void 331 tcds_dma_stop(sc) 332 struct ncr53c9x_softc *sc; 333 { 334 #if 0 335 struct asc_softc *asc = (struct asc_softc *)sc; 336 #endif 337 338 /* 339 * XXX STOP DMA HERE! 340 */ 341 } 342 343 /* 344 * Pseudo (chained) interrupt from the asc driver to kick the 345 * current running DMA transfer. Called from ncr53c9x_intr() 346 * for now. 347 * 348 * return 1 if it was a DMA continue. 349 */ 350 static int 351 tcds_dma_intr(sc) 352 struct ncr53c9x_softc *sc; 353 { 354 struct asc_softc *asc = (struct asc_softc *)sc; 355 struct tcds_slotconfig *tcds = asc->sc_tcds; 356 int trans, resid; 357 u_int32_t tcl, tcm; 358 u_int32_t dud, dudmask, *addr; 359 bus_addr_t pa; 360 361 NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot)); 362 363 if (tcds_scsi_iserr(tcds)) 364 return 0; 365 366 /* This is an "assertion" :) */ 367 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 368 panic("tcds_dma_intr: DMA wasn't active"); 369 370 /* DMA has stopped */ 371 tcds_dma_enable(tcds, 0); 372 asc->sc_flags &= ~ASC_DMAACTIVE; 373 374 if (asc->sc_dmasize == 0) { 375 /* A "Transfer Pad" operation completed */ 376 tcl = NCR_READ_REG(sc, NCR_TCL); 377 tcm = NCR_READ_REG(sc, NCR_TCM); 378 NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 379 tcl | (tcm << 8), tcl, tcm)); 380 return 0; 381 } 382 383 resid = 0; 384 if ((asc->sc_flags & ASC_ISPULLUP) == 0 && 385 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 386 NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid)); 387 DELAY(1); 388 } 389 390 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 391 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 392 393 trans = asc->sc_dmasize - resid; 394 if (trans < 0) { /* transferred < 0 ? */ 395 printf("tcds_dma %d: xfer (%d) > req (%d)\n", 396 tcds->sc_slot, trans, (int)asc->sc_dmasize); 397 trans = asc->sc_dmasize; 398 } 399 400 NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 401 tcl, tcm, trans, resid)); 402 403 *asc->sc_dmalen -= trans; 404 *asc->sc_dmaaddr += trans; 405 406 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 407 0, asc->sc_dmamap->dm_mapsize, 408 (sc->sc_flags & ASC_ISPULLUP) 409 ? BUS_DMASYNC_POSTREAD 410 : BUS_DMASYNC_POSTWRITE); 411 412 /* 413 * Clean up unaligned DMAs into main memory. 414 */ 415 if (asc->sc_flags & ASC_ISPULLUP) { 416 /* Handle unaligned starting address, length. */ 417 dud = bus_space_read_4(tcds->sc_bst, 418 tcds->sc_bsh, tcds->sc_dud0); 419 if ((dud & TCDS_DUD0_VALIDBITS) != 0) { 420 addr = (u_int32_t *) 421 ((paddr_t)*asc->sc_dmaaddr & ~0x3); 422 dudmask = 0; 423 if (dud & TCDS_DUD0_VALID00) 424 panic("tcds_dma: dud0 byte 0 valid"); 425 if (dud & TCDS_DUD0_VALID01) 426 dudmask |= TCDS_DUD_BYTE01; 427 if (dud & TCDS_DUD0_VALID10) 428 dudmask |= TCDS_DUD_BYTE10; 429 #ifdef DIAGNOSTIC 430 if (dud & TCDS_DUD0_VALID11) 431 dudmask |= TCDS_DUD_BYTE11; 432 #endif 433 NCR_DMA(("dud0 at 0x%p dudmask 0x%x\n", 434 addr, dudmask)); 435 *addr = (*addr & ~dudmask) | (dud & dudmask); 436 } 437 dud = bus_space_read_4(tcds->sc_bst, 438 tcds->sc_bsh, tcds->sc_dud1); 439 if ((dud & TCDS_DUD1_VALIDBITS) != 0) { 440 pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, 441 tcds->sc_sda) << 2; 442 dudmask = 0; 443 if (dud & TCDS_DUD1_VALID00) 444 dudmask |= TCDS_DUD_BYTE00; 445 if (dud & TCDS_DUD1_VALID01) 446 dudmask |= TCDS_DUD_BYTE01; 447 if (dud & TCDS_DUD1_VALID10) 448 dudmask |= TCDS_DUD_BYTE10; 449 #ifdef DIAGNOSTIC 450 if (dud & TCDS_DUD1_VALID11) 451 panic("tcds_dma: dud1 byte 3 valid"); 452 #endif 453 NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n", 454 pa, dudmask)); 455 /* XXX Fix TC_PHYS_TO_UNCACHED() */ 456 #if defined(__alpha__) 457 addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG(pa); 458 #elif defined(__mips__) 459 addr = (u_int32_t *)MIPS_PHYS_TO_KSEG1(pa); 460 #else 461 #error TURBOchannel only exists on DECs, folks... 462 #endif 463 *addr = (*addr & ~dudmask) | (dud & dudmask); 464 } 465 /* XXX deal with saved residual byte? */ 466 } 467 468 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 469 asc->sc_flags &= ~ASC_MAPLOADED; 470 471 return 0; 472 } 473 474 /* 475 * Glue functions. 476 */ 477 static u_char 478 asc_read_reg(sc, reg) 479 struct ncr53c9x_softc *sc; 480 int reg; 481 { 482 struct asc_softc *asc = (struct asc_softc *)sc; 483 u_int32_t v; 484 485 v = bus_space_read_4(asc->sc_bst, asc->sc_scsi_bsh, 486 reg * sizeof(u_int32_t)); 487 488 return v & 0xff; 489 } 490 491 static void 492 asc_write_reg(sc, reg, val) 493 struct ncr53c9x_softc *sc; 494 int reg; 495 u_char val; 496 { 497 struct asc_softc *asc = (struct asc_softc *)sc; 498 499 bus_space_write_4(asc->sc_bst, asc->sc_scsi_bsh, 500 reg * sizeof(u_int32_t), val); 501 } 502 503 static int 504 tcds_dma_isintr(sc) 505 struct ncr53c9x_softc *sc; 506 { 507 struct asc_softc *asc = (struct asc_softc *)sc; 508 int x; 509 510 x = tcds_scsi_isintr(asc->sc_tcds, 1); 511 512 /* XXX */ 513 return x; 514 } 515 516 static int 517 tcds_dma_isactive(sc) 518 struct ncr53c9x_softc *sc; 519 { 520 struct asc_softc *asc = (struct asc_softc *)sc; 521 522 return !!(asc->sc_flags & ASC_DMAACTIVE); 523 } 524 525 static void 526 tcds_clear_latched_intr(sc) 527 struct ncr53c9x_softc *sc; 528 { 529 struct asc_softc *asc = (struct asc_softc *)sc; 530 531 /* Clear the TCDS interrupt bit. */ 532 (void)tcds_scsi_isintr(asc->sc_tcds, 1); 533 } 534
Indexes created Tue Sep 30 20:09:53 GMT 2025