bba.c revision 1.2 1 1.2 gmcgarry /* $NetBSD: bba.c,v 1.2 2000/05/28 06:13:40 gmcgarry Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.1 augustss * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * Redistribution and use in source and binary forms, with or without
8 1.1 augustss * modification, are permitted provided that the following conditions
9 1.1 augustss * are met:
10 1.1 augustss * 1. Redistributions of source code must retain the above copyright
11 1.1 augustss * notice, this list of conditions and the following disclaimer.
12 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 augustss * notice, this list of conditions and the following disclaimer in the
14 1.1 augustss * documentation and/or other materials provided with the distribution.
15 1.1 augustss * 3. All advertising materials mentioning features or use of this software
16 1.1 augustss * must display the following acknowledgement:
17 1.1 augustss * This product includes software developed by the NetBSD
18 1.1 augustss * Foundation, Inc. and its contributors.
19 1.1 augustss * 4. Neither the name of The NetBSD Foundation nor the names of its
20 1.1 augustss * contributors may be used to endorse or promote products derived
21 1.1 augustss * from this software without specific prior written permission.
22 1.1 augustss *
23 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /* maxine/alpha baseboard audio (bba) */
37 1.1 augustss
38 1.1 augustss #include "audio.h"
39 1.1 augustss #if NAUDIO > 0
40 1.1 augustss
41 1.1 augustss #include <sys/param.h>
42 1.1 augustss #include <sys/systm.h>
43 1.1 augustss #include <sys/kernel.h>
44 1.1 augustss #include <sys/device.h>
45 1.1 augustss #include <sys/malloc.h>
46 1.1 augustss
47 1.1 augustss #include <machine/bus.h>
48 1.1 augustss #include <machine/autoconf.h>
49 1.1 augustss #include <machine/cpu.h>
50 1.1 augustss
51 1.1 augustss #include <vm/vm.h> /* for PAGE_SIZE */
52 1.1 augustss
53 1.1 augustss #include <sys/audioio.h>
54 1.1 augustss #include <dev/audio_if.h>
55 1.1 augustss
56 1.1 augustss #include <dev/ic/am7930reg.h>
57 1.1 augustss #include <dev/ic/am7930var.h>
58 1.1 augustss
59 1.1 augustss #include <dev/tc/tcvar.h>
60 1.1 augustss #include <dev/tc/ioasicreg.h>
61 1.1 augustss #include <dev/tc/ioasicvar.h>
62 1.1 augustss
63 1.1 augustss #ifdef AUDIO_DEBUG
64 1.1 augustss #define DPRINTF(x) if (am7930debug) printf x
65 1.1 augustss #else
66 1.1 augustss #define DPRINTF(x)
67 1.1 augustss #endif /* AUDIO_DEBUG */
68 1.1 augustss
69 1.1 augustss #define BBA_MAX_DMA_SEGMENTS 16
70 1.1 augustss
71 1.1 augustss struct bba_mem {
72 1.1 augustss bus_addr_t addr;
73 1.1 augustss bus_size_t size;
74 1.1 augustss caddr_t kva;
75 1.1 augustss struct bba_mem *next;
76 1.1 augustss };
77 1.1 augustss
78 1.1 augustss struct bba_dma_state {
79 1.1 augustss bus_dmamap_t dmam; /* dma map */
80 1.1 augustss int active;
81 1.1 augustss int curseg; /* current segment in dma buffer */
82 1.1 augustss void (*intr)__P((void *)); /* higher-level audio handler */
83 1.1 augustss void *intr_arg;
84 1.1 augustss };
85 1.1 augustss
86 1.1 augustss struct bba_softc {
87 1.1 augustss struct am7930_softc sc_am7930; /* glue to MI code */
88 1.1 augustss
89 1.1 augustss bus_space_tag_t sc_bst; /* IOASIC bus tag/handle */
90 1.1 augustss bus_space_handle_t sc_bsh;
91 1.1 augustss bus_dma_tag_t sc_dmat;
92 1.1 augustss bus_space_handle_t sc_codec_bsh; /* codec bus space handle */
93 1.1 augustss
94 1.1 augustss struct bba_mem *sc_mem_head; /* list of buffers */
95 1.1 augustss
96 1.1 augustss struct bba_dma_state sc_tx_dma_state;
97 1.1 augustss struct bba_dma_state sc_rx_dma_state;
98 1.1 augustss };
99 1.1 augustss
100 1.1 augustss int bba_match __P((struct device *, struct cfdata *, void *));
101 1.1 augustss void bba_attach __P((struct device *, struct device *, void *));
102 1.1 augustss
103 1.1 augustss struct cfattach bba_ca = {
104 1.1 augustss sizeof(struct bba_softc), bba_match, bba_attach
105 1.1 augustss };
106 1.1 augustss
107 1.1 augustss /*
108 1.1 augustss * Define our interface into the am7930 MI driver.
109 1.1 augustss */
110 1.1 augustss
111 1.1 augustss u_int8_t bba_codec_iread __P((struct am7930_softc *, int));
112 1.1 augustss u_int16_t bba_codec_iread16 __P((struct am7930_softc *, int));
113 1.1 augustss void bba_codec_iwrite __P((struct am7930_softc *, int, u_int8_t));
114 1.1 augustss void bba_codec_iwrite16 __P((struct am7930_softc *, int, u_int16_t));
115 1.1 augustss void bba_onopen __P((struct am7930_softc *sc));
116 1.1 augustss void bba_onclose __P((struct am7930_softc *sc));
117 1.1 augustss void bba_output_conv __P((void *, u_int8_t *, int));
118 1.1 augustss void bba_input_conv __P((void *, u_int8_t *, int));
119 1.1 augustss
120 1.1 augustss struct am7930_glue bba_glue = {
121 1.1 augustss bba_codec_iread,
122 1.1 augustss bba_codec_iwrite,
123 1.1 augustss bba_codec_iread16,
124 1.1 augustss bba_codec_iwrite16,
125 1.1 augustss bba_onopen,
126 1.1 augustss bba_onclose,
127 1.1 augustss 4,
128 1.1 augustss bba_input_conv,
129 1.1 augustss bba_output_conv,
130 1.1 augustss };
131 1.1 augustss
132 1.1 augustss /*
133 1.1 augustss * Define our interface to the higher level audio driver.
134 1.1 augustss */
135 1.1 augustss
136 1.1 augustss int bba_round_blocksize __P((void *, int));
137 1.1 augustss int bba_halt_output __P((void *));
138 1.1 augustss int bba_halt_input __P((void *));
139 1.1 augustss int bba_getdev __P((void *, struct audio_device *));
140 1.1 augustss void *bba_allocm __P((void *, int, size_t, int, int));
141 1.1 augustss void bba_freem __P((void *, void *, int));
142 1.1 augustss size_t bba_round_buffersize __P((void *, int, size_t));
143 1.1 augustss int bba_trigger_output __P((void *, void *, void *, int,
144 1.1 augustss void (*)(void *), void *, struct audio_params *));
145 1.1 augustss int bba_trigger_input __P((void *, void *, void *, int,
146 1.1 augustss void (*)(void *), void *, struct audio_params *));
147 1.1 augustss
148 1.1 augustss struct audio_hw_if sa_hw_if = {
149 1.1 augustss am7930_open,
150 1.1 augustss am7930_close,
151 1.1 augustss 0,
152 1.1 augustss am7930_query_encoding,
153 1.1 augustss am7930_set_params,
154 1.1 augustss bba_round_blocksize, /* md */
155 1.1 augustss am7930_commit_settings,
156 1.1 augustss 0,
157 1.1 augustss 0,
158 1.1 augustss 0,
159 1.1 augustss 0,
160 1.1 augustss bba_halt_output, /* md */
161 1.1 augustss bba_halt_input, /* md */
162 1.1 augustss 0,
163 1.1 augustss bba_getdev,
164 1.1 augustss 0,
165 1.1 augustss am7930_set_port,
166 1.1 augustss am7930_get_port,
167 1.1 augustss am7930_query_devinfo,
168 1.1 augustss bba_allocm, /* md */
169 1.1 augustss bba_freem, /* md */
170 1.1 augustss bba_round_buffersize, /* md */
171 1.1 augustss 0,
172 1.1 augustss am7930_get_props,
173 1.1 augustss bba_trigger_output, /* md */
174 1.1 augustss bba_trigger_input /* md */
175 1.1 augustss };
176 1.1 augustss
177 1.1 augustss struct audio_device bba_device = {
178 1.1 augustss "am7930",
179 1.1 augustss "x",
180 1.1 augustss "bba"
181 1.1 augustss };
182 1.1 augustss
183 1.1 augustss int bba_intr __P((void *));
184 1.1 augustss void bba_reset __P((struct bba_softc *, int));
185 1.1 augustss void bba_codec_dwrite __P((struct am7930_softc *, int, u_int8_t));
186 1.1 augustss u_int8_t bba_codec_dread __P((struct am7930_softc *, int));
187 1.1 augustss
188 1.1 augustss int bba_match(parent, cf, aux)
189 1.1 augustss struct device *parent;
190 1.1 augustss struct cfdata *cf;
191 1.1 augustss void *aux;
192 1.1 augustss {
193 1.1 augustss struct ioasicdev_attach_args *ia = aux;
194 1.1 augustss
195 1.1 augustss if (strcmp(ia->iada_modname, "isdn") != 0 &&
196 1.1 augustss strcmp(ia->iada_modname, "AMD79c30") != 0)
197 1.1 augustss return 0;
198 1.1 augustss
199 1.1 augustss return 1;
200 1.1 augustss }
201 1.1 augustss
202 1.1 augustss
203 1.1 augustss void
204 1.1 augustss bba_attach(parent, self, aux)
205 1.1 augustss struct device *parent;
206 1.1 augustss struct device *self;
207 1.1 augustss void *aux;
208 1.1 augustss {
209 1.1 augustss struct ioasicdev_attach_args *ia = aux;
210 1.1 augustss struct bba_softc *sc = (struct bba_softc *)self;
211 1.1 augustss struct am7930_softc *asc = &sc->sc_am7930;
212 1.1 augustss
213 1.1 augustss sc->sc_bst = ((struct ioasic_softc *)parent)->sc_bst;
214 1.1 augustss sc->sc_bsh = ((struct ioasic_softc *)parent)->sc_bsh;
215 1.1 augustss sc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat;
216 1.1 augustss
217 1.1 augustss /* get the bus space handle for codec */
218 1.1 augustss if (bus_space_subregion(sc->sc_bst, sc->sc_bsh,
219 1.1 augustss ia->iada_offset, 0, &sc->sc_codec_bsh)) {
220 1.1 augustss printf("%s: unable to map device\n", asc->sc_dev.dv_xname);
221 1.1 augustss return;
222 1.1 augustss }
223 1.1 augustss
224 1.1 augustss printf("\n");
225 1.1 augustss
226 1.1 augustss bba_reset(sc,1);
227 1.1 augustss
228 1.1 augustss /*
229 1.1 augustss * Set up glue for MI code early; we use some of it here.
230 1.1 augustss */
231 1.1 augustss asc->sc_glue = &bba_glue;
232 1.1 augustss
233 1.1 augustss /*
234 1.1 augustss * MI initialisation. We will be doing DMA.
235 1.1 augustss */
236 1.1 augustss am7930_init(asc, AUDIOAMD_DMA_MODE);
237 1.1 augustss
238 1.1 augustss ioasic_intr_establish(parent, ia->iada_cookie, TC_IPL_NONE,
239 1.1 augustss bba_intr, sc);
240 1.1 augustss
241 1.1 augustss audio_attach_mi(&sa_hw_if, asc, &asc->sc_dev);
242 1.1 augustss }
243 1.1 augustss
244 1.1 augustss
245 1.1 augustss void
246 1.1 augustss bba_onopen(sc)
247 1.1 augustss struct am7930_softc *sc;
248 1.1 augustss {
249 1.1 augustss bba_reset((struct bba_softc *)sc, 0);
250 1.1 augustss }
251 1.1 augustss
252 1.1 augustss
253 1.1 augustss void
254 1.1 augustss bba_onclose(sc)
255 1.1 augustss struct am7930_softc *sc;
256 1.1 augustss {
257 1.1 augustss bba_halt_input((struct bba_softc *)sc);
258 1.1 augustss bba_halt_output((struct bba_softc *)sc);
259 1.1 augustss }
260 1.1 augustss
261 1.1 augustss
262 1.1 augustss void
263 1.1 augustss bba_reset(sc, reset)
264 1.1 augustss struct bba_softc *sc;
265 1.1 augustss int reset;
266 1.1 augustss {
267 1.1 augustss u_int32_t ssr;
268 1.1 augustss
269 1.1 augustss /* disable any DMA and reset the codec */
270 1.1 augustss ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
271 1.1 augustss ssr &= ~(IOASIC_CSR_DMAEN_ISDN_T | IOASIC_CSR_DMAEN_ISDN_R);
272 1.1 augustss if (reset)
273 1.1 augustss ssr &= ~IOASIC_CSR_ISDN_ENABLE;
274 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
275 1.1 augustss DELAY(10); /* 400ns required for codec to reset */
276 1.1 augustss
277 1.1 augustss /* initialise DMA pointers */
278 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR, -1);
279 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR, -1);
280 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR, -1);
281 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR, -1);
282 1.1 augustss
283 1.1 augustss /* take out of reset state */
284 1.1 augustss if (reset) {
285 1.1 augustss ssr |= IOASIC_CSR_ISDN_ENABLE;
286 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
287 1.1 augustss }
288 1.1 augustss
289 1.1 augustss }
290 1.1 augustss
291 1.1 augustss
292 1.1 augustss void *
293 1.1 augustss bba_allocm(addr, direction, size, pool, flags)
294 1.1 augustss void *addr;
295 1.1 augustss int direction;
296 1.1 augustss size_t size;
297 1.1 augustss int pool, flags;
298 1.1 augustss {
299 1.1 augustss struct am7930_softc *asc = addr;
300 1.1 augustss struct bba_softc *sc = addr;
301 1.1 augustss bus_dma_segment_t seg;
302 1.1 augustss int rseg;
303 1.1 augustss caddr_t kva;
304 1.1 augustss struct bba_mem *m;
305 1.1 augustss int state = 0;
306 1.1 augustss
307 1.1 augustss DPRINTF(("bba_allocm: size = %d\n",size));
308 1.1 augustss
309 1.1 augustss if (bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg,
310 1.1 augustss 1, &rseg, BUS_DMA_NOWAIT)) {
311 1.1 augustss printf("%s: can't allocate DMA buffer\n",
312 1.1 augustss asc->sc_dev.dv_xname);
313 1.1 augustss goto bad;
314 1.1 augustss }
315 1.1 augustss state |= 1;
316 1.1 augustss
317 1.1 augustss if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, size,
318 1.1 augustss &kva, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
319 1.1 augustss printf("%s: can't map DMA buffer\n", asc->sc_dev.dv_xname);
320 1.1 augustss goto bad;
321 1.1 augustss }
322 1.1 augustss state |= 2;
323 1.1 augustss
324 1.1 augustss m = malloc(sizeof(struct bba_mem), pool, flags);
325 1.1 augustss if (m == NULL)
326 1.1 augustss goto bad;
327 1.1 augustss m->addr = seg.ds_addr;
328 1.1 augustss m->size = seg.ds_len;
329 1.1 augustss m->kva = kva;
330 1.1 augustss m->next = sc->sc_mem_head;
331 1.1 augustss sc->sc_mem_head = m;
332 1.1 augustss
333 1.1 augustss return (void *)kva;
334 1.1 augustss
335 1.1 augustss bad:
336 1.1 augustss if (state & 2)
337 1.1 augustss bus_dmamem_unmap(sc->sc_dmat, kva, size);
338 1.1 augustss if (state & 1)
339 1.1 augustss bus_dmamem_free(sc->sc_dmat, &seg, 1);
340 1.1 augustss return NULL;
341 1.1 augustss }
342 1.1 augustss
343 1.1 augustss
344 1.1 augustss void
345 1.1 augustss bba_freem(addr, ptr, pool)
346 1.1 augustss void *addr;
347 1.1 augustss void *ptr;
348 1.1 augustss int pool;
349 1.1 augustss {
350 1.1 augustss struct bba_softc *sc = addr;
351 1.1 augustss struct bba_mem **mp, *m;
352 1.1 augustss bus_dma_segment_t seg;
353 1.1 augustss caddr_t kva = (caddr_t)addr;
354 1.1 augustss
355 1.1 augustss for (mp = &sc->sc_mem_head; *mp && (*mp)->kva != kva;
356 1.1 augustss mp = &(*mp)->next)
357 1.1 augustss /* nothing */ ;
358 1.1 augustss m = *mp;
359 1.1 augustss if (m != NULL) {
360 1.1 augustss printf("bba_freem: freeing unallocted memory\n");
361 1.1 augustss return;
362 1.1 augustss }
363 1.1 augustss *mp = m->next;
364 1.1 augustss bus_dmamem_unmap(sc->sc_dmat, kva, m->size);
365 1.1 augustss
366 1.1 augustss seg.ds_addr = m->addr;
367 1.1 augustss seg.ds_len = m->size;
368 1.1 augustss bus_dmamem_free(sc->sc_dmat, &seg, 1);
369 1.1 augustss free(m, pool);
370 1.1 augustss }
371 1.1 augustss
372 1.1 augustss
373 1.1 augustss size_t
374 1.1 augustss bba_round_buffersize(addr, direction, size)
375 1.1 augustss void *addr;
376 1.1 augustss int direction;
377 1.1 augustss size_t size;
378 1.1 augustss {
379 1.1 augustss DPRINTF(("bba_round_buffersize: size=%d\n", size));
380 1.1 augustss
381 1.1 augustss #define BBA_BUFFERSIZE (BBA_MAX_DMA_SEGMENTS * PAGE_SIZE)
382 1.1 augustss return (size > BBA_BUFFERSIZE ? BBA_BUFFERSIZE : round_page(size));
383 1.1 augustss }
384 1.1 augustss
385 1.1 augustss
386 1.1 augustss int
387 1.1 augustss bba_halt_output(addr)
388 1.1 augustss void *addr;
389 1.1 augustss {
390 1.1 augustss struct bba_softc *sc = addr;
391 1.1 augustss struct bba_dma_state *d = &sc->sc_tx_dma_state;
392 1.1 augustss u_int32_t ssr;
393 1.1 augustss
394 1.1 augustss /* disable any DMA */
395 1.1 augustss ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
396 1.1 augustss ssr &= ~IOASIC_CSR_DMAEN_ISDN_T;
397 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
398 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR, -1);
399 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR, -1);
400 1.1 augustss
401 1.1 augustss if (d->active) {
402 1.1 augustss bus_dmamap_unload(sc->sc_dmat, d->dmam);
403 1.1 augustss bus_dmamap_destroy(sc->sc_dmat, d->dmam);
404 1.1 augustss d->active = 0;
405 1.1 augustss }
406 1.1 augustss
407 1.1 augustss return 0;
408 1.1 augustss }
409 1.1 augustss
410 1.1 augustss
411 1.1 augustss int
412 1.1 augustss bba_halt_input(addr)
413 1.1 augustss void *addr;
414 1.1 augustss {
415 1.1 augustss struct bba_softc *sc = addr;
416 1.1 augustss struct bba_dma_state *d = &sc->sc_rx_dma_state;
417 1.1 augustss u_int32_t ssr;
418 1.1 augustss
419 1.1 augustss /* disable any DMA */
420 1.1 augustss ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
421 1.1 augustss ssr &= ~IOASIC_CSR_DMAEN_ISDN_R;
422 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
423 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR, -1);
424 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR, -1);
425 1.1 augustss
426 1.1 augustss if (d->active) {
427 1.1 augustss bus_dmamap_unload(sc->sc_dmat, d->dmam);
428 1.1 augustss bus_dmamap_destroy(sc->sc_dmat, d->dmam);
429 1.1 augustss d->active = 0;
430 1.1 augustss }
431 1.1 augustss
432 1.1 augustss return 0;
433 1.1 augustss }
434 1.1 augustss
435 1.1 augustss
436 1.1 augustss int
437 1.1 augustss bba_getdev(addr, retp)
438 1.1 augustss void *addr;
439 1.1 augustss struct audio_device *retp;
440 1.1 augustss {
441 1.1 augustss *retp = bba_device;
442 1.1 augustss return 0;
443 1.1 augustss }
444 1.1 augustss
445 1.1 augustss
446 1.1 augustss int
447 1.1 augustss bba_trigger_output(addr, start, end, blksize, intr, arg, param)
448 1.1 augustss void *addr;
449 1.1 augustss void *start, *end;
450 1.1 augustss int blksize;
451 1.1 augustss void (*intr) __P((void *));
452 1.1 augustss void *arg;
453 1.1 augustss struct audio_params *param;
454 1.1 augustss {
455 1.1 augustss struct bba_softc *sc = addr;
456 1.1 augustss struct bba_dma_state *d = &sc->sc_tx_dma_state;
457 1.1 augustss u_int32_t ssr;
458 1.1 augustss tc_addr_t phys, nphys;
459 1.1 augustss int state = 0;
460 1.1 augustss
461 1.1 augustss DPRINTF(("bba_trigger_output: sc=%p start=%p end=%p blksize=%d intr=%p(%p)\n",
462 1.1 augustss addr, start, end, blksize, intr, arg));
463 1.1 augustss
464 1.1 augustss if (bus_dmamap_create(sc->sc_dmat, (char *)end - (char *)start,
465 1.1 augustss BBA_MAX_DMA_SEGMENTS, PAGE_SIZE, 0, BUS_DMA_NOWAIT, &d->dmam)) {
466 1.1 augustss printf("bba_trigger_output: can't create DMA map\n");
467 1.1 augustss goto bad;
468 1.1 augustss }
469 1.1 augustss state |= 1;
470 1.1 augustss
471 1.1 augustss if (bus_dmamap_load(sc->sc_dmat, d->dmam, start,
472 1.1 augustss (char *)end - (char *)start, NULL, BUS_DMA_NOWAIT)) {
473 1.1 augustss printf("bba_trigger_output: can't load DMA map\n");
474 1.1 augustss goto bad;
475 1.1 augustss }
476 1.1 augustss state |= 2;
477 1.1 augustss
478 1.1 augustss /* disable any DMA */
479 1.1 augustss ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
480 1.1 augustss ssr &= ~IOASIC_CSR_DMAEN_ISDN_T;
481 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
482 1.1 augustss
483 1.1 augustss d->intr = intr;
484 1.1 augustss d->intr_arg = arg;
485 1.1 augustss d->curseg = 1;
486 1.1 augustss
487 1.1 augustss /* get physical address of buffer start */
488 1.2 gmcgarry phys = (tc_addr_t)d->dmam->dm_segs[0].ds_addr;
489 1.2 gmcgarry nphys = (tc_addr_t)d->dmam->dm_segs[1].ds_addr;
490 1.1 augustss
491 1.1 augustss /* setup DMA pointer */
492 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR,
493 1.1 augustss IOASIC_DMA_ADDR(phys));
494 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR,
495 1.1 augustss IOASIC_DMA_ADDR(nphys));
496 1.1 augustss
497 1.1 augustss /* kick off DMA */
498 1.1 augustss ssr |= IOASIC_CSR_DMAEN_ISDN_T;
499 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
500 1.1 augustss
501 1.1 augustss wbflush();
502 1.1 augustss
503 1.1 augustss d->active = 1;
504 1.1 augustss
505 1.1 augustss return 0;
506 1.1 augustss
507 1.1 augustss bad:
508 1.1 augustss if (state & 2)
509 1.1 augustss bus_dmamap_unload(sc->sc_dmat, d->dmam);
510 1.1 augustss if (state & 1)
511 1.1 augustss bus_dmamap_destroy(sc->sc_dmat, d->dmam);
512 1.1 augustss return 1;
513 1.1 augustss }
514 1.1 augustss
515 1.1 augustss
516 1.1 augustss int
517 1.1 augustss bba_trigger_input(addr, start, end, blksize, intr, arg, param)
518 1.1 augustss void *addr;
519 1.1 augustss void *start, *end;
520 1.1 augustss int blksize;
521 1.1 augustss void (*intr) __P((void *));
522 1.1 augustss void *arg;
523 1.1 augustss struct audio_params *param;
524 1.1 augustss {
525 1.1 augustss struct bba_softc *sc = (struct bba_softc *)addr;
526 1.1 augustss struct bba_dma_state *d = &sc->sc_rx_dma_state;
527 1.1 augustss tc_addr_t phys, nphys;
528 1.1 augustss u_int32_t ssr;
529 1.1 augustss int state = 0;
530 1.1 augustss
531 1.1 augustss DPRINTF(("bba_trigger_input: sc=%p start=%p end=%p blksize=%d intr=%p(%p)\n",
532 1.1 augustss addr, start, end, blksize, intr, arg));
533 1.1 augustss
534 1.1 augustss if (bus_dmamap_create(sc->sc_dmat, (char *)end - (char *)start,
535 1.1 augustss BBA_MAX_DMA_SEGMENTS, PAGE_SIZE, 0, BUS_DMA_NOWAIT, &d->dmam)) {
536 1.1 augustss printf("bba_trigger_input: can't create DMA map\n");
537 1.1 augustss goto bad;
538 1.1 augustss }
539 1.1 augustss state |= 1;
540 1.1 augustss
541 1.1 augustss if (bus_dmamap_load(sc->sc_dmat, d->dmam, start,
542 1.1 augustss (char *)end - (char *)start, NULL, BUS_DMA_NOWAIT)) {
543 1.1 augustss printf("bba_trigger_input: can't load DMA map\n");
544 1.1 augustss goto bad;
545 1.1 augustss }
546 1.1 augustss state |= 2;
547 1.1 augustss
548 1.1 augustss /* disable any DMA */
549 1.1 augustss ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
550 1.1 augustss ssr &= ~IOASIC_CSR_DMAEN_ISDN_R;
551 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
552 1.1 augustss
553 1.1 augustss d->intr = intr;
554 1.1 augustss d->intr_arg = arg;
555 1.1 augustss d->curseg = 1;
556 1.1 augustss
557 1.1 augustss /* get physical address of buffer start */
558 1.2 gmcgarry phys = (tc_addr_t)d->dmam->dm_segs[0].ds_addr;
559 1.2 gmcgarry nphys = (tc_addr_t)d->dmam->dm_segs[1].ds_addr;
560 1.1 augustss
561 1.1 augustss /* setup DMA pointer */
562 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR,
563 1.1 augustss IOASIC_DMA_ADDR(phys));
564 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR,
565 1.1 augustss IOASIC_DMA_ADDR(nphys));
566 1.1 augustss
567 1.1 augustss /* kick off DMA */
568 1.1 augustss ssr |= IOASIC_CSR_DMAEN_ISDN_R;
569 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
570 1.1 augustss
571 1.1 augustss wbflush();
572 1.1 augustss
573 1.1 augustss d->active = 1;
574 1.1 augustss
575 1.1 augustss return 0;
576 1.1 augustss
577 1.1 augustss bad:
578 1.1 augustss if (state & 2)
579 1.1 augustss bus_dmamap_unload(sc->sc_dmat, d->dmam);
580 1.1 augustss if (state & 1)
581 1.1 augustss bus_dmamap_destroy(sc->sc_dmat, d->dmam);
582 1.1 augustss return 1;
583 1.1 augustss }
584 1.1 augustss
585 1.1 augustss int
586 1.1 augustss bba_intr(addr)
587 1.1 augustss void *addr;
588 1.1 augustss {
589 1.1 augustss struct bba_softc *sc = addr;
590 1.1 augustss struct bba_dma_state *d;
591 1.1 augustss tc_addr_t nphys;
592 1.1 augustss int s, mask;
593 1.1 augustss
594 1.1 augustss s = splaudio();
595 1.1 augustss
596 1.1 augustss mask = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_INTR);
597 1.1 augustss
598 1.1 augustss if (mask & IOASIC_INTR_ISDN_TXLOAD) {
599 1.1 augustss d = &sc->sc_tx_dma_state;
600 1.1 augustss d->curseg = (d->curseg+1) % d->dmam->dm_nsegs;
601 1.1 augustss nphys = (tc_addr_t)d->dmam->dm_segs[d->curseg].ds_addr;
602 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh,
603 1.1 augustss IOASIC_ISDN_X_NEXTPTR, IOASIC_DMA_ADDR(nphys));
604 1.1 augustss if (d->intr != NULL)
605 1.1 augustss (*d->intr)(d->intr_arg);
606 1.1 augustss }
607 1.1 augustss if (mask & IOASIC_INTR_ISDN_RXLOAD) {
608 1.1 augustss d = &sc->sc_rx_dma_state;
609 1.1 augustss d->curseg = (d->curseg+1) % d->dmam->dm_nsegs;
610 1.1 augustss nphys = (tc_addr_t)d->dmam->dm_segs[d->curseg].ds_addr;
611 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh,
612 1.1 augustss IOASIC_ISDN_R_NEXTPTR, IOASIC_DMA_ADDR(nphys));
613 1.1 augustss if (d->intr != NULL)
614 1.1 augustss (*d->intr)(d->intr_arg);
615 1.1 augustss }
616 1.1 augustss
617 1.1 augustss splx(s);
618 1.1 augustss
619 1.1 augustss return 0;
620 1.1 augustss }
621 1.1 augustss
622 1.1 augustss
623 1.1 augustss void
624 1.1 augustss bba_input_conv(v, p, cc)
625 1.1 augustss void *v;
626 1.1 augustss u_int8_t *p;
627 1.1 augustss int cc;
628 1.1 augustss {
629 1.1 augustss u_int8_t *q = p;
630 1.1 augustss
631 1.1 augustss DPRINTF(("bba_input_conv(): v=%p p=%p cc=%d\n", v, p, cc));
632 1.1 augustss
633 1.1 augustss /*
634 1.1 augustss * p points start of buffer
635 1.1 augustss * cc is the number of bytes in the destination buffer
636 1.1 augustss */
637 1.1 augustss
638 1.1 augustss while (--cc >= 0) {
639 1.1 augustss *p = ((*(u_int32_t *)q)>>16)&0xff;
640 1.1 augustss q += 4;
641 1.1 augustss p++;
642 1.1 augustss }
643 1.1 augustss }
644 1.1 augustss
645 1.1 augustss
646 1.1 augustss void
647 1.1 augustss bba_output_conv(v, p, cc)
648 1.1 augustss void *v;
649 1.1 augustss u_int8_t *p;
650 1.1 augustss int cc;
651 1.1 augustss {
652 1.1 augustss u_int8_t *q = p;
653 1.1 augustss
654 1.1 augustss DPRINTF(("bba_output_conv(): v=%p p=%p cc=%d\n", v, p, cc));
655 1.1 augustss
656 1.1 augustss /*
657 1.1 augustss * p points start of buffer
658 1.1 augustss * cc is the number of bytes in the source buffer
659 1.1 augustss */
660 1.1 augustss
661 1.1 augustss p += cc;
662 1.1 augustss q += cc * 4;
663 1.1 augustss while (--cc >= 0) {
664 1.1 augustss q -= 4;
665 1.1 augustss p -= 1;
666 1.1 augustss *(u_int32_t *)q = (*p<<16);
667 1.1 augustss }
668 1.1 augustss }
669 1.1 augustss
670 1.1 augustss
671 1.1 augustss int
672 1.1 augustss bba_round_blocksize(addr, blk)
673 1.1 augustss void *addr;
674 1.1 augustss int blk;
675 1.1 augustss {
676 1.1 augustss return (PAGE_SIZE);
677 1.1 augustss }
678 1.1 augustss
679 1.1 augustss
680 1.1 augustss /* indirect write */
681 1.1 augustss void
682 1.1 augustss bba_codec_iwrite(sc, reg, val)
683 1.1 augustss struct am7930_softc *sc;
684 1.1 augustss int reg;
685 1.1 augustss u_int8_t val;
686 1.1 augustss {
687 1.1 augustss DPRINTF(("bba_codec_iwrite(): sc=%p, reg=%d, val=%d\n",sc,reg,val));
688 1.1 augustss
689 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
690 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_DR, val);
691 1.1 augustss }
692 1.1 augustss
693 1.1 augustss
694 1.1 augustss void
695 1.1 augustss bba_codec_iwrite16(sc, reg, val)
696 1.1 augustss struct am7930_softc *sc;
697 1.1 augustss int reg;
698 1.1 augustss u_int16_t val;
699 1.1 augustss {
700 1.1 augustss DPRINTF(("bba_codec_iwrite16(): sc=%p, reg=%d, val=%d\n",sc,reg,val));
701 1.1 augustss
702 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
703 1.1 augustss #if 0
704 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_DR, val>>8);
705 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_DR, val);
706 1.1 augustss #else
707 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_DR, val);
708 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_DR, val>>8);
709 1.1 augustss #endif
710 1.1 augustss }
711 1.1 augustss
712 1.1 augustss
713 1.1 augustss u_int16_t
714 1.1 augustss bba_codec_iread16(sc, reg)
715 1.1 augustss struct am7930_softc *sc;
716 1.1 augustss int reg;
717 1.1 augustss {
718 1.1 augustss u_int16_t val;
719 1.1 augustss DPRINTF(("bba_codec_iread16(): sc=%p, reg=%d\n",sc,reg));
720 1.1 augustss
721 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
722 1.1 augustss #if 0
723 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_DR, val>>8);
724 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_DR, val);
725 1.1 augustss #else
726 1.1 augustss val = bba_codec_dread(sc, AM7930_DREG_DR) << 8;
727 1.1 augustss val |= bba_codec_dread(sc, AM7930_DREG_DR);
728 1.1 augustss #endif
729 1.1 augustss
730 1.1 augustss return val;
731 1.1 augustss }
732 1.1 augustss
733 1.1 augustss
734 1.1 augustss /* indirect read */
735 1.1 augustss u_int8_t
736 1.1 augustss bba_codec_iread(sc, reg)
737 1.1 augustss struct am7930_softc *sc;
738 1.1 augustss int reg;
739 1.1 augustss {
740 1.1 augustss u_int8_t val;
741 1.1 augustss
742 1.1 augustss DPRINTF(("bba_codec_iread(): sc=%p, reg=%d\n",sc,reg));
743 1.1 augustss
744 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
745 1.1 augustss val = bba_codec_dread(sc, AM7930_DREG_DR);
746 1.1 augustss
747 1.1 augustss DPRINTF(("read 0x%x (%d)\n", val, val));
748 1.1 augustss
749 1.1 augustss return val;
750 1.1 augustss }
751 1.1 augustss
752 1.1 augustss
753 1.1 augustss #define TIMETOWASTE 50
754 1.1 augustss
755 1.1 augustss /* direct write */
756 1.1 augustss void
757 1.1 augustss bba_codec_dwrite(asc, reg, val)
758 1.1 augustss struct am7930_softc *asc;
759 1.1 augustss int reg;
760 1.1 augustss u_int8_t val;
761 1.1 augustss {
762 1.1 augustss struct bba_softc *sc = (struct bba_softc *)asc;
763 1.1 augustss int i;
764 1.1 augustss
765 1.1 augustss DPRINTF(("bba_codec_dwrite(): sc=%p, reg=%d, val=%d\n",sc,reg,val));
766 1.1 augustss
767 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_codec_bsh, (reg<<6), val);
768 1.1 augustss
769 1.1 augustss for (i=0; i<TIMETOWASTE; i++) {};
770 1.1 augustss }
771 1.1 augustss
772 1.1 augustss /* direct read */
773 1.1 augustss u_int8_t
774 1.1 augustss bba_codec_dread(asc, reg)
775 1.1 augustss struct am7930_softc *asc;
776 1.1 augustss int reg;
777 1.1 augustss {
778 1.1 augustss struct bba_softc *sc = (struct bba_softc *)asc;
779 1.1 augustss u_int8_t val;
780 1.1 augustss int i;
781 1.1 augustss
782 1.1 augustss DPRINTF(("bba_codec_dread(): sc=%p, reg=%d\n",sc,reg));
783 1.1 augustss
784 1.1 augustss val = bus_space_read_1(sc->sc_bst, sc->sc_codec_bsh, (reg<<6));
785 1.1 augustss
786 1.1 augustss for (i=0; i<TIMETOWASTE; i++) {};
787 1.1 augustss
788 1.1 augustss return val;
789 1.1 augustss }
790 1.1 augustss
791 1.1 augustss #endif /* NAUDIO > 0 */
792