bba.c revision 1.5 1 1.5 gmcgarry /* $NetBSD: bba.c,v 1.5 2000/06/05 23:02:04 gmcgarry Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.1 augustss * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * Redistribution and use in source and binary forms, with or without
8 1.1 augustss * modification, are permitted provided that the following conditions
9 1.1 augustss * are met:
10 1.1 augustss * 1. Redistributions of source code must retain the above copyright
11 1.1 augustss * notice, this list of conditions and the following disclaimer.
12 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 augustss * notice, this list of conditions and the following disclaimer in the
14 1.1 augustss * documentation and/or other materials provided with the distribution.
15 1.1 augustss * 3. All advertising materials mentioning features or use of this software
16 1.1 augustss * must display the following acknowledgement:
17 1.1 augustss * This product includes software developed by the NetBSD
18 1.1 augustss * Foundation, Inc. and its contributors.
19 1.1 augustss * 4. Neither the name of The NetBSD Foundation nor the names of its
20 1.1 augustss * contributors may be used to endorse or promote products derived
21 1.1 augustss * from this software without specific prior written permission.
22 1.1 augustss *
23 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /* maxine/alpha baseboard audio (bba) */
37 1.1 augustss
38 1.1 augustss #include <sys/param.h>
39 1.1 augustss #include <sys/systm.h>
40 1.1 augustss #include <sys/kernel.h>
41 1.1 augustss #include <sys/device.h>
42 1.1 augustss #include <sys/malloc.h>
43 1.1 augustss
44 1.1 augustss #include <machine/bus.h>
45 1.1 augustss #include <machine/autoconf.h>
46 1.1 augustss #include <machine/cpu.h>
47 1.1 augustss
48 1.1 augustss #include <vm/vm.h> /* for PAGE_SIZE */
49 1.1 augustss
50 1.1 augustss #include <sys/audioio.h>
51 1.1 augustss #include <dev/audio_if.h>
52 1.1 augustss
53 1.1 augustss #include <dev/ic/am7930reg.h>
54 1.1 augustss #include <dev/ic/am7930var.h>
55 1.1 augustss
56 1.1 augustss #include <dev/tc/tcvar.h>
57 1.1 augustss #include <dev/tc/ioasicreg.h>
58 1.1 augustss #include <dev/tc/ioasicvar.h>
59 1.1 augustss
60 1.1 augustss #ifdef AUDIO_DEBUG
61 1.1 augustss #define DPRINTF(x) if (am7930debug) printf x
62 1.1 augustss #else
63 1.1 augustss #define DPRINTF(x)
64 1.1 augustss #endif /* AUDIO_DEBUG */
65 1.1 augustss
66 1.1 augustss #define BBA_MAX_DMA_SEGMENTS 16
67 1.5 gmcgarry #define BBA_REGISTER_SHIFT 6
68 1.1 augustss
69 1.1 augustss struct bba_mem {
70 1.1 augustss bus_addr_t addr;
71 1.1 augustss bus_size_t size;
72 1.1 augustss caddr_t kva;
73 1.1 augustss struct bba_mem *next;
74 1.1 augustss };
75 1.1 augustss
76 1.1 augustss struct bba_dma_state {
77 1.1 augustss bus_dmamap_t dmam; /* dma map */
78 1.1 augustss int active;
79 1.1 augustss int curseg; /* current segment in dma buffer */
80 1.1 augustss void (*intr)__P((void *)); /* higher-level audio handler */
81 1.1 augustss void *intr_arg;
82 1.1 augustss };
83 1.1 augustss
84 1.1 augustss struct bba_softc {
85 1.1 augustss struct am7930_softc sc_am7930; /* glue to MI code */
86 1.1 augustss
87 1.1 augustss bus_space_tag_t sc_bst; /* IOASIC bus tag/handle */
88 1.1 augustss bus_space_handle_t sc_bsh;
89 1.1 augustss bus_dma_tag_t sc_dmat;
90 1.1 augustss bus_space_handle_t sc_codec_bsh; /* codec bus space handle */
91 1.1 augustss
92 1.1 augustss struct bba_mem *sc_mem_head; /* list of buffers */
93 1.1 augustss
94 1.1 augustss struct bba_dma_state sc_tx_dma_state;
95 1.1 augustss struct bba_dma_state sc_rx_dma_state;
96 1.1 augustss };
97 1.1 augustss
98 1.1 augustss int bba_match __P((struct device *, struct cfdata *, void *));
99 1.1 augustss void bba_attach __P((struct device *, struct device *, void *));
100 1.1 augustss
101 1.1 augustss struct cfattach bba_ca = {
102 1.1 augustss sizeof(struct bba_softc), bba_match, bba_attach
103 1.1 augustss };
104 1.1 augustss
105 1.1 augustss /*
106 1.1 augustss * Define our interface into the am7930 MI driver.
107 1.1 augustss */
108 1.1 augustss
109 1.1 augustss u_int8_t bba_codec_iread __P((struct am7930_softc *, int));
110 1.1 augustss u_int16_t bba_codec_iread16 __P((struct am7930_softc *, int));
111 1.1 augustss void bba_codec_iwrite __P((struct am7930_softc *, int, u_int8_t));
112 1.1 augustss void bba_codec_iwrite16 __P((struct am7930_softc *, int, u_int16_t));
113 1.1 augustss void bba_onopen __P((struct am7930_softc *sc));
114 1.1 augustss void bba_onclose __P((struct am7930_softc *sc));
115 1.1 augustss void bba_output_conv __P((void *, u_int8_t *, int));
116 1.1 augustss void bba_input_conv __P((void *, u_int8_t *, int));
117 1.1 augustss
118 1.1 augustss struct am7930_glue bba_glue = {
119 1.1 augustss bba_codec_iread,
120 1.1 augustss bba_codec_iwrite,
121 1.1 augustss bba_codec_iread16,
122 1.1 augustss bba_codec_iwrite16,
123 1.1 augustss bba_onopen,
124 1.1 augustss bba_onclose,
125 1.1 augustss 4,
126 1.1 augustss bba_input_conv,
127 1.1 augustss bba_output_conv,
128 1.1 augustss };
129 1.1 augustss
130 1.1 augustss /*
131 1.1 augustss * Define our interface to the higher level audio driver.
132 1.1 augustss */
133 1.1 augustss
134 1.1 augustss int bba_round_blocksize __P((void *, int));
135 1.1 augustss int bba_halt_output __P((void *));
136 1.1 augustss int bba_halt_input __P((void *));
137 1.1 augustss int bba_getdev __P((void *, struct audio_device *));
138 1.1 augustss void *bba_allocm __P((void *, int, size_t, int, int));
139 1.1 augustss void bba_freem __P((void *, void *, int));
140 1.1 augustss size_t bba_round_buffersize __P((void *, int, size_t));
141 1.1 augustss int bba_trigger_output __P((void *, void *, void *, int,
142 1.1 augustss void (*)(void *), void *, struct audio_params *));
143 1.1 augustss int bba_trigger_input __P((void *, void *, void *, int,
144 1.1 augustss void (*)(void *), void *, struct audio_params *));
145 1.1 augustss
146 1.1 augustss struct audio_hw_if sa_hw_if = {
147 1.1 augustss am7930_open,
148 1.1 augustss am7930_close,
149 1.1 augustss 0,
150 1.1 augustss am7930_query_encoding,
151 1.1 augustss am7930_set_params,
152 1.1 augustss bba_round_blocksize, /* md */
153 1.1 augustss am7930_commit_settings,
154 1.1 augustss 0,
155 1.1 augustss 0,
156 1.1 augustss 0,
157 1.1 augustss 0,
158 1.1 augustss bba_halt_output, /* md */
159 1.1 augustss bba_halt_input, /* md */
160 1.1 augustss 0,
161 1.1 augustss bba_getdev,
162 1.1 augustss 0,
163 1.1 augustss am7930_set_port,
164 1.1 augustss am7930_get_port,
165 1.1 augustss am7930_query_devinfo,
166 1.1 augustss bba_allocm, /* md */
167 1.1 augustss bba_freem, /* md */
168 1.1 augustss bba_round_buffersize, /* md */
169 1.1 augustss 0,
170 1.1 augustss am7930_get_props,
171 1.1 augustss bba_trigger_output, /* md */
172 1.1 augustss bba_trigger_input /* md */
173 1.1 augustss };
174 1.1 augustss
175 1.1 augustss struct audio_device bba_device = {
176 1.1 augustss "am7930",
177 1.1 augustss "x",
178 1.1 augustss "bba"
179 1.1 augustss };
180 1.1 augustss
181 1.1 augustss int bba_intr __P((void *));
182 1.1 augustss void bba_reset __P((struct bba_softc *, int));
183 1.1 augustss void bba_codec_dwrite __P((struct am7930_softc *, int, u_int8_t));
184 1.1 augustss u_int8_t bba_codec_dread __P((struct am7930_softc *, int));
185 1.1 augustss
186 1.1 augustss int bba_match(parent, cf, aux)
187 1.1 augustss struct device *parent;
188 1.1 augustss struct cfdata *cf;
189 1.1 augustss void *aux;
190 1.1 augustss {
191 1.1 augustss struct ioasicdev_attach_args *ia = aux;
192 1.1 augustss
193 1.1 augustss if (strcmp(ia->iada_modname, "isdn") != 0 &&
194 1.1 augustss strcmp(ia->iada_modname, "AMD79c30") != 0)
195 1.1 augustss return 0;
196 1.1 augustss
197 1.1 augustss return 1;
198 1.1 augustss }
199 1.1 augustss
200 1.1 augustss
201 1.1 augustss void
202 1.1 augustss bba_attach(parent, self, aux)
203 1.1 augustss struct device *parent;
204 1.1 augustss struct device *self;
205 1.1 augustss void *aux;
206 1.1 augustss {
207 1.1 augustss struct ioasicdev_attach_args *ia = aux;
208 1.1 augustss struct bba_softc *sc = (struct bba_softc *)self;
209 1.1 augustss struct am7930_softc *asc = &sc->sc_am7930;
210 1.1 augustss
211 1.1 augustss sc->sc_bst = ((struct ioasic_softc *)parent)->sc_bst;
212 1.1 augustss sc->sc_bsh = ((struct ioasic_softc *)parent)->sc_bsh;
213 1.1 augustss sc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat;
214 1.1 augustss
215 1.1 augustss /* get the bus space handle for codec */
216 1.1 augustss if (bus_space_subregion(sc->sc_bst, sc->sc_bsh,
217 1.1 augustss ia->iada_offset, 0, &sc->sc_codec_bsh)) {
218 1.1 augustss printf("%s: unable to map device\n", asc->sc_dev.dv_xname);
219 1.1 augustss return;
220 1.1 augustss }
221 1.1 augustss
222 1.1 augustss printf("\n");
223 1.1 augustss
224 1.1 augustss bba_reset(sc,1);
225 1.1 augustss
226 1.1 augustss /*
227 1.1 augustss * Set up glue for MI code early; we use some of it here.
228 1.1 augustss */
229 1.1 augustss asc->sc_glue = &bba_glue;
230 1.1 augustss
231 1.1 augustss /*
232 1.1 augustss * MI initialisation. We will be doing DMA.
233 1.1 augustss */
234 1.1 augustss am7930_init(asc, AUDIOAMD_DMA_MODE);
235 1.1 augustss
236 1.1 augustss ioasic_intr_establish(parent, ia->iada_cookie, TC_IPL_NONE,
237 1.1 augustss bba_intr, sc);
238 1.1 augustss
239 1.1 augustss audio_attach_mi(&sa_hw_if, asc, &asc->sc_dev);
240 1.1 augustss }
241 1.1 augustss
242 1.1 augustss
243 1.1 augustss void
244 1.1 augustss bba_onopen(sc)
245 1.1 augustss struct am7930_softc *sc;
246 1.1 augustss {
247 1.1 augustss bba_reset((struct bba_softc *)sc, 0);
248 1.1 augustss }
249 1.1 augustss
250 1.1 augustss
251 1.1 augustss void
252 1.1 augustss bba_onclose(sc)
253 1.1 augustss struct am7930_softc *sc;
254 1.1 augustss {
255 1.1 augustss bba_halt_input((struct bba_softc *)sc);
256 1.1 augustss bba_halt_output((struct bba_softc *)sc);
257 1.1 augustss }
258 1.1 augustss
259 1.1 augustss
260 1.1 augustss void
261 1.1 augustss bba_reset(sc, reset)
262 1.1 augustss struct bba_softc *sc;
263 1.1 augustss int reset;
264 1.1 augustss {
265 1.1 augustss u_int32_t ssr;
266 1.1 augustss
267 1.1 augustss /* disable any DMA and reset the codec */
268 1.1 augustss ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
269 1.1 augustss ssr &= ~(IOASIC_CSR_DMAEN_ISDN_T | IOASIC_CSR_DMAEN_ISDN_R);
270 1.1 augustss if (reset)
271 1.1 augustss ssr &= ~IOASIC_CSR_ISDN_ENABLE;
272 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
273 1.1 augustss DELAY(10); /* 400ns required for codec to reset */
274 1.1 augustss
275 1.1 augustss /* initialise DMA pointers */
276 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR, -1);
277 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR, -1);
278 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR, -1);
279 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR, -1);
280 1.1 augustss
281 1.1 augustss /* take out of reset state */
282 1.1 augustss if (reset) {
283 1.1 augustss ssr |= IOASIC_CSR_ISDN_ENABLE;
284 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
285 1.1 augustss }
286 1.1 augustss
287 1.1 augustss }
288 1.1 augustss
289 1.1 augustss
290 1.1 augustss void *
291 1.1 augustss bba_allocm(addr, direction, size, pool, flags)
292 1.1 augustss void *addr;
293 1.1 augustss int direction;
294 1.1 augustss size_t size;
295 1.1 augustss int pool, flags;
296 1.1 augustss {
297 1.1 augustss struct am7930_softc *asc = addr;
298 1.1 augustss struct bba_softc *sc = addr;
299 1.1 augustss bus_dma_segment_t seg;
300 1.1 augustss int rseg;
301 1.1 augustss caddr_t kva;
302 1.1 augustss struct bba_mem *m;
303 1.1 augustss int state = 0;
304 1.1 augustss
305 1.1 augustss DPRINTF(("bba_allocm: size = %d\n",size));
306 1.1 augustss
307 1.1 augustss if (bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg,
308 1.1 augustss 1, &rseg, BUS_DMA_NOWAIT)) {
309 1.1 augustss printf("%s: can't allocate DMA buffer\n",
310 1.1 augustss asc->sc_dev.dv_xname);
311 1.1 augustss goto bad;
312 1.1 augustss }
313 1.1 augustss state |= 1;
314 1.1 augustss
315 1.1 augustss if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, size,
316 1.1 augustss &kva, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
317 1.1 augustss printf("%s: can't map DMA buffer\n", asc->sc_dev.dv_xname);
318 1.1 augustss goto bad;
319 1.1 augustss }
320 1.1 augustss state |= 2;
321 1.1 augustss
322 1.1 augustss m = malloc(sizeof(struct bba_mem), pool, flags);
323 1.1 augustss if (m == NULL)
324 1.1 augustss goto bad;
325 1.1 augustss m->addr = seg.ds_addr;
326 1.1 augustss m->size = seg.ds_len;
327 1.1 augustss m->kva = kva;
328 1.1 augustss m->next = sc->sc_mem_head;
329 1.1 augustss sc->sc_mem_head = m;
330 1.1 augustss
331 1.1 augustss return (void *)kva;
332 1.1 augustss
333 1.1 augustss bad:
334 1.1 augustss if (state & 2)
335 1.1 augustss bus_dmamem_unmap(sc->sc_dmat, kva, size);
336 1.1 augustss if (state & 1)
337 1.1 augustss bus_dmamem_free(sc->sc_dmat, &seg, 1);
338 1.1 augustss return NULL;
339 1.1 augustss }
340 1.1 augustss
341 1.1 augustss
342 1.1 augustss void
343 1.1 augustss bba_freem(addr, ptr, pool)
344 1.1 augustss void *addr;
345 1.1 augustss void *ptr;
346 1.1 augustss int pool;
347 1.1 augustss {
348 1.1 augustss struct bba_softc *sc = addr;
349 1.1 augustss struct bba_mem **mp, *m;
350 1.1 augustss bus_dma_segment_t seg;
351 1.1 augustss caddr_t kva = (caddr_t)addr;
352 1.1 augustss
353 1.1 augustss for (mp = &sc->sc_mem_head; *mp && (*mp)->kva != kva;
354 1.1 augustss mp = &(*mp)->next)
355 1.1 augustss /* nothing */ ;
356 1.1 augustss m = *mp;
357 1.1 augustss if (m != NULL) {
358 1.1 augustss printf("bba_freem: freeing unallocted memory\n");
359 1.1 augustss return;
360 1.1 augustss }
361 1.1 augustss *mp = m->next;
362 1.1 augustss bus_dmamem_unmap(sc->sc_dmat, kva, m->size);
363 1.1 augustss
364 1.1 augustss seg.ds_addr = m->addr;
365 1.1 augustss seg.ds_len = m->size;
366 1.1 augustss bus_dmamem_free(sc->sc_dmat, &seg, 1);
367 1.1 augustss free(m, pool);
368 1.1 augustss }
369 1.1 augustss
370 1.1 augustss
371 1.1 augustss size_t
372 1.1 augustss bba_round_buffersize(addr, direction, size)
373 1.1 augustss void *addr;
374 1.1 augustss int direction;
375 1.1 augustss size_t size;
376 1.1 augustss {
377 1.1 augustss DPRINTF(("bba_round_buffersize: size=%d\n", size));
378 1.1 augustss
379 1.1 augustss #define BBA_BUFFERSIZE (BBA_MAX_DMA_SEGMENTS * PAGE_SIZE)
380 1.1 augustss return (size > BBA_BUFFERSIZE ? BBA_BUFFERSIZE : round_page(size));
381 1.1 augustss }
382 1.1 augustss
383 1.1 augustss
384 1.1 augustss int
385 1.1 augustss bba_halt_output(addr)
386 1.1 augustss void *addr;
387 1.1 augustss {
388 1.1 augustss struct bba_softc *sc = addr;
389 1.1 augustss struct bba_dma_state *d = &sc->sc_tx_dma_state;
390 1.1 augustss u_int32_t ssr;
391 1.1 augustss
392 1.1 augustss /* disable any DMA */
393 1.1 augustss ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
394 1.1 augustss ssr &= ~IOASIC_CSR_DMAEN_ISDN_T;
395 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
396 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR, -1);
397 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR, -1);
398 1.1 augustss
399 1.1 augustss if (d->active) {
400 1.1 augustss bus_dmamap_unload(sc->sc_dmat, d->dmam);
401 1.1 augustss bus_dmamap_destroy(sc->sc_dmat, d->dmam);
402 1.1 augustss d->active = 0;
403 1.1 augustss }
404 1.1 augustss
405 1.1 augustss return 0;
406 1.1 augustss }
407 1.1 augustss
408 1.1 augustss
409 1.1 augustss int
410 1.1 augustss bba_halt_input(addr)
411 1.1 augustss void *addr;
412 1.1 augustss {
413 1.1 augustss struct bba_softc *sc = addr;
414 1.1 augustss struct bba_dma_state *d = &sc->sc_rx_dma_state;
415 1.1 augustss u_int32_t ssr;
416 1.1 augustss
417 1.1 augustss /* disable any DMA */
418 1.1 augustss ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
419 1.1 augustss ssr &= ~IOASIC_CSR_DMAEN_ISDN_R;
420 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
421 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR, -1);
422 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR, -1);
423 1.1 augustss
424 1.1 augustss if (d->active) {
425 1.1 augustss bus_dmamap_unload(sc->sc_dmat, d->dmam);
426 1.1 augustss bus_dmamap_destroy(sc->sc_dmat, d->dmam);
427 1.1 augustss d->active = 0;
428 1.1 augustss }
429 1.1 augustss
430 1.1 augustss return 0;
431 1.1 augustss }
432 1.1 augustss
433 1.1 augustss
434 1.1 augustss int
435 1.1 augustss bba_getdev(addr, retp)
436 1.1 augustss void *addr;
437 1.1 augustss struct audio_device *retp;
438 1.1 augustss {
439 1.1 augustss *retp = bba_device;
440 1.1 augustss return 0;
441 1.1 augustss }
442 1.1 augustss
443 1.1 augustss
444 1.1 augustss int
445 1.1 augustss bba_trigger_output(addr, start, end, blksize, intr, arg, param)
446 1.1 augustss void *addr;
447 1.1 augustss void *start, *end;
448 1.1 augustss int blksize;
449 1.1 augustss void (*intr) __P((void *));
450 1.1 augustss void *arg;
451 1.1 augustss struct audio_params *param;
452 1.1 augustss {
453 1.1 augustss struct bba_softc *sc = addr;
454 1.1 augustss struct bba_dma_state *d = &sc->sc_tx_dma_state;
455 1.1 augustss u_int32_t ssr;
456 1.1 augustss tc_addr_t phys, nphys;
457 1.1 augustss int state = 0;
458 1.1 augustss
459 1.1 augustss DPRINTF(("bba_trigger_output: sc=%p start=%p end=%p blksize=%d intr=%p(%p)\n",
460 1.1 augustss addr, start, end, blksize, intr, arg));
461 1.1 augustss
462 1.1 augustss if (bus_dmamap_create(sc->sc_dmat, (char *)end - (char *)start,
463 1.1 augustss BBA_MAX_DMA_SEGMENTS, PAGE_SIZE, 0, BUS_DMA_NOWAIT, &d->dmam)) {
464 1.1 augustss printf("bba_trigger_output: can't create DMA map\n");
465 1.1 augustss goto bad;
466 1.1 augustss }
467 1.1 augustss state |= 1;
468 1.1 augustss
469 1.1 augustss if (bus_dmamap_load(sc->sc_dmat, d->dmam, start,
470 1.1 augustss (char *)end - (char *)start, NULL, BUS_DMA_NOWAIT)) {
471 1.1 augustss printf("bba_trigger_output: can't load DMA map\n");
472 1.1 augustss goto bad;
473 1.1 augustss }
474 1.1 augustss state |= 2;
475 1.1 augustss
476 1.1 augustss /* disable any DMA */
477 1.1 augustss ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
478 1.1 augustss ssr &= ~IOASIC_CSR_DMAEN_ISDN_T;
479 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
480 1.1 augustss
481 1.1 augustss d->intr = intr;
482 1.1 augustss d->intr_arg = arg;
483 1.1 augustss d->curseg = 1;
484 1.1 augustss
485 1.1 augustss /* get physical address of buffer start */
486 1.2 gmcgarry phys = (tc_addr_t)d->dmam->dm_segs[0].ds_addr;
487 1.2 gmcgarry nphys = (tc_addr_t)d->dmam->dm_segs[1].ds_addr;
488 1.1 augustss
489 1.1 augustss /* setup DMA pointer */
490 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR,
491 1.1 augustss IOASIC_DMA_ADDR(phys));
492 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR,
493 1.1 augustss IOASIC_DMA_ADDR(nphys));
494 1.1 augustss
495 1.1 augustss /* kick off DMA */
496 1.1 augustss ssr |= IOASIC_CSR_DMAEN_ISDN_T;
497 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
498 1.1 augustss
499 1.1 augustss d->active = 1;
500 1.1 augustss
501 1.1 augustss return 0;
502 1.1 augustss
503 1.1 augustss bad:
504 1.1 augustss if (state & 2)
505 1.1 augustss bus_dmamap_unload(sc->sc_dmat, d->dmam);
506 1.1 augustss if (state & 1)
507 1.1 augustss bus_dmamap_destroy(sc->sc_dmat, d->dmam);
508 1.1 augustss return 1;
509 1.1 augustss }
510 1.1 augustss
511 1.1 augustss
512 1.1 augustss int
513 1.1 augustss bba_trigger_input(addr, start, end, blksize, intr, arg, param)
514 1.1 augustss void *addr;
515 1.1 augustss void *start, *end;
516 1.1 augustss int blksize;
517 1.1 augustss void (*intr) __P((void *));
518 1.1 augustss void *arg;
519 1.1 augustss struct audio_params *param;
520 1.1 augustss {
521 1.1 augustss struct bba_softc *sc = (struct bba_softc *)addr;
522 1.1 augustss struct bba_dma_state *d = &sc->sc_rx_dma_state;
523 1.1 augustss tc_addr_t phys, nphys;
524 1.1 augustss u_int32_t ssr;
525 1.1 augustss int state = 0;
526 1.1 augustss
527 1.1 augustss DPRINTF(("bba_trigger_input: sc=%p start=%p end=%p blksize=%d intr=%p(%p)\n",
528 1.1 augustss addr, start, end, blksize, intr, arg));
529 1.1 augustss
530 1.1 augustss if (bus_dmamap_create(sc->sc_dmat, (char *)end - (char *)start,
531 1.1 augustss BBA_MAX_DMA_SEGMENTS, PAGE_SIZE, 0, BUS_DMA_NOWAIT, &d->dmam)) {
532 1.1 augustss printf("bba_trigger_input: can't create DMA map\n");
533 1.1 augustss goto bad;
534 1.1 augustss }
535 1.1 augustss state |= 1;
536 1.1 augustss
537 1.1 augustss if (bus_dmamap_load(sc->sc_dmat, d->dmam, start,
538 1.1 augustss (char *)end - (char *)start, NULL, BUS_DMA_NOWAIT)) {
539 1.1 augustss printf("bba_trigger_input: can't load DMA map\n");
540 1.1 augustss goto bad;
541 1.1 augustss }
542 1.1 augustss state |= 2;
543 1.1 augustss
544 1.1 augustss /* disable any DMA */
545 1.1 augustss ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
546 1.1 augustss ssr &= ~IOASIC_CSR_DMAEN_ISDN_R;
547 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
548 1.1 augustss
549 1.1 augustss d->intr = intr;
550 1.1 augustss d->intr_arg = arg;
551 1.1 augustss d->curseg = 1;
552 1.1 augustss
553 1.1 augustss /* get physical address of buffer start */
554 1.2 gmcgarry phys = (tc_addr_t)d->dmam->dm_segs[0].ds_addr;
555 1.2 gmcgarry nphys = (tc_addr_t)d->dmam->dm_segs[1].ds_addr;
556 1.1 augustss
557 1.1 augustss /* setup DMA pointer */
558 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR,
559 1.1 augustss IOASIC_DMA_ADDR(phys));
560 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR,
561 1.1 augustss IOASIC_DMA_ADDR(nphys));
562 1.1 augustss
563 1.1 augustss /* kick off DMA */
564 1.1 augustss ssr |= IOASIC_CSR_DMAEN_ISDN_R;
565 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
566 1.1 augustss
567 1.1 augustss d->active = 1;
568 1.1 augustss
569 1.1 augustss return 0;
570 1.1 augustss
571 1.1 augustss bad:
572 1.1 augustss if (state & 2)
573 1.1 augustss bus_dmamap_unload(sc->sc_dmat, d->dmam);
574 1.1 augustss if (state & 1)
575 1.1 augustss bus_dmamap_destroy(sc->sc_dmat, d->dmam);
576 1.1 augustss return 1;
577 1.1 augustss }
578 1.1 augustss
579 1.1 augustss int
580 1.1 augustss bba_intr(addr)
581 1.1 augustss void *addr;
582 1.1 augustss {
583 1.1 augustss struct bba_softc *sc = addr;
584 1.1 augustss struct bba_dma_state *d;
585 1.1 augustss tc_addr_t nphys;
586 1.1 augustss int s, mask;
587 1.1 augustss
588 1.1 augustss s = splaudio();
589 1.1 augustss
590 1.1 augustss mask = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_INTR);
591 1.1 augustss
592 1.1 augustss if (mask & IOASIC_INTR_ISDN_TXLOAD) {
593 1.1 augustss d = &sc->sc_tx_dma_state;
594 1.1 augustss d->curseg = (d->curseg+1) % d->dmam->dm_nsegs;
595 1.1 augustss nphys = (tc_addr_t)d->dmam->dm_segs[d->curseg].ds_addr;
596 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh,
597 1.1 augustss IOASIC_ISDN_X_NEXTPTR, IOASIC_DMA_ADDR(nphys));
598 1.1 augustss if (d->intr != NULL)
599 1.1 augustss (*d->intr)(d->intr_arg);
600 1.1 augustss }
601 1.1 augustss if (mask & IOASIC_INTR_ISDN_RXLOAD) {
602 1.1 augustss d = &sc->sc_rx_dma_state;
603 1.1 augustss d->curseg = (d->curseg+1) % d->dmam->dm_nsegs;
604 1.1 augustss nphys = (tc_addr_t)d->dmam->dm_segs[d->curseg].ds_addr;
605 1.1 augustss bus_space_write_4(sc->sc_bst, sc->sc_bsh,
606 1.1 augustss IOASIC_ISDN_R_NEXTPTR, IOASIC_DMA_ADDR(nphys));
607 1.1 augustss if (d->intr != NULL)
608 1.1 augustss (*d->intr)(d->intr_arg);
609 1.1 augustss }
610 1.1 augustss
611 1.1 augustss splx(s);
612 1.1 augustss
613 1.1 augustss return 0;
614 1.1 augustss }
615 1.1 augustss
616 1.1 augustss
617 1.1 augustss void
618 1.1 augustss bba_input_conv(v, p, cc)
619 1.1 augustss void *v;
620 1.1 augustss u_int8_t *p;
621 1.1 augustss int cc;
622 1.1 augustss {
623 1.1 augustss u_int8_t *q = p;
624 1.1 augustss
625 1.1 augustss DPRINTF(("bba_input_conv(): v=%p p=%p cc=%d\n", v, p, cc));
626 1.1 augustss
627 1.1 augustss /*
628 1.1 augustss * p points start of buffer
629 1.1 augustss * cc is the number of bytes in the destination buffer
630 1.1 augustss */
631 1.1 augustss
632 1.1 augustss while (--cc >= 0) {
633 1.1 augustss *p = ((*(u_int32_t *)q)>>16)&0xff;
634 1.1 augustss q += 4;
635 1.1 augustss p++;
636 1.1 augustss }
637 1.1 augustss }
638 1.1 augustss
639 1.1 augustss
640 1.1 augustss void
641 1.1 augustss bba_output_conv(v, p, cc)
642 1.1 augustss void *v;
643 1.1 augustss u_int8_t *p;
644 1.1 augustss int cc;
645 1.1 augustss {
646 1.1 augustss u_int8_t *q = p;
647 1.1 augustss
648 1.1 augustss DPRINTF(("bba_output_conv(): v=%p p=%p cc=%d\n", v, p, cc));
649 1.1 augustss
650 1.1 augustss /*
651 1.1 augustss * p points start of buffer
652 1.1 augustss * cc is the number of bytes in the source buffer
653 1.1 augustss */
654 1.1 augustss
655 1.1 augustss p += cc;
656 1.1 augustss q += cc * 4;
657 1.1 augustss while (--cc >= 0) {
658 1.1 augustss q -= 4;
659 1.1 augustss p -= 1;
660 1.1 augustss *(u_int32_t *)q = (*p<<16);
661 1.1 augustss }
662 1.1 augustss }
663 1.1 augustss
664 1.1 augustss
665 1.1 augustss int
666 1.1 augustss bba_round_blocksize(addr, blk)
667 1.1 augustss void *addr;
668 1.1 augustss int blk;
669 1.1 augustss {
670 1.1 augustss return (PAGE_SIZE);
671 1.1 augustss }
672 1.1 augustss
673 1.1 augustss
674 1.1 augustss /* indirect write */
675 1.1 augustss void
676 1.1 augustss bba_codec_iwrite(sc, reg, val)
677 1.1 augustss struct am7930_softc *sc;
678 1.1 augustss int reg;
679 1.1 augustss u_int8_t val;
680 1.1 augustss {
681 1.1 augustss DPRINTF(("bba_codec_iwrite(): sc=%p, reg=%d, val=%d\n",sc,reg,val));
682 1.1 augustss
683 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
684 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_DR, val);
685 1.1 augustss }
686 1.1 augustss
687 1.1 augustss
688 1.1 augustss void
689 1.1 augustss bba_codec_iwrite16(sc, reg, val)
690 1.1 augustss struct am7930_softc *sc;
691 1.1 augustss int reg;
692 1.1 augustss u_int16_t val;
693 1.1 augustss {
694 1.1 augustss DPRINTF(("bba_codec_iwrite16(): sc=%p, reg=%d, val=%d\n",sc,reg,val));
695 1.1 augustss
696 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
697 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_DR, val);
698 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_DR, val>>8);
699 1.1 augustss }
700 1.1 augustss
701 1.1 augustss
702 1.1 augustss u_int16_t
703 1.1 augustss bba_codec_iread16(sc, reg)
704 1.1 augustss struct am7930_softc *sc;
705 1.1 augustss int reg;
706 1.1 augustss {
707 1.1 augustss u_int16_t val;
708 1.1 augustss DPRINTF(("bba_codec_iread16(): sc=%p, reg=%d\n",sc,reg));
709 1.1 augustss
710 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
711 1.1 augustss val = bba_codec_dread(sc, AM7930_DREG_DR) << 8;
712 1.1 augustss val |= bba_codec_dread(sc, AM7930_DREG_DR);
713 1.1 augustss
714 1.1 augustss return val;
715 1.1 augustss }
716 1.1 augustss
717 1.1 augustss
718 1.1 augustss /* indirect read */
719 1.1 augustss u_int8_t
720 1.1 augustss bba_codec_iread(sc, reg)
721 1.1 augustss struct am7930_softc *sc;
722 1.1 augustss int reg;
723 1.1 augustss {
724 1.1 augustss u_int8_t val;
725 1.1 augustss
726 1.1 augustss DPRINTF(("bba_codec_iread(): sc=%p, reg=%d\n",sc,reg));
727 1.1 augustss
728 1.1 augustss bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
729 1.1 augustss val = bba_codec_dread(sc, AM7930_DREG_DR);
730 1.1 augustss
731 1.1 augustss DPRINTF(("read 0x%x (%d)\n", val, val));
732 1.1 augustss
733 1.1 augustss return val;
734 1.1 augustss }
735 1.1 augustss
736 1.1 augustss
737 1.1 augustss #define TIMETOWASTE 50
738 1.1 augustss
739 1.1 augustss /* direct write */
740 1.1 augustss void
741 1.1 augustss bba_codec_dwrite(asc, reg, val)
742 1.1 augustss struct am7930_softc *asc;
743 1.1 augustss int reg;
744 1.1 augustss u_int8_t val;
745 1.1 augustss {
746 1.1 augustss struct bba_softc *sc = (struct bba_softc *)asc;
747 1.1 augustss int i;
748 1.1 augustss
749 1.1 augustss DPRINTF(("bba_codec_dwrite(): sc=%p, reg=%d, val=%d\n",sc,reg,val));
750 1.1 augustss
751 1.5 gmcgarry bus_space_write_4(sc->sc_bst, sc->sc_codec_bsh,
752 1.5 gmcgarry (reg<<BBA_REGISTER_SHIFT), val);
753 1.1 augustss
754 1.1 augustss for (i=0; i<TIMETOWASTE; i++) {};
755 1.1 augustss }
756 1.1 augustss
757 1.1 augustss /* direct read */
758 1.1 augustss u_int8_t
759 1.1 augustss bba_codec_dread(asc, reg)
760 1.1 augustss struct am7930_softc *asc;
761 1.1 augustss int reg;
762 1.1 augustss {
763 1.1 augustss struct bba_softc *sc = (struct bba_softc *)asc;
764 1.1 augustss u_int8_t val;
765 1.1 augustss int i;
766 1.1 augustss
767 1.1 augustss DPRINTF(("bba_codec_dread(): sc=%p, reg=%d\n",sc,reg));
768 1.1 augustss
769 1.5 gmcgarry val = bus_space_read_1(sc->sc_bst, sc->sc_codec_bsh,
770 1.5 gmcgarry (reg<<BBA_REGISTER_SHIFT));
771 1.1 augustss
772 1.1 augustss for (i=0; i<TIMETOWASTE; i++) {};
773 1.1 augustss
774 1.1 augustss return val;
775 1.1 augustss }
776