bba.c revision 1.10
1 /* $NetBSD: bba.c,v 1.10 2000/07/17 17:43:16 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* maxine/alpha baseboard audio (bba) */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #include <machine/bus.h> 45 #include <machine/autoconf.h> 46 #include <machine/cpu.h> 47 48 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 49 50 #include <sys/audioio.h> 51 #include <dev/audio_if.h> 52 53 #include <dev/ic/am7930reg.h> 54 #include <dev/ic/am7930var.h> 55 56 #include <dev/tc/tcvar.h> 57 #include <dev/tc/ioasicreg.h> 58 #include <dev/tc/ioasicvar.h> 59 60 #ifdef AUDIO_DEBUG 61 #define DPRINTF(x) if (am7930debug) printf x 62 #else 63 #define DPRINTF(x) 64 #endif /* AUDIO_DEBUG */ 65 66 #define BBA_MAX_DMA_SEGMENTS 16 67 #define BBA_DMABUF_SIZE (BBA_MAX_DMA_SEGMENTS*IOASIC_DMA_BLOCKSIZE) 68 #define BBA_DMABUF_ALIGN IOASIC_DMA_BLOCKSIZE 69 #define BBA_DMABUF_BOUNDARY 0 70 71 struct bba_mem { 72 struct bba_mem *next; 73 bus_addr_t addr; 74 bus_size_t size; 75 caddr_t kva; 76 }; 77 78 struct bba_dma_state { 79 bus_dmamap_t dmam; /* dma map */ 80 int active; 81 int curseg; /* current segment in dma buffer */ 82 void (*intr)__P((void *)); /* higher-level audio handler */ 83 void *intr_arg; 84 }; 85 86 struct bba_softc { 87 struct am7930_softc sc_am7930; /* glue to MI code */ 88 89 bus_space_tag_t sc_bst; /* IOASIC bus tag/handle */ 90 bus_space_handle_t sc_bsh; 91 bus_dma_tag_t sc_dmat; 92 bus_space_handle_t sc_codec_bsh; /* codec bus space handle */ 93 94 struct bba_mem *sc_mem_head; /* list of buffers */ 95 96 struct bba_dma_state sc_tx_dma_state; 97 struct bba_dma_state sc_rx_dma_state; 98 }; 99 100 int bba_match __P((struct device *, struct cfdata *, void *)); 101 void bba_attach __P((struct device *, struct device *, void *)); 102 103 struct cfattach bba_ca = { 104 sizeof(struct bba_softc), bba_match, bba_attach 105 }; 106 107 /* 108 * Define our interface into the am7930 MI driver. 109 */ 110 111 u_int8_t bba_codec_iread __P((struct am7930_softc *, int)); 112 u_int16_t bba_codec_iread16 __P((struct am7930_softc *, int)); 113 void bba_codec_iwrite __P((struct am7930_softc *, int, u_int8_t)); 114 void bba_codec_iwrite16 __P((struct am7930_softc *, int, u_int16_t)); 115 void bba_onopen __P((struct am7930_softc *sc)); 116 void bba_onclose __P((struct am7930_softc *sc)); 117 void bba_output_conv __P((void *, u_int8_t *, int)); 118 void bba_input_conv __P((void *, u_int8_t *, int)); 119 120 struct am7930_glue bba_glue = { 121 bba_codec_iread, 122 bba_codec_iwrite, 123 bba_codec_iread16, 124 bba_codec_iwrite16, 125 bba_onopen, 126 bba_onclose, 127 4, 128 bba_input_conv, 129 bba_output_conv, 130 }; 131 132 /* 133 * Define our interface to the higher level audio driver. 134 */ 135 136 int bba_round_blocksize __P((void *, int)); 137 int bba_halt_output __P((void *)); 138 int bba_halt_input __P((void *)); 139 int bba_getdev __P((void *, struct audio_device *)); 140 void *bba_allocm __P((void *, int, size_t, int, int)); 141 void bba_freem __P((void *, void *, int)); 142 size_t bba_round_buffersize __P((void *, int, size_t)); 143 int bba_get_props __P((void *)); 144 paddr_t bba_mappage __P((void *, void *, off_t, int)); 145 int bba_trigger_output __P((void *, void *, void *, int, 146 void (*)(void *), void *, struct audio_params *)); 147 int bba_trigger_input __P((void *, void *, void *, int, 148 void (*)(void *), void *, struct audio_params *)); 149 150 struct audio_hw_if sa_hw_if = { 151 am7930_open, 152 am7930_close, 153 0, 154 am7930_query_encoding, 155 am7930_set_params, 156 bba_round_blocksize, /* md */ 157 am7930_commit_settings, 158 0, 159 0, 160 0, 161 0, 162 bba_halt_output, /* md */ 163 bba_halt_input, /* md */ 164 0, 165 bba_getdev, 166 0, 167 am7930_set_port, 168 am7930_get_port, 169 am7930_query_devinfo, 170 bba_allocm, /* md */ 171 bba_freem, /* md */ 172 bba_round_buffersize, /* md */ 173 bba_mappage, 174 bba_get_props, 175 bba_trigger_output, /* md */ 176 bba_trigger_input /* md */ 177 }; 178 179 struct audio_device bba_device = { 180 "am7930", 181 "x", 182 "bba" 183 }; 184 185 int bba_intr __P((void *)); 186 void bba_reset __P((struct bba_softc *, int)); 187 void bba_codec_dwrite __P((struct am7930_softc *, int, u_int8_t)); 188 u_int8_t bba_codec_dread __P((struct am7930_softc *, int)); 189 190 int bba_match(parent, cf, aux) 191 struct device *parent; 192 struct cfdata *cf; 193 void *aux; 194 { 195 struct ioasicdev_attach_args *ia = aux; 196 197 if (strcmp(ia->iada_modname, "isdn") != 0 && 198 strcmp(ia->iada_modname, "AMD79c30") != 0) 199 return 0; 200 201 return 1; 202 } 203 204 205 void 206 bba_attach(parent, self, aux) 207 struct device *parent; 208 struct device *self; 209 void *aux; 210 { 211 struct ioasicdev_attach_args *ia = aux; 212 struct bba_softc *sc = (struct bba_softc *)self; 213 struct am7930_softc *asc = &sc->sc_am7930; 214 215 sc->sc_bst = ((struct ioasic_softc *)parent)->sc_bst; 216 sc->sc_bsh = ((struct ioasic_softc *)parent)->sc_bsh; 217 sc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat; 218 219 /* get the bus space handle for codec */ 220 if (bus_space_subregion(sc->sc_bst, sc->sc_bsh, 221 ia->iada_offset, 0, &sc->sc_codec_bsh)) { 222 printf("%s: unable to map device\n", asc->sc_dev.dv_xname); 223 return; 224 } 225 226 printf("\n"); 227 228 bba_reset(sc,1); 229 230 /* 231 * Set up glue for MI code early; we use some of it here. 232 */ 233 asc->sc_glue = &bba_glue; 234 235 /* 236 * MI initialisation. We will be doing DMA. 237 */ 238 am7930_init(asc, AUDIOAMD_DMA_MODE); 239 240 ioasic_intr_establish(parent, ia->iada_cookie, TC_IPL_NONE, 241 bba_intr, sc); 242 243 audio_attach_mi(&sa_hw_if, asc, &asc->sc_dev); 244 } 245 246 247 void 248 bba_onopen(sc) 249 struct am7930_softc *sc; 250 { 251 bba_reset((struct bba_softc *)sc, 0); 252 } 253 254 255 void 256 bba_onclose(sc) 257 struct am7930_softc *sc; 258 { 259 bba_halt_input((struct bba_softc *)sc); 260 bba_halt_output((struct bba_softc *)sc); 261 } 262 263 264 void 265 bba_reset(sc, reset) 266 struct bba_softc *sc; 267 int reset; 268 { 269 u_int32_t ssr; 270 271 /* disable any DMA and reset the codec */ 272 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 273 ssr &= ~(IOASIC_CSR_DMAEN_ISDN_T | IOASIC_CSR_DMAEN_ISDN_R); 274 if (reset) 275 ssr &= ~IOASIC_CSR_ISDN_ENABLE; 276 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 277 DELAY(10); /* 400ns required for codec to reset */ 278 279 /* initialise DMA pointers */ 280 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR, -1); 281 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR, -1); 282 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR, -1); 283 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR, -1); 284 285 /* take out of reset state */ 286 if (reset) { 287 ssr |= IOASIC_CSR_ISDN_ENABLE; 288 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 289 } 290 291 } 292 293 294 void * 295 bba_allocm(addr, direction, size, pool, flags) 296 void *addr; 297 int direction; 298 size_t size; 299 int pool, flags; 300 { 301 struct am7930_softc *asc = addr; 302 struct bba_softc *sc = addr; 303 bus_dma_segment_t seg; 304 int rseg; 305 caddr_t kva; 306 struct bba_mem *m; 307 int w; 308 int state = 0; 309 310 DPRINTF(("bba_allocm: size = %d\n",size)); 311 312 w = (flags & M_NOWAIT) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK; 313 314 if (bus_dmamem_alloc(sc->sc_dmat, size, BBA_DMABUF_ALIGN, 315 BBA_DMABUF_BOUNDARY, &seg, 1, &rseg, w)) { 316 printf("%s: can't allocate DMA buffer\n", 317 asc->sc_dev.dv_xname); 318 goto bad; 319 } 320 state |= 1; 321 322 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 323 &kva, w | BUS_DMA_COHERENT)) { 324 printf("%s: can't map DMA buffer\n", asc->sc_dev.dv_xname); 325 goto bad; 326 } 327 state |= 2; 328 329 m = malloc(sizeof(struct bba_mem), pool, flags); 330 if (m == NULL) 331 goto bad; 332 m->addr = seg.ds_addr; 333 m->size = seg.ds_len; 334 m->kva = kva; 335 m->next = sc->sc_mem_head; 336 sc->sc_mem_head = m; 337 338 return (void *)kva; 339 340 bad: 341 if (state & 2) 342 bus_dmamem_unmap(sc->sc_dmat, kva, size); 343 if (state & 1) 344 bus_dmamem_free(sc->sc_dmat, &seg, 1); 345 return NULL; 346 } 347 348 349 void 350 bba_freem(addr, ptr, pool) 351 void *addr; 352 void *ptr; 353 int pool; 354 { 355 struct bba_softc *sc = addr; 356 struct bba_mem **mp, *m; 357 bus_dma_segment_t seg; 358 caddr_t kva = (caddr_t)addr; 359 360 for (mp = &sc->sc_mem_head; *mp && (*mp)->kva != kva; 361 mp = &(*mp)->next) 362 /* nothing */ ; 363 m = *mp; 364 if (m == NULL) { 365 printf("bba_freem: freeing unallocated memory\n"); 366 return; 367 } 368 *mp = m->next; 369 bus_dmamem_unmap(sc->sc_dmat, kva, m->size); 370 371 seg.ds_addr = m->addr; 372 seg.ds_len = m->size; 373 bus_dmamem_free(sc->sc_dmat, &seg, 1); 374 free(m, pool); 375 } 376 377 378 size_t 379 bba_round_buffersize(addr, direction, size) 380 void *addr; 381 int direction; 382 size_t size; 383 { 384 DPRINTF(("bba_round_buffersize: size=%d\n", size)); 385 386 return (size > BBA_DMABUF_SIZE ? BBA_DMABUF_SIZE : 387 roundup(size, IOASIC_DMA_BLOCKSIZE)); 388 } 389 390 391 int 392 bba_halt_output(addr) 393 void *addr; 394 { 395 struct bba_softc *sc = addr; 396 struct bba_dma_state *d = &sc->sc_tx_dma_state; 397 u_int32_t ssr; 398 399 /* disable any DMA */ 400 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 401 ssr &= ~IOASIC_CSR_DMAEN_ISDN_T; 402 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 403 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR, -1); 404 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR, -1); 405 406 if (d->active) { 407 bus_dmamap_unload(sc->sc_dmat, d->dmam); 408 bus_dmamap_destroy(sc->sc_dmat, d->dmam); 409 d->active = 0; 410 } 411 412 return 0; 413 } 414 415 416 int 417 bba_halt_input(addr) 418 void *addr; 419 { 420 struct bba_softc *sc = addr; 421 struct bba_dma_state *d = &sc->sc_rx_dma_state; 422 u_int32_t ssr; 423 424 /* disable any DMA */ 425 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 426 ssr &= ~IOASIC_CSR_DMAEN_ISDN_R; 427 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 428 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR, -1); 429 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR, -1); 430 431 if (d->active) { 432 bus_dmamap_unload(sc->sc_dmat, d->dmam); 433 bus_dmamap_destroy(sc->sc_dmat, d->dmam); 434 d->active = 0; 435 } 436 437 return 0; 438 } 439 440 441 int 442 bba_getdev(addr, retp) 443 void *addr; 444 struct audio_device *retp; 445 { 446 *retp = bba_device; 447 return 0; 448 } 449 450 451 int 452 bba_trigger_output(addr, start, end, blksize, intr, arg, param) 453 void *addr; 454 void *start, *end; 455 int blksize; 456 void (*intr) __P((void *)); 457 void *arg; 458 struct audio_params *param; 459 { 460 struct bba_softc *sc = addr; 461 struct bba_dma_state *d = &sc->sc_tx_dma_state; 462 u_int32_t ssr; 463 tc_addr_t phys, nphys; 464 int state = 0; 465 466 DPRINTF(("bba_trigger_output: sc=%p start=%p end=%p blksize=%d intr=%p(%p)\n", 467 addr, start, end, blksize, intr, arg)); 468 469 /* disable any DMA */ 470 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 471 ssr &= ~IOASIC_CSR_DMAEN_ISDN_T; 472 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 473 474 if (bus_dmamap_create(sc->sc_dmat, (char *)end - (char *)start, 475 BBA_MAX_DMA_SEGMENTS, IOASIC_DMA_BLOCKSIZE, 476 BBA_DMABUF_BOUNDARY, BUS_DMA_NOWAIT, &d->dmam)) { 477 printf("bba_trigger_output: can't create DMA map\n"); 478 goto bad; 479 } 480 state |= 1; 481 482 if (bus_dmamap_load(sc->sc_dmat, d->dmam, start, 483 (char *)end - (char *)start, NULL, BUS_DMA_NOWAIT)) { 484 printf("bba_trigger_output: can't load DMA map\n"); 485 goto bad; 486 } 487 state |= 2; 488 489 d->intr = intr; 490 d->intr_arg = arg; 491 d->curseg = 1; 492 493 /* get physical address of buffer start */ 494 phys = (tc_addr_t)d->dmam->dm_segs[0].ds_addr; 495 nphys = (tc_addr_t)d->dmam->dm_segs[1].ds_addr; 496 497 /* setup DMA pointer */ 498 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR, 499 IOASIC_DMA_ADDR(phys)); 500 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR, 501 IOASIC_DMA_ADDR(nphys)); 502 503 /* kick off DMA */ 504 ssr |= IOASIC_CSR_DMAEN_ISDN_T; 505 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 506 507 d->active = 1; 508 509 return 0; 510 511 bad: 512 if (state & 2) 513 bus_dmamap_unload(sc->sc_dmat, d->dmam); 514 if (state & 1) 515 bus_dmamap_destroy(sc->sc_dmat, d->dmam); 516 return 1; 517 } 518 519 520 int 521 bba_trigger_input(addr, start, end, blksize, intr, arg, param) 522 void *addr; 523 void *start, *end; 524 int blksize; 525 void (*intr) __P((void *)); 526 void *arg; 527 struct audio_params *param; 528 { 529 struct bba_softc *sc = (struct bba_softc *)addr; 530 struct bba_dma_state *d = &sc->sc_rx_dma_state; 531 tc_addr_t phys, nphys; 532 u_int32_t ssr; 533 int state = 0; 534 535 DPRINTF(("bba_trigger_input: sc=%p start=%p end=%p blksize=%d intr=%p(%p)\n", 536 addr, start, end, blksize, intr, arg)); 537 538 /* disable any DMA */ 539 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 540 ssr &= ~IOASIC_CSR_DMAEN_ISDN_R; 541 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 542 543 if (bus_dmamap_create(sc->sc_dmat, (char *)end - (char *)start, 544 BBA_MAX_DMA_SEGMENTS, IOASIC_DMA_BLOCKSIZE, 545 BBA_DMABUF_BOUNDARY, BUS_DMA_NOWAIT, &d->dmam)) { 546 printf("bba_trigger_input: can't create DMA map\n"); 547 goto bad; 548 } 549 state |= 1; 550 551 if (bus_dmamap_load(sc->sc_dmat, d->dmam, start, 552 (char *)end - (char *)start, NULL, BUS_DMA_NOWAIT)) { 553 printf("bba_trigger_input: can't load DMA map\n"); 554 goto bad; 555 } 556 state |= 2; 557 558 d->intr = intr; 559 d->intr_arg = arg; 560 d->curseg = 1; 561 562 /* get physical address of buffer start */ 563 phys = (tc_addr_t)d->dmam->dm_segs[0].ds_addr; 564 nphys = (tc_addr_t)d->dmam->dm_segs[1].ds_addr; 565 566 /* setup DMA pointer */ 567 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR, 568 IOASIC_DMA_ADDR(phys)); 569 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR, 570 IOASIC_DMA_ADDR(nphys)); 571 572 /* kick off DMA */ 573 ssr |= IOASIC_CSR_DMAEN_ISDN_R; 574 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 575 576 d->active = 1; 577 578 return 0; 579 580 bad: 581 if (state & 2) 582 bus_dmamap_unload(sc->sc_dmat, d->dmam); 583 if (state & 1) 584 bus_dmamap_destroy(sc->sc_dmat, d->dmam); 585 return 1; 586 } 587 588 int 589 bba_intr(addr) 590 void *addr; 591 { 592 struct bba_softc *sc = addr; 593 struct bba_dma_state *d; 594 tc_addr_t nphys; 595 int s, mask; 596 597 s = splaudio(); 598 599 mask = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_INTR); 600 601 if (mask & IOASIC_INTR_ISDN_TXLOAD) { 602 mask &= ~IOASIC_INTR_ISDN_TXLOAD; 603 d = &sc->sc_tx_dma_state; 604 d->curseg = (d->curseg+1) % d->dmam->dm_nsegs; 605 nphys = (tc_addr_t)d->dmam->dm_segs[d->curseg].ds_addr; 606 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 607 IOASIC_ISDN_X_NEXTPTR, IOASIC_DMA_ADDR(nphys)); 608 if (d->intr != NULL) 609 (*d->intr)(d->intr_arg); 610 } 611 if (mask & IOASIC_INTR_ISDN_RXLOAD) { 612 mask &= ~IOASIC_INTR_ISDN_RXLOAD; 613 d = &sc->sc_rx_dma_state; 614 d->curseg = (d->curseg+1) % d->dmam->dm_nsegs; 615 nphys = (tc_addr_t)d->dmam->dm_segs[d->curseg].ds_addr; 616 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 617 IOASIC_ISDN_R_NEXTPTR, IOASIC_DMA_ADDR(nphys)); 618 if (d->intr != NULL) 619 (*d->intr)(d->intr_arg); 620 } 621 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_INTR, mask); 622 623 splx(s); 624 625 return 0; 626 } 627 628 int 629 bba_get_props(addr) 630 void *addr; 631 { 632 return (AUDIO_PROP_MMAP | am7930_get_props(addr)); 633 } 634 635 paddr_t 636 bba_mappage(addr, mem, offset, prot) 637 void *addr; 638 void *mem; 639 off_t offset; 640 int prot; 641 { 642 struct bba_softc *sc = addr; 643 struct bba_mem **mp; 644 bus_dma_segment_t seg; 645 caddr_t kva = (caddr_t)mem; 646 647 for (mp = &sc->sc_mem_head; *mp && (*mp)->kva != kva; 648 mp = &(*mp)->next) 649 /* nothing */ ; 650 if (*mp == NULL || offset < 0) { 651 return -1; 652 } 653 654 seg.ds_addr = (*mp)->addr; 655 seg.ds_len = (*mp)->size; 656 657 return bus_dmamem_mmap(sc->sc_dmat, &seg, 1, offset, 658 prot, BUS_DMA_WAITOK); 659 } 660 661 662 void 663 bba_input_conv(v, p, cc) 664 void *v; 665 u_int8_t *p; 666 int cc; 667 { 668 u_int8_t *q = p; 669 670 DPRINTF(("bba_input_conv(): v=%p p=%p cc=%d\n", v, p, cc)); 671 672 /* 673 * p points start of buffer 674 * cc is the number of bytes in the destination buffer 675 */ 676 677 while (--cc >= 0) { 678 *p = ((*(u_int32_t *)q)>>16)&0xff; 679 q += 4; 680 p++; 681 } 682 } 683 684 685 void 686 bba_output_conv(v, p, cc) 687 void *v; 688 u_int8_t *p; 689 int cc; 690 { 691 u_int8_t *q = p; 692 693 DPRINTF(("bba_output_conv(): v=%p p=%p cc=%d\n", v, p, cc)); 694 695 /* 696 * p points start of buffer 697 * cc is the number of bytes in the source buffer 698 */ 699 700 p += cc; 701 q += cc * 4; 702 while (--cc >= 0) { 703 q -= 4; 704 p -= 1; 705 *(u_int32_t *)q = (*p<<16); 706 } 707 } 708 709 710 int 711 bba_round_blocksize(addr, blk) 712 void *addr; 713 int blk; 714 { 715 return (PAGE_SIZE); 716 } 717 718 719 /* indirect write */ 720 void 721 bba_codec_iwrite(sc, reg, val) 722 struct am7930_softc *sc; 723 int reg; 724 u_int8_t val; 725 { 726 DPRINTF(("bba_codec_iwrite(): sc=%p, reg=%d, val=%d\n",sc,reg,val)); 727 728 bba_codec_dwrite(sc, AM7930_DREG_CR, reg); 729 bba_codec_dwrite(sc, AM7930_DREG_DR, val); 730 } 731 732 733 void 734 bba_codec_iwrite16(sc, reg, val) 735 struct am7930_softc *sc; 736 int reg; 737 u_int16_t val; 738 { 739 DPRINTF(("bba_codec_iwrite16(): sc=%p, reg=%d, val=%d\n",sc,reg,val)); 740 741 bba_codec_dwrite(sc, AM7930_DREG_CR, reg); 742 bba_codec_dwrite(sc, AM7930_DREG_DR, val); 743 bba_codec_dwrite(sc, AM7930_DREG_DR, val>>8); 744 } 745 746 747 u_int16_t 748 bba_codec_iread16(sc, reg) 749 struct am7930_softc *sc; 750 int reg; 751 { 752 u_int16_t val; 753 DPRINTF(("bba_codec_iread16(): sc=%p, reg=%d\n",sc,reg)); 754 755 bba_codec_dwrite(sc, AM7930_DREG_CR, reg); 756 val = bba_codec_dread(sc, AM7930_DREG_DR) << 8; 757 val |= bba_codec_dread(sc, AM7930_DREG_DR); 758 759 return val; 760 } 761 762 763 /* indirect read */ 764 u_int8_t 765 bba_codec_iread(sc, reg) 766 struct am7930_softc *sc; 767 int reg; 768 { 769 u_int8_t val; 770 771 DPRINTF(("bba_codec_iread(): sc=%p, reg=%d\n",sc,reg)); 772 773 bba_codec_dwrite(sc, AM7930_DREG_CR, reg); 774 val = bba_codec_dread(sc, AM7930_DREG_DR); 775 776 DPRINTF(("read 0x%x (%d)\n", val, val)); 777 778 return val; 779 } 780 781 /* direct write */ 782 void 783 bba_codec_dwrite(asc, reg, val) 784 struct am7930_softc *asc; 785 int reg; 786 u_int8_t val; 787 { 788 struct bba_softc *sc = (struct bba_softc *)asc; 789 790 DPRINTF(("bba_codec_dwrite(): sc=%p, reg=%d, val=%d\n",sc,reg,val)); 791 792 #if defined(__alpha__) 793 bus_space_write_4(sc->sc_bst, sc->sc_codec_bsh, 794 reg << 2, val << 8); 795 #else 796 bus_space_write_4(sc->sc_bst, sc->sc_codec_bsh, 797 reg << 6, val); 798 #endif 799 } 800 801 /* direct read */ 802 u_int8_t 803 bba_codec_dread(asc, reg) 804 struct am7930_softc *asc; 805 int reg; 806 { 807 struct bba_softc *sc = (struct bba_softc *)asc; 808 809 DPRINTF(("bba_codec_dread(): sc=%p, reg=%d\n",sc,reg)); 810 811 #if defined(__alpha__) 812 return ((bus_space_read_4(sc->sc_bst, sc->sc_codec_bsh, 813 reg << 2) >> 8) & 0xff); 814 #else 815 return (bus_space_read_4(sc->sc_bst, sc->sc_codec_bsh, 816 reg << 6) & 0xff); 817 #endif 818 } 819
Indexes created Mon Oct 13 16:09:52 GMT 2025