bba.c revision 1.4
1 /* $NetBSD: bba.c,v 1.4 2000/06/04 22:21:09 gmcgarry Exp $ */ 2 3 /* 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* maxine/alpha baseboard audio (bba) */ 37 38 #include "audio.h" 39 #if NAUDIO > 0 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <machine/bus.h> 48 #include <machine/autoconf.h> 49 #include <machine/cpu.h> 50 51 #include <vm/vm.h> /* for PAGE_SIZE */ 52 53 #include <sys/audioio.h> 54 #include <dev/audio_if.h> 55 56 #include <dev/ic/am7930reg.h> 57 #include <dev/ic/am7930var.h> 58 59 #include <dev/tc/tcvar.h> 60 #include <dev/tc/ioasicreg.h> 61 #include <dev/tc/ioasicvar.h> 62 63 #ifdef AUDIO_DEBUG 64 #define DPRINTF(x) if (am7930debug) printf x 65 #else 66 #define DPRINTF(x) 67 #endif /* AUDIO_DEBUG */ 68 69 #define BBA_MAX_DMA_SEGMENTS 16 70 71 struct bba_mem { 72 bus_addr_t addr; 73 bus_size_t size; 74 caddr_t kva; 75 struct bba_mem *next; 76 }; 77 78 struct bba_dma_state { 79 bus_dmamap_t dmam; /* dma map */ 80 int active; 81 int curseg; /* current segment in dma buffer */ 82 void (*intr)__P((void *)); /* higher-level audio handler */ 83 void *intr_arg; 84 }; 85 86 struct bba_softc { 87 struct am7930_softc sc_am7930; /* glue to MI code */ 88 89 bus_space_tag_t sc_bst; /* IOASIC bus tag/handle */ 90 bus_space_handle_t sc_bsh; 91 bus_dma_tag_t sc_dmat; 92 bus_space_handle_t sc_codec_bsh; /* codec bus space handle */ 93 94 struct bba_mem *sc_mem_head; /* list of buffers */ 95 96 struct bba_dma_state sc_tx_dma_state; 97 struct bba_dma_state sc_rx_dma_state; 98 }; 99 100 int bba_match __P((struct device *, struct cfdata *, void *)); 101 void bba_attach __P((struct device *, struct device *, void *)); 102 103 struct cfattach bba_ca = { 104 sizeof(struct bba_softc), bba_match, bba_attach 105 }; 106 107 /* 108 * Define our interface into the am7930 MI driver. 109 */ 110 111 u_int8_t bba_codec_iread __P((struct am7930_softc *, int)); 112 u_int16_t bba_codec_iread16 __P((struct am7930_softc *, int)); 113 void bba_codec_iwrite __P((struct am7930_softc *, int, u_int8_t)); 114 void bba_codec_iwrite16 __P((struct am7930_softc *, int, u_int16_t)); 115 void bba_onopen __P((struct am7930_softc *sc)); 116 void bba_onclose __P((struct am7930_softc *sc)); 117 void bba_output_conv __P((void *, u_int8_t *, int)); 118 void bba_input_conv __P((void *, u_int8_t *, int)); 119 120 struct am7930_glue bba_glue = { 121 bba_codec_iread, 122 bba_codec_iwrite, 123 bba_codec_iread16, 124 bba_codec_iwrite16, 125 bba_onopen, 126 bba_onclose, 127 4, 128 bba_input_conv, 129 bba_output_conv, 130 }; 131 132 /* 133 * Define our interface to the higher level audio driver. 134 */ 135 136 int bba_round_blocksize __P((void *, int)); 137 int bba_halt_output __P((void *)); 138 int bba_halt_input __P((void *)); 139 int bba_getdev __P((void *, struct audio_device *)); 140 void *bba_allocm __P((void *, int, size_t, int, int)); 141 void bba_freem __P((void *, void *, int)); 142 size_t bba_round_buffersize __P((void *, int, size_t)); 143 int bba_trigger_output __P((void *, void *, void *, int, 144 void (*)(void *), void *, struct audio_params *)); 145 int bba_trigger_input __P((void *, void *, void *, int, 146 void (*)(void *), void *, struct audio_params *)); 147 148 struct audio_hw_if sa_hw_if = { 149 am7930_open, 150 am7930_close, 151 0, 152 am7930_query_encoding, 153 am7930_set_params, 154 bba_round_blocksize, /* md */ 155 am7930_commit_settings, 156 0, 157 0, 158 0, 159 0, 160 bba_halt_output, /* md */ 161 bba_halt_input, /* md */ 162 0, 163 bba_getdev, 164 0, 165 am7930_set_port, 166 am7930_get_port, 167 am7930_query_devinfo, 168 bba_allocm, /* md */ 169 bba_freem, /* md */ 170 bba_round_buffersize, /* md */ 171 0, 172 am7930_get_props, 173 bba_trigger_output, /* md */ 174 bba_trigger_input /* md */ 175 }; 176 177 struct audio_device bba_device = { 178 "am7930", 179 "x", 180 "bba" 181 }; 182 183 int bba_intr __P((void *)); 184 void bba_reset __P((struct bba_softc *, int)); 185 void bba_codec_dwrite __P((struct am7930_softc *, int, u_int8_t)); 186 u_int8_t bba_codec_dread __P((struct am7930_softc *, int)); 187 188 int bba_match(parent, cf, aux) 189 struct device *parent; 190 struct cfdata *cf; 191 void *aux; 192 { 193 struct ioasicdev_attach_args *ia = aux; 194 195 if (strcmp(ia->iada_modname, "isdn") != 0 && 196 strcmp(ia->iada_modname, "AMD79c30") != 0) 197 return 0; 198 199 return 1; 200 } 201 202 203 void 204 bba_attach(parent, self, aux) 205 struct device *parent; 206 struct device *self; 207 void *aux; 208 { 209 struct ioasicdev_attach_args *ia = aux; 210 struct bba_softc *sc = (struct bba_softc *)self; 211 struct am7930_softc *asc = &sc->sc_am7930; 212 213 sc->sc_bst = ((struct ioasic_softc *)parent)->sc_bst; 214 sc->sc_bsh = ((struct ioasic_softc *)parent)->sc_bsh; 215 sc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat; 216 217 /* get the bus space handle for codec */ 218 if (bus_space_subregion(sc->sc_bst, sc->sc_bsh, 219 ia->iada_offset, 0, &sc->sc_codec_bsh)) { 220 printf("%s: unable to map device\n", asc->sc_dev.dv_xname); 221 return; 222 } 223 224 printf("\n"); 225 226 bba_reset(sc,1); 227 228 /* 229 * Set up glue for MI code early; we use some of it here. 230 */ 231 asc->sc_glue = &bba_glue; 232 233 /* 234 * MI initialisation. We will be doing DMA. 235 */ 236 am7930_init(asc, AUDIOAMD_DMA_MODE); 237 238 ioasic_intr_establish(parent, ia->iada_cookie, TC_IPL_NONE, 239 bba_intr, sc); 240 241 audio_attach_mi(&sa_hw_if, asc, &asc->sc_dev); 242 } 243 244 245 void 246 bba_onopen(sc) 247 struct am7930_softc *sc; 248 { 249 bba_reset((struct bba_softc *)sc, 0); 250 } 251 252 253 void 254 bba_onclose(sc) 255 struct am7930_softc *sc; 256 { 257 bba_halt_input((struct bba_softc *)sc); 258 bba_halt_output((struct bba_softc *)sc); 259 } 260 261 262 void 263 bba_reset(sc, reset) 264 struct bba_softc *sc; 265 int reset; 266 { 267 u_int32_t ssr; 268 269 /* disable any DMA and reset the codec */ 270 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 271 ssr &= ~(IOASIC_CSR_DMAEN_ISDN_T | IOASIC_CSR_DMAEN_ISDN_R); 272 if (reset) 273 ssr &= ~IOASIC_CSR_ISDN_ENABLE; 274 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 275 DELAY(10); /* 400ns required for codec to reset */ 276 277 /* initialise DMA pointers */ 278 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR, -1); 279 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR, -1); 280 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR, -1); 281 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR, -1); 282 283 /* take out of reset state */ 284 if (reset) { 285 ssr |= IOASIC_CSR_ISDN_ENABLE; 286 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 287 } 288 289 } 290 291 292 void * 293 bba_allocm(addr, direction, size, pool, flags) 294 void *addr; 295 int direction; 296 size_t size; 297 int pool, flags; 298 { 299 struct am7930_softc *asc = addr; 300 struct bba_softc *sc = addr; 301 bus_dma_segment_t seg; 302 int rseg; 303 caddr_t kva; 304 struct bba_mem *m; 305 int state = 0; 306 307 DPRINTF(("bba_allocm: size = %d\n",size)); 308 309 if (bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 310 1, &rseg, BUS_DMA_NOWAIT)) { 311 printf("%s: can't allocate DMA buffer\n", 312 asc->sc_dev.dv_xname); 313 goto bad; 314 } 315 state |= 1; 316 317 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 318 &kva, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 319 printf("%s: can't map DMA buffer\n", asc->sc_dev.dv_xname); 320 goto bad; 321 } 322 state |= 2; 323 324 m = malloc(sizeof(struct bba_mem), pool, flags); 325 if (m == NULL) 326 goto bad; 327 m->addr = seg.ds_addr; 328 m->size = seg.ds_len; 329 m->kva = kva; 330 m->next = sc->sc_mem_head; 331 sc->sc_mem_head = m; 332 333 return (void *)kva; 334 335 bad: 336 if (state & 2) 337 bus_dmamem_unmap(sc->sc_dmat, kva, size); 338 if (state & 1) 339 bus_dmamem_free(sc->sc_dmat, &seg, 1); 340 return NULL; 341 } 342 343 344 void 345 bba_freem(addr, ptr, pool) 346 void *addr; 347 void *ptr; 348 int pool; 349 { 350 struct bba_softc *sc = addr; 351 struct bba_mem **mp, *m; 352 bus_dma_segment_t seg; 353 caddr_t kva = (caddr_t)addr; 354 355 for (mp = &sc->sc_mem_head; *mp && (*mp)->kva != kva; 356 mp = &(*mp)->next) 357 /* nothing */ ; 358 m = *mp; 359 if (m != NULL) { 360 printf("bba_freem: freeing unallocted memory\n"); 361 return; 362 } 363 *mp = m->next; 364 bus_dmamem_unmap(sc->sc_dmat, kva, m->size); 365 366 seg.ds_addr = m->addr; 367 seg.ds_len = m->size; 368 bus_dmamem_free(sc->sc_dmat, &seg, 1); 369 free(m, pool); 370 } 371 372 373 size_t 374 bba_round_buffersize(addr, direction, size) 375 void *addr; 376 int direction; 377 size_t size; 378 { 379 DPRINTF(("bba_round_buffersize: size=%d\n", size)); 380 381 #define BBA_BUFFERSIZE (BBA_MAX_DMA_SEGMENTS * PAGE_SIZE) 382 return (size > BBA_BUFFERSIZE ? BBA_BUFFERSIZE : round_page(size)); 383 } 384 385 386 int 387 bba_halt_output(addr) 388 void *addr; 389 { 390 struct bba_softc *sc = addr; 391 struct bba_dma_state *d = &sc->sc_tx_dma_state; 392 u_int32_t ssr; 393 394 /* disable any DMA */ 395 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 396 ssr &= ~IOASIC_CSR_DMAEN_ISDN_T; 397 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 398 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR, -1); 399 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR, -1); 400 401 if (d->active) { 402 bus_dmamap_unload(sc->sc_dmat, d->dmam); 403 bus_dmamap_destroy(sc->sc_dmat, d->dmam); 404 d->active = 0; 405 } 406 407 return 0; 408 } 409 410 411 int 412 bba_halt_input(addr) 413 void *addr; 414 { 415 struct bba_softc *sc = addr; 416 struct bba_dma_state *d = &sc->sc_rx_dma_state; 417 u_int32_t ssr; 418 419 /* disable any DMA */ 420 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 421 ssr &= ~IOASIC_CSR_DMAEN_ISDN_R; 422 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 423 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR, -1); 424 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR, -1); 425 426 if (d->active) { 427 bus_dmamap_unload(sc->sc_dmat, d->dmam); 428 bus_dmamap_destroy(sc->sc_dmat, d->dmam); 429 d->active = 0; 430 } 431 432 return 0; 433 } 434 435 436 int 437 bba_getdev(addr, retp) 438 void *addr; 439 struct audio_device *retp; 440 { 441 *retp = bba_device; 442 return 0; 443 } 444 445 446 int 447 bba_trigger_output(addr, start, end, blksize, intr, arg, param) 448 void *addr; 449 void *start, *end; 450 int blksize; 451 void (*intr) __P((void *)); 452 void *arg; 453 struct audio_params *param; 454 { 455 struct bba_softc *sc = addr; 456 struct bba_dma_state *d = &sc->sc_tx_dma_state; 457 u_int32_t ssr; 458 tc_addr_t phys, nphys; 459 int state = 0; 460 461 DPRINTF(("bba_trigger_output: sc=%p start=%p end=%p blksize=%d intr=%p(%p)\n", 462 addr, start, end, blksize, intr, arg)); 463 464 if (bus_dmamap_create(sc->sc_dmat, (char *)end - (char *)start, 465 BBA_MAX_DMA_SEGMENTS, PAGE_SIZE, 0, BUS_DMA_NOWAIT, &d->dmam)) { 466 printf("bba_trigger_output: can't create DMA map\n"); 467 goto bad; 468 } 469 state |= 1; 470 471 if (bus_dmamap_load(sc->sc_dmat, d->dmam, start, 472 (char *)end - (char *)start, NULL, BUS_DMA_NOWAIT)) { 473 printf("bba_trigger_output: can't load DMA map\n"); 474 goto bad; 475 } 476 state |= 2; 477 478 /* disable any DMA */ 479 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 480 ssr &= ~IOASIC_CSR_DMAEN_ISDN_T; 481 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 482 483 d->intr = intr; 484 d->intr_arg = arg; 485 d->curseg = 1; 486 487 /* get physical address of buffer start */ 488 phys = (tc_addr_t)d->dmam->dm_segs[0].ds_addr; 489 nphys = (tc_addr_t)d->dmam->dm_segs[1].ds_addr; 490 491 /* setup DMA pointer */ 492 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_DMAPTR, 493 IOASIC_DMA_ADDR(phys)); 494 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_X_NEXTPTR, 495 IOASIC_DMA_ADDR(nphys)); 496 497 /* kick off DMA */ 498 ssr |= IOASIC_CSR_DMAEN_ISDN_T; 499 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 500 501 d->active = 1; 502 503 return 0; 504 505 bad: 506 if (state & 2) 507 bus_dmamap_unload(sc->sc_dmat, d->dmam); 508 if (state & 1) 509 bus_dmamap_destroy(sc->sc_dmat, d->dmam); 510 return 1; 511 } 512 513 514 int 515 bba_trigger_input(addr, start, end, blksize, intr, arg, param) 516 void *addr; 517 void *start, *end; 518 int blksize; 519 void (*intr) __P((void *)); 520 void *arg; 521 struct audio_params *param; 522 { 523 struct bba_softc *sc = (struct bba_softc *)addr; 524 struct bba_dma_state *d = &sc->sc_rx_dma_state; 525 tc_addr_t phys, nphys; 526 u_int32_t ssr; 527 int state = 0; 528 529 DPRINTF(("bba_trigger_input: sc=%p start=%p end=%p blksize=%d intr=%p(%p)\n", 530 addr, start, end, blksize, intr, arg)); 531 532 if (bus_dmamap_create(sc->sc_dmat, (char *)end - (char *)start, 533 BBA_MAX_DMA_SEGMENTS, PAGE_SIZE, 0, BUS_DMA_NOWAIT, &d->dmam)) { 534 printf("bba_trigger_input: can't create DMA map\n"); 535 goto bad; 536 } 537 state |= 1; 538 539 if (bus_dmamap_load(sc->sc_dmat, d->dmam, start, 540 (char *)end - (char *)start, NULL, BUS_DMA_NOWAIT)) { 541 printf("bba_trigger_input: can't load DMA map\n"); 542 goto bad; 543 } 544 state |= 2; 545 546 /* disable any DMA */ 547 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 548 ssr &= ~IOASIC_CSR_DMAEN_ISDN_R; 549 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 550 551 d->intr = intr; 552 d->intr_arg = arg; 553 d->curseg = 1; 554 555 /* get physical address of buffer start */ 556 phys = (tc_addr_t)d->dmam->dm_segs[0].ds_addr; 557 nphys = (tc_addr_t)d->dmam->dm_segs[1].ds_addr; 558 559 /* setup DMA pointer */ 560 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_DMAPTR, 561 IOASIC_DMA_ADDR(phys)); 562 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_ISDN_R_NEXTPTR, 563 IOASIC_DMA_ADDR(nphys)); 564 565 /* kick off DMA */ 566 ssr |= IOASIC_CSR_DMAEN_ISDN_R; 567 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 568 569 d->active = 1; 570 571 return 0; 572 573 bad: 574 if (state & 2) 575 bus_dmamap_unload(sc->sc_dmat, d->dmam); 576 if (state & 1) 577 bus_dmamap_destroy(sc->sc_dmat, d->dmam); 578 return 1; 579 } 580 581 int 582 bba_intr(addr) 583 void *addr; 584 { 585 struct bba_softc *sc = addr; 586 struct bba_dma_state *d; 587 tc_addr_t nphys; 588 int s, mask; 589 590 s = splaudio(); 591 592 mask = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_INTR); 593 594 if (mask & IOASIC_INTR_ISDN_TXLOAD) { 595 d = &sc->sc_tx_dma_state; 596 d->curseg = (d->curseg+1) % d->dmam->dm_nsegs; 597 nphys = (tc_addr_t)d->dmam->dm_segs[d->curseg].ds_addr; 598 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 599 IOASIC_ISDN_X_NEXTPTR, IOASIC_DMA_ADDR(nphys)); 600 if (d->intr != NULL) 601 (*d->intr)(d->intr_arg); 602 } 603 if (mask & IOASIC_INTR_ISDN_RXLOAD) { 604 d = &sc->sc_rx_dma_state; 605 d->curseg = (d->curseg+1) % d->dmam->dm_nsegs; 606 nphys = (tc_addr_t)d->dmam->dm_segs[d->curseg].ds_addr; 607 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 608 IOASIC_ISDN_R_NEXTPTR, IOASIC_DMA_ADDR(nphys)); 609 if (d->intr != NULL) 610 (*d->intr)(d->intr_arg); 611 } 612 613 splx(s); 614 615 return 0; 616 } 617 618 619 void 620 bba_input_conv(v, p, cc) 621 void *v; 622 u_int8_t *p; 623 int cc; 624 { 625 u_int8_t *q = p; 626 627 DPRINTF(("bba_input_conv(): v=%p p=%p cc=%d\n", v, p, cc)); 628 629 /* 630 * p points start of buffer 631 * cc is the number of bytes in the destination buffer 632 */ 633 634 while (--cc >= 0) { 635 *p = ((*(u_int32_t *)q)>>16)&0xff; 636 q += 4; 637 p++; 638 } 639 } 640 641 642 void 643 bba_output_conv(v, p, cc) 644 void *v; 645 u_int8_t *p; 646 int cc; 647 { 648 u_int8_t *q = p; 649 650 DPRINTF(("bba_output_conv(): v=%p p=%p cc=%d\n", v, p, cc)); 651 652 /* 653 * p points start of buffer 654 * cc is the number of bytes in the source buffer 655 */ 656 657 p += cc; 658 q += cc * 4; 659 while (--cc >= 0) { 660 q -= 4; 661 p -= 1; 662 *(u_int32_t *)q = (*p<<16); 663 } 664 } 665 666 667 int 668 bba_round_blocksize(addr, blk) 669 void *addr; 670 int blk; 671 { 672 return (PAGE_SIZE); 673 } 674 675 676 /* indirect write */ 677 void 678 bba_codec_iwrite(sc, reg, val) 679 struct am7930_softc *sc; 680 int reg; 681 u_int8_t val; 682 { 683 DPRINTF(("bba_codec_iwrite(): sc=%p, reg=%d, val=%d\n",sc,reg,val)); 684 685 bba_codec_dwrite(sc, AM7930_DREG_CR, reg); 686 bba_codec_dwrite(sc, AM7930_DREG_DR, val); 687 } 688 689 690 void 691 bba_codec_iwrite16(sc, reg, val) 692 struct am7930_softc *sc; 693 int reg; 694 u_int16_t val; 695 { 696 DPRINTF(("bba_codec_iwrite16(): sc=%p, reg=%d, val=%d\n",sc,reg,val)); 697 698 bba_codec_dwrite(sc, AM7930_DREG_CR, reg); 699 bba_codec_dwrite(sc, AM7930_DREG_DR, val); 700 bba_codec_dwrite(sc, AM7930_DREG_DR, val>>8); 701 } 702 703 704 u_int16_t 705 bba_codec_iread16(sc, reg) 706 struct am7930_softc *sc; 707 int reg; 708 { 709 u_int16_t val; 710 DPRINTF(("bba_codec_iread16(): sc=%p, reg=%d\n",sc,reg)); 711 712 bba_codec_dwrite(sc, AM7930_DREG_CR, reg); 713 val = bba_codec_dread(sc, AM7930_DREG_DR) << 8; 714 val |= bba_codec_dread(sc, AM7930_DREG_DR); 715 716 return val; 717 } 718 719 720 /* indirect read */ 721 u_int8_t 722 bba_codec_iread(sc, reg) 723 struct am7930_softc *sc; 724 int reg; 725 { 726 u_int8_t val; 727 728 DPRINTF(("bba_codec_iread(): sc=%p, reg=%d\n",sc,reg)); 729 730 bba_codec_dwrite(sc, AM7930_DREG_CR, reg); 731 val = bba_codec_dread(sc, AM7930_DREG_DR); 732 733 DPRINTF(("read 0x%x (%d)\n", val, val)); 734 735 return val; 736 } 737 738 739 #define TIMETOWASTE 50 740 741 /* direct write */ 742 void 743 bba_codec_dwrite(asc, reg, val) 744 struct am7930_softc *asc; 745 int reg; 746 u_int8_t val; 747 { 748 struct bba_softc *sc = (struct bba_softc *)asc; 749 int i; 750 751 DPRINTF(("bba_codec_dwrite(): sc=%p, reg=%d, val=%d\n",sc,reg,val)); 752 753 bus_space_write_4(sc->sc_bst, sc->sc_codec_bsh, (reg<<6), val); 754 755 for (i=0; i<TIMETOWASTE; i++) {}; 756 } 757 758 /* direct read */ 759 u_int8_t 760 bba_codec_dread(asc, reg) 761 struct am7930_softc *asc; 762 int reg; 763 { 764 struct bba_softc *sc = (struct bba_softc *)asc; 765 u_int8_t val; 766 int i; 767 768 DPRINTF(("bba_codec_dread(): sc=%p, reg=%d\n",sc,reg)); 769 770 val = bus_space_read_1(sc->sc_bst, sc->sc_codec_bsh, (reg<<6)); 771 772 for (i=0; i<TIMETOWASTE; i++) {}; 773 774 return val; 775 } 776 777 #endif /* NAUDIO > 0 */ 778
Indexes created Wed Oct 15 03:09:54 GMT 2025