if_le_ioasic.c revision 1.8
1 /* $NetBSD: if_le_ioasic.c,v 1.8 1997/08/26 01:27:12 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * LANCE on DEC IOCTL ASIC. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/mbuf.h> 37 #include <sys/syslog.h> 38 #include <sys/socket.h> 39 #include <sys/device.h> 40 41 #include <net/if.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 45 #ifdef INET 46 #include <netinet/in.h> 47 #include <netinet/if_inarp.h> 48 #endif 49 50 #include <dev/ic/am7990reg.h> 51 #include <dev/ic/am7990var.h> 52 53 #include <dev/tc/if_levar.h> 54 #include <dev/tc/tcvar.h> 55 #include <dev/tc/ioasicvar.h> 56 57 extern caddr_t le_iomem; 58 59 int le_ioasic_match __P((struct device *, struct cfdata *, void *)); 60 void le_ioasic_attach __P((struct device *, struct device *, void *)); 61 62 hide void le_ioasic_copytobuf_gap2 __P((struct am7990_softc *, void *, 63 int, int)); 64 hide void le_ioasic_copyfrombuf_gap2 __P((struct am7990_softc *, void *, 65 int, int)); 66 67 hide void le_ioasic_copytobuf_gap16 __P((struct am7990_softc *, void *, 68 int, int)); 69 hide void le_ioasic_copyfrombuf_gap16 __P((struct am7990_softc *, void *, 70 int, int)); 71 hide void le_ioasic_zerobuf_gap16 __P((struct am7990_softc *, int, int)); 72 73 struct cfattach le_ioasic_ca = { 74 sizeof(struct le_softc), le_ioasic_match, le_ioasic_attach 75 }; 76 77 int 78 le_ioasic_match(parent, match, aux) 79 struct device *parent; 80 struct cfdata *match; 81 void *aux; 82 { 83 struct ioasicdev_attach_args *d = aux; 84 85 if (!ioasic_submatch(match, aux)) 86 return (0); 87 if (strncmp("lance", d->iada_modname, TC_ROM_LLEN)) 88 return (0); 89 90 return (1); 91 } 92 93 void 94 le_ioasic_attach(parent, self, aux) 95 struct device *parent, *self; 96 void *aux; 97 { 98 struct ioasicdev_attach_args *d = aux; 99 register struct le_softc *lesc = (void *)self; 100 register struct am7990_softc *sc = &lesc->sc_am7990; 101 102 lesc->sc_r1 = (struct lereg1 *) 103 TC_DENSE_TO_SPARSE(TC_PHYS_TO_UNCACHED(d->iada_addr)); 104 sc->sc_mem = (void *)TC_PHYS_TO_UNCACHED(le_iomem); 105 106 sc->sc_copytodesc = le_ioasic_copytobuf_gap2; 107 sc->sc_copyfromdesc = le_ioasic_copyfrombuf_gap2; 108 sc->sc_copytobuf = le_ioasic_copytobuf_gap16; 109 sc->sc_copyfrombuf = le_ioasic_copyfrombuf_gap16; 110 sc->sc_zerobuf = le_ioasic_zerobuf_gap16; 111 112 ioasic_lance_dma_setup(le_iomem); /* XXX more thought */ 113 114 dec_le_common_attach(sc, ioasic_lance_ether_address()); 115 116 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_NET, 117 am7990_intr, sc); 118 } 119 120 /* 121 * Special memory access functions needed by ioasic-attached LANCE 122 * chips. 123 */ 124 125 /* 126 * gap2: two bytes of data followed by two bytes of pad. 127 * 128 * Buffers must be 4-byte aligned. The code doesn't worry about 129 * doing an extra byte. 130 */ 131 132 void 133 le_ioasic_copytobuf_gap2(sc, fromv, boff, len) 134 struct am7990_softc *sc; 135 void *fromv; 136 int boff; 137 register int len; 138 { 139 volatile caddr_t buf = sc->sc_mem; 140 register caddr_t from = fromv; 141 register volatile u_int16_t *bptr; 142 143 if (boff & 0x1) { 144 /* handle unaligned first byte */ 145 bptr = ((volatile u_int16_t *)buf) + (boff - 1); 146 *bptr = (*from++ << 8) | (*bptr & 0xff); 147 bptr += 2; 148 len--; 149 } else 150 bptr = ((volatile u_int16_t *)buf) + boff; 151 while (len > 1) { 152 *bptr = (from[1] << 8) | (from[0] & 0xff); 153 bptr += 2; 154 from += 2; 155 len -= 2; 156 } 157 if (len == 1) 158 *bptr = (u_int16_t)*from; 159 } 160 161 void 162 le_ioasic_copyfrombuf_gap2(sc, tov, boff, len) 163 struct am7990_softc *sc; 164 void *tov; 165 int boff, len; 166 { 167 volatile caddr_t buf = sc->sc_mem; 168 register caddr_t to = tov; 169 register volatile u_int16_t *bptr; 170 register u_int16_t tmp; 171 172 if (boff & 0x1) { 173 /* handle unaligned first byte */ 174 bptr = ((volatile u_int16_t *)buf) + (boff - 1); 175 *to++ = (*bptr >> 8) & 0xff; 176 bptr += 2; 177 len--; 178 } else 179 bptr = ((volatile u_int16_t *)buf) + boff; 180 while (len > 1) { 181 tmp = *bptr; 182 *to++ = tmp & 0xff; 183 *to++ = (tmp >> 8) & 0xff; 184 bptr += 2; 185 len -= 2; 186 } 187 if (len == 1) 188 *to = *bptr & 0xff; 189 } 190 191 /* 192 * gap16: 16 bytes of data followed by 16 bytes of pad. 193 * 194 * Buffers must be 32-byte aligned. 195 */ 196 197 void 198 le_ioasic_copytobuf_gap16(sc, fromv, boff, len) 199 struct am7990_softc *sc; 200 void *fromv; 201 int boff; 202 register int len; 203 { 204 volatile caddr_t buf = sc->sc_mem; 205 register caddr_t from = fromv; 206 register caddr_t bptr; 207 208 bptr = buf + ((boff << 1) & ~0x1f); 209 boff &= 0xf; 210 211 /* 212 * Dispose of boff so destination of subsequent copies is 213 * 16-byte aligned. 214 */ 215 if (boff) { 216 register int xfer; 217 xfer = min(len, 16 - boff); 218 bcopy(from, bptr + boff, xfer); 219 from += xfer; 220 bptr += 32; 221 len -= xfer; 222 } 223 224 /* Destination of copies is now 16-byte aligned. */ 225 if (len >= 16) 226 switch ((u_long)from & (sizeof(u_int32_t) -1)) { 227 case 2: 228 /* Ethernet headers make this the dominant case. */ 229 do { 230 register u_int32_t *dst = (u_int32_t*)bptr; 231 register u_int16_t t0; 232 register u_int32_t t1, t2, t3, t4; 233 234 /* read from odd-16-bit-aligned, cached src */ 235 t0 = *(u_int16_t*)from; 236 t1 = *(u_int32_t*)(from+2); 237 t2 = *(u_int32_t*)(from+6); 238 t3 = *(u_int32_t*)(from+10); 239 t4 = *(u_int16_t*)(from+14); 240 241 /* DMA buffer is uncached on mips */ 242 dst[0] = t0 | (t1 << 16); 243 dst[1] = (t1 >> 16) | (t2 << 16); 244 dst[2] = (t2 >> 16) | (t3 << 16); 245 dst[3] = (t3 >> 16) | (t4 << 16); 246 247 from += 16; 248 bptr += 32; 249 len -= 16; 250 } while (len >= 16); 251 break; 252 253 case 0: 254 do { 255 register u_int32_t *src = (u_int32_t*)from; 256 register u_int32_t *dst = (u_int32_t*)bptr; 257 register u_int32_t t0, t1, t2, t3; 258 259 t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3]; 260 dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3; 261 262 from += 16; 263 bptr += 32; 264 len -= 16; 265 } while (len >= 16); 266 break; 267 268 default: 269 /* Does odd-aligned case ever happen? */ 270 do { 271 bcopy(from, bptr, 16); 272 from += 16; 273 bptr += 32; 274 len -= 16; 275 } while (len >= 16); 276 break; 277 } 278 if (len) 279 bcopy(from, bptr, len); 280 } 281 282 void 283 le_ioasic_copyfrombuf_gap16(sc, tov, boff, len) 284 struct am7990_softc *sc; 285 void *tov; 286 int boff, len; 287 { 288 volatile caddr_t buf = sc->sc_mem; 289 register caddr_t to = tov; 290 register caddr_t bptr; 291 292 bptr = buf + ((boff << 1) & ~0x1f); 293 boff &= 0xf; 294 295 /* Dispose of boff. source of copy is subsequently 16-byte aligned. */ 296 if (boff) { 297 register int xfer; 298 xfer = min(len, 16 - boff); 299 bcopy(bptr+boff, to, xfer); 300 to += xfer; 301 bptr += 32; 302 len -= xfer; 303 } 304 if (len >= 16) 305 switch ((u_long)to & (sizeof(u_int32_t) -1)) { 306 case 2: 307 /* 308 * to is aligned to an odd 16-bit boundary. Ethernet headers 309 * make this the dominant case (98% or more). 310 */ 311 do { 312 register u_int32_t *src = (u_int32_t*)bptr; 313 register u_int32_t t0, t1, t2, t3; 314 315 /* read from uncached aligned DMA buf */ 316 t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3]; 317 318 /* write to odd-16-bit-word aligned dst */ 319 *(u_int16_t *) (to+0) = (u_short) t0; 320 *(u_int32_t *) (to+2) = (t0 >> 16) | (t1 << 16); 321 *(u_int32_t *) (to+6) = (t1 >> 16) | (t2 << 16); 322 *(u_int32_t *) (to+10) = (t2 >> 16) | (t3 << 16); 323 *(u_int16_t *) (to+14) = (t3 >> 16); 324 bptr += 32; 325 to += 16; 326 len -= 16; 327 } while (len > 16); 328 break; 329 case 0: 330 /* 32-bit aligned aligned copy. Rare. */ 331 do { 332 register u_int32_t *src = (u_int32_t*)bptr; 333 register u_int32_t *dst = (u_int32_t*)to; 334 register u_int32_t t0, t1, t2, t3; 335 336 t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3]; 337 dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3; 338 to += 16; 339 bptr += 32; 340 len -= 16; 341 } while (len > 16); 342 break; 343 344 /* XXX Does odd-byte-aligned case ever happen? */ 345 default: 346 do { 347 bcopy(bptr, to, 16); 348 to += 16; 349 bptr += 32; 350 len -= 16; 351 } while (len > 16); 352 break; 353 } 354 if (len) 355 bcopy(bptr, to, len); 356 } 357 358 void 359 le_ioasic_zerobuf_gap16(sc, boff, len) 360 struct am7990_softc *sc; 361 int boff, len; 362 { 363 volatile caddr_t buf = sc->sc_mem; 364 register caddr_t bptr; 365 register int xfer; 366 367 bptr = buf + ((boff << 1) & ~0x1f); 368 boff &= 0xf; 369 xfer = min(len, 16 - boff); 370 while (len > 0) { 371 bzero(bptr + boff, xfer); 372 bptr += 32; 373 boff = 0; 374 len -= xfer; 375 xfer = min(len, 16); 376 } 377 } 378
Indexes created Tue Sep 30 07:10:03 GMT 2025