1 1.9 christos /* $NetBSD: ioasicreg.h,v 1.9 2005/12/11 12:24:00 christos Exp $ */ 2 1.2 nisimura 3 1.8 perry /* 4 1.2 nisimura * Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University 5 1.2 nisimura * All Rights Reserved. 6 1.8 perry * 7 1.2 nisimura * Permission to use, copy, modify and distribute this software and 8 1.2 nisimura * its documentation is hereby granted, provided that both the copyright 9 1.2 nisimura * notice and this permission notice appear in all copies of the 10 1.2 nisimura * software, derivative works or modified versions, and any portions 11 1.2 nisimura * thereof, and that both notices appear in supporting documentation. 12 1.8 perry * 13 1.8 perry * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 14 1.8 perry * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 15 1.2 nisimura * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 16 1.8 perry * 17 1.2 nisimura * Carnegie Mellon requests users of this software to return to 18 1.2 nisimura * 19 1.2 nisimura * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 20 1.2 nisimura * School of Computer Science 21 1.2 nisimura * Carnegie Mellon University 22 1.2 nisimura * Pittsburgh PA 15213-3890 23 1.2 nisimura * 24 1.2 nisimura * any improvements or extensions that they make and grant Carnegie the 25 1.2 nisimura * rights to redistribute these changes. 26 1.2 nisimura */ 27 1.2 nisimura 28 1.2 nisimura /*- 29 1.2 nisimura * Copyright (c) 1992, 1993 30 1.2 nisimura * The Regents of the University of California. All rights reserved. 31 1.2 nisimura * 32 1.2 nisimura * This code is derived from software contributed to Berkeley by 33 1.2 nisimura * The Mach Operating System project at Carnegie-Mellon University, 34 1.2 nisimura * Ralph Campbell and Rick Macklem. 35 1.2 nisimura * 36 1.2 nisimura * Redistribution and use in source and binary forms, with or without 37 1.2 nisimura * modification, are permitted provided that the following conditions 38 1.2 nisimura * are met: 39 1.2 nisimura * 1. Redistributions of source code must retain the above copyright 40 1.2 nisimura * notice, this list of conditions and the following disclaimer. 41 1.2 nisimura * 2. Redistributions in binary form must reproduce the above copyright 42 1.2 nisimura * notice, this list of conditions and the following disclaimer in the 43 1.2 nisimura * documentation and/or other materials provided with the distribution. 44 1.7 agc * 3. Neither the name of the University nor the names of its contributors 45 1.2 nisimura * may be used to endorse or promote products derived from this software 46 1.2 nisimura * without specific prior written permission. 47 1.2 nisimura * 48 1.2 nisimura * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 1.2 nisimura * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 1.2 nisimura * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 1.2 nisimura * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 1.2 nisimura * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 1.2 nisimura * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 1.2 nisimura * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 1.2 nisimura * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 1.2 nisimura * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 1.2 nisimura * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 1.2 nisimura * SUCH DAMAGE. 59 1.2 nisimura * 60 1.2 nisimura * @(#)asic.h 8.1 (Berkeley) 6/10/93 61 1.2 nisimura */ 62 1.1 thorpej 63 1.1 thorpej /* 64 1.2 nisimura * Slot definitions 65 1.1 thorpej */ 66 1.1 thorpej 67 1.2 nisimura #define IOASIC_SLOT_0_START 0x000000 68 1.2 nisimura #define IOASIC_SLOT_1_START 0x040000 69 1.2 nisimura #define IOASIC_SLOT_2_START 0x080000 70 1.2 nisimura #define IOASIC_SLOT_3_START 0x0c0000 71 1.2 nisimura #define IOASIC_SLOT_4_START 0x100000 72 1.2 nisimura #define IOASIC_SLOT_5_START 0x140000 73 1.2 nisimura #define IOASIC_SLOT_6_START 0x180000 74 1.2 nisimura #define IOASIC_SLOT_7_START 0x1c0000 75 1.2 nisimura #define IOASIC_SLOT_8_START 0x200000 76 1.2 nisimura #define IOASIC_SLOT_9_START 0x240000 77 1.2 nisimura #define IOASIC_SLOT_10_START 0x280000 78 1.2 nisimura #define IOASIC_SLOT_11_START 0x2c0000 79 1.2 nisimura #define IOASIC_SLOT_12_START 0x300000 80 1.2 nisimura #define IOASIC_SLOT_13_START 0x340000 81 1.2 nisimura #define IOASIC_SLOT_14_START 0x380000 82 1.2 nisimura #define IOASIC_SLOT_15_START 0x3c0000 83 1.2 nisimura #define IOASIC_SLOTS_END 0x3fffff 84 1.2 nisimura 85 1.2 nisimura /* 86 1.2 nisimura * Register offsets (slot 1) 87 1.2 nisimura */ 88 1.2 nisimura 89 1.2 nisimura #define IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000 90 1.2 nisimura #define IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010 91 1.2 nisimura #define IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020 92 1.2 nisimura #define IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030 93 1.2 nisimura #define IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040 94 1.2 nisimura #define IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050 95 1.2 nisimura #define IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060 96 1.2 nisimura #define IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070 97 1.2 nisimura #define IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080 98 1.2 nisimura #define IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090 99 1.2 nisimura #define IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0 100 1.2 nisimura #define IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0 101 1.2 nisimura #define IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0 102 1.2 nisimura #define IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0 103 1.2 nisimura #define IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0 104 1.2 nisimura #define IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0 105 1.2 nisimura #define IOASIC_CSR IOASIC_SLOT_1_START+0x100 106 1.2 nisimura #define IOASIC_INTR IOASIC_SLOT_1_START+0x110 107 1.2 nisimura #define IOASIC_IMSK IOASIC_SLOT_1_START+0x120 108 1.2 nisimura #define IOASIC_CURADDR IOASIC_SLOT_1_START+0x130 109 1.2 nisimura #define IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140 110 1.2 nisimura #define IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150 111 1.2 nisimura #define IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160 112 1.2 nisimura #define IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170 113 1.2 nisimura #define IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180 114 1.2 nisimura #define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190 115 1.2 nisimura #define IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0 116 1.2 nisimura #define IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0 117 1.2 nisimura #define IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0 118 1.2 nisimura #define IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0 119 1.2 nisimura #define IOASIC_CTR IOASIC_SLOT_1_START+0x1e0 /*3max+/3000*/ 120 1.2 nisimura 121 1.2 nisimura /* System Status and control Register (SSR). */ 122 1.2 nisimura #define IOASIC_CSR_DMAEN_T1 0x80000000 /* rw */ 123 1.2 nisimura #define IOASIC_CSR_DMAEN_R1 0x40000000 /* rw */ 124 1.2 nisimura #define IOASIC_CSR_DMAEN_T2 0x20000000 /* rw */ 125 1.2 nisimura #define IOASIC_CSR_DMAEN_R2 0x10000000 /* rw */ 126 1.2 nisimura #define IOASIC_CSR_FASTMODE 0x08000000 /* rw - 3000 */ 127 1.2 nisimura #define IOASIC_CSR_xxx 0x07800000 /* reserved - 3000 */ 128 1.2 nisimura #define IOASIC_CSR_DS_xxx 0x0f800000 /* reserved - DS */ 129 1.2 nisimura #define IOASIC_CSR_FLOPPY_DIR 0x00400000 /* rw - maxine */ 130 1.2 nisimura #define IOASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw - maxine */ 131 1.2 nisimura #define IOASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */ 132 1.2 nisimura #define IOASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */ 133 1.2 nisimura #define IOASIC_CSR_SCSI_DIR 0x00040000 /* rw - DS */ 134 1.2 nisimura #define IOASIC_CSR_DMAEN_SCSI 0x00020000 /* rw - DS */ 135 1.2 nisimura #define IOASIC_CSR_DMAEN_LANCE 0x00010000 /* rw - DS */ 136 1.2 nisimura /* low 16 bits are rw gp outputs */ 137 1.2 nisimura #define IOASIC_CSR_DIAGDN 0x00008000 /* rw */ 138 1.2 nisimura #define IOASIC_CSR_TXDIS_2 0x00004000 /* rw - 3min,3max+ */ 139 1.2 nisimura #define IOASIC_CSR_TXDIS_1 0x00002000 /* rw - 3min,3max+ */ 140 1.3 gmcgarry #define IOASIC_CSR_ISDN_ENABLE 0x00001000 /* rw - 3000/maxine */ 141 1.2 nisimura #define IOASIC_CSR_SCC_ENABLE 0x00000800 /* rw */ 142 1.2 nisimura #define IOASIC_CSR_RTC_ENABLE 0x00000400 /* rw */ 143 1.2 nisimura #define IOASIC_CSR_SCSI_ENABLE 0x00000200 /* rw - DS */ 144 1.2 nisimura #define IOASIC_CSR_LANCE_ENABLE 0x00000100 /* rw */ 145 1.2 nisimura 146 1.2 nisimura /* System Interrupt Register (and Interrupt Mask Register). */ 147 1.2 nisimura #define IOASIC_INTR_T1_PAGE_END 0x80000000 /* rz */ 148 1.2 nisimura #define IOASIC_INTR_T1_READ_E 0x40000000 /* rz */ 149 1.2 nisimura #define IOASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */ 150 1.2 nisimura #define IOASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */ 151 1.2 nisimura #define IOASIC_INTR_T2_PAGE_END 0x08000000 /* rz */ 152 1.2 nisimura #define IOASIC_INTR_T2_READ_E 0x04000000 /* rz */ 153 1.2 nisimura #define IOASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */ 154 1.2 nisimura #define IOASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */ 155 1.2 nisimura #define IOASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz - maxine */ 156 1.3 gmcgarry #define IOASIC_INTR_ISDN_TXLOAD 0x00400000 /* rz - 3000/maxine */ 157 1.3 gmcgarry #define IOASIC_INTR_ISDN_RXLOAD 0x00200000 /* rz - 3000/maxine */ 158 1.3 gmcgarry #define IOASIC_INTR_ISDN_OVRUN 0x00100000 /* rz - 3000/maxine */ 159 1.2 nisimura #define IOASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz - DS */ 160 1.2 nisimura #define IOASIC_INTR_SCSI_OVRUN 0x00040000 /* rz - DS */ 161 1.2 nisimura #define IOASIC_INTR_SCSI_READ_E 0x00020000 /* rz - DS */ 162 1.2 nisimura #define IOASIC_INTR_LANCE_READ_E 0x00010000 /* rz - DS */ 163 1.2 nisimura 164 1.2 nisimura /* low 16 bits are model-dependent; see also model specific *.h */ 165 1.2 nisimura #define IOASIC_INTR_NVR_JUMPER 0x00004000 /* ro */ 166 1.3 gmcgarry #define IOASIC_INTR_ISDN 0x00002000 /* ro - 3000 */ 167 1.2 nisimura #define IOASIC_INTR_NRMOD_JUMPER 0x00000400 /* ro */ 168 1.2 nisimura #define IOASIC_INTR_SEC_CON 0x00000200 /* ro */ 169 1.2 nisimura #define IOASIC_INTR_SCSI 0x00000200 /* ro - DS */ 170 1.2 nisimura #define IOASIC_INTR_LANCE 0x00000100 /* ro */ 171 1.2 nisimura #define IOASIC_INTR_SCC_1 0x00000080 /* ro */ 172 1.2 nisimura #define IOASIC_INTR_SCC_0 0x00000040 /* ro */ 173 1.2 nisimura #define IOASIC_INTR_ALT_CON 0x00000008 /* ro - 3000/500 */ 174 1.2 nisimura #define IOASIC_INTR_300_OPT1 0x00000008 /* ro - 3000/300 */ 175 1.2 nisimura #define IOASIC_INTR_300_OPT0 0x00000004 /* ro - 3000/300 */ 176 1.2 nisimura 177 1.2 nisimura /* DMA pointer registers (SCSI, Comm, ...) */ 178 1.2 nisimura 179 1.4 thorpej #define IOASIC_DMA_ADDR(p) \ 180 1.4 thorpej ((((p) << 3) & ~0x1f) | (((p) >> 29) & 0x1f)) 181 1.6 thorpej #define IOASIC_DMA_BLOCKSIZE 0x1000 182 1.2 nisimura 183 1.2 nisimura /* For the LANCE DMA pointer register initialization the above suffices */ 184 1.2 nisimura 185 1.2 nisimura /* More SCSI DMA registers */ 186 1.2 nisimura 187 1.2 nisimura #define IOASIC_SCR_STATUS 0x00000004 188 1.2 nisimura #define IOASIC_SCR_WORD 0x00000003 189 1.2 nisimura 190 1.2 nisimura /* Various Decode registers */ 191 1.2 nisimura 192 1.2 nisimura #define IOASIC_DECODE_HW_ADDRESS 0x000003f0 193 1.2 nisimura #define IOASIC_DECODE_CHIP_SELECT 0x0000000f 194 1.2 nisimura 195 1.2 nisimura /* 196 1.2 nisimura * And slot assignments. 197 1.2 nisimura */ 198 1.2 nisimura #define IOASIC_SYS_ETHER_ADDRESS(base) ((base) + IOASIC_SLOT_2_START) 199 1.2 nisimura #define IOASIC_SYS_LANCE(base) ((base) + IOASIC_SLOT_3_START) 200
Indexes created Sun Sep 21 20:09:37 GMT 2025