px.c revision 1.10
1 /* $NetBSD: px.c,v 1.10 2001/11/13 06:26:10 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Driver for DEC PixelStamp graphics adapters (PMAG-C). 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: px.c,v 1.10 2001/11/13 06:26:10 lukem Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/types.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 #include <sys/callout.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #if defined(pmax) 56 #include <mips/cpuregs.h> 57 #elif defined(alpha) 58 #include <alpha/alpha_cpu.h> 59 #endif 60 61 #include <machine/autoconf.h> 62 #include <machine/cpu.h> 63 #include <machine/bus.h> 64 65 #include <dev/cons.h> 66 67 #include <dev/wscons/wsconsio.h> 68 #include <dev/wscons/wsdisplayvar.h> 69 70 #include <dev/ic/bt459reg.h> 71 72 #include <dev/tc/tcvar.h> 73 #include <dev/tc/sticreg.h> 74 #include <dev/tc/sticio.h> 75 #include <dev/tc/sticvar.h> 76 77 #define PX_STIC_POLL_OFFSET 0x000000 /* STIC DMA poll space */ 78 #define PX_STAMP_OFFSET 0x0c0000 /* pixelstamp space on STIC */ 79 #define PX_STIC_OFFSET 0x180000 /* STIC registers */ 80 #define PX_VDAC_OFFSET 0x200000 /* VDAC registers (bt459) */ 81 #define PX_VDAC_RESET_OFFSET 0x300000 /* VDAC reset register */ 82 #define PX_ROM_OFFSET 0x300000 /* ROM code */ 83 84 #define PX_BUF_COUNT 16 85 #define PX_BUF_INC(x) ((x + 1) & (PX_BUF_COUNT - 1)) 86 87 /* 88 * We need enough aligned memory to hold: 89 * 90 * - Xserver communication area (4096 bytes) 91 * - 16 packet buffers (4096 bytes each) 92 * - 2 image buffers (5120 bytes each) 93 * 94 */ 95 #define PX_BUF_SIZE \ 96 (STIC_PACKET_SIZE * PX_BUF_COUNT + STIC_IMGBUF_SIZE*2 + STIC_XCOMM_SIZE) 97 #define PX_BUF_ALIGN 32768 98 99 #define PXF_QUEUE 0x01 100 101 void px_attach(struct device *, struct device *, void *); 102 void px_init(struct stic_info *, int); 103 int px_ioctl(struct stic_info *, u_long, caddr_t, int, struct proc *); 104 int px_match(struct device *, struct cfdata *, void *); 105 106 int px_intr(void *); 107 u_int32_t *px_pbuf_get(struct stic_info *); 108 int px_pbuf_post(struct stic_info *, u_int32_t *); 109 110 void px_cnattach(tc_addr_t); 111 112 struct px_softc { 113 struct device px_dv; 114 struct stic_info *px_si; 115 volatile u_int32_t *px_qpoll[PX_BUF_COUNT]; 116 }; 117 118 struct cfattach px_ca = { 119 sizeof(struct px_softc), px_match, px_attach 120 }; 121 122 int 123 px_match(struct device *parent, struct cfdata *match, void *aux) 124 { 125 struct tc_attach_args *ta; 126 127 ta = aux; 128 129 return (strncmp("PMAG-CA ", ta->ta_modname, TC_ROM_LLEN) == 0); 130 } 131 132 void 133 px_attach(struct device *parent, struct device *self, void *aux) 134 { 135 struct stic_info *si; 136 struct tc_attach_args *ta; 137 struct px_softc *px; 138 int console, i; 139 u_long v; 140 141 px = (struct px_softc *)self; 142 ta = (struct tc_attach_args *)aux; 143 144 if (ta->ta_addr == stic_consinfo.si_slotbase) { 145 si = &stic_consinfo; 146 console = 1; 147 } else { 148 if (stic_consinfo.si_slotbase == NULL) 149 si = &stic_consinfo; 150 else { 151 si = malloc(sizeof(*si), M_DEVBUF, M_NOWAIT); 152 memset(si, 0, sizeof(*si)); 153 } 154 si->si_slotbase = ta->ta_addr; 155 px_init(si, 0); 156 console = 0; 157 } 158 159 px->px_si = si; 160 si->si_dv = self; 161 tc_intr_establish(parent, ta->ta_cookie, IPL_TTY, px_intr, si); 162 163 printf(": 8 plane, %dx%d stamp\n", si->si_stampw, si->si_stamph); 164 165 for (i = 0; i < PX_BUF_COUNT; i++) { 166 v = i * STIC_PACKET_SIZE + 167 si->si_buf_phys + STIC_XCOMM_SIZE; 168 v = ((v & 0xffff8000) << 3) | (v & 0x7fff); 169 px->px_qpoll[i] = (volatile u_int32_t *) 170 ((caddr_t)si->si_slotbase + (v >> 9)); 171 } 172 173 stic_attach(self, si, console); 174 } 175 176 void 177 px_cnattach(tc_addr_t addr) 178 { 179 struct stic_info *si; 180 181 si = &stic_consinfo; 182 si->si_slotbase = addr; 183 px_init(si, 1); 184 stic_cnattach(si); 185 } 186 187 void 188 px_init(struct stic_info *si, int bootstrap) 189 { 190 struct pglist pglist; 191 caddr_t kva, bva; 192 paddr_t bpa; 193 194 /* 195 * Allocate memory for the packet buffers. It must be located below 196 * 8MB, since the STIC can't access outside that region. Also, due 197 * to the holes in STIC address space, each buffer mustn't cross a 198 * 32kB boundary. 199 */ 200 if (bootstrap) { 201 /* 202 * UVM won't be initialised at this point, so grab memory 203 * directly from vm_physmem[]. 204 */ 205 bva = (caddr_t)uvm_pageboot_alloc(PX_BUF_SIZE + PX_BUF_ALIGN); 206 bpa = (STIC_KSEG_TO_PHYS(kva) + PX_BUF_ALIGN - 1) & 207 ~(PX_BUF_ALIGN - 1); 208 if (bpa + PX_BUF_SIZE > 8192*1024) 209 panic("px_init: allocation out of bounds"); 210 } else { 211 TAILQ_INIT(&pglist); 212 if (uvm_pglistalloc(PX_BUF_SIZE, 0, 8192*1024, PX_BUF_ALIGN, 213 0, &pglist, 1, 0) != 0) 214 panic("px_init: allocation failure"); 215 bpa = TAILQ_FIRST(&pglist)->phys_addr; 216 } 217 218 kva = (caddr_t)si->si_slotbase; 219 220 si->si_vdac = (u_int32_t *)(kva + PX_VDAC_OFFSET); 221 si->si_vdac_reset = (u_int32_t *)(kva + PX_VDAC_RESET_OFFSET); 222 si->si_stic = (volatile struct stic_regs *)(kva + PX_STIC_OFFSET); 223 si->si_stamp = (u_int32_t *)(kva + PX_STAMP_OFFSET); 224 si->si_buf = (u_int32_t *)TC_PHYS_TO_UNCACHED(bpa); 225 si->si_buf_phys = bpa; 226 si->si_buf_size = PX_BUF_SIZE; 227 si->si_disptype = WSDISPLAY_TYPE_PX; 228 si->si_depth = 8; 229 si->si_sxc = (volatile struct stic_xcomm *)si->si_buf; 230 231 si->si_pbuf_get = px_pbuf_get; 232 si->si_pbuf_post = px_pbuf_post; 233 si->si_ioctl = px_ioctl; 234 235 memset(si->si_buf, 0, PX_BUF_SIZE); 236 237 stic_init(si); 238 } 239 240 int 241 px_intr(void *cookie) 242 { 243 volatile struct stic_regs *sr; 244 volatile struct stic_xcomm *sxc; 245 struct stic_info *si; 246 struct px_softc *px; 247 int state; 248 249 si = cookie; 250 px = (struct px_softc *)si->si_dv; 251 sr = si->si_stic; 252 state = sr->sr_ipdvint; 253 sxc = si->si_sxc; 254 255 /* 256 * Vertical-retrace condition. 257 * 258 * Clear the flag and flush out any waiting VDAC updates. We do 259 * this at retrace time to avoid producing `shearing' and other 260 * nasty artifacts. 261 */ 262 if ((state & STIC_INT_V) != 0) { 263 sr->sr_ipdvint = STIC_INT_V_WE | STIC_INT_V_EN; 264 tc_wmb(); 265 stic_flush(si); 266 } 267 268 /* 269 * Error condition. 270 * 271 * Simply clear the flag and report the error. 272 */ 273 if ((state & STIC_INT_E) != 0) { 274 printf("%s: error intr, %x %x %x %x %x", px->px_dv.dv_xname, 275 sr->sr_ipdvint, sr->sr_sticsr, sr->sr_buscsr, 276 sr->sr_busadr, sr->sr_busdat); 277 sr->sr_ipdvint = STIC_INT_E_WE | STIC_INT_E_EN; 278 tc_wmb(); 279 } 280 281 /* 282 * Check for queue stalls. 283 */ 284 if (sxc->sxc_tail != sxc->sxc_head && !sxc->sxc_busy) 285 state |= STIC_INT_P; 286 287 /* 288 * Packet-done condition. 289 * 290 * If packet queueing is enabled, clear the condition, and increment 291 * the tail (submitted) pointer. 292 */ 293 if ((si->si_hwflags & PXF_QUEUE) != 0 && (state & STIC_INT_P) != 0) { 294 sr->sr_ipdvint = STIC_INT_P_WE | STIC_INT_P_EN; 295 tc_wmb(); 296 297 if (sxc->sxc_tail != sxc->sxc_head) { 298 sxc->sxc_done[sxc->sxc_tail] = 0; 299 sxc->sxc_tail = PX_BUF_INC(sxc->sxc_tail); 300 } 301 302 if (sxc->sxc_tail != sxc->sxc_head) { 303 if (*px->px_qpoll[sxc->sxc_tail] != STAMP_OK) { 304 sxc->sxc_nreject++; 305 sxc->sxc_busy = 0; 306 } else 307 sxc->sxc_busy = 1; 308 } else 309 sxc->sxc_busy = 0; 310 } 311 312 if ((si->si_hwflags & PXF_QUEUE) != 0 && (state & STIC_INT_P_EN) == 0) 313 printf("px_intr: STIC_INT_P_EN == 0\n"); 314 315 return (1); 316 } 317 318 u_int32_t * 319 px_pbuf_get(struct stic_info *si) 320 { 321 u_long off; 322 323 si->si_pbuf_select ^= STIC_PACKET_SIZE; 324 off = si->si_pbuf_select + STIC_XCOMM_SIZE; 325 return ((u_int32_t *)((caddr_t)si->si_buf + off)); 326 } 327 328 int 329 px_pbuf_post(struct stic_info *si, u_int32_t *buf) 330 { 331 volatile u_int32_t *poll, junk; 332 volatile struct stic_regs *sr; 333 u_long v; 334 int c; 335 336 sr = si->si_stic; 337 338 /* Get address of poll register for this buffer. */ 339 v = (u_long)STIC_KSEG_TO_PHYS(buf); 340 v = ((v & 0xffff8000) << 3) | (v & 0x7fff); 341 poll = (volatile u_int32_t *)((caddr_t)si->si_slotbase + (v >> 9)); 342 343 /* 344 * Read the poll register and make sure the stamp wants to accept 345 * our packet. This read will initiate the DMA. Don't wait for 346 * ever, just in case something's wrong. 347 */ 348 tc_mb(); 349 350 for (c = STAMP_RETRIES; c != 0; c--) { 351 if ((sr->sr_ipdvint & STIC_INT_P) != 0) { 352 sr->sr_ipdvint = STIC_INT_P_WE; 353 tc_wmb(); 354 junk = *poll; 355 return (0); 356 } 357 DELAY(STAMP_DELAY); 358 } 359 360 /* STIC has lost the plot, punish it. */ 361 stic_reset(si); 362 return (-1); 363 } 364 365 int 366 px_ioctl(struct stic_info *si, u_long cmd, caddr_t data, int flag, 367 struct proc *p) 368 { 369 volatile struct stic_xcomm *sxc; 370 volatile struct stic_regs *sr; 371 struct stic_xinfo *sxi; 372 int rv, s; 373 374 sr = si->si_stic; 375 376 switch (cmd) { 377 case STICIO_STARTQ: 378 if (si->si_dispmode != WSDISPLAYIO_MODE_MAPPED || 379 (si->si_hwflags & PXF_QUEUE) != 0) { 380 rv = EBUSY; 381 break; 382 } 383 384 sxc = si->si_sxc; 385 memset((void *)sxc->sxc_done, 0, sizeof(sxc->sxc_done)); 386 sxc->sxc_head = 0; 387 sxc->sxc_tail = 0; 388 sxc->sxc_nreject = 0; 389 sxc->sxc_nstall = 0; 390 391 s = spltty(); 392 si->si_hwflags |= PXF_QUEUE; 393 sr->sr_ipdvint = STIC_INT_P_WE | STIC_INT_P_EN; 394 tc_wmb(); 395 splx(s); 396 397 rv = 0; 398 break; 399 400 case STICIO_STOPQ: 401 s = spltty(); 402 si->si_hwflags &= ~PXF_QUEUE; 403 sr->sr_ipdvint = STIC_INT_P_WE | STIC_INT_P; 404 tc_wmb(); 405 splx(s); 406 rv = 0; 407 break; 408 409 case STICIO_GXINFO: 410 sxi = (struct stic_xinfo *)data; 411 sxi->sxi_unit = si->si_unit; 412 sxi->sxi_stampw = si->si_stampw; 413 sxi->sxi_stamph = si->si_stamph; 414 sxi->sxi_buf_size = si->si_buf_size; 415 sxi->sxi_buf_phys = (u_int)si->si_buf_phys; 416 sxi->sxi_buf_pktoff = STIC_XCOMM_SIZE; 417 sxi->sxi_buf_pktcnt = PX_BUF_COUNT; 418 sxi->sxi_buf_imgoff = 419 STIC_XCOMM_SIZE + STIC_PACKET_SIZE * PX_BUF_COUNT; 420 rv = 0; 421 break; 422 423 default: 424 rv = ENOTTY; 425 break; 426 } 427 428 return (rv); 429 } 430
Indexes created Wed Oct 01 15:09:59 GMT 2025