sticreg.h revision 1.3 1 /* $NetBSD: sticreg.h,v 1.3 2000/12/17 13:52:04 ad Exp $ */
2
3 /*-
4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Andrew Doran.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #ifndef _TC_STICREG_H_
40 #define _TC_STICREG_H_
41
42 /*
43 * PixelStamp command packets take this general format:
44 *
45 * command word
46 * plane mask & primitive count
47 * always zero
48 * update method
49 *
50 * per-packet context (optional):
51 * line width
52 * xy mask
53 * cliping rectangle min & max
54 * rgb constant
55 * z constant
56 *
57 * per-primitive context (optional):
58 * xy mask
59 * xy mask address
60 * primitive data (vertices, spans info, video)
61 * line width
62 * halfspace equals conditions
63 * rgb flat, or rgb{1,2,3} smooth
64 * z flat, or z{1,2,3} smooth
65 */
66
67 /*
68 * Command word.
69 */
70 #define STAMP_CMD_POINTS (0x0000)
71 #define STAMP_CMD_LINES (0x0001)
72 #define STAMP_CMD_TRIANGLES (0x0002)
73 #define STAMP_CMD_COPYSPANS (0x0005)
74 #define STAMP_CMD_READSPANS (0x0006)
75 #define STAMP_CMD_WRITESPANS (0x0007)
76 #define STAMP_CMD_VIDEO (0x0008)
77
78 #define STAMP_RGB_NONE (0x0000)
79 #define STAMP_RGB_CONST (0x0010)
80 #define STAMP_RGB_FLAT (0x0020)
81 #define STAMP_RGB_SMOOTH (0x0030)
82
83 #define STAMP_Z_NONE (0x0000)
84 #define STAMP_Z_CONST (0x0040)
85 #define STAMP_Z_FLAT (0x0080)
86 #define STAMP_Z_SMOOTH (0x00c0)
87
88 #define STAMP_XY_NONE (0x0000)
89 #define STAMP_XY_PERPACKET (0x0100)
90 #define STAMP_XY_PERPRIMATIVE (0x0200)
91
92 #define STAMP_LW_NONE (0x0000)
93 #define STAMP_LW_PERPACKET (0x0400)
94 #define STAMP_LW_PERPRIMATIVE (0x0800)
95
96 #define STAMP_CLIPRECT (0x00080000)
97 #define STAMP_MESH (0x00200000)
98 #define STAMP_AALINE (0x00800000)
99 #define STAMP_HS_EQUALS (0x80000000)
100
101 /*
102 * Update word.
103 */
104 #define STAMP_PLANE_8X3 (0 << 5)
105 #define STAMP_PLANE_24 (1 << 5)
106
107 /* Write enable */
108 #define STAMP_WE_SIGN (0x04 << 8)
109 #define STAMP_WE_XYMASK (0x02 << 8)
110 #define STAMP_WE_CLIPRECT (0x01 << 8)
111 #define STAMP_WE_NONE (0x00 << 8)
112
113 #define STAMP_METHOD_CLEAR (0x60 << 12)
114 #define STAMP_METHOD_AND (0x14 << 12)
115 #define STAMP_METHOD_ANDREV (0x15 << 12)
116 #define STAMP_METHOD_COPY (0x20 << 12)
117 #define STAMP_METHOD_ANDINV (0x16 << 12)
118 #define STAMP_METHOD_NOOP (0x40 << 12)
119 #define STAMP_METHOD_XOR (0x11 << 12)
120 #define STAMP_METHOD_OR (0x0f << 12)
121 #define STAMP_METHOD_NOR (0x17 << 12)
122 #define STAMP_METHOD_EQUIV (0x10 << 12)
123 #define STAMP_METHOD_INV (0x4e << 12)
124 #define STAMP_METHOD_ORREV (0x0e << 12)
125 #define STAMP_METHOD_COPYINV (0x2d << 12)
126 #define STAMP_METHOD_ORINV (0x0d << 12)
127 #define STAMP_METHOD_NAND (0x0c << 12)
128 #define STAMP_METHOD_SET (0x6c << 12)
129 #define STAMP_METHOD_SUM (0x00 << 12)
130 #define STAMP_METHOD_DIFF (0x02 << 12)
131 #define STAMP_METHOD_REVDIFF (0x01 << 12)
132
133 /* Double buffering */
134 #define STAMP_DB_NONE (0x00 << 28)
135 #define STAMP_DB_01 (0x01 << 28)
136 #define STAMP_DB_12 (0x02 << 28)
137 #define STAMP_DB_02 (0x04 << 28)
138
139 #define STAMP_UPDATE_ENABLE (1 << 0)
140 #define STAMP_SAVE_SIGN (1 << 6)
141 #define STAMP_SAVE_ALPHA (1 << 7)
142 #define STAMP_SUPERSAMPLE (1 << 11)
143 #define STAMP_SPAN (1 << 19)
144 #define STAMP_COPYSPAN_ALIGNED (1 << 20)
145 #define STAMP_MINMAX (1 << 21)
146 #define STAMP_MULT (1 << 22)
147 #define STAMP_MULTACC (1 << 23)
148 #define STAMP_HALF_BUFF (1 << 27)
149 #define STAMP_INITIALIZE (1 << 31)
150
151 /*
152 * Mask address calculation.
153 */
154 #define XMASKADDR(sw, sx, a) (((a)-((sx) % (sw))) & 15)
155 #define YMASKADDR(sh, sy, b) (((b)-((sy) % (sh))) & 15)
156 #define XYMASKADDR(sw,sh,x,y,a,b) \
157 (XMASKADDR(sw,x,a) << 16 | YMASKADDR(sh,y,b))
158
159 /*
160 * Miscellenous constants.
161 */
162 #define STIC_MAGIC_X 370
163 #define STIC_MAGIC_Y 37
164
165 #define STAMP_OK (0)
166 #define STAMP_BUSY (1)
167 #define STAMP_RETRIES (7000)
168 #define STAMP_DELAY (20)
169
170 /*
171 * STIC registers.
172 */
173 struct stic_regs {
174 u_int32_t sr_pad0;
175 u_int32_t sr_pad1;
176 u_int32_t sr_hsync;
177 u_int32_t sr_hsync2;
178 u_int32_t sr_hblank;
179 u_int32_t sr_vsync;
180 u_int32_t sr_vblank;
181 u_int32_t sr_vtest;
182 u_int32_t sr_ipdvint;
183 u_int32_t sr_pad2;
184 u_int32_t sr_sticsr;
185 u_int32_t sr_busdat;
186 u_int32_t sr_busadr;
187 u_int32_t sr_pad3;
188 u_int32_t sr_buscsr;
189 u_int32_t sr_modcl;
190 };
191
192 /*
193 * Bit definitions for stic_regs::sticsr.
194 */
195 #define STIC_CSR_TSTFNC 0x00000003
196 # define STIC_CSR_TSTFNC_NORMAL 0
197 # define STIC_CSR_TSTFNC_PARITY 1
198 # define STIC_CSR_TSTFNC_CNTPIX 2
199 # define STIC_CSR_TSTFNC_TSTDAC 3
200 #define STIC_CSR_CHECKPAR 0x00000004
201 #define STIC_CSR_STARTVT 0x00000010
202 #define STIC_CSR_START 0x00000020
203 #define STIC_CSR_RESET 0x00000040
204 #define STIC_CSR_STARTST 0x00000080
205
206 /*
207 * Bit definitions for stic_regs::int. Three four-bit wide fields, for
208 * error (E), vertical-blank (V), and packetbuf-done (P) intererupts,
209 * respectively. The low-order three bits of each field are enable,
210 * requested, and acknowledge bits. The top bit of each field is unused.
211 */
212 #define STIC_INT_E_EN 0x00000001
213 #define STIC_INT_E 0x00000002
214 #define STIC_INT_E_WE 0x00000004
215
216 #define STIC_INT_V_EN 0x00000100
217 #define STIC_INT_V 0x00000200
218 #define STIC_INT_V_WE 0x00000400
219
220 #define STIC_INT_P_EN 0x00010000
221 #define STIC_INT_P 0x00020000
222 #define STIC_INT_P_WE 0x00040000
223
224 #define STIC_INT_E_MASK (STIC_INT_E_EN | STIC_INT_E | STIC_INT_E_WE)
225 #define STIC_INT_V_MASK (STIC_INT_V_EN | STIC_INT_V | STIC_INT_V_WE)
226 #define STIC_INT_P_MASK (STIC_INT_P_EN | STIC_INT_P | STIC_INT_P_WE)
227 #define STIC_INT_MASK (STIC_INT_E_MASK | STIC_INT_P_MASK | STIC_INT_V_MASK)
228
229 #define STIC_INT_WE (STIC_INT_E_WE | STIC_INT_V_WE | STIC_INT_P_WE)
230 #define STIC_INT_CLR (STIC_INT_E_EN | STIC_INT_V_EN | STIC_INT_P_EN)
231
232 /*
233 * On DMA: reading from a STIC poll register causes load & execution of
234 * the packet at the correspoinding physical address. Either STAMP_OK
235 * or STAMP_BUSY will be returned to indicate status.
236 *
237 * The STIC sees only 23-bits (8MB) of address space. Bits 21-22 in
238 * physical address space map to bits 27-28, and bits 15-20 map to bits
239 * 18-23 in the STIC's warped view of the word. On the PXG, the STIC
240 * sees only the onboard SRAM (so any `physical addresses' are offsets
241 * into the beginning of the SRAM).
242 */
243
244 #endif /* _TC_STICREG_H_ */
245