tcds.c revision 1.22
1 /* $NetBSD: tcds.c,v 1.22 2008/04/28 20:23:58 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Keith Bostic, Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: tcds.c,v 1.22 2008/04/28 20:23:58 martin Exp $"); 62 63 #include <sys/param.h> 64 #include <sys/kernel.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/malloc.h> 68 69 #ifdef __alpha__ 70 #include <machine/rpb.h> 71 #endif /* __alpha__ */ 72 73 #include <dev/scsipi/scsi_all.h> 74 #include <dev/scsipi/scsipi_all.h> 75 #include <dev/scsipi/scsiconf.h> 76 77 #include <dev/ic/ncr53c9xvar.h> 78 79 #include <sys/bus.h> 80 81 #include <dev/tc/tcvar.h> 82 #include <dev/tc/tcdsreg.h> 83 #include <dev/tc/tcdsvar.h> 84 85 #include "locators.h" 86 87 struct tcds_softc { 88 struct device sc_dv; 89 bus_space_tag_t sc_bst; 90 bus_space_handle_t sc_bsh; 91 bus_dma_tag_t sc_dmat; 92 void *sc_cookie; 93 int sc_flags; 94 struct tcds_slotconfig sc_slots[2]; 95 }; 96 97 /* sc_flags */ 98 #define TCDSF_BASEBOARD 0x01 /* baseboard on DEC 3000 */ 99 #define TCDSF_FASTSCSI 0x02 /* supports Fast SCSI */ 100 101 /* Definition of the driver for autoconfig. */ 102 static int tcdsmatch(struct device *, struct cfdata *, void *); 103 static void tcdsattach(struct device *, struct device *, void *); 104 static int tcdsprint(void *, const char *); 105 106 CFATTACH_DECL(tcds, sizeof(struct tcds_softc), 107 tcdsmatch, tcdsattach, NULL, NULL); 108 109 /*static*/ int tcds_intr(void *); 110 /*static*/ int tcds_intrnull(void *); 111 112 static const struct tcds_device { 113 const char *td_name; 114 int td_flags; 115 } tcds_devices[] = { 116 #ifdef __alpha__ 117 { "PMAZ-DS ", TCDSF_BASEBOARD }, 118 { "PMAZ-FS ", TCDSF_BASEBOARD|TCDSF_FASTSCSI }, 119 #endif /* __alpha__ */ 120 { "PMAZB-AA", 0 }, 121 { "PMAZC-AA", TCDSF_FASTSCSI }, 122 { NULL, 0 }, 123 }; 124 125 static void tcds_params(struct tcds_softc *, int, int *, int *); 126 127 static const struct tcds_device * 128 tcds_lookup(const char *modname) 129 { 130 const struct tcds_device *td; 131 132 for (td = tcds_devices; td->td_name != NULL; td++) 133 if (strncmp(td->td_name, modname, TC_ROM_LLEN) == 0) 134 return (td); 135 136 return (NULL); 137 } 138 139 static int 140 tcdsmatch(struct device *parent, struct cfdata *cfdata, void *aux) 141 { 142 struct tc_attach_args *ta = aux; 143 144 return (tcds_lookup(ta->ta_modname) != NULL); 145 } 146 147 static void 148 tcdsattach(struct device *parent, struct device *self, void *aux) 149 { 150 struct tcds_softc *sc = device_private(self); 151 struct tc_attach_args *ta = aux; 152 struct tcdsdev_attach_args tcdsdev; 153 struct tcds_slotconfig *slotc; 154 const struct tcds_device *td; 155 bus_space_handle_t sbsh[2]; 156 int i, gpi2; 157 const struct evcnt *pevcnt; 158 int locs[TCDSCF_NLOCS]; 159 160 td = tcds_lookup(ta->ta_modname); 161 if (td == NULL) 162 panic("\ntcdsattach: impossible"); 163 164 printf(": TurboChannel Dual SCSI"); 165 if (td->td_flags & TCDSF_BASEBOARD) 166 printf(" (baseboard)"); 167 printf("\n"); 168 169 sc->sc_flags = td->td_flags; 170 171 sc->sc_bst = ta->ta_memt; 172 sc->sc_dmat = ta->ta_dmat; 173 174 /* 175 * Map the device. 176 */ 177 if (bus_space_map(sc->sc_bst, ta->ta_addr, 178 (TCDS_SCSI1_OFFSET + 0x100), 0, &sc->sc_bsh)) { 179 aprint_error_dev(&sc->sc_dv, "unable to map device\n"); 180 return; 181 } 182 183 /* 184 * Now, slice off two subregions for the individual NCR SCSI chips. 185 */ 186 if (bus_space_subregion(sc->sc_bst, sc->sc_bsh, TCDS_SCSI0_OFFSET, 187 0x100, &sbsh[0]) || 188 bus_space_subregion(sc->sc_bst, sc->sc_bsh, TCDS_SCSI1_OFFSET, 189 0x100, &sbsh[1])) { 190 aprint_error_dev(&sc->sc_dv, "unable to subregion SCSI chip space\n"); 191 return; 192 } 193 194 sc->sc_cookie = ta->ta_cookie; 195 196 pevcnt = tc_intr_evcnt(parent, sc->sc_cookie); 197 tc_intr_establish(parent, sc->sc_cookie, TC_IPL_BIO, tcds_intr, sc); 198 199 /* 200 * XXX 201 * IMER apparently has some random (or, not so random, but still 202 * not useful) bits set in it when the system boots. Clear it. 203 */ 204 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_IMER, 0); 205 206 /* XXX Initial contents of CIR? */ 207 208 /* 209 * Remember if GPI2 is set in the CIR; we'll need it later. 210 */ 211 gpi2 = (bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR) & 212 TCDS_CIR_GPI_2) != 0; 213 214 /* 215 * Set up the per-slot definitions for later use. 216 */ 217 218 /* fill in common information first */ 219 for (i = 0; i < 2; i++) { 220 char *cp; 221 222 slotc = &sc->sc_slots[i]; 223 bzero(slotc, sizeof *slotc); /* clear everything */ 224 225 cp = slotc->sc_name; 226 snprintf(cp, sizeof(slotc->sc_name), "chip %d", i); 227 evcnt_attach_dynamic(&slotc->sc_evcnt, EVCNT_TYPE_INTR, 228 pevcnt, device_xname(&sc->sc_dv), cp); 229 230 slotc->sc_slot = i; 231 slotc->sc_bst = sc->sc_bst; 232 slotc->sc_bsh = sc->sc_bsh; 233 slotc->sc_intrhand = tcds_intrnull; 234 slotc->sc_intrarg = (void *)(long)i; 235 } 236 237 /* information for slot 0 */ 238 slotc = &sc->sc_slots[0]; 239 slotc->sc_resetbits = TCDS_CIR_SCSI0_RESET; 240 slotc->sc_intrmaskbits = 241 TCDS_IMER_SCSI0_MASK | TCDS_IMER_SCSI0_ENB; 242 slotc->sc_intrbits = TCDS_CIR_SCSI0_INT; 243 slotc->sc_dmabits = TCDS_CIR_SCSI0_DMAENA; 244 slotc->sc_errorbits = 0; /* XXX */ 245 slotc->sc_sda = TCDS_SCSI0_DMA_ADDR; 246 slotc->sc_dic = TCDS_SCSI0_DMA_INTR; 247 slotc->sc_dud0 = TCDS_SCSI0_DMA_DUD0; 248 slotc->sc_dud1 = TCDS_SCSI0_DMA_DUD1; 249 250 /* information for slot 1 */ 251 slotc = &sc->sc_slots[1]; 252 slotc->sc_resetbits = TCDS_CIR_SCSI1_RESET; 253 slotc->sc_intrmaskbits = 254 TCDS_IMER_SCSI1_MASK | TCDS_IMER_SCSI1_ENB; 255 slotc->sc_intrbits = TCDS_CIR_SCSI1_INT; 256 slotc->sc_dmabits = TCDS_CIR_SCSI1_DMAENA; 257 slotc->sc_errorbits = 0; /* XXX */ 258 slotc->sc_sda = TCDS_SCSI1_DMA_ADDR; 259 slotc->sc_dic = TCDS_SCSI1_DMA_INTR; 260 slotc->sc_dud0 = TCDS_SCSI1_DMA_DUD0; 261 slotc->sc_dud1 = TCDS_SCSI1_DMA_DUD1; 262 263 /* find the hardware attached to the TCDS ASIC */ 264 for (i = 0; i < 2; i++) { 265 tcds_params(sc, i, &tcdsdev.tcdsda_id, 266 &tcdsdev.tcdsda_fast); 267 268 tcdsdev.tcdsda_bst = sc->sc_bst; 269 tcdsdev.tcdsda_bsh = sbsh[i]; 270 tcdsdev.tcdsda_dmat = sc->sc_dmat; 271 tcdsdev.tcdsda_chip = i; 272 tcdsdev.tcdsda_sc = &sc->sc_slots[i]; 273 /* 274 * Determine the chip frequency. TCDSF_FASTSCSI will be set 275 * for TC option cards. For baseboard chips, GPI2 is set, for a 276 * 25MHz clock, else a 40MHz clock. 277 */ 278 if ((sc->sc_flags & TCDSF_BASEBOARD && gpi2 == 0) || 279 sc->sc_flags & TCDSF_FASTSCSI) { 280 tcdsdev.tcdsda_freq = 40000000; 281 tcdsdev.tcdsda_period = tcdsdev.tcdsda_fast ? 4 : 8; 282 } else { 283 tcdsdev.tcdsda_freq = 25000000; 284 tcdsdev.tcdsda_period = 5; 285 } 286 if (sc->sc_flags & TCDSF_BASEBOARD) 287 tcdsdev.tcdsda_variant = NCR_VARIANT_NCR53C94; 288 else 289 tcdsdev.tcdsda_variant = NCR_VARIANT_NCR53C96; 290 291 tcds_scsi_reset(tcdsdev.tcdsda_sc); 292 293 locs[TCDSCF_CHIP] = i; 294 295 config_found_sm_loc(self, "tcds", locs, &tcdsdev, 296 tcdsprint, config_stdsubmatch); 297 #ifdef __alpha__ 298 /* 299 * The second SCSI chip isn't present on the baseboard TCDS 300 * on the DEC Alpha 3000/300 series. 301 */ 302 if (sc->sc_flags & TCDSF_BASEBOARD && 303 cputype == ST_DEC_3000_300) 304 break; 305 #endif /* __alpha__ */ 306 } 307 } 308 309 static int 310 tcdsprint(void *aux, const char *pnp) 311 { 312 struct tcdsdev_attach_args *tcdsdev = aux; 313 314 /* Only ASCs can attach to TCDSs; easy. */ 315 if (pnp) 316 aprint_normal("asc at %s", pnp); 317 318 aprint_normal(" chip %d", tcdsdev->tcdsda_chip); 319 320 return (UNCONF); 321 } 322 323 void 324 tcds_intr_establish(struct device *tcds, int slot, int (*func)(void *), 325 void *arg) 326 { 327 struct tcds_softc *sc = device_private(tcds); 328 329 if (sc->sc_slots[slot].sc_intrhand != tcds_intrnull) 330 panic("tcds_intr_establish: chip %d twice", slot); 331 332 sc->sc_slots[slot].sc_intrhand = func; 333 sc->sc_slots[slot].sc_intrarg = arg; 334 tcds_scsi_reset(&sc->sc_slots[slot]); 335 } 336 337 void 338 tcds_intr_disestablish(struct device *tcds, int slot) 339 { 340 struct tcds_softc *sc = device_private(tcds); 341 342 if (sc->sc_slots[slot].sc_intrhand == tcds_intrnull) 343 panic("tcds_intr_disestablish: chip %d missing intr", 344 slot); 345 346 sc->sc_slots[slot].sc_intrhand = tcds_intrnull; 347 sc->sc_slots[slot].sc_intrarg = (void *)(u_long)slot; 348 349 tcds_dma_enable(&sc->sc_slots[slot], 0); 350 tcds_scsi_enable(&sc->sc_slots[slot], 0); 351 } 352 353 int 354 tcds_intrnull(void *val) 355 { 356 357 panic("tcds_intrnull: uncaught TCDS intr for chip %lu", 358 (u_long)val); 359 } 360 361 void 362 tcds_scsi_reset(struct tcds_slotconfig *sc) 363 { 364 u_int32_t cir; 365 366 tcds_dma_enable(sc, 0); 367 tcds_scsi_enable(sc, 0); 368 369 cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 370 TCDS_CIR_CLR(cir, sc->sc_resetbits); 371 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, cir); 372 373 DELAY(1); 374 375 cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 376 TCDS_CIR_SET(cir, sc->sc_resetbits); 377 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, cir); 378 379 tcds_scsi_enable(sc, 1); 380 tcds_dma_enable(sc, 1); 381 } 382 383 void 384 tcds_scsi_enable(struct tcds_slotconfig *sc, int on) 385 { 386 u_int32_t imer; 387 388 imer = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_IMER); 389 390 if (on) 391 imer |= sc->sc_intrmaskbits; 392 else 393 imer &= ~sc->sc_intrmaskbits; 394 395 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_IMER, imer); 396 } 397 398 void 399 tcds_dma_enable(struct tcds_slotconfig *sc, int on) 400 { 401 u_int32_t cir; 402 403 cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 404 405 /* XXX Clear/set IOSLOT/PBS bits. */ 406 if (on) 407 TCDS_CIR_SET(cir, sc->sc_dmabits); 408 else 409 TCDS_CIR_CLR(cir, sc->sc_dmabits); 410 411 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, cir); 412 } 413 414 int 415 tcds_scsi_isintr(struct tcds_slotconfig *sc, int clear) 416 { 417 u_int32_t cir; 418 419 cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 420 421 if ((cir & sc->sc_intrbits) != 0) { 422 if (clear) { 423 TCDS_CIR_CLR(cir, sc->sc_intrbits); 424 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, 425 cir); 426 } 427 return (1); 428 } else 429 return (0); 430 } 431 432 int 433 tcds_scsi_iserr(struct tcds_slotconfig *sc) 434 { 435 u_int32_t cir; 436 437 cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 438 return ((cir & sc->sc_errorbits) != 0); 439 } 440 441 int 442 tcds_intr(void *arg) 443 { 444 struct tcds_softc *sc = arg; 445 u_int32_t ir, ir0; 446 447 /* 448 * XXX 449 * Copy and clear (gag!) the interrupts. 450 */ 451 ir = ir0 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 452 TCDS_CIR_CLR(ir0, TCDS_CIR_ALLINTR); 453 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, ir0); 454 tc_syncbus(); 455 456 #define INCRINTRCNT(slot) sc->sc_slots[slot].sc_evcnt.ev_count++ 457 458 #define CHECKINTR(slot) \ 459 if (ir & sc->sc_slots[slot].sc_intrbits) { \ 460 INCRINTRCNT(slot); \ 461 (void)(*sc->sc_slots[slot].sc_intrhand) \ 462 (sc->sc_slots[slot].sc_intrarg); \ 463 } 464 CHECKINTR(0); 465 CHECKINTR(1); 466 #undef CHECKINTR 467 468 #ifdef DIAGNOSTIC 469 /* 470 * Interrupts not currently handled, but would like to know if they 471 * occur. 472 * 473 * XXX 474 * Don't know if we have to set the interrupt mask and enable bits 475 * in the IMER to allow some of them to happen? 476 */ 477 #define PRINTINTR(msg, bits) \ 478 if (ir & bits) \ 479 printf("%s: %s", device_xname(&sc->sc_dv), msg); 480 PRINTINTR("SCSI0 DREQ interrupt.\n", TCDS_CIR_SCSI0_DREQ); 481 PRINTINTR("SCSI1 DREQ interrupt.\n", TCDS_CIR_SCSI1_DREQ); 482 PRINTINTR("SCSI0 prefetch interrupt.\n", TCDS_CIR_SCSI0_PREFETCH); 483 PRINTINTR("SCSI1 prefetch interrupt.\n", TCDS_CIR_SCSI1_PREFETCH); 484 PRINTINTR("SCSI0 DMA error.\n", TCDS_CIR_SCSI0_DMA); 485 PRINTINTR("SCSI1 DMA error.\n", TCDS_CIR_SCSI1_DMA); 486 PRINTINTR("SCSI0 DB parity error.\n", TCDS_CIR_SCSI0_DB); 487 PRINTINTR("SCSI1 DB parity error.\n", TCDS_CIR_SCSI1_DB); 488 PRINTINTR("SCSI0 DMA buffer parity error.\n", TCDS_CIR_SCSI0_DMAB_PAR); 489 PRINTINTR("SCSI1 DMA buffer parity error.\n", TCDS_CIR_SCSI1_DMAB_PAR); 490 PRINTINTR("SCSI0 DMA read parity error.\n", TCDS_CIR_SCSI0_DMAR_PAR); 491 PRINTINTR("SCSI1 DMA read parity error.\n", TCDS_CIR_SCSI1_DMAR_PAR); 492 PRINTINTR("TC write parity error.\n", TCDS_CIR_TCIOW_PAR); 493 PRINTINTR("TC I/O address parity error.\n", TCDS_CIR_TCIOA_PAR); 494 #undef PRINTINTR 495 #endif 496 497 /* 498 * XXX 499 * The MACH source had this, with the comment: 500 * This is wrong, but machine keeps dying. 501 */ 502 DELAY(1); 503 504 return (1); 505 } 506 507 static void 508 tcds_params(struct tcds_softc *sc, int chip, int *idp, int *fastp) 509 { 510 int id, fast; 511 u_int32_t ids; 512 513 #ifdef __alpha__ 514 if (sc->sc_flags & TCDSF_BASEBOARD) { 515 extern u_int8_t dec_3000_scsiid[], dec_3000_scsifast[]; 516 517 id = dec_3000_scsiid[chip]; 518 fast = dec_3000_scsifast[chip]; 519 } else 520 #endif /* __alpha__ */ 521 { 522 /* 523 * SCSI IDs are stored in the EEPROM, along with whether or 524 * not the device is "fast". Chip 0 is the high nibble, 525 * chip 1 the low nibble. 526 */ 527 ids = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_EEPROM_IDS); 528 if (chip == 0) 529 ids >>= 4; 530 531 id = ids & 0x7; 532 fast = ids & 0x8; 533 } 534 535 if (id < 0 || id > 7) { 536 printf("%s: WARNING: bad SCSI ID %d for chip %d, using 7\n", 537 device_xname(&sc->sc_dv), id, chip); 538 id = 7; 539 } 540 541 if (fast) 542 printf("%s: fast mode set for chip %d\n", 543 device_xname(&sc->sc_dv), chip); 544 545 *idp = id; 546 *fastp = fast; 547 } 548
Indexes created Fri Oct 03 02:09:57 GMT 2025