tcds.c revision 1.26.22.2
1 /* $NetBSD: tcds.c,v 1.26.22.2 2021/03/22 16:23:46 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Keith Bostic, Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: tcds.c,v 1.26.22.2 2021/03/22 16:23:46 thorpej Exp $"); 62 63 #include <sys/param.h> 64 #include <sys/kernel.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/malloc.h> 68 69 #ifdef __alpha__ 70 #include <machine/rpb.h> 71 #endif /* __alpha__ */ 72 73 #include <dev/scsipi/scsi_all.h> 74 #include <dev/scsipi/scsipi_all.h> 75 #include <dev/scsipi/scsiconf.h> 76 77 #include <dev/ic/ncr53c9xvar.h> 78 79 #include <sys/bus.h> 80 81 #include <dev/tc/tcvar.h> 82 #include <dev/tc/tcdsreg.h> 83 #include <dev/tc/tcdsvar.h> 84 85 #include "locators.h" 86 87 struct tcds_softc { 88 device_t sc_dev; 89 bus_space_tag_t sc_bst; 90 bus_space_handle_t sc_bsh; 91 bus_dma_tag_t sc_dmat; 92 void *sc_cookie; 93 int sc_flags; 94 struct tcds_slotconfig sc_slots[2]; 95 }; 96 97 /* sc_flags */ 98 #define TCDSF_BASEBOARD 0x01 /* baseboard on DEC 3000 */ 99 #define TCDSF_FASTSCSI 0x02 /* supports Fast SCSI */ 100 101 /* Definition of the driver for autoconfig. */ 102 static int tcdsmatch(device_t, cfdata_t, void *); 103 static void tcdsattach(device_t, device_t, void *); 104 static int tcdsprint(void *, const char *); 105 106 CFATTACH_DECL_NEW(tcds, sizeof(struct tcds_softc), 107 tcdsmatch, tcdsattach, NULL, NULL); 108 109 /*static*/ int tcds_intr(void *); 110 /*static*/ int tcds_intrnull(void *); 111 112 static const struct tcds_device { 113 const char *td_name; 114 int td_flags; 115 } tcds_devices[] = { 116 #ifdef __alpha__ 117 { "PMAZ-DS ", TCDSF_BASEBOARD }, 118 { "PMAZ-FS ", TCDSF_BASEBOARD|TCDSF_FASTSCSI }, 119 #endif /* __alpha__ */ 120 { "PMAZB-AA", 0 }, 121 { "PMAZC-AA", TCDSF_FASTSCSI }, 122 { NULL, 0 }, 123 }; 124 125 static void tcds_params(struct tcds_softc *, int, int *, int *); 126 127 static const struct tcds_device * 128 tcds_lookup(const char *modname) 129 { 130 const struct tcds_device *td; 131 132 for (td = tcds_devices; td->td_name != NULL; td++) 133 if (strncmp(td->td_name, modname, TC_ROM_LLEN) == 0) 134 return (td); 135 136 return (NULL); 137 } 138 139 static int 140 tcdsmatch(device_t parent, cfdata_t cfdata, void *aux) 141 { 142 struct tc_attach_args *ta = aux; 143 144 return (tcds_lookup(ta->ta_modname) != NULL); 145 } 146 147 static void 148 tcdsattach(device_t parent, device_t self, void *aux) 149 { 150 struct tcds_softc *sc = device_private(self); 151 struct tc_attach_args *ta = aux; 152 struct tcdsdev_attach_args tcdsdev; 153 struct tcds_slotconfig *slotc; 154 const struct tcds_device *td; 155 bus_space_handle_t sbsh[2]; 156 int i, gpi2; 157 const struct evcnt *pevcnt; 158 int locs[TCDSCF_NLOCS]; 159 160 sc->sc_dev = self; 161 162 td = tcds_lookup(ta->ta_modname); 163 if (td == NULL) 164 panic("\ntcdsattach: impossible"); 165 166 printf(": TURBOchannel Dual SCSI"); 167 if (td->td_flags & TCDSF_BASEBOARD) 168 printf(" (baseboard)"); 169 printf("\n"); 170 171 sc->sc_flags = td->td_flags; 172 173 sc->sc_bst = ta->ta_memt; 174 sc->sc_dmat = ta->ta_dmat; 175 176 /* 177 * Map the device. 178 */ 179 if (bus_space_map(sc->sc_bst, ta->ta_addr, 180 (TCDS_SCSI1_OFFSET + 0x100), 0, &sc->sc_bsh)) { 181 aprint_error_dev(self, "unable to map device\n"); 182 return; 183 } 184 185 /* 186 * Now, slice off two subregions for the individual NCR SCSI chips. 187 */ 188 if (bus_space_subregion(sc->sc_bst, sc->sc_bsh, TCDS_SCSI0_OFFSET, 189 0x100, &sbsh[0]) || 190 bus_space_subregion(sc->sc_bst, sc->sc_bsh, TCDS_SCSI1_OFFSET, 191 0x100, &sbsh[1])) { 192 aprint_error_dev(self, "unable to subregion SCSI chip space\n"); 193 return; 194 } 195 196 sc->sc_cookie = ta->ta_cookie; 197 198 pevcnt = tc_intr_evcnt(parent, sc->sc_cookie); 199 tc_intr_establish(parent, sc->sc_cookie, TC_IPL_BIO, tcds_intr, sc); 200 201 /* 202 * XXX 203 * IMER apparently has some random (or, not so random, but still 204 * not useful) bits set in it when the system boots. Clear it. 205 */ 206 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_IMER, 0); 207 208 /* XXX Initial contents of CIR? */ 209 210 /* 211 * Remember if GPI2 is set in the CIR; we'll need it later. 212 */ 213 gpi2 = (bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR) & 214 TCDS_CIR_GPI_2) != 0; 215 216 /* 217 * Set up the per-slot definitions for later use. 218 */ 219 220 /* fill in common information first */ 221 for (i = 0; i < 2; i++) { 222 char *cp; 223 224 slotc = &sc->sc_slots[i]; 225 memset(slotc, 0, sizeof *slotc); /* clear everything */ 226 227 cp = slotc->sc_name; 228 snprintf(cp, sizeof(slotc->sc_name), "chip %d", i); 229 evcnt_attach_dynamic(&slotc->sc_evcnt, EVCNT_TYPE_INTR, 230 pevcnt, device_xname(self), cp); 231 232 slotc->sc_slot = i; 233 slotc->sc_bst = sc->sc_bst; 234 slotc->sc_bsh = sc->sc_bsh; 235 slotc->sc_intrhand = tcds_intrnull; 236 slotc->sc_intrarg = (void *)(long)i; 237 } 238 239 /* information for slot 0 */ 240 slotc = &sc->sc_slots[0]; 241 slotc->sc_resetbits = TCDS_CIR_SCSI0_RESET; 242 slotc->sc_intrmaskbits = 243 TCDS_IMER_SCSI0_MASK | TCDS_IMER_SCSI0_ENB; 244 slotc->sc_intrbits = TCDS_CIR_SCSI0_INT; 245 slotc->sc_dmabits = TCDS_CIR_SCSI0_DMAENA; 246 slotc->sc_errorbits = 0; /* XXX */ 247 slotc->sc_sda = TCDS_SCSI0_DMA_ADDR; 248 slotc->sc_dic = TCDS_SCSI0_DMA_INTR; 249 slotc->sc_dud0 = TCDS_SCSI0_DMA_DUD0; 250 slotc->sc_dud1 = TCDS_SCSI0_DMA_DUD1; 251 252 /* information for slot 1 */ 253 slotc = &sc->sc_slots[1]; 254 slotc->sc_resetbits = TCDS_CIR_SCSI1_RESET; 255 slotc->sc_intrmaskbits = 256 TCDS_IMER_SCSI1_MASK | TCDS_IMER_SCSI1_ENB; 257 slotc->sc_intrbits = TCDS_CIR_SCSI1_INT; 258 slotc->sc_dmabits = TCDS_CIR_SCSI1_DMAENA; 259 slotc->sc_errorbits = 0; /* XXX */ 260 slotc->sc_sda = TCDS_SCSI1_DMA_ADDR; 261 slotc->sc_dic = TCDS_SCSI1_DMA_INTR; 262 slotc->sc_dud0 = TCDS_SCSI1_DMA_DUD0; 263 slotc->sc_dud1 = TCDS_SCSI1_DMA_DUD1; 264 265 /* find the hardware attached to the TCDS ASIC */ 266 for (i = 0; i < 2; i++) { 267 tcds_params(sc, i, &tcdsdev.tcdsda_id, 268 &tcdsdev.tcdsda_fast); 269 270 tcdsdev.tcdsda_bst = sc->sc_bst; 271 tcdsdev.tcdsda_bsh = sbsh[i]; 272 tcdsdev.tcdsda_dmat = sc->sc_dmat; 273 tcdsdev.tcdsda_chip = i; 274 tcdsdev.tcdsda_sc = &sc->sc_slots[i]; 275 /* 276 * Determine the chip frequency. TCDSF_FASTSCSI will be set 277 * for TC option cards. For baseboard chips, GPI2 is set, for a 278 * 25MHz clock, else a 40MHz clock. 279 */ 280 if ((sc->sc_flags & TCDSF_BASEBOARD && gpi2 == 0) || 281 sc->sc_flags & TCDSF_FASTSCSI) { 282 tcdsdev.tcdsda_freq = 40000000; 283 tcdsdev.tcdsda_period = tcdsdev.tcdsda_fast ? 4 : 8; 284 } else { 285 tcdsdev.tcdsda_freq = 25000000; 286 tcdsdev.tcdsda_period = 5; 287 } 288 if (sc->sc_flags & TCDSF_BASEBOARD) 289 tcdsdev.tcdsda_variant = NCR_VARIANT_NCR53C94; 290 else 291 tcdsdev.tcdsda_variant = NCR_VARIANT_NCR53C96; 292 293 tcds_scsi_reset(tcdsdev.tcdsda_sc); 294 295 locs[TCDSCF_CHIP] = i; 296 297 config_found(self, &tcdsdev, tcdsprint, 298 CFARG_SUBMATCH, config_stdsubmatch, 299 CFARG_LOCATORS, locs, 300 CFARG_EOL); 301 #ifdef __alpha__ 302 /* 303 * The second SCSI chip isn't present on the baseboard TCDS 304 * on the DEC Alpha 3000/300 series. 305 */ 306 if (sc->sc_flags & TCDSF_BASEBOARD && 307 cputype == ST_DEC_3000_300) 308 break; 309 #endif /* __alpha__ */ 310 } 311 } 312 313 static int 314 tcdsprint(void *aux, const char *pnp) 315 { 316 struct tcdsdev_attach_args *tcdsdev = aux; 317 318 /* Only ASCs can attach to TCDSs; easy. */ 319 if (pnp) 320 aprint_normal("asc at %s", pnp); 321 322 aprint_normal(" chip %d", tcdsdev->tcdsda_chip); 323 324 return (UNCONF); 325 } 326 327 void 328 tcds_intr_establish(device_t tcds, int slot, int (*func)(void *), 329 void *arg) 330 { 331 struct tcds_softc *sc = device_private(tcds); 332 333 if (sc->sc_slots[slot].sc_intrhand != tcds_intrnull) 334 panic("tcds_intr_establish: chip %d twice", slot); 335 336 sc->sc_slots[slot].sc_intrhand = func; 337 sc->sc_slots[slot].sc_intrarg = arg; 338 tcds_scsi_reset(&sc->sc_slots[slot]); 339 } 340 341 void 342 tcds_intr_disestablish(device_t tcds, int slot) 343 { 344 struct tcds_softc *sc = device_private(tcds); 345 346 if (sc->sc_slots[slot].sc_intrhand == tcds_intrnull) 347 panic("tcds_intr_disestablish: chip %d missing intr", 348 slot); 349 350 sc->sc_slots[slot].sc_intrhand = tcds_intrnull; 351 sc->sc_slots[slot].sc_intrarg = (void *)(u_long)slot; 352 353 tcds_dma_enable(&sc->sc_slots[slot], 0); 354 tcds_scsi_enable(&sc->sc_slots[slot], 0); 355 } 356 357 int 358 tcds_intrnull(void *val) 359 { 360 361 panic("tcds_intrnull: uncaught TCDS intr for chip %lu", 362 (u_long)val); 363 } 364 365 void 366 tcds_scsi_reset(struct tcds_slotconfig *sc) 367 { 368 uint32_t cir; 369 370 tcds_dma_enable(sc, 0); 371 tcds_scsi_enable(sc, 0); 372 373 cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 374 TCDS_CIR_CLR(cir, sc->sc_resetbits); 375 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, cir); 376 377 DELAY(1); 378 379 cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 380 TCDS_CIR_SET(cir, sc->sc_resetbits); 381 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, cir); 382 383 tcds_scsi_enable(sc, 1); 384 tcds_dma_enable(sc, 1); 385 } 386 387 void 388 tcds_scsi_enable(struct tcds_slotconfig *sc, int on) 389 { 390 uint32_t imer; 391 392 imer = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_IMER); 393 394 if (on) 395 imer |= sc->sc_intrmaskbits; 396 else 397 imer &= ~sc->sc_intrmaskbits; 398 399 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_IMER, imer); 400 } 401 402 void 403 tcds_dma_enable(struct tcds_slotconfig *sc, int on) 404 { 405 uint32_t cir; 406 407 cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 408 409 /* XXX Clear/set IOSLOT/PBS bits. */ 410 if (on) 411 TCDS_CIR_SET(cir, sc->sc_dmabits); 412 else 413 TCDS_CIR_CLR(cir, sc->sc_dmabits); 414 415 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, cir); 416 } 417 418 int 419 tcds_scsi_isintr(struct tcds_slotconfig *sc, int clear) 420 { 421 uint32_t cir; 422 423 cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 424 425 if ((cir & sc->sc_intrbits) != 0) { 426 if (clear) { 427 TCDS_CIR_CLR(cir, sc->sc_intrbits); 428 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, 429 cir); 430 } 431 return (1); 432 } else 433 return (0); 434 } 435 436 int 437 tcds_scsi_iserr(struct tcds_slotconfig *sc) 438 { 439 uint32_t cir; 440 441 cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 442 return ((cir & sc->sc_errorbits) != 0); 443 } 444 445 int 446 tcds_intr(void *arg) 447 { 448 struct tcds_softc *sc = arg; 449 uint32_t ir, ir0; 450 451 /* 452 * XXX 453 * Copy and clear (gag!) the interrupts. 454 */ 455 ir = ir0 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); 456 TCDS_CIR_CLR(ir0, TCDS_CIR_ALLINTR); 457 bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, ir0); 458 tc_syncbus(); 459 460 #define INCRINTRCNT(slot) sc->sc_slots[slot].sc_evcnt.ev_count++ 461 462 #define CHECKINTR(slot) \ 463 if (ir & sc->sc_slots[slot].sc_intrbits) { \ 464 INCRINTRCNT(slot); \ 465 (void)(*sc->sc_slots[slot].sc_intrhand) \ 466 (sc->sc_slots[slot].sc_intrarg); \ 467 } 468 CHECKINTR(0); 469 CHECKINTR(1); 470 #undef CHECKINTR 471 472 #ifdef DIAGNOSTIC 473 /* 474 * Interrupts not currently handled, but would like to know if they 475 * occur. 476 * 477 * XXX 478 * Don't know if we have to set the interrupt mask and enable bits 479 * in the IMER to allow some of them to happen? 480 */ 481 #define PRINTINTR(msg, bits) \ 482 if (ir & bits) \ 483 printf("%s: %s", device_xname(sc->sc_dev), msg); 484 PRINTINTR("SCSI0 DREQ interrupt.\n", TCDS_CIR_SCSI0_DREQ); 485 PRINTINTR("SCSI1 DREQ interrupt.\n", TCDS_CIR_SCSI1_DREQ); 486 PRINTINTR("SCSI0 prefetch interrupt.\n", TCDS_CIR_SCSI0_PREFETCH); 487 PRINTINTR("SCSI1 prefetch interrupt.\n", TCDS_CIR_SCSI1_PREFETCH); 488 PRINTINTR("SCSI0 DMA error.\n", TCDS_CIR_SCSI0_DMA); 489 PRINTINTR("SCSI1 DMA error.\n", TCDS_CIR_SCSI1_DMA); 490 PRINTINTR("SCSI0 DB parity error.\n", TCDS_CIR_SCSI0_DB); 491 PRINTINTR("SCSI1 DB parity error.\n", TCDS_CIR_SCSI1_DB); 492 PRINTINTR("SCSI0 DMA buffer parity error.\n", TCDS_CIR_SCSI0_DMAB_PAR); 493 PRINTINTR("SCSI1 DMA buffer parity error.\n", TCDS_CIR_SCSI1_DMAB_PAR); 494 PRINTINTR("SCSI0 DMA read parity error.\n", TCDS_CIR_SCSI0_DMAR_PAR); 495 PRINTINTR("SCSI1 DMA read parity error.\n", TCDS_CIR_SCSI1_DMAR_PAR); 496 PRINTINTR("TC write parity error.\n", TCDS_CIR_TCIOW_PAR); 497 PRINTINTR("TC I/O address parity error.\n", TCDS_CIR_TCIOA_PAR); 498 #undef PRINTINTR 499 #endif 500 501 /* 502 * XXX 503 * The MACH source had this, with the comment: 504 * This is wrong, but machine keeps dying. 505 */ 506 DELAY(1); 507 508 return (1); 509 } 510 511 static void 512 tcds_params(struct tcds_softc *sc, int chip, int *idp, int *fastp) 513 { 514 int id, fast; 515 uint32_t ids; 516 517 #ifdef __alpha__ 518 if (sc->sc_flags & TCDSF_BASEBOARD) { 519 extern uint8_t dec_3000_scsiid[], dec_3000_scsifast[]; 520 521 id = dec_3000_scsiid[chip]; 522 fast = dec_3000_scsifast[chip]; 523 } else 524 #endif /* __alpha__ */ 525 { 526 /* 527 * SCSI IDs are stored in the EEPROM, along with whether or 528 * not the device is "fast". Chip 0 is the high nibble, 529 * chip 1 the low nibble. 530 */ 531 ids = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_EEPROM_IDS); 532 if (chip == 0) 533 ids >>= 4; 534 535 id = ids & 0x7; 536 fast = ids & 0x8; 537 } 538 539 if (id < 0 || id > 7) { 540 printf("%s: WARNING: bad SCSI ID %d for chip %d, using 7\n", 541 device_xname(sc->sc_dev), id, chip); 542 id = 7; 543 } 544 545 if (fast) 546 printf("%s: fast mode set for chip %d\n", 547 device_xname(sc->sc_dev), chip); 548 549 *idp = id; 550 *fastp = fast; 551 } 552
Indexes created Fri Oct 03 02:09:57 GMT 2025