tprof_armv7.c revision 1.2.2.2
1 1.2.2.2 pgoyette /* $NetBSD: tprof_armv7.c,v 1.2.2.2 2018/07/28 04:37:57 pgoyette Exp $ */ 2 1.2.2.2 pgoyette 3 1.2.2.2 pgoyette /*- 4 1.2.2.2 pgoyette * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 1.2.2.2 pgoyette * All rights reserved. 6 1.2.2.2 pgoyette * 7 1.2.2.2 pgoyette * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 pgoyette * modification, are permitted provided that the following conditions 9 1.2.2.2 pgoyette * are met: 10 1.2.2.2 pgoyette * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 pgoyette * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 pgoyette * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 pgoyette * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 pgoyette * documentation and/or other materials provided with the distribution. 15 1.2.2.2 pgoyette * 16 1.2.2.2 pgoyette * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.2.2.2 pgoyette * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.2.2.2 pgoyette * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.2.2.2 pgoyette * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.2.2.2 pgoyette * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.2.2.2 pgoyette * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.2.2.2 pgoyette * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.2.2.2 pgoyette * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.2.2.2 pgoyette * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.2.2.2 pgoyette * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.2.2.2 pgoyette * SUCH DAMAGE. 27 1.2.2.2 pgoyette */ 28 1.2.2.2 pgoyette 29 1.2.2.2 pgoyette #include <sys/cdefs.h> 30 1.2.2.2 pgoyette __KERNEL_RCSID(0, "$NetBSD: tprof_armv7.c,v 1.2.2.2 2018/07/28 04:37:57 pgoyette Exp $"); 31 1.2.2.2 pgoyette 32 1.2.2.2 pgoyette #include <sys/param.h> 33 1.2.2.2 pgoyette #include <sys/bus.h> 34 1.2.2.2 pgoyette #include <sys/cpu.h> 35 1.2.2.2 pgoyette #include <sys/xcall.h> 36 1.2.2.2 pgoyette 37 1.2.2.2 pgoyette #include <dev/tprof/tprof.h> 38 1.2.2.2 pgoyette 39 1.2.2.2 pgoyette #include <arm/armreg.h> 40 1.2.2.2 pgoyette #include <arm/locore.h> 41 1.2.2.2 pgoyette 42 1.2.2.2 pgoyette #include <dev/tprof/tprof_armv7.h> 43 1.2.2.2 pgoyette 44 1.2.2.2 pgoyette #define PMCR_D __BIT(3) 45 1.2.2.2 pgoyette #define PMCR_E __BIT(0) 46 1.2.2.2 pgoyette 47 1.2.2.2 pgoyette #define PMEVTYPER_P __BIT(31) 48 1.2.2.2 pgoyette #define PMEVTYPER_U __BIT(30) 49 1.2.2.2 pgoyette #define PMEVTYPER_EVTCOUNT __BITS(7,0) 50 1.2.2.2 pgoyette 51 1.2.2.2 pgoyette static tprof_param_t armv7_pmu_param; 52 1.2.2.2 pgoyette static const u_int armv7_pmu_counter = 1; 53 1.2.2.2 pgoyette static uint32_t counter_val; 54 1.2.2.2 pgoyette static uint32_t counter_reset_val; 55 1.2.2.2 pgoyette 56 1.2.2.2 pgoyette static bool 57 1.2.2.2 pgoyette armv7_pmu_event_implemented(uint16_t event) 58 1.2.2.2 pgoyette { 59 1.2.2.2 pgoyette uint32_t eid[2]; 60 1.2.2.2 pgoyette 61 1.2.2.2 pgoyette if (event >= 64) 62 1.2.2.2 pgoyette return false; 63 1.2.2.2 pgoyette 64 1.2.2.2 pgoyette eid[0] = armreg_pmceid0_read(); 65 1.2.2.2 pgoyette eid[1] = armreg_pmceid1_read(); 66 1.2.2.2 pgoyette 67 1.2.2.2 pgoyette const u_int idx = event / 32; 68 1.2.2.2 pgoyette const u_int bit = event % 32; 69 1.2.2.2 pgoyette 70 1.2.2.2 pgoyette if (eid[idx] & __BIT(bit)) 71 1.2.2.2 pgoyette return true; 72 1.2.2.2 pgoyette 73 1.2.2.2 pgoyette return false; 74 1.2.2.2 pgoyette } 75 1.2.2.2 pgoyette 76 1.2.2.2 pgoyette static void 77 1.2.2.2 pgoyette armv7_pmu_set_pmevtyper(u_int counter, uint64_t val) 78 1.2.2.2 pgoyette { 79 1.2.2.2 pgoyette armreg_pmselr_write(counter); 80 1.2.2.2 pgoyette arm_isb(); 81 1.2.2.2 pgoyette armreg_pmxevtyper_write(val); 82 1.2.2.2 pgoyette } 83 1.2.2.2 pgoyette 84 1.2.2.2 pgoyette static void 85 1.2.2.2 pgoyette armv7_pmu_set_pmevcntr(u_int counter, uint32_t val) 86 1.2.2.2 pgoyette { 87 1.2.2.2 pgoyette armreg_pmselr_write(counter); 88 1.2.2.2 pgoyette arm_isb(); 89 1.2.2.2 pgoyette armreg_pmxevcntr_write(val); 90 1.2.2.2 pgoyette } 91 1.2.2.2 pgoyette 92 1.2.2.2 pgoyette static void 93 1.2.2.2 pgoyette armv7_pmu_start_cpu(void *arg1, void *arg2) 94 1.2.2.2 pgoyette { 95 1.2.2.2 pgoyette const uint32_t counter_mask = __BIT(armv7_pmu_counter); 96 1.2.2.2 pgoyette uint64_t pmcr, pmevtyper; 97 1.2.2.2 pgoyette 98 1.2.2.2 pgoyette /* Enable performance monitor */ 99 1.2.2.2 pgoyette pmcr = armreg_pmcr_read(); 100 1.2.2.2 pgoyette pmcr |= PMCR_E; 101 1.2.2.2 pgoyette armreg_pmcr_write(pmcr); 102 1.2.2.2 pgoyette 103 1.2.2.2 pgoyette /* Disable event counter */ 104 1.2.2.2 pgoyette armreg_pmcntenclr_write(counter_mask); 105 1.2.2.2 pgoyette 106 1.2.2.2 pgoyette /* Configure event counter */ 107 1.2.2.2 pgoyette pmevtyper = __SHIFTIN(armv7_pmu_param.p_event, PMEVTYPER_EVTCOUNT); 108 1.2.2.2 pgoyette if (!ISSET(armv7_pmu_param.p_flags, TPROF_PARAM_USER)) 109 1.2.2.2 pgoyette pmevtyper |= PMEVTYPER_U; 110 1.2.2.2 pgoyette if (!ISSET(armv7_pmu_param.p_flags, TPROF_PARAM_KERN)) 111 1.2.2.2 pgoyette pmevtyper |= PMEVTYPER_P; 112 1.2.2.2 pgoyette 113 1.2.2.2 pgoyette armv7_pmu_set_pmevtyper(armv7_pmu_counter, pmevtyper); 114 1.2.2.2 pgoyette 115 1.2.2.2 pgoyette /* Enable overflow interrupts */ 116 1.2.2.2 pgoyette armreg_pmintenset_write(counter_mask); 117 1.2.2.2 pgoyette 118 1.2.2.2 pgoyette /* Clear overflow flag */ 119 1.2.2.2 pgoyette armreg_pmovsr_write(counter_mask); 120 1.2.2.2 pgoyette 121 1.2.2.2 pgoyette /* Initialize event counter value */ 122 1.2.2.2 pgoyette armv7_pmu_set_pmevcntr(armv7_pmu_counter, counter_reset_val); 123 1.2.2.2 pgoyette 124 1.2.2.2 pgoyette /* Enable event counter */ 125 1.2.2.2 pgoyette armreg_pmcntenset_write(counter_mask); 126 1.2.2.2 pgoyette } 127 1.2.2.2 pgoyette 128 1.2.2.2 pgoyette static void 129 1.2.2.2 pgoyette armv7_pmu_stop_cpu(void *arg1, void *arg2) 130 1.2.2.2 pgoyette { 131 1.2.2.2 pgoyette const uint32_t counter_mask = __BIT(armv7_pmu_counter); 132 1.2.2.2 pgoyette uint32_t pmcr; 133 1.2.2.2 pgoyette 134 1.2.2.2 pgoyette /* Disable overflow interrupts */ 135 1.2.2.2 pgoyette armreg_pmintenclr_write(counter_mask); 136 1.2.2.2 pgoyette 137 1.2.2.2 pgoyette /* Disable event counter */ 138 1.2.2.2 pgoyette armreg_pmcntenclr_write(counter_mask); 139 1.2.2.2 pgoyette 140 1.2.2.2 pgoyette /* Disable performance monitor */ 141 1.2.2.2 pgoyette pmcr = armreg_pmcr_read(); 142 1.2.2.2 pgoyette pmcr &= ~PMCR_E; 143 1.2.2.2 pgoyette armreg_pmcr_write(pmcr); 144 1.2.2.2 pgoyette } 145 1.2.2.2 pgoyette 146 1.2.2.2 pgoyette static uint64_t 147 1.2.2.2 pgoyette armv7_pmu_estimate_freq(void) 148 1.2.2.2 pgoyette { 149 1.2.2.2 pgoyette uint64_t cpufreq = curcpu()->ci_data.cpu_cc_freq; 150 1.2.2.2 pgoyette uint64_t freq = 10000; 151 1.2.2.2 pgoyette uint32_t pmcr; 152 1.2.2.2 pgoyette 153 1.2.2.2 pgoyette counter_val = cpufreq / freq; 154 1.2.2.2 pgoyette if (counter_val == 0) 155 1.2.2.2 pgoyette counter_val = 4000000000ULL / freq; 156 1.2.2.2 pgoyette 157 1.2.2.2 pgoyette pmcr = armreg_pmcr_read(); 158 1.2.2.2 pgoyette if (pmcr & PMCR_D) 159 1.2.2.2 pgoyette counter_val /= 64; 160 1.2.2.2 pgoyette 161 1.2.2.2 pgoyette return freq; 162 1.2.2.2 pgoyette } 163 1.2.2.2 pgoyette 164 1.2.2.2 pgoyette static uint32_t 165 1.2.2.2 pgoyette armv7_pmu_ident(void) 166 1.2.2.2 pgoyette { 167 1.2.2.2 pgoyette return TPROF_IDENT_ARMV7_GENERIC; 168 1.2.2.2 pgoyette } 169 1.2.2.2 pgoyette 170 1.2.2.2 pgoyette static int 171 1.2.2.2 pgoyette armv7_pmu_start(const tprof_param_t *param) 172 1.2.2.2 pgoyette { 173 1.2.2.2 pgoyette uint64_t xc; 174 1.2.2.2 pgoyette 175 1.2.2.2 pgoyette if (!armv7_pmu_event_implemented(param->p_event)) { 176 1.2.2.2 pgoyette printf("%s: event 0x%#llx not implemented on this CPU\n", 177 1.2.2.2 pgoyette __func__, param->p_event); 178 1.2.2.2 pgoyette return EINVAL; 179 1.2.2.2 pgoyette } 180 1.2.2.2 pgoyette 181 1.2.2.2 pgoyette counter_reset_val = -counter_val + 1; 182 1.2.2.2 pgoyette 183 1.2.2.2 pgoyette armv7_pmu_param = *param; 184 1.2.2.2 pgoyette xc = xc_broadcast(0, armv7_pmu_start_cpu, NULL, NULL); 185 1.2.2.2 pgoyette xc_wait(xc); 186 1.2.2.2 pgoyette 187 1.2.2.2 pgoyette return 0; 188 1.2.2.2 pgoyette } 189 1.2.2.2 pgoyette 190 1.2.2.2 pgoyette static void 191 1.2.2.2 pgoyette armv7_pmu_stop(const tprof_param_t *param) 192 1.2.2.2 pgoyette { 193 1.2.2.2 pgoyette uint64_t xc; 194 1.2.2.2 pgoyette 195 1.2.2.2 pgoyette xc = xc_broadcast(0, armv7_pmu_stop_cpu, NULL, NULL); 196 1.2.2.2 pgoyette xc_wait(xc); 197 1.2.2.2 pgoyette } 198 1.2.2.2 pgoyette 199 1.2.2.2 pgoyette static const tprof_backend_ops_t tprof_armv7_pmu_ops = { 200 1.2.2.2 pgoyette .tbo_estimate_freq = armv7_pmu_estimate_freq, 201 1.2.2.2 pgoyette .tbo_ident = armv7_pmu_ident, 202 1.2.2.2 pgoyette .tbo_start = armv7_pmu_start, 203 1.2.2.2 pgoyette .tbo_stop = armv7_pmu_stop, 204 1.2.2.2 pgoyette }; 205 1.2.2.2 pgoyette 206 1.2.2.2 pgoyette int 207 1.2.2.2 pgoyette armv7_pmu_intr(void *priv) 208 1.2.2.2 pgoyette { 209 1.2.2.2 pgoyette const struct trapframe * const tf = priv; 210 1.2.2.2 pgoyette const uint32_t counter_mask = __BIT(armv7_pmu_counter); 211 1.2.2.2 pgoyette tprof_frame_info_t tfi; 212 1.2.2.2 pgoyette 213 1.2.2.2 pgoyette const uint32_t pmovsr = armreg_pmovsr_read(); 214 1.2.2.2 pgoyette if ((pmovsr & counter_mask) != 0) { 215 1.2.2.2 pgoyette tfi.tfi_pc = tf->tf_pc; 216 1.2.2.2 pgoyette tfi.tfi_inkernel = tfi.tfi_pc >= VM_MIN_KERNEL_ADDRESS && 217 1.2.2.2 pgoyette tfi.tfi_pc < VM_MAX_KERNEL_ADDRESS; 218 1.2.2.2 pgoyette tprof_sample(NULL, &tfi); 219 1.2.2.2 pgoyette 220 1.2.2.2 pgoyette armv7_pmu_set_pmevcntr(armv7_pmu_counter, counter_reset_val); 221 1.2.2.2 pgoyette } 222 1.2.2.2 pgoyette armreg_pmovsr_write(pmovsr); 223 1.2.2.2 pgoyette 224 1.2.2.2 pgoyette return 1; 225 1.2.2.2 pgoyette } 226 1.2.2.2 pgoyette 227 1.2.2.2 pgoyette int 228 1.2.2.2 pgoyette armv7_pmu_init(void) 229 1.2.2.2 pgoyette { 230 1.2.2.2 pgoyette /* Disable user mode access to performance monitors */ 231 1.2.2.2 pgoyette armreg_pmuserenr_write(0); 232 1.2.2.2 pgoyette 233 1.2.2.2 pgoyette /* Disable interrupts */ 234 1.2.2.2 pgoyette armreg_pmintenclr_write(~0U); 235 1.2.2.2 pgoyette 236 1.2.2.2 pgoyette /* Disable counters */ 237 1.2.2.2 pgoyette armreg_pmcntenclr_write(~0U); 238 1.2.2.2 pgoyette 239 1.2.2.2 pgoyette /* Disable performance monitor */ 240 1.2.2.2 pgoyette armreg_pmcr_write(0); 241 1.2.2.2 pgoyette 242 1.2.2.2 pgoyette return tprof_backend_register("tprof_armv7", &tprof_armv7_pmu_ops, 243 1.2.2.2 pgoyette TPROF_BACKEND_VERSION); 244 1.2.2.2 pgoyette } 245
Indexes created Tue Sep 30 20:09:53 GMT 2025