1 1.1 aymeric 2 1.1 aymeric #define AR3K_FIRMWARE_HEADER_SIZE 20 3 1.1 aymeric 4 1.1 aymeric #define AR3K_SEND_FIRMWARE 1 5 1.1 aymeric #define AR3K_GET_STATE 5 6 1.1 aymeric #define AR3K_SET_NORMAL_MODE 7 7 1.1 aymeric #define AR3K_GET_VERSION 9 8 1.1 aymeric #define AR3K_SWITCH_VID_PID 10 9 1.1 aymeric 10 1.1 aymeric #define AR3K_STATE_MODE_MASK 0x3f 11 1.1 aymeric #define AR3K_STATE_MODE_NORMAL 14 12 1.1 aymeric #define AR3K_STATE_IS_SYSCFGED 0x40 13 1.1 aymeric #define AR3K_STATE_IS_PATCHED 0x80 14 1.1 aymeric 15 1.1 aymeric struct ar3k_version { 16 1.1 aymeric uint32_t rom; 17 1.1 aymeric uint32_t build; 18 1.1 aymeric uint32_t ram; 19 1.1 aymeric uint8_t clock; 20 1.1 aymeric #define AR3K_CLOCK_26M 0 21 1.1 aymeric #define AR3K_CLOCK_40M 1 22 1.1 aymeric #define AR3K_CLOCK_19M 2 23 1.1 aymeric uint8_t pad[7]; 24 1.1 aymeric }; 25