ehci.c revision 1.123.12.3 1 1.123.12.3 itohy /* $NetBSD: ehci.c,v 1.123.12.3 2008/05/21 05:01:45 itohy Exp $ */
2 1.1 augustss
3 1.123.12.1 itohy /*-
4 1.123.12.1 itohy * Copyright (c) 2004, 2005, 2007 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.61 mycroft * by Lennart Augustsson (lennart (at) augustsson.net) and by Charles M. Hannum.
9 1.1 augustss *
10 1.1 augustss * Redistribution and use in source and binary forms, with or without
11 1.1 augustss * modification, are permitted provided that the following conditions
12 1.1 augustss * are met:
13 1.1 augustss * 1. Redistributions of source code must retain the above copyright
14 1.1 augustss * notice, this list of conditions and the following disclaimer.
15 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer in the
17 1.1 augustss * documentation and/or other materials provided with the distribution.
18 1.1 augustss * 3. All advertising materials mentioning features or use of this software
19 1.1 augustss * must display the following acknowledgement:
20 1.1 augustss * This product includes software developed by the NetBSD
21 1.1 augustss * Foundation, Inc. and its contributors.
22 1.1 augustss * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 augustss * contributors may be used to endorse or promote products derived
24 1.1 augustss * from this software without specific prior written permission.
25 1.1 augustss *
26 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
37 1.1 augustss */
38 1.1 augustss
39 1.1 augustss /*
40 1.3 augustss * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
41 1.1 augustss *
42 1.35 enami * The EHCI 1.0 spec can be found at
43 1.34 augustss * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
44 1.7 augustss * and the USB 2.0 spec at
45 1.43 ichiro * http://www.usb.org/developers/docs/usb_20.zip
46 1.1 augustss *
47 1.1 augustss */
48 1.4 lukem
49 1.52 jdolecek /*
50 1.52 jdolecek * TODO:
51 1.123.12.1 itohy * 1) The EHCI driver lacks support for isochronous transfers, so
52 1.52 jdolecek * devices using them don't work.
53 1.52 jdolecek *
54 1.123.12.1 itohy * 2) Interrupt transfer scheduling does not manage the time available
55 1.123.12.1 itohy * in each frame, so it is possible for the transfers to overrun
56 1.123.12.1 itohy * the end of the frame.
57 1.52 jdolecek *
58 1.123.12.1 itohy * 3) Command failures are not recovered correctly.
59 1.123.12.1 itohy */
60 1.52 jdolecek
61 1.4 lukem #include <sys/cdefs.h>
62 1.123.12.3 itohy __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.123.12.3 2008/05/21 05:01:45 itohy Exp $");
63 1.123.12.1 itohy /* __FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/dev/usb/ehci.c,v 1.52 2006/10/19 01:15:58 iedowse Exp $"); */
64 1.47 augustss
65 1.123.12.1 itohy #if defined(__NetBSD__) || defined(__OpenBSD__)
66 1.47 augustss #include "ohci.h"
67 1.47 augustss #include "uhci.h"
68 1.123.12.1 itohy #endif
69 1.1 augustss
70 1.1 augustss #include <sys/param.h>
71 1.1 augustss #include <sys/systm.h>
72 1.1 augustss #include <sys/kernel.h>
73 1.1 augustss #include <sys/malloc.h>
74 1.123.12.1 itohy #if defined(__NetBSD__) || defined(__OpenBSD__)
75 1.1 augustss #include <sys/device.h>
76 1.1 augustss #include <sys/select.h>
77 1.123.12.1 itohy #elif defined(__FreeBSD__)
78 1.123.12.1 itohy #include <sys/endian.h>
79 1.123.12.1 itohy #include <sys/module.h>
80 1.123.12.1 itohy #include <sys/bus.h>
81 1.123.12.1 itohy #include <sys/lockmgr.h>
82 1.123.12.1 itohy #if defined(DIAGNOSTIC) && defined(__i386__) && defined(__FreeBSD__)
83 1.123.12.1 itohy #include <machine/cpu.h>
84 1.123.12.1 itohy #endif
85 1.123.12.1 itohy #endif
86 1.1 augustss #include <sys/proc.h>
87 1.1 augustss #include <sys/queue.h>
88 1.123.12.1 itohy #include <sys/sysctl.h>
89 1.1 augustss
90 1.1 augustss #include <machine/bus.h>
91 1.1 augustss #include <machine/endian.h>
92 1.1 augustss
93 1.1 augustss #include <dev/usb/usb.h>
94 1.1 augustss #include <dev/usb/usbdi.h>
95 1.1 augustss #include <dev/usb/usbdivar.h>
96 1.1 augustss #include <dev/usb/usb_mem.h>
97 1.1 augustss #include <dev/usb/usb_quirks.h>
98 1.1 augustss
99 1.1 augustss #include <dev/usb/ehcireg.h>
100 1.1 augustss #include <dev/usb/ehcivar.h>
101 1.1 augustss
102 1.123.12.1 itohy #if defined(__FreeBSD__)
103 1.123.12.1 itohy
104 1.123.12.1 itohy #define delay(d) DELAY(d)
105 1.123.12.1 itohy #endif
106 1.123.12.1 itohy
107 1.123.12.1 itohy #ifdef USB_DEBUG
108 1.123.12.1 itohy /* #define EHCI_DEBUG USB_DEBUG */
109 1.123.12.1 itohy #define DPRINTF(x) do { if (ehcidebug) logprintf x; } while (0)
110 1.123.12.1 itohy #define DPRINTFN(n,x) do { if (ehcidebug>(n)) logprintf x; } while (0)
111 1.6 augustss int ehcidebug = 0;
112 1.123.12.1 itohy #ifdef __FreeBSD__
113 1.123.12.1 itohy SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
114 1.123.12.1 itohy SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW,
115 1.123.12.1 itohy &ehcidebug, 0, "ehci debug level");
116 1.123.12.1 itohy #endif
117 1.15 augustss #ifndef __NetBSD__
118 1.1 augustss #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f))
119 1.15 augustss #endif
120 1.1 augustss #else
121 1.1 augustss #define DPRINTF(x)
122 1.1 augustss #define DPRINTFN(n,x)
123 1.1 augustss #endif
124 1.1 augustss
125 1.5 augustss struct ehci_pipe {
126 1.5 augustss struct usbd_pipe pipe;
127 1.55 mycroft
128 1.10 augustss ehci_soft_qh_t *sqh;
129 1.10 augustss union {
130 1.10 augustss ehci_soft_qtd_t *qtd;
131 1.10 augustss /* ehci_soft_itd_t *itd; */
132 1.10 augustss } tail;
133 1.10 augustss union {
134 1.10 augustss /* Control pipe */
135 1.10 augustss struct {
136 1.10 augustss usb_dma_t reqdma;
137 1.10 augustss u_int length;
138 1.10 augustss } ctl;
139 1.10 augustss /* Interrupt pipe */
140 1.78 augustss struct {
141 1.78 augustss u_int length;
142 1.78 augustss } intr;
143 1.10 augustss /* Bulk pipe */
144 1.10 augustss struct {
145 1.10 augustss u_int length;
146 1.10 augustss } bulk;
147 1.10 augustss /* Iso pipe */
148 1.15 augustss /* XXX */
149 1.10 augustss } u;
150 1.5 augustss };
151 1.5 augustss
152 1.5 augustss Static usbd_status ehci_open(usbd_pipe_handle);
153 1.5 augustss Static void ehci_poll(struct usbd_bus *);
154 1.5 augustss Static void ehci_softintr(void *);
155 1.11 augustss Static int ehci_intr1(ehci_softc_t *);
156 1.15 augustss Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle);
157 1.18 augustss Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *);
158 1.18 augustss Static void ehci_idone(struct ehci_xfer *);
159 1.15 augustss Static void ehci_timeout(void *);
160 1.15 augustss Static void ehci_timeout_task(void *);
161 1.108 xtraeme Static void ehci_intrlist_timeout(void *);
162 1.5 augustss
163 1.123.12.3 itohy Static void ehci_aux_mem_init(struct ehci_aux_mem *);
164 1.123.12.3 itohy Static usbd_status ehci_aux_mem_alloc(ehci_softc_t *,
165 1.123.12.3 itohy struct ehci_aux_mem *,
166 1.123.12.3 itohy int /*naux*/, int /*maxp*/);
167 1.123.12.3 itohy Static void ehci_aux_mem_free(ehci_softc_t *,
168 1.123.12.3 itohy struct ehci_aux_mem *);
169 1.123.12.3 itohy struct aux_desc {
170 1.123.12.3 itohy void *aux_kern;
171 1.123.12.3 itohy };
172 1.123.12.3 itohy Static bus_addr_t ehci_aux_dma_alloc(struct ehci_aux_mem *, int,
173 1.123.12.3 itohy struct aux_desc *);
174 1.123.12.3 itohy Static void ehci_aux_dma_sync(ehci_softc_t *,
175 1.123.12.3 itohy struct ehci_aux_mem *, int /*op*/);
176 1.123.12.3 itohy
177 1.123.12.1 itohy Static usbd_status ehci_prealloc(struct ehci_softc *, struct ehci_xfer *,
178 1.123.12.1 itohy size_t, int);
179 1.123.12.1 itohy Static usbd_status ehci_allocm(struct usbd_bus *, usbd_xfer_handle,
180 1.123.12.1 itohy void *, size_t);
181 1.123.12.1 itohy Static void ehci_freem(struct usbd_bus *, usbd_xfer_handle,
182 1.123.12.1 itohy enum usbd_waitflg);
183 1.123.12.1 itohy
184 1.123.12.1 itohy Static usbd_status ehci_map_alloc(usbd_xfer_handle);
185 1.123.12.1 itohy Static void ehci_map_free(usbd_xfer_handle);
186 1.123.12.1 itohy Static void ehci_mapm(usbd_xfer_handle, void *, size_t);
187 1.123.12.2 itohy Static usbd_status ehci_mapm_mbuf(usbd_xfer_handle, struct mbuf *);
188 1.123.12.1 itohy Static void ehci_unmapm(usbd_xfer_handle);
189 1.5 augustss
190 1.123.12.1 itohy Static usbd_xfer_handle ehci_allocx(struct usbd_bus *, usbd_pipe_handle,
191 1.123.12.1 itohy enum usbd_waitflg);
192 1.5 augustss Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle);
193 1.5 augustss
194 1.5 augustss Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle);
195 1.5 augustss Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle);
196 1.5 augustss Static void ehci_root_ctrl_abort(usbd_xfer_handle);
197 1.5 augustss Static void ehci_root_ctrl_close(usbd_pipe_handle);
198 1.5 augustss Static void ehci_root_ctrl_done(usbd_xfer_handle);
199 1.5 augustss
200 1.5 augustss Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle);
201 1.5 augustss Static usbd_status ehci_root_intr_start(usbd_xfer_handle);
202 1.5 augustss Static void ehci_root_intr_abort(usbd_xfer_handle);
203 1.5 augustss Static void ehci_root_intr_close(usbd_pipe_handle);
204 1.5 augustss Static void ehci_root_intr_done(usbd_xfer_handle);
205 1.5 augustss
206 1.5 augustss Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle);
207 1.5 augustss Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle);
208 1.5 augustss Static void ehci_device_ctrl_abort(usbd_xfer_handle);
209 1.5 augustss Static void ehci_device_ctrl_close(usbd_pipe_handle);
210 1.5 augustss Static void ehci_device_ctrl_done(usbd_xfer_handle);
211 1.5 augustss
212 1.5 augustss Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle);
213 1.5 augustss Static usbd_status ehci_device_bulk_start(usbd_xfer_handle);
214 1.5 augustss Static void ehci_device_bulk_abort(usbd_xfer_handle);
215 1.5 augustss Static void ehci_device_bulk_close(usbd_pipe_handle);
216 1.5 augustss Static void ehci_device_bulk_done(usbd_xfer_handle);
217 1.5 augustss
218 1.5 augustss Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle);
219 1.5 augustss Static usbd_status ehci_device_intr_start(usbd_xfer_handle);
220 1.5 augustss Static void ehci_device_intr_abort(usbd_xfer_handle);
221 1.5 augustss Static void ehci_device_intr_close(usbd_pipe_handle);
222 1.5 augustss Static void ehci_device_intr_done(usbd_xfer_handle);
223 1.5 augustss
224 1.5 augustss Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle);
225 1.5 augustss Static usbd_status ehci_device_isoc_start(usbd_xfer_handle);
226 1.5 augustss Static void ehci_device_isoc_abort(usbd_xfer_handle);
227 1.5 augustss Static void ehci_device_isoc_close(usbd_pipe_handle);
228 1.5 augustss Static void ehci_device_isoc_done(usbd_xfer_handle);
229 1.5 augustss
230 1.5 augustss Static void ehci_device_clear_toggle(usbd_pipe_handle pipe);
231 1.5 augustss Static void ehci_noop(usbd_pipe_handle pipe);
232 1.5 augustss
233 1.104 christos Static int ehci_str(usb_string_descriptor_t *, int, const char *);
234 1.6 augustss Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle);
235 1.6 augustss Static void ehci_disown(ehci_softc_t *, int, int);
236 1.5 augustss
237 1.123.12.1 itohy Static usbd_status ehci_grow_sqtd(ehci_softc_t *);
238 1.9 augustss Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *);
239 1.9 augustss Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
240 1.9 augustss
241 1.9 augustss Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
242 1.123.12.1 itohy Static ehci_soft_qtd_t *ehci_alloc_sqtd_norsv(ehci_softc_t *);
243 1.9 augustss Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
244 1.123.12.1 itohy Static void ehci_free_sqtd_norsv(ehci_softc_t *, ehci_soft_qtd_t *);
245 1.25 augustss Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *,
246 1.15 augustss ehci_softc_t *, int, int, usbd_xfer_handle,
247 1.123.12.1 itohy ehci_soft_qtd_t *, ehci_soft_qtd_t *,
248 1.15 augustss ehci_soft_qtd_t **, ehci_soft_qtd_t **);
249 1.123.12.1 itohy Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qh_t *,
250 1.123.12.1 itohy ehci_soft_qtd_t *, ehci_soft_qtd_t *);
251 1.123.12.1 itohy Static void ehci_free_desc_chunks(ehci_softc_t *,
252 1.123.12.1 itohy struct ehci_mdescs *);
253 1.15 augustss
254 1.15 augustss Static usbd_status ehci_device_request(usbd_xfer_handle xfer);
255 1.9 augustss
256 1.78 augustss Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *,
257 1.78 augustss int ival);
258 1.78 augustss
259 1.123.12.1 itohy Static void ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *,
260 1.123.12.1 itohy ehci_soft_qh_t *);
261 1.10 augustss Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
262 1.10 augustss ehci_soft_qh_t *);
263 1.123.12.1 itohy Static void ehci_activate_qh(ehci_softc_t *, ehci_soft_qh_t *,
264 1.123.12.1 itohy ehci_soft_qtd_t *);
265 1.11 augustss Static void ehci_sync_hc(ehci_softc_t *);
266 1.10 augustss
267 1.10 augustss Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *);
268 1.10 augustss Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status);
269 1.9 augustss
270 1.5 augustss #ifdef EHCI_DEBUG
271 1.18 augustss Static void ehci_dump_regs(ehci_softc_t *);
272 1.107 augustss void ehci_dump(void);
273 1.6 augustss Static ehci_softc_t *theehci;
274 1.15 augustss Static void ehci_dump_link(ehci_link_t, int);
275 1.15 augustss Static void ehci_dump_sqtds(ehci_soft_qtd_t *);
276 1.9 augustss Static void ehci_dump_sqtd(ehci_soft_qtd_t *);
277 1.9 augustss Static void ehci_dump_qtd(ehci_qtd_t *);
278 1.9 augustss Static void ehci_dump_sqh(ehci_soft_qh_t *);
279 1.38 martin #ifdef DIAGNOSTIC
280 1.18 augustss Static void ehci_dump_exfer(struct ehci_xfer *);
281 1.5 augustss #endif
282 1.38 martin #endif
283 1.5 augustss
284 1.11 augustss #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
285 1.11 augustss
286 1.5 augustss #define EHCI_INTR_ENDPT 1
287 1.5 augustss
288 1.18 augustss #define ehci_add_intr_list(sc, ex) \
289 1.18 augustss LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext);
290 1.18 augustss #define ehci_del_intr_list(ex) \
291 1.44 augustss do { \
292 1.44 augustss LIST_REMOVE((ex), inext); \
293 1.44 augustss (ex)->inext.le_prev = NULL; \
294 1.44 augustss } while (0)
295 1.44 augustss #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL)
296 1.18 augustss
297 1.123 drochner Static const struct usbd_bus_methods ehci_bus_methods = {
298 1.5 augustss ehci_open,
299 1.5 augustss ehci_softintr,
300 1.5 augustss ehci_poll,
301 1.5 augustss ehci_allocm,
302 1.5 augustss ehci_freem,
303 1.123.12.1 itohy ehci_map_alloc,
304 1.123.12.1 itohy ehci_map_free,
305 1.123.12.1 itohy ehci_mapm,
306 1.123.12.1 itohy ehci_mapm_mbuf,
307 1.123.12.1 itohy ehci_unmapm,
308 1.5 augustss ehci_allocx,
309 1.5 augustss ehci_freex,
310 1.5 augustss };
311 1.5 augustss
312 1.123 drochner Static const struct usbd_pipe_methods ehci_root_ctrl_methods = {
313 1.5 augustss ehci_root_ctrl_transfer,
314 1.5 augustss ehci_root_ctrl_start,
315 1.5 augustss ehci_root_ctrl_abort,
316 1.5 augustss ehci_root_ctrl_close,
317 1.5 augustss ehci_noop,
318 1.5 augustss ehci_root_ctrl_done,
319 1.5 augustss };
320 1.5 augustss
321 1.123 drochner Static const struct usbd_pipe_methods ehci_root_intr_methods = {
322 1.5 augustss ehci_root_intr_transfer,
323 1.5 augustss ehci_root_intr_start,
324 1.5 augustss ehci_root_intr_abort,
325 1.5 augustss ehci_root_intr_close,
326 1.5 augustss ehci_noop,
327 1.5 augustss ehci_root_intr_done,
328 1.5 augustss };
329 1.5 augustss
330 1.123 drochner Static const struct usbd_pipe_methods ehci_device_ctrl_methods = {
331 1.5 augustss ehci_device_ctrl_transfer,
332 1.5 augustss ehci_device_ctrl_start,
333 1.5 augustss ehci_device_ctrl_abort,
334 1.5 augustss ehci_device_ctrl_close,
335 1.5 augustss ehci_noop,
336 1.5 augustss ehci_device_ctrl_done,
337 1.5 augustss };
338 1.5 augustss
339 1.123 drochner Static const struct usbd_pipe_methods ehci_device_intr_methods = {
340 1.5 augustss ehci_device_intr_transfer,
341 1.5 augustss ehci_device_intr_start,
342 1.5 augustss ehci_device_intr_abort,
343 1.5 augustss ehci_device_intr_close,
344 1.5 augustss ehci_device_clear_toggle,
345 1.5 augustss ehci_device_intr_done,
346 1.5 augustss };
347 1.5 augustss
348 1.123 drochner Static const struct usbd_pipe_methods ehci_device_bulk_methods = {
349 1.5 augustss ehci_device_bulk_transfer,
350 1.5 augustss ehci_device_bulk_start,
351 1.5 augustss ehci_device_bulk_abort,
352 1.5 augustss ehci_device_bulk_close,
353 1.5 augustss ehci_device_clear_toggle,
354 1.5 augustss ehci_device_bulk_done,
355 1.5 augustss };
356 1.5 augustss
357 1.123 drochner Static const struct usbd_pipe_methods ehci_device_isoc_methods = {
358 1.5 augustss ehci_device_isoc_transfer,
359 1.5 augustss ehci_device_isoc_start,
360 1.5 augustss ehci_device_isoc_abort,
361 1.5 augustss ehci_device_isoc_close,
362 1.5 augustss ehci_noop,
363 1.5 augustss ehci_device_isoc_done,
364 1.5 augustss };
365 1.5 augustss
366 1.123 drochner static const uint8_t revbits[EHCI_MAX_POLLRATE] = {
367 1.95 augustss 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78,
368 1.95 augustss 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c,
369 1.95 augustss 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a,
370 1.95 augustss 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e,
371 1.95 augustss 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79,
372 1.95 augustss 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d,
373 1.95 augustss 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b,
374 1.95 augustss 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f,
375 1.94 augustss };
376 1.94 augustss
377 1.1 augustss usbd_status
378 1.1 augustss ehci_init(ehci_softc_t *sc)
379 1.1 augustss {
380 1.104 christos u_int32_t vers, sparams, cparams, hcr;
381 1.3 augustss u_int i;
382 1.3 augustss usbd_status err;
383 1.11 augustss ehci_soft_qh_t *sqh;
384 1.89 augustss u_int ncomp;
385 1.123.12.1 itohy int lev;
386 1.3 augustss
387 1.3 augustss DPRINTF(("ehci_init: start\n"));
388 1.6 augustss #ifdef EHCI_DEBUG
389 1.6 augustss theehci = sc;
390 1.6 augustss #endif
391 1.3 augustss
392 1.3 augustss sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
393 1.3 augustss
394 1.104 christos vers = EREAD2(sc, EHCI_HCIVERSION);
395 1.121 ad aprint_verbose("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev),
396 1.104 christos vers >> 8, vers & 0xff);
397 1.3 augustss
398 1.3 augustss sparams = EREAD4(sc, EHCI_HCSPARAMS);
399 1.3 augustss DPRINTF(("ehci_init: sparams=0x%x\n", sparams));
400 1.6 augustss sc->sc_npcomp = EHCI_HCS_N_PCC(sparams);
401 1.89 augustss ncomp = EHCI_HCS_N_CC(sparams);
402 1.89 augustss if (ncomp != sc->sc_ncomp) {
403 1.121 ad aprint_verbose("%s: wrong number of companions (%d != %d)\n",
404 1.3 augustss USBDEVNAME(sc->sc_bus.bdev),
405 1.89 augustss ncomp, sc->sc_ncomp);
406 1.89 augustss if (ncomp < sc->sc_ncomp)
407 1.89 augustss sc->sc_ncomp = ncomp;
408 1.3 augustss }
409 1.3 augustss if (sc->sc_ncomp > 0) {
410 1.123.12.1 itohy printf("%s: companion controller%s, %d port%s each:",
411 1.3 augustss USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "",
412 1.3 augustss EHCI_HCS_N_PCC(sparams),
413 1.3 augustss EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "");
414 1.3 augustss for (i = 0; i < sc->sc_ncomp; i++)
415 1.123.12.1 itohy printf(" %s", USBDEVNAME(sc->sc_comps[i]->bdev));
416 1.123.12.1 itohy printf("\n");
417 1.3 augustss }
418 1.5 augustss sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
419 1.3 augustss cparams = EREAD4(sc, EHCI_HCCPARAMS);
420 1.3 augustss DPRINTF(("ehci_init: cparams=0x%x\n", cparams));
421 1.106 augustss sc->sc_hasppc = EHCI_HCS_PPC(sparams);
422 1.36 augustss
423 1.36 augustss if (EHCI_HCC_64BIT(cparams)) {
424 1.36 augustss /* MUST clear segment register if 64 bit capable. */
425 1.36 augustss EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
426 1.36 augustss }
427 1.33 augustss
428 1.3 augustss sc->sc_bus.usbrev = USBREV_2_0;
429 1.123.12.1 itohy usb_dma_tag_init(&sc->sc_dmatag);
430 1.90 fvdl
431 1.3 augustss /* Reset the controller */
432 1.3 augustss DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev)));
433 1.3 augustss EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
434 1.3 augustss usb_delay_ms(&sc->sc_bus, 1);
435 1.3 augustss EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
436 1.3 augustss for (i = 0; i < 100; i++) {
437 1.34 augustss usb_delay_ms(&sc->sc_bus, 1);
438 1.3 augustss hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
439 1.3 augustss if (!hcr)
440 1.3 augustss break;
441 1.3 augustss }
442 1.3 augustss if (hcr) {
443 1.123.12.1 itohy printf("%s: reset timeout\n",
444 1.41 thorpej USBDEVNAME(sc->sc_bus.bdev));
445 1.3 augustss return (USBD_IOERROR);
446 1.3 augustss }
447 1.3 augustss
448 1.3 augustss /* frame list size at default, read back what we got and use that */
449 1.3 augustss switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
450 1.78 augustss case 0: sc->sc_flsize = 1024; break;
451 1.78 augustss case 1: sc->sc_flsize = 512; break;
452 1.78 augustss case 2: sc->sc_flsize = 256; break;
453 1.3 augustss case 3: return (USBD_IOERROR);
454 1.3 augustss }
455 1.123.12.1 itohy err = usb_allocmem(&sc->sc_dmatag, sc->sc_flsize * sizeof(ehci_link_t),
456 1.78 augustss EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
457 1.3 augustss if (err)
458 1.3 augustss return (err);
459 1.3 augustss DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize));
460 1.78 augustss sc->sc_flist = KERNADDR(&sc->sc_fldma, 0);
461 1.78 augustss EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
462 1.3 augustss
463 1.5 augustss /* Set up the bus struct. */
464 1.5 augustss sc->sc_bus.methods = &ehci_bus_methods;
465 1.5 augustss sc->sc_bus.pipe_size = sizeof(struct ehci_pipe);
466 1.5 augustss
467 1.123.12.1 itohy #if defined(__NetBSD__) || defined(__OpenBSD__)
468 1.112 jmcneill sc->sc_powerhook = powerhook_establish(USBDEVNAME(sc->sc_bus.bdev),
469 1.112 jmcneill ehci_power, sc);
470 1.5 augustss sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc);
471 1.123.12.1 itohy #endif
472 1.5 augustss
473 1.6 augustss sc->sc_eintrs = EHCI_NORMAL_INTRS;
474 1.6 augustss
475 1.78 augustss /*
476 1.123.12.1 itohy * Allocate the interrupt dummy QHs. These are arranged to give
477 1.123.12.1 itohy * poll intervals that are powers of 2 times 1ms.
478 1.78 augustss */
479 1.78 augustss for (i = 0; i < EHCI_INTRQHS; i++) {
480 1.78 augustss sqh = ehci_alloc_sqh(sc);
481 1.78 augustss if (sqh == NULL) {
482 1.78 augustss err = USBD_NOMEM;
483 1.78 augustss goto bad1;
484 1.78 augustss }
485 1.78 augustss sc->sc_islots[i].sqh = sqh;
486 1.78 augustss }
487 1.123.12.1 itohy lev = 0;
488 1.78 augustss for (i = 0; i < EHCI_INTRQHS; i++) {
489 1.123.12.1 itohy if (i == EHCI_IQHIDX(lev + 1, 0))
490 1.123.12.1 itohy lev++;
491 1.78 augustss sqh = sc->sc_islots[i].sqh;
492 1.78 augustss if (i == 0) {
493 1.78 augustss /* The last (1ms) QH terminates. */
494 1.78 augustss sqh->qh.qh_link = EHCI_NULL;
495 1.78 augustss sqh->next = NULL;
496 1.78 augustss } else {
497 1.78 augustss /* Otherwise the next QH has half the poll interval */
498 1.123.12.1 itohy sqh->next =
499 1.123.12.1 itohy sc->sc_islots[EHCI_IQHIDX(lev - 1, i + 1)].sqh;
500 1.123.12.1 itohy sqh->qh.qh_link = htole32(EHCI_SQH_DMAADDR(sqh->next) |
501 1.78 augustss EHCI_LINK_QH);
502 1.78 augustss }
503 1.78 augustss sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
504 1.123.12.1 itohy sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1));
505 1.78 augustss sqh->qh.qh_curqtd = EHCI_NULL;
506 1.78 augustss sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
507 1.78 augustss sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
508 1.78 augustss sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
509 1.78 augustss }
510 1.78 augustss /* Point the frame list at the last level (128ms). */
511 1.78 augustss for (i = 0; i < sc->sc_flsize; i++) {
512 1.94 augustss int j;
513 1.94 augustss
514 1.94 augustss j = (i & ~(EHCI_MAX_POLLRATE-1)) |
515 1.94 augustss revbits[i & (EHCI_MAX_POLLRATE-1)];
516 1.94 augustss sc->sc_flist[j] = htole32(EHCI_LINK_QH |
517 1.123.12.1 itohy EHCI_SQH_DMAADDR(sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES
518 1.123.12.1 itohy - 1, i)].sqh));
519 1.78 augustss }
520 1.123.12.1 itohy EHCI_SQH_SYNC(sc, sqh, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
521 1.78 augustss
522 1.11 augustss /* Allocate dummy QH that starts the async list. */
523 1.11 augustss sqh = ehci_alloc_sqh(sc);
524 1.11 augustss if (sqh == NULL) {
525 1.9 augustss err = USBD_NOMEM;
526 1.9 augustss goto bad1;
527 1.9 augustss }
528 1.11 augustss /* Fill the QH */
529 1.11 augustss sqh->qh.qh_endp =
530 1.11 augustss htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
531 1.11 augustss sqh->qh.qh_link =
532 1.123.12.1 itohy htole32(EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH);
533 1.11 augustss sqh->qh.qh_curqtd = EHCI_NULL;
534 1.123.12.1 itohy sqh->prev = sqh; /*It's a circular list.. */
535 1.123.12.1 itohy sqh->next = sqh;
536 1.11 augustss /* Fill the overlay qTD */
537 1.11 augustss sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
538 1.11 augustss sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
539 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_status = htole32(0);
540 1.9 augustss #ifdef EHCI_DEBUG
541 1.9 augustss if (ehcidebug) {
542 1.27 enami ehci_dump_sqh(sqh);
543 1.9 augustss }
544 1.9 augustss #endif
545 1.123.12.1 itohy EHCI_SQH_SYNC(sc, sqh, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
546 1.9 augustss
547 1.9 augustss /* Point to async list */
548 1.11 augustss sc->sc_async_head = sqh;
549 1.123.12.1 itohy EOWRITE4(sc, EHCI_ASYNCLISTADDR, EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH);
550 1.9 augustss
551 1.108 xtraeme usb_callout_init(sc->sc_tmo_intrlist);
552 1.9 augustss
553 1.10 augustss lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0);
554 1.10 augustss
555 1.123.12.1 itohy /* Enable interrupts */
556 1.123.12.1 itohy EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
557 1.123.12.1 itohy
558 1.6 augustss /* Turn on controller */
559 1.6 augustss EOWRITE4(sc, EHCI_USBCMD,
560 1.88 augustss EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */
561 1.6 augustss (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
562 1.10 augustss EHCI_CMD_ASE |
563 1.78 augustss EHCI_CMD_PSE |
564 1.6 augustss EHCI_CMD_RS);
565 1.6 augustss
566 1.6 augustss /* Take over port ownership */
567 1.6 augustss EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
568 1.6 augustss
569 1.8 augustss for (i = 0; i < 100; i++) {
570 1.34 augustss usb_delay_ms(&sc->sc_bus, 1);
571 1.8 augustss hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
572 1.8 augustss if (!hcr)
573 1.8 augustss break;
574 1.8 augustss }
575 1.8 augustss if (hcr) {
576 1.123.12.1 itohy printf("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev));
577 1.8 augustss return (USBD_IOERROR);
578 1.8 augustss }
579 1.8 augustss
580 1.105 augustss /* Enable interrupts */
581 1.105 augustss DPRINTFN(1,("ehci_init: enabling\n"));
582 1.105 augustss EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
583 1.105 augustss
584 1.5 augustss return (USBD_NORMAL_COMPLETION);
585 1.9 augustss
586 1.9 augustss #if 0
587 1.11 augustss bad2:
588 1.15 augustss ehci_free_sqh(sc, sc->sc_async_head);
589 1.9 augustss #endif
590 1.9 augustss bad1:
591 1.123.12.1 itohy usb_freemem(&sc->sc_dmatag, &sc->sc_fldma);
592 1.123.12.1 itohy usb_dma_tag_finish(&sc->sc_dmatag);
593 1.9 augustss return (err);
594 1.1 augustss }
595 1.1 augustss
596 1.1 augustss int
597 1.1 augustss ehci_intr(void *v)
598 1.1 augustss {
599 1.6 augustss ehci_softc_t *sc = v;
600 1.6 augustss
601 1.17 augustss if (sc == NULL || sc->sc_dying)
602 1.15 augustss return (0);
603 1.15 augustss
604 1.6 augustss /* If we get an interrupt while polling, then just ignore it. */
605 1.6 augustss if (sc->sc_bus.use_polling) {
606 1.78 augustss u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
607 1.78 augustss
608 1.78 augustss if (intrs)
609 1.78 augustss EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
610 1.6 augustss #ifdef DIAGNOSTIC
611 1.65 mycroft DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n"));
612 1.6 augustss #endif
613 1.6 augustss return (0);
614 1.6 augustss }
615 1.6 augustss
616 1.33 augustss return (ehci_intr1(sc));
617 1.6 augustss }
618 1.6 augustss
619 1.6 augustss Static int
620 1.6 augustss ehci_intr1(ehci_softc_t *sc)
621 1.6 augustss {
622 1.6 augustss u_int32_t intrs, eintrs;
623 1.6 augustss
624 1.6 augustss DPRINTFN(20,("ehci_intr1: enter\n"));
625 1.6 augustss
626 1.6 augustss /* In case the interrupt occurs before initialization has completed. */
627 1.6 augustss if (sc == NULL) {
628 1.6 augustss #ifdef DIAGNOSTIC
629 1.72 augustss printf("ehci_intr1: sc == NULL\n");
630 1.6 augustss #endif
631 1.6 augustss return (0);
632 1.6 augustss }
633 1.6 augustss
634 1.6 augustss intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
635 1.6 augustss if (!intrs)
636 1.6 augustss return (0);
637 1.6 augustss
638 1.6 augustss eintrs = intrs & sc->sc_eintrs;
639 1.72 augustss DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n",
640 1.6 augustss sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS),
641 1.6 augustss (u_int)eintrs));
642 1.6 augustss if (!eintrs)
643 1.6 augustss return (0);
644 1.6 augustss
645 1.68 mycroft EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
646 1.6 augustss sc->sc_bus.intr_context++;
647 1.6 augustss sc->sc_bus.no_intrs++;
648 1.10 augustss if (eintrs & EHCI_STS_IAA) {
649 1.10 augustss DPRINTF(("ehci_intr1: door bell\n"));
650 1.11 augustss wakeup(&sc->sc_async_head);
651 1.20 augustss eintrs &= ~EHCI_STS_IAA;
652 1.10 augustss }
653 1.18 augustss if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
654 1.46 augustss DPRINTFN(5,("ehci_intr1: %s %s\n",
655 1.46 augustss eintrs & EHCI_STS_INT ? "INT" : "",
656 1.46 augustss eintrs & EHCI_STS_ERRINT ? "ERRINT" : ""));
657 1.18 augustss usb_schedsoftintr(&sc->sc_bus);
658 1.21 augustss eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
659 1.6 augustss }
660 1.6 augustss if (eintrs & EHCI_STS_HSE) {
661 1.6 augustss printf("%s: unrecoverable error, controller halted\n",
662 1.6 augustss USBDEVNAME(sc->sc_bus.bdev));
663 1.6 augustss /* XXX what else */
664 1.6 augustss }
665 1.6 augustss if (eintrs & EHCI_STS_PCD) {
666 1.6 augustss ehci_pcd(sc, sc->sc_intrxfer);
667 1.6 augustss eintrs &= ~EHCI_STS_PCD;
668 1.6 augustss }
669 1.6 augustss
670 1.6 augustss sc->sc_bus.intr_context--;
671 1.6 augustss
672 1.6 augustss if (eintrs != 0) {
673 1.6 augustss /* Block unprocessed interrupts. */
674 1.6 augustss sc->sc_eintrs &= ~eintrs;
675 1.6 augustss EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
676 1.6 augustss printf("%s: blocking intrs 0x%x\n",
677 1.6 augustss USBDEVNAME(sc->sc_bus.bdev), eintrs);
678 1.6 augustss }
679 1.6 augustss
680 1.6 augustss return (1);
681 1.6 augustss }
682 1.6 augustss
683 1.6 augustss
684 1.6 augustss void
685 1.6 augustss ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer)
686 1.6 augustss {
687 1.6 augustss usbd_pipe_handle pipe;
688 1.6 augustss u_char *p;
689 1.6 augustss int i, m;
690 1.6 augustss
691 1.6 augustss if (xfer == NULL) {
692 1.6 augustss /* Just ignore the change. */
693 1.6 augustss return;
694 1.6 augustss }
695 1.6 augustss
696 1.6 augustss pipe = xfer->pipe;
697 1.6 augustss
698 1.123.12.1 itohy p = xfer->hcbuffer;
699 1.6 augustss m = min(sc->sc_noport, xfer->length * 8 - 1);
700 1.6 augustss memset(p, 0, xfer->length);
701 1.6 augustss for (i = 1; i <= m; i++) {
702 1.6 augustss /* Pick out CHANGE bits from the status reg. */
703 1.6 augustss if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
704 1.6 augustss p[i/8] |= 1 << (i%8);
705 1.6 augustss }
706 1.6 augustss DPRINTF(("ehci_pcd: change=0x%02x\n", *p));
707 1.6 augustss xfer->actlen = xfer->length;
708 1.6 augustss xfer->status = USBD_NORMAL_COMPLETION;
709 1.6 augustss
710 1.123.12.1 itohy usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf);
711 1.1 augustss }
712 1.1 augustss
713 1.5 augustss void
714 1.5 augustss ehci_softintr(void *v)
715 1.5 augustss {
716 1.18 augustss ehci_softc_t *sc = v;
717 1.53 chs struct ehci_xfer *ex, *nextex;
718 1.18 augustss
719 1.18 augustss DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev),
720 1.18 augustss sc->sc_bus.intr_context));
721 1.18 augustss
722 1.18 augustss sc->sc_bus.intr_context++;
723 1.18 augustss
724 1.18 augustss /*
725 1.18 augustss * The only explanation I can think of for why EHCI is as brain dead
726 1.18 augustss * as UHCI interrupt-wise is that Intel was involved in both.
727 1.18 augustss * An interrupt just tells us that something is done, we have no
728 1.18 augustss * clue what, so we need to scan through all active transfers. :-(
729 1.18 augustss */
730 1.53 chs for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) {
731 1.53 chs nextex = LIST_NEXT(ex, inext);
732 1.18 augustss ehci_check_intr(sc, ex);
733 1.53 chs }
734 1.18 augustss
735 1.108 xtraeme /* Schedule a callout to catch any dropped transactions. */
736 1.123.12.1 itohy if ((sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) &&
737 1.123.12.1 itohy !LIST_EMPTY(&sc->sc_intrhead))
738 1.123.12.1 itohy usb_callout(sc->sc_tmo_intrlist, hz / 5, ehci_intrlist_timeout,
739 1.123.12.1 itohy sc);
740 1.123.12.1 itohy
741 1.123.12.1 itohy /* Schedule a callout to catch any dropped transactions. */
742 1.108 xtraeme if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) &&
743 1.108 xtraeme !LIST_EMPTY(&sc->sc_intrhead))
744 1.108 xtraeme usb_callout(sc->sc_tmo_intrlist, hz,
745 1.108 xtraeme ehci_intrlist_timeout, sc);
746 1.108 xtraeme
747 1.77 augustss #ifdef USB_USE_SOFTINTR
748 1.29 augustss if (sc->sc_softwake) {
749 1.29 augustss sc->sc_softwake = 0;
750 1.29 augustss wakeup(&sc->sc_softwake);
751 1.29 augustss }
752 1.77 augustss #endif /* USB_USE_SOFTINTR */
753 1.29 augustss
754 1.18 augustss sc->sc_bus.intr_context--;
755 1.18 augustss }
756 1.18 augustss
757 1.18 augustss /* Check for an interrupt. */
758 1.18 augustss void
759 1.115 christos ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
760 1.18 augustss {
761 1.18 augustss ehci_soft_qtd_t *sqtd, *lsqtd;
762 1.18 augustss u_int32_t status;
763 1.18 augustss
764 1.22 augustss DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex));
765 1.18 augustss
766 1.18 augustss if (ex->sqtdstart == NULL) {
767 1.18 augustss printf("ehci_check_intr: sqtdstart=NULL\n");
768 1.18 augustss return;
769 1.18 augustss }
770 1.18 augustss lsqtd = ex->sqtdend;
771 1.18 augustss #ifdef DIAGNOSTIC
772 1.18 augustss if (lsqtd == NULL) {
773 1.84 augustss printf("ehci_check_intr: lsqtd==0\n");
774 1.18 augustss return;
775 1.18 augustss }
776 1.18 augustss #endif
777 1.33 augustss /*
778 1.18 augustss * If the last TD is still active we need to check whether there
779 1.18 augustss * is a an error somewhere in the middle, or whether there was a
780 1.18 augustss * short packet (SPD and not ACTIVE).
781 1.18 augustss */
782 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, lsqtd, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
783 1.18 augustss if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) {
784 1.18 augustss DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex));
785 1.18 augustss for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) {
786 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, sqtd,
787 1.123.12.1 itohy BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
788 1.18 augustss status = le32toh(sqtd->qtd.qtd_status);
789 1.18 augustss /* If there's an active QTD the xfer isn't done. */
790 1.18 augustss if (status & EHCI_QTD_ACTIVE)
791 1.18 augustss break;
792 1.18 augustss /* Any kind of error makes the xfer done. */
793 1.18 augustss if (status & EHCI_QTD_HALTED)
794 1.18 augustss goto done;
795 1.18 augustss /* We want short packets, and it is short: it's done */
796 1.58 mycroft if (EHCI_QTD_GET_BYTES(status) != 0)
797 1.18 augustss goto done;
798 1.18 augustss }
799 1.18 augustss DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n",
800 1.18 augustss ex, ex->sqtdstart));
801 1.18 augustss return;
802 1.18 augustss }
803 1.18 augustss done:
804 1.18 augustss DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex));
805 1.18 augustss usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex);
806 1.123.12.1 itohy usb_rem_task(ex->xfer.pipe->device, &ex->abort_task);
807 1.18 augustss ehci_idone(ex);
808 1.18 augustss }
809 1.18 augustss
810 1.18 augustss void
811 1.18 augustss ehci_idone(struct ehci_xfer *ex)
812 1.18 augustss {
813 1.18 augustss usbd_xfer_handle xfer = &ex->xfer;
814 1.18 augustss struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
815 1.123.12.1 itohy ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
816 1.82 augustss ehci_soft_qtd_t *sqtd, *lsqtd;
817 1.82 augustss u_int32_t status = 0, nstatus = 0;
818 1.123.12.1 itohy ehci_physaddr_t nextphys, altnextphys;
819 1.123.12.1 itohy ehci_physaddr_t stdma;
820 1.123.12.1 itohy int actlen, cerr;
821 1.18 augustss
822 1.22 augustss DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex));
823 1.18 augustss #ifdef DIAGNOSTIC
824 1.18 augustss {
825 1.18 augustss int s = splhigh();
826 1.18 augustss if (ex->isdone) {
827 1.18 augustss splx(s);
828 1.18 augustss #ifdef EHCI_DEBUG
829 1.18 augustss printf("ehci_idone: ex is done!\n ");
830 1.18 augustss ehci_dump_exfer(ex);
831 1.18 augustss #else
832 1.18 augustss printf("ehci_idone: ex=%p is done!\n", ex);
833 1.18 augustss #endif
834 1.18 augustss return;
835 1.18 augustss }
836 1.18 augustss ex->isdone = 1;
837 1.18 augustss splx(s);
838 1.18 augustss }
839 1.18 augustss #endif
840 1.18 augustss
841 1.18 augustss if (xfer->status == USBD_CANCELLED ||
842 1.18 augustss xfer->status == USBD_TIMEOUT) {
843 1.18 augustss DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer));
844 1.18 augustss return;
845 1.18 augustss }
846 1.18 augustss
847 1.18 augustss #ifdef EHCI_DEBUG
848 1.23 augustss DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe));
849 1.18 augustss if (ehcidebug > 10)
850 1.18 augustss ehci_dump_sqtds(ex->sqtdstart);
851 1.18 augustss #endif
852 1.18 augustss
853 1.123.12.1 itohy /*
854 1.123.12.1 itohy * Make sure that the QH overlay qTD does not reference any
855 1.123.12.1 itohy * of the qTDs we are about to free. This is probably only
856 1.123.12.1 itohy * necessary if the transfer is marked as HALTED.
857 1.123.12.1 itohy */
858 1.123.12.1 itohy EHCI_SQH_SYNC(sc, epipe->sqh,
859 1.123.12.1 itohy BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
860 1.123.12.1 itohy nextphys = EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_next));
861 1.123.12.1 itohy altnextphys =
862 1.123.12.1 itohy EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_altnext));
863 1.123.12.1 itohy for (sqtd = ex->sqtdstart; sqtd != ex->sqtdend->nextqtd;
864 1.123.12.1 itohy sqtd = sqtd->nextqtd) {
865 1.123.12.1 itohy stdma = EHCI_SQTD_DMAADDR(sqtd);
866 1.123.12.1 itohy if (stdma == nextphys) {
867 1.123.12.1 itohy epipe->sqh->qh.qh_qtd.qtd_next =
868 1.123.12.1 itohy htole32(EHCI_SQTD_DMAADDR(ex->sqtdend->nextqtd));
869 1.123.12.1 itohy DPRINTFN(4, ("ehci_idone: updated overlay next ptr\n"));
870 1.123.12.1 itohy EHCI_SQH_SYNC(sc, epipe->sqh,
871 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
872 1.123.12.1 itohy
873 1.123.12.1 itohy }
874 1.123.12.1 itohy if (stdma == altnextphys) {
875 1.123.12.1 itohy DPRINTFN(4,
876 1.123.12.1 itohy ("ehci_idone: updated overlay altnext ptr\n"));
877 1.123.12.1 itohy epipe->sqh->qh.qh_qtd.qtd_altnext =
878 1.123.12.1 itohy htole32(EHCI_SQTD_DMAADDR(ex->sqtdend->nextqtd));
879 1.123.12.1 itohy EHCI_SQH_SYNC(sc, epipe->sqh,
880 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
881 1.123.12.1 itohy }
882 1.123.12.1 itohy }
883 1.123.12.1 itohy
884 1.18 augustss /* The transfer is done, compute actual length and status. */
885 1.82 augustss lsqtd = ex->sqtdend;
886 1.18 augustss actlen = 0;
887 1.82 augustss for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd=sqtd->nextqtd) {
888 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, sqtd,
889 1.123.12.1 itohy BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
890 1.18 augustss nstatus = le32toh(sqtd->qtd.qtd_status);
891 1.18 augustss if (nstatus & EHCI_QTD_ACTIVE)
892 1.18 augustss break;
893 1.18 augustss
894 1.18 augustss status = nstatus;
895 1.18 augustss if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
896 1.18 augustss actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
897 1.18 augustss }
898 1.22 augustss
899 1.123.12.1 itohy cerr = EHCI_QTD_GET_CERR(status);
900 1.123.12.1 itohy DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, "
901 1.123.12.1 itohy "status=0x%x\n", xfer->length, actlen, cerr, status));
902 1.18 augustss xfer->actlen = actlen;
903 1.123.12.1 itohy if ((status & EHCI_QTD_HALTED) != 0) {
904 1.18 augustss #ifdef EHCI_DEBUG
905 1.18 augustss char sbuf[128];
906 1.18 augustss
907 1.18 augustss bitmask_snprintf((u_int32_t)status,
908 1.123.12.1 itohy "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR"
909 1.123.12.1 itohy "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf));
910 1.18 augustss
911 1.123.12.1 itohy DPRINTFN(2,
912 1.123.12.1 itohy ("ehci_idone: error, addr=%d, endpt=0x%02x, "
913 1.18 augustss "status 0x%s\n",
914 1.18 augustss xfer->pipe->device->address,
915 1.18 augustss xfer->pipe->endpoint->edesc->bEndpointAddress,
916 1.18 augustss sbuf));
917 1.23 augustss if (ehcidebug > 2) {
918 1.23 augustss ehci_dump_sqh(epipe->sqh);
919 1.23 augustss ehci_dump_sqtds(ex->sqtdstart);
920 1.23 augustss }
921 1.18 augustss #endif
922 1.98 augustss /* low&full speed has an extra error flag */
923 1.98 augustss if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) !=
924 1.98 augustss EHCI_QH_SPEED_HIGH)
925 1.98 augustss status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE;
926 1.98 augustss else
927 1.98 augustss status &= EHCI_QTD_STATERRS;
928 1.98 augustss if (status == 0) /* no other errors means a stall */
929 1.18 augustss xfer->status = USBD_STALLED;
930 1.18 augustss else
931 1.18 augustss xfer->status = USBD_IOERROR; /* more info XXX */
932 1.98 augustss /* XXX need to reset TT on missed microframe */
933 1.98 augustss if (status & EHCI_QTD_MISSEDMICRO) {
934 1.98 augustss printf("%s: missed microframe, TT reset not "
935 1.98 augustss "implemented, hub might be inoperational\n",
936 1.98 augustss USBDEVNAME(sc->sc_bus.bdev));
937 1.98 augustss }
938 1.18 augustss } else {
939 1.18 augustss xfer->status = USBD_NORMAL_COMPLETION;
940 1.18 augustss }
941 1.18 augustss
942 1.123.12.1 itohy usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf);
943 1.22 augustss DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex));
944 1.5 augustss }
945 1.5 augustss
946 1.15 augustss /*
947 1.15 augustss * Wait here until controller claims to have an interrupt.
948 1.18 augustss * Then call ehci_intr and return. Use timeout to avoid waiting
949 1.15 augustss * too long.
950 1.15 augustss */
951 1.15 augustss void
952 1.15 augustss ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer)
953 1.15 augustss {
954 1.97 augustss int timo;
955 1.15 augustss u_int32_t intrs;
956 1.15 augustss
957 1.15 augustss xfer->status = USBD_IN_PROGRESS;
958 1.97 augustss for (timo = xfer->timeout; timo >= 0; timo--) {
959 1.15 augustss usb_delay_ms(&sc->sc_bus, 1);
960 1.17 augustss if (sc->sc_dying)
961 1.17 augustss break;
962 1.15 augustss intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) &
963 1.15 augustss sc->sc_eintrs;
964 1.15 augustss DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs));
965 1.70 yamt #ifdef EHCI_DEBUG
966 1.15 augustss if (ehcidebug > 15)
967 1.18 augustss ehci_dump_regs(sc);
968 1.15 augustss #endif
969 1.15 augustss if (intrs) {
970 1.15 augustss ehci_intr1(sc);
971 1.15 augustss if (xfer->status != USBD_IN_PROGRESS)
972 1.15 augustss return;
973 1.15 augustss }
974 1.15 augustss }
975 1.15 augustss
976 1.15 augustss /* Timeout */
977 1.15 augustss DPRINTF(("ehci_waitintr: timeout\n"));
978 1.15 augustss xfer->status = USBD_TIMEOUT;
979 1.123.12.1 itohy usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf);
980 1.15 augustss /* XXX should free TD */
981 1.15 augustss }
982 1.15 augustss
983 1.5 augustss void
984 1.5 augustss ehci_poll(struct usbd_bus *bus)
985 1.5 augustss {
986 1.5 augustss ehci_softc_t *sc = (ehci_softc_t *)bus;
987 1.5 augustss #ifdef EHCI_DEBUG
988 1.5 augustss static int last;
989 1.5 augustss int new;
990 1.6 augustss new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
991 1.5 augustss if (new != last) {
992 1.5 augustss DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new));
993 1.5 augustss last = new;
994 1.5 augustss }
995 1.5 augustss #endif
996 1.5 augustss
997 1.6 augustss if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs)
998 1.5 augustss ehci_intr1(sc);
999 1.5 augustss }
1000 1.5 augustss
1001 1.1 augustss int
1002 1.1 augustss ehci_detach(struct ehci_softc *sc, int flags)
1003 1.1 augustss {
1004 1.1 augustss int rv = 0;
1005 1.123.12.1 itohy usbd_xfer_handle xfer;
1006 1.1 augustss
1007 1.123.12.1 itohy #if defined(__NetBSD__) || defined(__OpenBSD__)
1008 1.1 augustss if (sc->sc_child != NULL)
1009 1.1 augustss rv = config_detach(sc->sc_child, flags);
1010 1.33 augustss
1011 1.1 augustss if (rv != 0)
1012 1.1 augustss return (rv);
1013 1.123.12.1 itohy #else
1014 1.123.12.1 itohy sc->sc_dying = 1;
1015 1.123.12.1 itohy #endif
1016 1.1 augustss
1017 1.123.12.1 itohy if (sc->sc_bus.methods == NULL)
1018 1.123.12.1 itohy return (rv); /* attach has been aborted */
1019 1.123.12.1 itohy
1020 1.123.12.1 itohy #if defined(__NetBSD__) || defined(__OpenBSD__)
1021 1.123.12.1 itohy /* Don't touch hardware if it has already been gone. */
1022 1.123.12.1 itohy if ((flags & DETACH_FORCE) == 0)
1023 1.123.12.1 itohy #endif
1024 1.123.12.1 itohy {
1025 1.123.12.1 itohy EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1026 1.123.12.1 itohy EOWRITE4(sc, EHCI_USBCMD, 0);
1027 1.123.12.1 itohy EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
1028 1.123.12.1 itohy }
1029 1.108 xtraeme usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc);
1030 1.6 augustss
1031 1.123.12.1 itohy #if defined(__NetBSD__) || defined(__OpenBSD__)
1032 1.1 augustss if (sc->sc_powerhook != NULL)
1033 1.1 augustss powerhook_disestablish(sc->sc_powerhook);
1034 1.1 augustss if (sc->sc_shutdownhook != NULL)
1035 1.1 augustss shutdownhook_disestablish(sc->sc_shutdownhook);
1036 1.123.12.1 itohy #endif
1037 1.1 augustss
1038 1.17 augustss usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
1039 1.15 augustss
1040 1.123.12.1 itohy usb_freemem(&sc->sc_dmatag, &sc->sc_fldma);
1041 1.1 augustss /* XXX free other data structures XXX */
1042 1.1 augustss
1043 1.123.12.1 itohy while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) {
1044 1.123.12.1 itohy SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
1045 1.123.12.1 itohy usb_clean_buffer_dma(&sc->sc_dmatag, &EXFER(xfer)->dmabuf);
1046 1.123.12.1 itohy free(xfer, M_USB);
1047 1.123.12.1 itohy }
1048 1.123.12.1 itohy ehci_free_desc_chunks(sc, &sc->sc_sqh_chunks);
1049 1.123.12.1 itohy ehci_free_desc_chunks(sc, &sc->sc_sqtd_chunks);
1050 1.123.12.1 itohy usb_dma_tag_finish(&sc->sc_dmatag);
1051 1.123.12.1 itohy
1052 1.1 augustss return (rv);
1053 1.1 augustss }
1054 1.1 augustss
1055 1.123.12.1 itohy Static void
1056 1.123.12.1 itohy ehci_free_desc_chunks(ehci_softc_t *sc, struct ehci_mdescs *c)
1057 1.123.12.1 itohy {
1058 1.123.12.1 itohy struct ehci_mem_desc *em;
1059 1.123.12.1 itohy
1060 1.123.12.1 itohy while ((em = SIMPLEQ_FIRST(c)) != NULL) {
1061 1.123.12.1 itohy SIMPLEQ_REMOVE_HEAD(c, em_next);
1062 1.123.12.1 itohy usb_freemem(&sc->sc_dmatag, &em->em_dma);
1063 1.123.12.1 itohy }
1064 1.123.12.1 itohy }
1065 1.1 augustss
1066 1.123.12.1 itohy #if defined(__NetBSD__) || defined(__OpenBSD__)
1067 1.1 augustss int
1068 1.123.12.1 itohy ehci_activate(device_t self, enum devact act)
1069 1.1 augustss {
1070 1.1 augustss struct ehci_softc *sc = (struct ehci_softc *)self;
1071 1.1 augustss int rv = 0;
1072 1.1 augustss
1073 1.1 augustss switch (act) {
1074 1.1 augustss case DVACT_ACTIVATE:
1075 1.1 augustss return (EOPNOTSUPP);
1076 1.1 augustss
1077 1.1 augustss case DVACT_DEACTIVATE:
1078 1.1 augustss if (sc->sc_child != NULL)
1079 1.1 augustss rv = config_deactivate(sc->sc_child);
1080 1.5 augustss sc->sc_dying = 1;
1081 1.1 augustss break;
1082 1.1 augustss }
1083 1.1 augustss return (rv);
1084 1.1 augustss }
1085 1.123.12.1 itohy #endif
1086 1.1 augustss
1087 1.5 augustss /*
1088 1.5 augustss * Handle suspend/resume.
1089 1.5 augustss *
1090 1.5 augustss * We need to switch to polling mode here, because this routine is
1091 1.73 augustss * called from an interrupt context. This is all right since we
1092 1.5 augustss * are almost suspended anyway.
1093 1.5 augustss */
1094 1.5 augustss void
1095 1.5 augustss ehci_power(int why, void *v)
1096 1.5 augustss {
1097 1.5 augustss ehci_softc_t *sc = v;
1098 1.74 augustss u_int32_t cmd, hcr;
1099 1.74 augustss int s, i;
1100 1.5 augustss
1101 1.5 augustss #ifdef EHCI_DEBUG
1102 1.5 augustss DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why));
1103 1.74 augustss if (ehcidebug > 0)
1104 1.74 augustss ehci_dump_regs(sc);
1105 1.5 augustss #endif
1106 1.5 augustss
1107 1.5 augustss s = splhardusb();
1108 1.5 augustss switch (why) {
1109 1.123.12.1 itohy USB_PWR_CASE_SUSPEND:
1110 1.5 augustss sc->sc_bus.use_polling++;
1111 1.74 augustss
1112 1.123.12.1 itohy for (i = 1; i <= sc->sc_noport; i++) {
1113 1.123.12.1 itohy cmd = EOREAD4(sc, EHCI_PORTSC(i));
1114 1.123.12.1 itohy if ((cmd & EHCI_PS_PO) == 0 &&
1115 1.123.12.1 itohy (cmd & EHCI_PS_PE) == EHCI_PS_PE)
1116 1.123.12.1 itohy EOWRITE4(sc, EHCI_PORTSC(i),
1117 1.123.12.1 itohy cmd | EHCI_PS_SUSP);
1118 1.123.12.1 itohy }
1119 1.123.12.1 itohy
1120 1.74 augustss sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
1121 1.74 augustss
1122 1.74 augustss cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
1123 1.74 augustss EOWRITE4(sc, EHCI_USBCMD, cmd);
1124 1.74 augustss
1125 1.74 augustss for (i = 0; i < 100; i++) {
1126 1.74 augustss hcr = EOREAD4(sc, EHCI_USBSTS) &
1127 1.74 augustss (EHCI_STS_ASS | EHCI_STS_PSS);
1128 1.74 augustss if (hcr == 0)
1129 1.74 augustss break;
1130 1.74 augustss
1131 1.74 augustss usb_delay_ms(&sc->sc_bus, 1);
1132 1.74 augustss }
1133 1.74 augustss if (hcr != 0) {
1134 1.74 augustss printf("%s: reset timeout\n",
1135 1.74 augustss USBDEVNAME(sc->sc_bus.bdev));
1136 1.74 augustss }
1137 1.74 augustss
1138 1.74 augustss cmd &= ~EHCI_CMD_RS;
1139 1.74 augustss EOWRITE4(sc, EHCI_USBCMD, cmd);
1140 1.74 augustss
1141 1.74 augustss for (i = 0; i < 100; i++) {
1142 1.74 augustss hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1143 1.74 augustss if (hcr == EHCI_STS_HCH)
1144 1.74 augustss break;
1145 1.74 augustss
1146 1.74 augustss usb_delay_ms(&sc->sc_bus, 1);
1147 1.74 augustss }
1148 1.74 augustss if (hcr != EHCI_STS_HCH) {
1149 1.74 augustss printf("%s: config timeout\n",
1150 1.74 augustss USBDEVNAME(sc->sc_bus.bdev));
1151 1.5 augustss }
1152 1.74 augustss
1153 1.5 augustss sc->sc_bus.use_polling--;
1154 1.5 augustss break;
1155 1.74 augustss
1156 1.123.12.1 itohy USB_PWR_CASE_RESUME:
1157 1.5 augustss sc->sc_bus.use_polling++;
1158 1.74 augustss
1159 1.74 augustss /* restore things in case the bios sucks */
1160 1.74 augustss EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
1161 1.74 augustss EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
1162 1.74 augustss EOWRITE4(sc, EHCI_ASYNCLISTADDR,
1163 1.123.12.1 itohy EHCI_SQH_DMAADDR(sc->sc_async_head) | EHCI_LINK_QH);
1164 1.74 augustss EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1165 1.74 augustss
1166 1.123.12.1 itohy hcr = 0;
1167 1.123.12.1 itohy for (i = 1; i <= sc->sc_noport; i++) {
1168 1.123.12.1 itohy cmd = EOREAD4(sc, EHCI_PORTSC(i));
1169 1.123.12.1 itohy if ((cmd & EHCI_PS_PO) == 0 &&
1170 1.123.12.1 itohy (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) {
1171 1.123.12.1 itohy EOWRITE4(sc, EHCI_PORTSC(i),
1172 1.123.12.1 itohy cmd | EHCI_PS_FPR);
1173 1.123.12.1 itohy hcr = 1;
1174 1.123.12.1 itohy }
1175 1.123.12.1 itohy }
1176 1.123.12.1 itohy
1177 1.123.12.1 itohy if (hcr) {
1178 1.123.12.1 itohy usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1179 1.123.12.1 itohy
1180 1.123.12.1 itohy for (i = 1; i <= sc->sc_noport; i++) {
1181 1.123.12.1 itohy cmd = EOREAD4(sc, EHCI_PORTSC(i));
1182 1.123.12.1 itohy if ((cmd & EHCI_PS_PO) == 0 &&
1183 1.123.12.1 itohy (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)
1184 1.123.12.1 itohy EOWRITE4(sc, EHCI_PORTSC(i),
1185 1.123.12.1 itohy cmd & ~EHCI_PS_FPR);
1186 1.123.12.1 itohy }
1187 1.123.12.1 itohy }
1188 1.123.12.1 itohy
1189 1.74 augustss EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1190 1.74 augustss
1191 1.74 augustss for (i = 0; i < 100; i++) {
1192 1.74 augustss hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1193 1.74 augustss if (hcr != EHCI_STS_HCH)
1194 1.74 augustss break;
1195 1.74 augustss
1196 1.74 augustss usb_delay_ms(&sc->sc_bus, 1);
1197 1.74 augustss }
1198 1.74 augustss if (hcr == EHCI_STS_HCH) {
1199 1.74 augustss printf("%s: config timeout\n",
1200 1.74 augustss USBDEVNAME(sc->sc_bus.bdev));
1201 1.74 augustss }
1202 1.74 augustss
1203 1.74 augustss usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1204 1.74 augustss
1205 1.5 augustss sc->sc_bus.use_polling--;
1206 1.5 augustss break;
1207 1.123.12.1 itohy
1208 1.123.12.1 itohy default:
1209 1.5 augustss break;
1210 1.5 augustss }
1211 1.5 augustss splx(s);
1212 1.74 augustss
1213 1.74 augustss #ifdef EHCI_DEBUG
1214 1.74 augustss DPRINTF(("ehci_power: sc=%p\n", sc));
1215 1.74 augustss if (ehcidebug > 0)
1216 1.74 augustss ehci_dump_regs(sc);
1217 1.74 augustss #endif
1218 1.5 augustss }
1219 1.5 augustss
1220 1.5 augustss /*
1221 1.5 augustss * Shut down the controller when the system is going down.
1222 1.5 augustss */
1223 1.5 augustss void
1224 1.5 augustss ehci_shutdown(void *v)
1225 1.5 augustss {
1226 1.8 augustss ehci_softc_t *sc = v;
1227 1.5 augustss
1228 1.5 augustss DPRINTF(("ehci_shutdown: stopping the HC\n"));
1229 1.8 augustss EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
1230 1.8 augustss EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
1231 1.5 augustss }
1232 1.5 augustss
1233 1.123.12.3 itohy /*
1234 1.123.12.3 itohy * Allocate a physically contiguous buffer to handle cases where EHCI
1235 1.123.12.3 itohy * cannot handle a packet because it is not physically contiguous.
1236 1.123.12.3 itohy */
1237 1.123.12.3 itohy Static void
1238 1.123.12.3 itohy ehci_aux_mem_init(struct ehci_aux_mem *aux)
1239 1.123.12.3 itohy {
1240 1.123.12.3 itohy
1241 1.123.12.3 itohy aux->aux_curchunk = aux->aux_chunkoff = aux->aux_naux = 0;
1242 1.123.12.3 itohy }
1243 1.123.12.3 itohy
1244 1.123.12.3 itohy Static usbd_status
1245 1.123.12.3 itohy ehci_aux_mem_alloc(ehci_softc_t *sc, struct ehci_aux_mem *aux,
1246 1.123.12.3 itohy int naux, int maxp)
1247 1.123.12.3 itohy {
1248 1.123.12.3 itohy int nchunk, i, j;
1249 1.123.12.3 itohy usbd_status err;
1250 1.123.12.3 itohy
1251 1.123.12.3 itohy USB_KASSERT(aux->aux_nchunk == 0);
1252 1.123.12.3 itohy
1253 1.123.12.3 itohy nchunk = EHCI_NCHUNK(naux, maxp);
1254 1.123.12.3 itohy for (i = 0; i < nchunk; i++) {
1255 1.123.12.3 itohy err = usb_allocmem(&sc->sc_dmatag, EHCI_AUX_CHUNK_SIZE,
1256 1.123.12.3 itohy EHCI_AUX_CHUNK_SIZE, &aux->aux_chunk_dma[i]);
1257 1.123.12.3 itohy if (err) {
1258 1.123.12.3 itohy for (j = 0; j < i; j++)
1259 1.123.12.3 itohy usb_freemem(&sc->sc_dmatag,
1260 1.123.12.3 itohy &aux->aux_chunk_dma[j]);
1261 1.123.12.3 itohy return (err);
1262 1.123.12.3 itohy }
1263 1.123.12.3 itohy }
1264 1.123.12.3 itohy
1265 1.123.12.3 itohy aux->aux_nchunk = nchunk;
1266 1.123.12.3 itohy ehci_aux_mem_init(aux);
1267 1.123.12.3 itohy
1268 1.123.12.3 itohy return (USBD_NORMAL_COMPLETION);
1269 1.123.12.3 itohy }
1270 1.123.12.3 itohy
1271 1.123.12.3 itohy Static void
1272 1.123.12.3 itohy ehci_aux_mem_free(ehci_softc_t *sc, struct ehci_aux_mem *aux)
1273 1.123.12.3 itohy {
1274 1.123.12.3 itohy int i;
1275 1.123.12.3 itohy
1276 1.123.12.3 itohy /* sync last aux (just in case, probably a no-op) */
1277 1.123.12.3 itohy if (aux->aux_naux)
1278 1.123.12.3 itohy ehci_aux_dma_sync(sc, aux, BUS_DMASYNC_POSTWRITE);
1279 1.123.12.3 itohy
1280 1.123.12.3 itohy for (i = 0; i < aux->aux_nchunk; i++)
1281 1.123.12.3 itohy usb_freemem(&sc->sc_dmatag, &aux->aux_chunk_dma[i]);
1282 1.123.12.3 itohy
1283 1.123.12.3 itohy aux->aux_nchunk = 0;
1284 1.123.12.3 itohy }
1285 1.123.12.3 itohy
1286 1.123.12.3 itohy Static bus_addr_t
1287 1.123.12.3 itohy ehci_aux_dma_alloc(struct ehci_aux_mem *aux, int len, struct aux_desc *ad)
1288 1.123.12.3 itohy {
1289 1.123.12.3 itohy bus_addr_t auxdma;
1290 1.123.12.3 itohy
1291 1.123.12.3 itohy if (aux->aux_chunkoff + len > EHCI_AUX_CHUNK_SIZE) {
1292 1.123.12.3 itohy aux->aux_curchunk++;
1293 1.123.12.3 itohy aux->aux_chunkoff = 0;
1294 1.123.12.3 itohy }
1295 1.123.12.3 itohy USB_KASSERT(aux->aux_curchunk < aux->aux_nchunk);
1296 1.123.12.3 itohy
1297 1.123.12.3 itohy auxdma =
1298 1.123.12.3 itohy DMAADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff);
1299 1.123.12.3 itohy ad->aux_kern =
1300 1.123.12.3 itohy KERNADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff);
1301 1.123.12.3 itohy
1302 1.123.12.3 itohy aux->aux_chunkoff += len;
1303 1.123.12.3 itohy aux->aux_naux++;
1304 1.123.12.3 itohy
1305 1.123.12.3 itohy return auxdma;
1306 1.123.12.3 itohy }
1307 1.123.12.3 itohy
1308 1.123.12.3 itohy Static void
1309 1.123.12.3 itohy ehci_aux_dma_sync(ehci_softc_t *sc, struct ehci_aux_mem *aux, int op)
1310 1.123.12.3 itohy {
1311 1.123.12.3 itohy int i;
1312 1.123.12.3 itohy
1313 1.123.12.3 itohy for (i = 0; i < aux->aux_curchunk; i++)
1314 1.123.12.3 itohy USB_MEM_SYNC(&sc->sc_dmatag, &aux->aux_chunk_dma[i], op);
1315 1.123.12.3 itohy if (aux->aux_chunkoff)
1316 1.123.12.3 itohy USB_MEM_SYNC2(&sc->sc_dmatag, &aux->aux_chunk_dma[i],
1317 1.123.12.3 itohy 0, aux->aux_chunkoff, op);
1318 1.123.12.3 itohy }
1319 1.123.12.3 itohy
1320 1.123.12.1 itohy Static usbd_status
1321 1.123.12.1 itohy ehci_prealloc(struct ehci_softc *sc, struct ehci_xfer *exfer,
1322 1.123.12.1 itohy size_t bufsize, int nseg)
1323 1.123.12.1 itohy {
1324 1.123.12.3 itohy usb_endpoint_descriptor_t *endpt;
1325 1.123.12.3 itohy int maxseg, mps, naux;
1326 1.123.12.1 itohy int seglen, ntd;
1327 1.123.12.1 itohy int s;
1328 1.123.12.1 itohy int err;
1329 1.123.12.1 itohy
1330 1.123.12.3 itohy endpt = exfer->xfer.pipe->endpoint->edesc;
1331 1.123.12.3 itohy mps = UE_MAXPKTSZ(endpt);
1332 1.123.12.3 itohy
1333 1.123.12.3 itohy if (mps == 0)
1334 1.123.12.3 itohy return (USBD_INVAL);
1335 1.123.12.3 itohy
1336 1.123.12.1 itohy /* (over) estimate needed number of TDs */
1337 1.123.12.3 itohy maxseg = EHCI_PAGE_SIZE * EHCI_QTD_NBUFFERS;
1338 1.123.12.3 itohy seglen = maxseg - (maxseg % mps);
1339 1.123.12.1 itohy ntd = bufsize / seglen + nseg;
1340 1.123.12.1 itohy
1341 1.123.12.3 itohy #if 1
1342 1.123.12.3 itohy /* allocate aux buffer for non-isoc OUT transfer */
1343 1.123.12.3 itohy naux = 0;
1344 1.123.12.3 itohy if (nseg > 1 &&
1345 1.123.12.3 itohy (endpt->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS &&
1346 1.123.12.3 itohy UE_GET_DIR(endpt->bEndpointAddress) == UE_DIR_OUT) {
1347 1.123.12.3 itohy /* estimate needed aux segments */
1348 1.123.12.3 itohy naux = nseg - 1;
1349 1.123.12.3 itohy
1350 1.123.12.3 itohy /* pre-allocate aux memory */
1351 1.123.12.3 itohy err = ehci_aux_mem_alloc(sc, &exfer->aux, naux, mps);
1352 1.123.12.3 itohy if (err)
1353 1.123.12.3 itohy return err;
1354 1.123.12.3 itohy
1355 1.123.12.3 itohy /* an aux segment will consume a TD */
1356 1.123.12.3 itohy ntd += naux;
1357 1.123.12.3 itohy }
1358 1.123.12.3 itohy #endif
1359 1.123.12.3 itohy
1360 1.123.12.1 itohy s = splusb();
1361 1.123.12.1 itohy /* pre-allocate QDs */
1362 1.123.12.1 itohy /* XXX ITDs */
1363 1.123.12.1 itohy while (sc->sc_nfreeqtds < ntd) {
1364 1.123.12.1 itohy DPRINTF(("%s: qhci_prealloc: need %d QTD (%d cur)\n",
1365 1.123.12.1 itohy USBDEVNAME(sc->sc_bus.bdev), ntd, sc->sc_nfreeqtds));
1366 1.123.12.1 itohy if ((err = ehci_grow_sqtd(sc)) != USBD_NORMAL_COMPLETION) {
1367 1.123.12.1 itohy splx(s);
1368 1.123.12.3 itohy ehci_aux_mem_free(sc, &exfer->aux);
1369 1.123.12.1 itohy return err;
1370 1.123.12.1 itohy }
1371 1.123.12.1 itohy }
1372 1.123.12.1 itohy sc->sc_nfreeqtds -= ntd;
1373 1.123.12.1 itohy splx(s);
1374 1.123.12.1 itohy
1375 1.123.12.1 itohy exfer->rsvd_tds = ntd;
1376 1.123.12.1 itohy
1377 1.123.12.1 itohy return USBD_NORMAL_COMPLETION;
1378 1.123.12.1 itohy }
1379 1.123.12.1 itohy
1380 1.5 augustss usbd_status
1381 1.123.12.1 itohy ehci_allocm(struct usbd_bus *bus, usbd_xfer_handle xfer, void *buf, size_t size)
1382 1.5 augustss {
1383 1.5 augustss struct ehci_softc *sc = (struct ehci_softc *)bus;
1384 1.123.12.1 itohy struct ehci_xfer *exfer = EXFER(xfer);
1385 1.25 augustss usbd_status err;
1386 1.5 augustss
1387 1.123.12.1 itohy if ((err = usb_alloc_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf,
1388 1.123.12.1 itohy buf, size, &xfer->hcbuffer)) == USBD_NORMAL_COMPLETION) {
1389 1.123.12.1 itohy if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0 &&
1390 1.123.12.1 itohy (err = ehci_prealloc(sc, exfer, size,
1391 1.123.12.1 itohy USB_BUFFER_NSEGS(&exfer->dmabuf)))
1392 1.123.12.1 itohy != USBD_NORMAL_COMPLETION) {
1393 1.123.12.1 itohy usb_free_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf,
1394 1.123.12.1 itohy U_WAITOK);
1395 1.123.12.1 itohy }
1396 1.123.12.1 itohy }
1397 1.25 augustss #ifdef EHCI_DEBUG
1398 1.25 augustss if (err)
1399 1.123.12.1 itohy printf("ehci_allocm: usb_alloc_buffer_dma()=%d\n", err);
1400 1.25 augustss #endif
1401 1.25 augustss return (err);
1402 1.5 augustss }
1403 1.5 augustss
1404 1.5 augustss void
1405 1.123.12.1 itohy ehci_freem(struct usbd_bus *bus, usbd_xfer_handle xfer,
1406 1.123.12.1 itohy enum usbd_waitflg waitflg)
1407 1.5 augustss {
1408 1.5 augustss struct ehci_softc *sc = (struct ehci_softc *)bus;
1409 1.123.12.1 itohy struct ehci_xfer *exfer = EXFER(xfer);
1410 1.123.12.1 itohy int s;
1411 1.5 augustss
1412 1.123.12.1 itohy usb_free_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, waitflg);
1413 1.123.12.1 itohy
1414 1.123.12.3 itohy if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0) {
1415 1.123.12.3 itohy /* XXX ITDs */
1416 1.123.12.1 itohy
1417 1.123.12.3 itohy s = splusb();
1418 1.123.12.3 itohy sc->sc_nfreeqtds += exfer->rsvd_tds;
1419 1.123.12.3 itohy splx(s);
1420 1.123.12.3 itohy exfer->rsvd_tds = 0;
1421 1.123.12.3 itohy ehci_aux_mem_free(sc, &exfer->aux);
1422 1.123.12.3 itohy }
1423 1.123.12.1 itohy }
1424 1.123.12.1 itohy
1425 1.123.12.1 itohy Static usbd_status
1426 1.123.12.1 itohy ehci_map_alloc(usbd_xfer_handle xfer)
1427 1.123.12.1 itohy {
1428 1.123.12.1 itohy struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus;
1429 1.123.12.1 itohy struct ehci_xfer *exfer = EXFER(xfer);
1430 1.123.12.1 itohy usbd_status st;
1431 1.123.12.1 itohy
1432 1.123.12.1 itohy st = usb_alloc_dma_resources(&sc->sc_dmatag, &exfer->dmabuf);
1433 1.123.12.1 itohy if (st)
1434 1.123.12.1 itohy return st;
1435 1.123.12.1 itohy
1436 1.123.12.1 itohy if ((st = ehci_prealloc(sc, exfer, MAXPHYS, USB_DMA_NSEG))) {
1437 1.123.12.1 itohy usb_free_dma_resources(&sc->sc_dmatag, &exfer->dmabuf);
1438 1.90 fvdl }
1439 1.123.12.1 itohy
1440 1.123.12.1 itohy return st;
1441 1.123.12.1 itohy }
1442 1.123.12.1 itohy
1443 1.123.12.1 itohy Static void
1444 1.123.12.1 itohy ehci_map_free(usbd_xfer_handle xfer)
1445 1.123.12.1 itohy {
1446 1.123.12.1 itohy struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus;
1447 1.123.12.1 itohy struct ehci_xfer *exfer = EXFER(xfer);
1448 1.123.12.1 itohy int s;
1449 1.123.12.1 itohy
1450 1.123.12.1 itohy USB_KASSERT(xfer->rqflags & URQ_DEV_MAP_PREPARED);
1451 1.123.12.1 itohy
1452 1.123.12.1 itohy usb_free_dma_resources(&sc->sc_dmatag, &exfer->dmabuf);
1453 1.123.12.1 itohy
1454 1.123.12.1 itohy /* XXX ITDs */
1455 1.123.12.1 itohy
1456 1.123.12.1 itohy s = splusb();
1457 1.123.12.1 itohy sc->sc_nfreeqtds += exfer->rsvd_tds;
1458 1.123.12.1 itohy splx(s);
1459 1.123.12.1 itohy exfer->rsvd_tds = 0;
1460 1.123.12.3 itohy ehci_aux_mem_free(sc, &exfer->aux);
1461 1.123.12.1 itohy }
1462 1.123.12.1 itohy
1463 1.123.12.1 itohy Static void
1464 1.123.12.1 itohy ehci_mapm(usbd_xfer_handle xfer, void *buf, size_t size)
1465 1.123.12.1 itohy {
1466 1.123.12.1 itohy struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus;
1467 1.123.12.1 itohy struct ehci_xfer *exfer = EXFER(xfer);
1468 1.123.12.1 itohy
1469 1.123.12.1 itohy usb_map_dma(&sc->sc_dmatag, &exfer->dmabuf, buf, size);
1470 1.123.12.1 itohy }
1471 1.123.12.1 itohy
1472 1.123.12.2 itohy Static usbd_status
1473 1.123.12.1 itohy ehci_mapm_mbuf(usbd_xfer_handle xfer, struct mbuf *chain)
1474 1.123.12.1 itohy {
1475 1.123.12.1 itohy struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus;
1476 1.123.12.1 itohy struct ehci_xfer *exfer = EXFER(xfer);
1477 1.123.12.1 itohy
1478 1.123.12.2 itohy return (usb_map_mbuf_dma(&sc->sc_dmatag, &exfer->dmabuf, chain));
1479 1.123.12.1 itohy }
1480 1.123.12.1 itohy
1481 1.123.12.1 itohy Static void
1482 1.123.12.1 itohy ehci_unmapm(usbd_xfer_handle xfer)
1483 1.123.12.1 itohy {
1484 1.123.12.1 itohy struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus;
1485 1.123.12.1 itohy struct ehci_xfer *exfer = EXFER(xfer);
1486 1.123.12.1 itohy
1487 1.123.12.1 itohy usb_unmap_dma(&sc->sc_dmatag, &exfer->dmabuf);
1488 1.5 augustss }
1489 1.5 augustss
1490 1.5 augustss usbd_xfer_handle
1491 1.123.12.1 itohy ehci_allocx(struct usbd_bus *bus, usbd_pipe_handle pipe,
1492 1.123.12.1 itohy enum usbd_waitflg waitflg)
1493 1.5 augustss {
1494 1.5 augustss struct ehci_softc *sc = (struct ehci_softc *)bus;
1495 1.5 augustss usbd_xfer_handle xfer;
1496 1.5 augustss
1497 1.5 augustss xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers);
1498 1.28 augustss if (xfer != NULL) {
1499 1.32 lukem SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
1500 1.28 augustss #ifdef DIAGNOSTIC
1501 1.28 augustss if (xfer->busy_free != XFER_FREE) {
1502 1.72 augustss printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer,
1503 1.28 augustss xfer->busy_free);
1504 1.28 augustss }
1505 1.28 augustss #endif
1506 1.28 augustss } else {
1507 1.123.12.1 itohy xfer = malloc(sizeof(struct ehci_xfer), M_USB,
1508 1.123.12.1 itohy waitflg == U_WAITOK ? M_WAITOK : M_NOWAIT);
1509 1.28 augustss }
1510 1.18 augustss if (xfer != NULL) {
1511 1.71 augustss memset(xfer, 0, sizeof(struct ehci_xfer));
1512 1.123.12.1 itohy usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task,
1513 1.123.12.1 itohy xfer);
1514 1.123.12.1 itohy EXFER(xfer)->ehci_xfer_flags = 0;
1515 1.123.12.1 itohy EXFER(xfer)->rsvd_tds = 0;
1516 1.18 augustss #ifdef DIAGNOSTIC
1517 1.18 augustss EXFER(xfer)->isdone = 1;
1518 1.18 augustss xfer->busy_free = XFER_BUSY;
1519 1.18 augustss #endif
1520 1.18 augustss }
1521 1.5 augustss return (xfer);
1522 1.5 augustss }
1523 1.5 augustss
1524 1.5 augustss void
1525 1.5 augustss ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
1526 1.5 augustss {
1527 1.5 augustss struct ehci_softc *sc = (struct ehci_softc *)bus;
1528 1.5 augustss
1529 1.18 augustss #ifdef DIAGNOSTIC
1530 1.18 augustss if (xfer->busy_free != XFER_BUSY) {
1531 1.18 augustss printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer,
1532 1.18 augustss xfer->busy_free);
1533 1.18 augustss }
1534 1.18 augustss xfer->busy_free = XFER_FREE;
1535 1.18 augustss if (!EXFER(xfer)->isdone) {
1536 1.18 augustss printf("ehci_freex: !isdone\n");
1537 1.18 augustss }
1538 1.18 augustss #endif
1539 1.5 augustss SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next);
1540 1.5 augustss }
1541 1.5 augustss
1542 1.5 augustss Static void
1543 1.5 augustss ehci_device_clear_toggle(usbd_pipe_handle pipe)
1544 1.5 augustss {
1545 1.15 augustss struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1546 1.123.12.1 itohy ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
1547 1.123.12.1 itohy
1548 1.123.12.1 itohy EHCI_SQH_SYNC(sc, epipe->sqh,
1549 1.123.12.1 itohy BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1550 1.15 augustss
1551 1.23 augustss DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n",
1552 1.23 augustss epipe, epipe->sqh->qh.qh_qtd.qtd_status));
1553 1.22 augustss #ifdef USB_DEBUG
1554 1.22 augustss if (ehcidebug)
1555 1.22 augustss usbd_dump_pipe(pipe);
1556 1.5 augustss #endif
1557 1.123.12.1 itohy USB_KASSERT2((epipe->sqh->qh.qh_qtd.qtd_status &
1558 1.123.12.1 itohy htole32(EHCI_QTD_ACTIVE)) == 0,
1559 1.123.12.1 itohy ("ehci_device_clear_toggle: queue active"));
1560 1.123.12.1 itohy epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK);
1561 1.123.12.1 itohy EHCI_SQH_SYNC(sc, epipe->sqh,
1562 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1563 1.5 augustss }
1564 1.5 augustss
1565 1.5 augustss Static void
1566 1.115 christos ehci_noop(usbd_pipe_handle pipe)
1567 1.5 augustss {
1568 1.5 augustss }
1569 1.5 augustss
1570 1.5 augustss #ifdef EHCI_DEBUG
1571 1.5 augustss void
1572 1.18 augustss ehci_dump_regs(ehci_softc_t *sc)
1573 1.5 augustss {
1574 1.6 augustss int i;
1575 1.6 augustss printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n",
1576 1.6 augustss EOREAD4(sc, EHCI_USBCMD),
1577 1.6 augustss EOREAD4(sc, EHCI_USBSTS),
1578 1.6 augustss EOREAD4(sc, EHCI_USBINTR));
1579 1.29 augustss printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
1580 1.15 augustss EOREAD4(sc, EHCI_FRINDEX),
1581 1.15 augustss EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1582 1.15 augustss EOREAD4(sc, EHCI_PERIODICLISTBASE),
1583 1.15 augustss EOREAD4(sc, EHCI_ASYNCLISTADDR));
1584 1.6 augustss for (i = 1; i <= sc->sc_noport; i++)
1585 1.33 augustss printf("port %d status=0x%08x\n", i,
1586 1.6 augustss EOREAD4(sc, EHCI_PORTSC(i)));
1587 1.39 martin }
1588 1.39 martin
1589 1.40 martin /*
1590 1.40 martin * Unused function - this is meant to be called from a kernel
1591 1.40 martin * debugger.
1592 1.40 martin */
1593 1.39 martin void
1594 1.39 martin ehci_dump()
1595 1.39 martin {
1596 1.39 martin ehci_dump_regs(theehci);
1597 1.6 augustss }
1598 1.6 augustss
1599 1.6 augustss void
1600 1.15 augustss ehci_dump_link(ehci_link_t link, int type)
1601 1.9 augustss {
1602 1.15 augustss link = le32toh(link);
1603 1.15 augustss printf("0x%08x", link);
1604 1.9 augustss if (link & EHCI_LINK_TERMINATE)
1605 1.15 augustss printf("<T>");
1606 1.15 augustss else {
1607 1.15 augustss printf("<");
1608 1.15 augustss if (type) {
1609 1.15 augustss switch (EHCI_LINK_TYPE(link)) {
1610 1.15 augustss case EHCI_LINK_ITD: printf("ITD"); break;
1611 1.15 augustss case EHCI_LINK_QH: printf("QH"); break;
1612 1.15 augustss case EHCI_LINK_SITD: printf("SITD"); break;
1613 1.15 augustss case EHCI_LINK_FSTN: printf("FSTN"); break;
1614 1.16 augustss }
1615 1.15 augustss }
1616 1.9 augustss printf(">");
1617 1.15 augustss }
1618 1.15 augustss }
1619 1.15 augustss
1620 1.15 augustss void
1621 1.15 augustss ehci_dump_sqtds(ehci_soft_qtd_t *sqtd)
1622 1.15 augustss {
1623 1.29 augustss int i;
1624 1.29 augustss u_int32_t stop;
1625 1.29 augustss
1626 1.29 augustss stop = 0;
1627 1.29 augustss for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) {
1628 1.15 augustss ehci_dump_sqtd(sqtd);
1629 1.72 augustss stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE);
1630 1.29 augustss }
1631 1.29 augustss if (sqtd)
1632 1.29 augustss printf("dump aborted, too many TDs\n");
1633 1.9 augustss }
1634 1.9 augustss
1635 1.9 augustss void
1636 1.9 augustss ehci_dump_sqtd(ehci_soft_qtd_t *sqtd)
1637 1.9 augustss {
1638 1.123.12.1 itohy printf("QTD(%p) at 0x%08x:\n", sqtd, EHCI_SQTD_DMAADDR(sqtd));
1639 1.9 augustss ehci_dump_qtd(&sqtd->qtd);
1640 1.9 augustss }
1641 1.9 augustss
1642 1.9 augustss void
1643 1.9 augustss ehci_dump_qtd(ehci_qtd_t *qtd)
1644 1.9 augustss {
1645 1.9 augustss u_int32_t s;
1646 1.15 augustss char sbuf[128];
1647 1.9 augustss
1648 1.15 augustss printf(" next="); ehci_dump_link(qtd->qtd_next, 0);
1649 1.15 augustss printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0);
1650 1.9 augustss printf("\n");
1651 1.15 augustss s = le32toh(qtd->qtd_status);
1652 1.15 augustss bitmask_snprintf(EHCI_QTD_GET_STATUS(s),
1653 1.15 augustss "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR"
1654 1.15 augustss "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf));
1655 1.9 augustss printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
1656 1.9 augustss s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
1657 1.9 augustss EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
1658 1.15 augustss printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s),
1659 1.15 augustss EHCI_QTD_GET_PID(s), sbuf);
1660 1.9 augustss for (s = 0; s < 5; s++)
1661 1.15 augustss printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s]));
1662 1.9 augustss }
1663 1.9 augustss
1664 1.9 augustss void
1665 1.9 augustss ehci_dump_sqh(ehci_soft_qh_t *sqh)
1666 1.9 augustss {
1667 1.9 augustss ehci_qh_t *qh = &sqh->qh;
1668 1.15 augustss u_int32_t endp, endphub;
1669 1.9 augustss
1670 1.123.12.1 itohy printf("QH(%p) at 0x%08x:\n", sqh, EHCI_SQH_DMAADDR(sqh));
1671 1.123.12.1 itohy printf(" sqtd=%p inactivesqtd=%p\n", sqh->sqtd, sqh->inactivesqtd);
1672 1.15 augustss printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n");
1673 1.15 augustss endp = le32toh(qh->qh_endp);
1674 1.15 augustss printf(" endp=0x%08x\n", endp);
1675 1.15 augustss printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
1676 1.15 augustss EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
1677 1.15 augustss EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
1678 1.15 augustss EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
1679 1.15 augustss printf(" mpl=0x%x ctl=%d nrl=%d\n",
1680 1.15 augustss EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
1681 1.15 augustss EHCI_QH_GET_NRL(endp));
1682 1.15 augustss endphub = le32toh(qh->qh_endphub);
1683 1.15 augustss printf(" endphub=0x%08x\n", endphub);
1684 1.15 augustss printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
1685 1.15 augustss EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
1686 1.15 augustss EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
1687 1.15 augustss EHCI_QH_GET_MULT(endphub));
1688 1.15 augustss printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n");
1689 1.12 augustss printf("Overlay qTD:\n");
1690 1.9 augustss ehci_dump_qtd(&qh->qh_qtd);
1691 1.9 augustss }
1692 1.9 augustss
1693 1.38 martin #ifdef DIAGNOSTIC
1694 1.18 augustss Static void
1695 1.18 augustss ehci_dump_exfer(struct ehci_xfer *ex)
1696 1.18 augustss {
1697 1.18 augustss printf("ehci_dump_exfer: ex=%p\n", ex);
1698 1.18 augustss }
1699 1.38 martin #endif
1700 1.5 augustss #endif
1701 1.5 augustss
1702 1.5 augustss usbd_status
1703 1.5 augustss ehci_open(usbd_pipe_handle pipe)
1704 1.5 augustss {
1705 1.5 augustss usbd_device_handle dev = pipe->device;
1706 1.5 augustss ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
1707 1.5 augustss usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1708 1.5 augustss u_int8_t addr = dev->address;
1709 1.5 augustss u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
1710 1.5 augustss struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1711 1.10 augustss ehci_soft_qh_t *sqh;
1712 1.10 augustss usbd_status err;
1713 1.10 augustss int s;
1714 1.78 augustss int ival, speed, naks;
1715 1.80 augustss int hshubaddr, hshubport;
1716 1.5 augustss
1717 1.5 augustss DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1718 1.5 augustss pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1719 1.5 augustss
1720 1.80 augustss if (dev->myhsport) {
1721 1.80 augustss hshubaddr = dev->myhsport->parent->address;
1722 1.80 augustss hshubport = dev->myhsport->portno;
1723 1.80 augustss } else {
1724 1.80 augustss hshubaddr = 0;
1725 1.80 augustss hshubport = 0;
1726 1.80 augustss }
1727 1.80 augustss
1728 1.17 augustss if (sc->sc_dying)
1729 1.17 augustss return (USBD_IOERROR);
1730 1.17 augustss
1731 1.5 augustss if (addr == sc->sc_addr) {
1732 1.5 augustss switch (ed->bEndpointAddress) {
1733 1.5 augustss case USB_CONTROL_ENDPOINT:
1734 1.5 augustss pipe->methods = &ehci_root_ctrl_methods;
1735 1.5 augustss break;
1736 1.5 augustss case UE_DIR_IN | EHCI_INTR_ENDPT:
1737 1.5 augustss pipe->methods = &ehci_root_intr_methods;
1738 1.5 augustss break;
1739 1.5 augustss default:
1740 1.5 augustss return (USBD_INVAL);
1741 1.5 augustss }
1742 1.10 augustss return (USBD_NORMAL_COMPLETION);
1743 1.10 augustss }
1744 1.10 augustss
1745 1.24 augustss /* XXX All this stuff is only valid for async. */
1746 1.11 augustss switch (dev->speed) {
1747 1.11 augustss case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break;
1748 1.11 augustss case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break;
1749 1.11 augustss case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break;
1750 1.37 provos default: panic("ehci_open: bad device speed %d", dev->speed);
1751 1.11 augustss }
1752 1.99 augustss if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) {
1753 1.99 augustss printf("%s: *** WARNING: opening low/full speed isoc device, "
1754 1.99 augustss "this does not work yet.\n",
1755 1.80 augustss USBDEVNAME(sc->sc_bus.bdev));
1756 1.80 augustss DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n",
1757 1.80 augustss hshubaddr, hshubport));
1758 1.99 augustss return USBD_INVAL;
1759 1.80 augustss }
1760 1.80 augustss
1761 1.10 augustss naks = 8; /* XXX */
1762 1.10 augustss sqh = ehci_alloc_sqh(sc);
1763 1.10 augustss if (sqh == NULL)
1764 1.116 drochner return (USBD_NOMEM);
1765 1.10 augustss /* qh_link filled when the QH is added */
1766 1.10 augustss sqh->qh.qh_endp = htole32(
1767 1.10 augustss EHCI_QH_SET_ADDR(addr) |
1768 1.56 mycroft EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) |
1769 1.55 mycroft EHCI_QH_SET_EPS(speed) |
1770 1.123.12.1 itohy (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) |
1771 1.123.12.1 itohy EHCI_QH_SET_MPL(UE_MAXPKTSZ(ed)) |
1772 1.10 augustss (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ?
1773 1.10 augustss EHCI_QH_CTL : 0) |
1774 1.10 augustss EHCI_QH_SET_NRL(naks)
1775 1.10 augustss );
1776 1.10 augustss sqh->qh.qh_endphub = htole32(
1777 1.78 augustss EHCI_QH_SET_MULT(1) |
1778 1.80 augustss EHCI_QH_SET_HUBA(hshubaddr) |
1779 1.80 augustss EHCI_QH_SET_PORT(hshubport) |
1780 1.123.12.1 itohy EHCI_QH_SET_CMASK(0x1c) |
1781 1.123.12.1 itohy EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0)
1782 1.10 augustss );
1783 1.11 augustss sqh->qh.qh_curqtd = EHCI_NULL;
1784 1.123.12.1 itohy /* The overlay qTD was already set up by ehci_alloc_sqh(). */
1785 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_status =
1786 1.123.12.1 itohy htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle));
1787 1.10 augustss
1788 1.10 augustss epipe->sqh = sqh;
1789 1.5 augustss
1790 1.10 augustss switch (xfertype) {
1791 1.10 augustss case UE_CONTROL:
1792 1.123.12.1 itohy err = usb_allocmem(&sc->sc_dmatag, sizeof(usb_device_request_t),
1793 1.10 augustss 0, &epipe->u.ctl.reqdma);
1794 1.25 augustss #ifdef EHCI_DEBUG
1795 1.25 augustss if (err)
1796 1.25 augustss printf("ehci_open: usb_allocmem()=%d\n", err);
1797 1.25 augustss #endif
1798 1.10 augustss if (err)
1799 1.116 drochner goto bad;
1800 1.11 augustss pipe->methods = &ehci_device_ctrl_methods;
1801 1.10 augustss s = splusb();
1802 1.123.12.1 itohy ehci_add_qh(sc, sqh, sc->sc_async_head);
1803 1.10 augustss splx(s);
1804 1.10 augustss break;
1805 1.10 augustss case UE_BULK:
1806 1.10 augustss pipe->methods = &ehci_device_bulk_methods;
1807 1.10 augustss s = splusb();
1808 1.123.12.1 itohy ehci_add_qh(sc, sqh, sc->sc_async_head);
1809 1.10 augustss splx(s);
1810 1.10 augustss break;
1811 1.24 augustss case UE_INTERRUPT:
1812 1.24 augustss pipe->methods = &ehci_device_intr_methods;
1813 1.78 augustss ival = pipe->interval;
1814 1.116 drochner if (ival == USBD_DEFAULT_INTERVAL) {
1815 1.116 drochner if (speed == EHCI_QH_SPEED_HIGH) {
1816 1.116 drochner if (ed->bInterval > 16) {
1817 1.116 drochner /*
1818 1.116 drochner * illegal with high-speed, but there
1819 1.116 drochner * were documentation bugs in the spec,
1820 1.116 drochner * so be generous
1821 1.116 drochner */
1822 1.116 drochner ival = 256;
1823 1.116 drochner } else
1824 1.116 drochner ival = (1 << (ed->bInterval - 1)) / 8;
1825 1.116 drochner } else
1826 1.116 drochner ival = ed->bInterval;
1827 1.116 drochner }
1828 1.116 drochner err = ehci_device_setintr(sc, sqh, ival);
1829 1.116 drochner if (err)
1830 1.116 drochner goto bad;
1831 1.116 drochner break;
1832 1.24 augustss case UE_ISOCHRONOUS:
1833 1.24 augustss pipe->methods = &ehci_device_isoc_methods;
1834 1.116 drochner /* FALLTHROUGH */
1835 1.10 augustss default:
1836 1.116 drochner err = USBD_INVAL;
1837 1.116 drochner goto bad;
1838 1.5 augustss }
1839 1.5 augustss return (USBD_NORMAL_COMPLETION);
1840 1.5 augustss
1841 1.116 drochner bad:
1842 1.11 augustss ehci_free_sqh(sc, sqh);
1843 1.116 drochner return (err);
1844 1.10 augustss }
1845 1.10 augustss
1846 1.10 augustss /*
1847 1.10 augustss * Add an ED to the schedule. Called at splusb().
1848 1.123.12.1 itohy * If in the async schedule, it will always have a next.
1849 1.123.12.1 itohy * If in the intr schedule it may not.
1850 1.10 augustss */
1851 1.10 augustss void
1852 1.123.12.1 itohy ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1853 1.10 augustss {
1854 1.10 augustss SPLUSBCHECK;
1855 1.10 augustss
1856 1.10 augustss sqh->next = head->next;
1857 1.123.12.1 itohy sqh->prev = head;
1858 1.10 augustss sqh->qh.qh_link = head->qh.qh_link;
1859 1.123.12.1 itohy EHCI_SQH_SYNC(sc, sqh,
1860 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1861 1.10 augustss head->next = sqh;
1862 1.123.12.1 itohy if (sqh->next)
1863 1.123.12.1 itohy sqh->next->prev = sqh;
1864 1.123.12.1 itohy head->qh.qh_link = htole32(EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH);
1865 1.123.12.1 itohy EHCI_SQH_SYNC(sc, head,
1866 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1867 1.10 augustss
1868 1.10 augustss #ifdef EHCI_DEBUG
1869 1.22 augustss if (ehcidebug > 5) {
1870 1.10 augustss printf("ehci_add_qh:\n");
1871 1.10 augustss ehci_dump_sqh(sqh);
1872 1.10 augustss }
1873 1.5 augustss #endif
1874 1.5 augustss }
1875 1.5 augustss
1876 1.10 augustss /*
1877 1.10 augustss * Remove an ED from the schedule. Called at splusb().
1878 1.123.12.1 itohy * Will always have a 'next' if it's in the async list as it's circular.
1879 1.10 augustss */
1880 1.10 augustss void
1881 1.10 augustss ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1882 1.10 augustss {
1883 1.10 augustss SPLUSBCHECK;
1884 1.10 augustss /* XXX */
1885 1.123.12.1 itohy sqh->prev->qh.qh_link = sqh->qh.qh_link;
1886 1.123.12.1 itohy EHCI_SQH_SYNC(sc, sqh->prev,
1887 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1888 1.123.12.1 itohy sqh->prev->next = sqh->next;
1889 1.123.12.1 itohy if (sqh->next)
1890 1.123.12.1 itohy sqh->next->prev = sqh->prev;
1891 1.11 augustss ehci_sync_hc(sc);
1892 1.11 augustss }
1893 1.11 augustss
1894 1.123.12.1 itohy /* Restart a QH following the addition of a qTD. */
1895 1.23 augustss void
1896 1.123.12.1 itohy ehci_activate_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd)
1897 1.23 augustss {
1898 1.123.12.1 itohy ehci_physaddr_t qtddma;
1899 1.85 augustss
1900 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, sqtd, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1901 1.123.12.1 itohy
1902 1.123.12.1 itohy USB_KASSERT2((sqtd->qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) == 0,
1903 1.123.12.1 itohy ("ehci_activate_qh: already active"));
1904 1.123.12.1 itohy
1905 1.123.12.1 itohy /*
1906 1.123.12.1 itohy * When a QH is idle, the overlay qTD should be marked as not
1907 1.123.12.1 itohy * halted and not active. This causes the host controller to
1908 1.123.12.1 itohy * retrieve the real qTD on each pass (rather than just examinig
1909 1.123.12.1 itohy * the overlay), so it will notice when we activate the qTD.
1910 1.123.12.1 itohy */
1911 1.123.12.1 itohy if (sqtd == sqh->sqtd) {
1912 1.123.12.1 itohy /* Check that the hardware is in the state we expect. */
1913 1.123.12.1 itohy qtddma = EHCI_SQTD_DMAADDR(sqtd);
1914 1.123.12.1 itohy if (EHCI_LINK_ADDR(le32toh(sqh->qh.qh_qtd.qtd_next)) !=
1915 1.123.12.1 itohy qtddma) {
1916 1.123.12.1 itohy #ifdef EHCI_DEBUG
1917 1.123.12.1 itohy printf("ehci_activate_qh: unexpected next ptr\n");
1918 1.123.12.1 itohy ehci_dump_sqh(sqh);
1919 1.123.12.1 itohy ehci_dump_sqtds(sqh->sqtd);
1920 1.123.12.1 itohy #endif
1921 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_next = htole32(qtddma);
1922 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1923 1.123.12.1 itohy }
1924 1.123.12.1 itohy /* Ensure the flags are correct. */
1925 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_status &= htole32(EHCI_QTD_PINGSTATE |
1926 1.123.12.1 itohy EHCI_QTD_TOGGLE_MASK);
1927 1.123.12.1 itohy EHCI_SQH_SYNC(sc, sqh,
1928 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1929 1.123.12.1 itohy }
1930 1.123.12.1 itohy
1931 1.123.12.1 itohy /* Now activate the qTD. */
1932 1.123.12.1 itohy sqtd->qtd.qtd_status |= htole32(EHCI_QTD_ACTIVE);
1933 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, sqtd, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1934 1.23 augustss }
1935 1.23 augustss
1936 1.11 augustss /*
1937 1.11 augustss * Ensure that the HC has released all references to the QH. We do this
1938 1.11 augustss * by asking for a Async Advance Doorbell interrupt and then we wait for
1939 1.11 augustss * the interrupt.
1940 1.11 augustss * To make this easier we first obtain exclusive use of the doorbell.
1941 1.11 augustss */
1942 1.11 augustss void
1943 1.11 augustss ehci_sync_hc(ehci_softc_t *sc)
1944 1.11 augustss {
1945 1.15 augustss int s, error;
1946 1.11 augustss
1947 1.12 augustss if (sc->sc_dying) {
1948 1.12 augustss DPRINTFN(2,("ehci_sync_hc: dying\n"));
1949 1.12 augustss return;
1950 1.12 augustss }
1951 1.12 augustss DPRINTFN(2,("ehci_sync_hc: enter\n"));
1952 1.123.12.1 itohy /* get doorbell */
1953 1.123.12.1 itohy usb_lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL);
1954 1.10 augustss s = splhardusb();
1955 1.10 augustss /* ask for doorbell */
1956 1.10 augustss EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD);
1957 1.15 augustss DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1958 1.15 augustss EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1959 1.15 augustss error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */
1960 1.15 augustss DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1961 1.15 augustss EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1962 1.10 augustss splx(s);
1963 1.123.12.1 itohy /* release doorbell */
1964 1.123.12.1 itohy usb_lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL);
1965 1.15 augustss #ifdef DIAGNOSTIC
1966 1.15 augustss if (error)
1967 1.15 augustss printf("ehci_sync_hc: tsleep() = %d\n", error);
1968 1.15 augustss #endif
1969 1.12 augustss DPRINTFN(2,("ehci_sync_hc: exit\n"));
1970 1.10 augustss }
1971 1.10 augustss
1972 1.5 augustss /***********/
1973 1.5 augustss
1974 1.5 augustss /*
1975 1.5 augustss * Data structures and routines to emulate the root hub.
1976 1.5 augustss */
1977 1.5 augustss Static usb_device_descriptor_t ehci_devd = {
1978 1.5 augustss USB_DEVICE_DESCRIPTOR_SIZE,
1979 1.5 augustss UDESC_DEVICE, /* type */
1980 1.5 augustss {0x00, 0x02}, /* USB version */
1981 1.5 augustss UDCLASS_HUB, /* class */
1982 1.5 augustss UDSUBCLASS_HUB, /* subclass */
1983 1.11 augustss UDPROTO_HSHUBSTT, /* protocol */
1984 1.5 augustss 64, /* max packet */
1985 1.5 augustss {0},{0},{0x00,0x01}, /* device id */
1986 1.5 augustss 1,2,0, /* string indicies */
1987 1.5 augustss 1 /* # of configurations */
1988 1.5 augustss };
1989 1.5 augustss
1990 1.123 drochner Static const usb_device_qualifier_t ehci_odevd = {
1991 1.11 augustss USB_DEVICE_DESCRIPTOR_SIZE,
1992 1.11 augustss UDESC_DEVICE_QUALIFIER, /* type */
1993 1.11 augustss {0x00, 0x02}, /* USB version */
1994 1.11 augustss UDCLASS_HUB, /* class */
1995 1.11 augustss UDSUBCLASS_HUB, /* subclass */
1996 1.11 augustss UDPROTO_FSHUB, /* protocol */
1997 1.11 augustss 64, /* max packet */
1998 1.11 augustss 1, /* # of configurations */
1999 1.11 augustss 0
2000 1.11 augustss };
2001 1.11 augustss
2002 1.123 drochner Static const usb_config_descriptor_t ehci_confd = {
2003 1.5 augustss USB_CONFIG_DESCRIPTOR_SIZE,
2004 1.5 augustss UDESC_CONFIG,
2005 1.5 augustss {USB_CONFIG_DESCRIPTOR_SIZE +
2006 1.5 augustss USB_INTERFACE_DESCRIPTOR_SIZE +
2007 1.5 augustss USB_ENDPOINT_DESCRIPTOR_SIZE},
2008 1.5 augustss 1,
2009 1.5 augustss 1,
2010 1.5 augustss 0,
2011 1.120 drochner UC_ATTR_MBO | UC_SELF_POWERED,
2012 1.5 augustss 0 /* max power */
2013 1.5 augustss };
2014 1.5 augustss
2015 1.123 drochner Static const usb_interface_descriptor_t ehci_ifcd = {
2016 1.5 augustss USB_INTERFACE_DESCRIPTOR_SIZE,
2017 1.5 augustss UDESC_INTERFACE,
2018 1.5 augustss 0,
2019 1.5 augustss 0,
2020 1.5 augustss 1,
2021 1.5 augustss UICLASS_HUB,
2022 1.5 augustss UISUBCLASS_HUB,
2023 1.11 augustss UIPROTO_HSHUBSTT,
2024 1.5 augustss 0
2025 1.5 augustss };
2026 1.5 augustss
2027 1.123 drochner Static const usb_endpoint_descriptor_t ehci_endpd = {
2028 1.5 augustss USB_ENDPOINT_DESCRIPTOR_SIZE,
2029 1.5 augustss UDESC_ENDPOINT,
2030 1.5 augustss UE_DIR_IN | EHCI_INTR_ENDPT,
2031 1.5 augustss UE_INTERRUPT,
2032 1.5 augustss {8, 0}, /* max packet */
2033 1.118 drochner 12
2034 1.5 augustss };
2035 1.5 augustss
2036 1.123 drochner Static const usb_hub_descriptor_t ehci_hubd = {
2037 1.5 augustss USB_HUB_DESCRIPTOR_SIZE,
2038 1.5 augustss UDESC_HUB,
2039 1.5 augustss 0,
2040 1.5 augustss {0,0},
2041 1.5 augustss 0,
2042 1.5 augustss 0,
2043 1.111 christos {""},
2044 1.111 christos {""},
2045 1.5 augustss };
2046 1.5 augustss
2047 1.5 augustss Static int
2048 1.104 christos ehci_str(usb_string_descriptor_t *p, int l, const char *s)
2049 1.5 augustss {
2050 1.5 augustss int i;
2051 1.5 augustss
2052 1.5 augustss if (l == 0)
2053 1.5 augustss return (0);
2054 1.5 augustss p->bLength = 2 * strlen(s) + 2;
2055 1.5 augustss if (l == 1)
2056 1.5 augustss return (1);
2057 1.5 augustss p->bDescriptorType = UDESC_STRING;
2058 1.5 augustss l -= 2;
2059 1.5 augustss for (i = 0; s[i] && l > 1; i++, l -= 2)
2060 1.5 augustss USETW2(p->bString[i], 0, s[i]);
2061 1.5 augustss return (2*i+2);
2062 1.5 augustss }
2063 1.5 augustss
2064 1.5 augustss /*
2065 1.5 augustss * Simulate a hardware hub by handling all the necessary requests.
2066 1.5 augustss */
2067 1.5 augustss Static usbd_status
2068 1.5 augustss ehci_root_ctrl_transfer(usbd_xfer_handle xfer)
2069 1.5 augustss {
2070 1.5 augustss usbd_status err;
2071 1.5 augustss
2072 1.5 augustss /* Insert last in queue. */
2073 1.5 augustss err = usb_insert_transfer(xfer);
2074 1.5 augustss if (err)
2075 1.5 augustss return (err);
2076 1.5 augustss
2077 1.5 augustss /* Pipe isn't running, start first */
2078 1.5 augustss return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2079 1.5 augustss }
2080 1.5 augustss
2081 1.5 augustss Static usbd_status
2082 1.5 augustss ehci_root_ctrl_start(usbd_xfer_handle xfer)
2083 1.5 augustss {
2084 1.5 augustss ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2085 1.5 augustss usb_device_request_t *req;
2086 1.5 augustss void *buf = NULL;
2087 1.5 augustss int port, i;
2088 1.5 augustss int s, len, value, index, l, totlen = 0;
2089 1.5 augustss usb_port_status_t ps;
2090 1.5 augustss usb_hub_descriptor_t hubd;
2091 1.5 augustss usbd_status err;
2092 1.5 augustss u_int32_t v;
2093 1.5 augustss
2094 1.5 augustss if (sc->sc_dying)
2095 1.5 augustss return (USBD_IOERROR);
2096 1.5 augustss
2097 1.5 augustss #ifdef DIAGNOSTIC
2098 1.5 augustss if (!(xfer->rqflags & URQ_REQUEST))
2099 1.5 augustss /* XXX panic */
2100 1.5 augustss return (USBD_INVAL);
2101 1.5 augustss #endif
2102 1.5 augustss req = &xfer->request;
2103 1.5 augustss
2104 1.72 augustss DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n",
2105 1.5 augustss req->bmRequestType, req->bRequest));
2106 1.5 augustss
2107 1.5 augustss len = UGETW(req->wLength);
2108 1.5 augustss value = UGETW(req->wValue);
2109 1.5 augustss index = UGETW(req->wIndex);
2110 1.5 augustss
2111 1.123.12.2 itohy if (len != 0) {
2112 1.123.12.2 itohy /* mbuf transfer is not supported */
2113 1.123.12.2 itohy if (xfer->rqflags & URQ_DEV_MAP_MBUF)
2114 1.123.12.2 itohy return (USBD_INVAL);
2115 1.123.12.1 itohy buf = xfer->hcbuffer;
2116 1.123.12.2 itohy }
2117 1.5 augustss
2118 1.5 augustss #define C(x,y) ((x) | ((y) << 8))
2119 1.5 augustss switch(C(req->bRequest, req->bmRequestType)) {
2120 1.5 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2121 1.5 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2122 1.5 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
2123 1.33 augustss /*
2124 1.5 augustss * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2125 1.5 augustss * for the integrated root hub.
2126 1.5 augustss */
2127 1.5 augustss break;
2128 1.5 augustss case C(UR_GET_CONFIG, UT_READ_DEVICE):
2129 1.5 augustss if (len > 0) {
2130 1.5 augustss *(u_int8_t *)buf = sc->sc_conf;
2131 1.5 augustss totlen = 1;
2132 1.5 augustss }
2133 1.5 augustss break;
2134 1.5 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2135 1.72 augustss DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value));
2136 1.109 christos if (len == 0)
2137 1.109 christos break;
2138 1.5 augustss switch(value >> 8) {
2139 1.5 augustss case UDESC_DEVICE:
2140 1.5 augustss if ((value & 0xff) != 0) {
2141 1.5 augustss err = USBD_IOERROR;
2142 1.5 augustss goto ret;
2143 1.5 augustss }
2144 1.5 augustss totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
2145 1.5 augustss USETW(ehci_devd.idVendor, sc->sc_id_vendor);
2146 1.5 augustss memcpy(buf, &ehci_devd, l);
2147 1.5 augustss break;
2148 1.33 augustss /*
2149 1.11 augustss * We can't really operate at another speed, but the spec says
2150 1.11 augustss * we need this descriptor.
2151 1.11 augustss */
2152 1.11 augustss case UDESC_DEVICE_QUALIFIER:
2153 1.11 augustss if ((value & 0xff) != 0) {
2154 1.11 augustss err = USBD_IOERROR;
2155 1.11 augustss goto ret;
2156 1.11 augustss }
2157 1.11 augustss totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
2158 1.11 augustss memcpy(buf, &ehci_odevd, l);
2159 1.11 augustss break;
2160 1.33 augustss /*
2161 1.11 augustss * We can't really operate at another speed, but the spec says
2162 1.11 augustss * we need this descriptor.
2163 1.11 augustss */
2164 1.11 augustss case UDESC_OTHER_SPEED_CONFIGURATION:
2165 1.5 augustss case UDESC_CONFIG:
2166 1.5 augustss if ((value & 0xff) != 0) {
2167 1.5 augustss err = USBD_IOERROR;
2168 1.5 augustss goto ret;
2169 1.5 augustss }
2170 1.5 augustss totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
2171 1.5 augustss memcpy(buf, &ehci_confd, l);
2172 1.11 augustss ((usb_config_descriptor_t *)buf)->bDescriptorType =
2173 1.11 augustss value >> 8;
2174 1.5 augustss buf = (char *)buf + l;
2175 1.5 augustss len -= l;
2176 1.5 augustss l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
2177 1.5 augustss totlen += l;
2178 1.5 augustss memcpy(buf, &ehci_ifcd, l);
2179 1.5 augustss buf = (char *)buf + l;
2180 1.5 augustss len -= l;
2181 1.5 augustss l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
2182 1.5 augustss totlen += l;
2183 1.5 augustss memcpy(buf, &ehci_endpd, l);
2184 1.5 augustss break;
2185 1.5 augustss case UDESC_STRING:
2186 1.5 augustss *(u_int8_t *)buf = 0;
2187 1.5 augustss totlen = 1;
2188 1.5 augustss switch (value & 0xff) {
2189 1.88 augustss case 0: /* Language table */
2190 1.123 drochner if (len > 0)
2191 1.123 drochner *(u_int8_t *)buf = 4;
2192 1.123 drochner if (len >= 4) {
2193 1.123 drochner USETW(((usb_string_descriptor_t *)buf)->bString[0], 0x0409);
2194 1.123 drochner totlen = 4;
2195 1.123 drochner }
2196 1.88 augustss break;
2197 1.5 augustss case 1: /* Vendor */
2198 1.5 augustss totlen = ehci_str(buf, len, sc->sc_vendor);
2199 1.5 augustss break;
2200 1.5 augustss case 2: /* Product */
2201 1.5 augustss totlen = ehci_str(buf, len, "EHCI root hub");
2202 1.5 augustss break;
2203 1.5 augustss }
2204 1.5 augustss break;
2205 1.5 augustss default:
2206 1.5 augustss err = USBD_IOERROR;
2207 1.5 augustss goto ret;
2208 1.5 augustss }
2209 1.5 augustss break;
2210 1.5 augustss case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
2211 1.5 augustss if (len > 0) {
2212 1.5 augustss *(u_int8_t *)buf = 0;
2213 1.5 augustss totlen = 1;
2214 1.5 augustss }
2215 1.5 augustss break;
2216 1.5 augustss case C(UR_GET_STATUS, UT_READ_DEVICE):
2217 1.5 augustss if (len > 1) {
2218 1.5 augustss USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
2219 1.5 augustss totlen = 2;
2220 1.5 augustss }
2221 1.5 augustss break;
2222 1.5 augustss case C(UR_GET_STATUS, UT_READ_INTERFACE):
2223 1.5 augustss case C(UR_GET_STATUS, UT_READ_ENDPOINT):
2224 1.5 augustss if (len > 1) {
2225 1.5 augustss USETW(((usb_status_t *)buf)->wStatus, 0);
2226 1.5 augustss totlen = 2;
2227 1.5 augustss }
2228 1.5 augustss break;
2229 1.5 augustss case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
2230 1.5 augustss if (value >= USB_MAX_DEVICES) {
2231 1.5 augustss err = USBD_IOERROR;
2232 1.5 augustss goto ret;
2233 1.5 augustss }
2234 1.5 augustss sc->sc_addr = value;
2235 1.5 augustss break;
2236 1.5 augustss case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
2237 1.5 augustss if (value != 0 && value != 1) {
2238 1.5 augustss err = USBD_IOERROR;
2239 1.5 augustss goto ret;
2240 1.5 augustss }
2241 1.5 augustss sc->sc_conf = value;
2242 1.5 augustss break;
2243 1.5 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
2244 1.5 augustss break;
2245 1.5 augustss case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
2246 1.5 augustss case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
2247 1.5 augustss case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
2248 1.5 augustss err = USBD_IOERROR;
2249 1.5 augustss goto ret;
2250 1.5 augustss case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
2251 1.5 augustss break;
2252 1.5 augustss case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
2253 1.5 augustss break;
2254 1.5 augustss /* Hub requests */
2255 1.5 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2256 1.5 augustss break;
2257 1.5 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2258 1.106 augustss DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE "
2259 1.5 augustss "port=%d feature=%d\n",
2260 1.5 augustss index, value));
2261 1.5 augustss if (index < 1 || index > sc->sc_noport) {
2262 1.5 augustss err = USBD_IOERROR;
2263 1.5 augustss goto ret;
2264 1.5 augustss }
2265 1.5 augustss port = EHCI_PORTSC(index);
2266 1.106 augustss v = EOREAD4(sc, port);
2267 1.106 augustss DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v));
2268 1.106 augustss v &= ~EHCI_PS_CLEAR;
2269 1.5 augustss switch(value) {
2270 1.5 augustss case UHF_PORT_ENABLE:
2271 1.5 augustss EOWRITE4(sc, port, v &~ EHCI_PS_PE);
2272 1.5 augustss break;
2273 1.5 augustss case UHF_PORT_SUSPEND:
2274 1.5 augustss EOWRITE4(sc, port, v &~ EHCI_PS_SUSP);
2275 1.5 augustss break;
2276 1.5 augustss case UHF_PORT_POWER:
2277 1.106 augustss if (sc->sc_hasppc)
2278 1.106 augustss EOWRITE4(sc, port, v &~ EHCI_PS_PP);
2279 1.5 augustss break;
2280 1.14 augustss case UHF_PORT_TEST:
2281 1.72 augustss DPRINTFN(2,("ehci_root_ctrl_start: clear port test "
2282 1.14 augustss "%d\n", index));
2283 1.14 augustss break;
2284 1.14 augustss case UHF_PORT_INDICATOR:
2285 1.72 augustss DPRINTFN(2,("ehci_root_ctrl_start: clear port ind "
2286 1.14 augustss "%d\n", index));
2287 1.14 augustss EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
2288 1.14 augustss break;
2289 1.5 augustss case UHF_C_PORT_CONNECTION:
2290 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_CSC);
2291 1.5 augustss break;
2292 1.5 augustss case UHF_C_PORT_ENABLE:
2293 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_PEC);
2294 1.5 augustss break;
2295 1.5 augustss case UHF_C_PORT_SUSPEND:
2296 1.5 augustss /* how? */
2297 1.5 augustss break;
2298 1.5 augustss case UHF_C_PORT_OVER_CURRENT:
2299 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_OCC);
2300 1.5 augustss break;
2301 1.5 augustss case UHF_C_PORT_RESET:
2302 1.106 augustss sc->sc_isreset[index] = 0;
2303 1.5 augustss break;
2304 1.5 augustss default:
2305 1.5 augustss err = USBD_IOERROR;
2306 1.5 augustss goto ret;
2307 1.5 augustss }
2308 1.5 augustss #if 0
2309 1.5 augustss switch(value) {
2310 1.5 augustss case UHF_C_PORT_CONNECTION:
2311 1.5 augustss case UHF_C_PORT_ENABLE:
2312 1.5 augustss case UHF_C_PORT_SUSPEND:
2313 1.5 augustss case UHF_C_PORT_OVER_CURRENT:
2314 1.5 augustss case UHF_C_PORT_RESET:
2315 1.5 augustss default:
2316 1.5 augustss break;
2317 1.5 augustss }
2318 1.5 augustss #endif
2319 1.5 augustss break;
2320 1.5 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2321 1.109 christos if (len == 0)
2322 1.109 christos break;
2323 1.51 toshii if ((value & 0xff) != 0) {
2324 1.5 augustss err = USBD_IOERROR;
2325 1.5 augustss goto ret;
2326 1.5 augustss }
2327 1.5 augustss hubd = ehci_hubd;
2328 1.5 augustss hubd.bNbrPorts = sc->sc_noport;
2329 1.5 augustss v = EOREAD4(sc, EHCI_HCSPARAMS);
2330 1.5 augustss USETW(hubd.wHubCharacteristics,
2331 1.14 augustss EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH |
2332 1.78 augustss EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS))
2333 1.14 augustss ? UHD_PORT_IND : 0);
2334 1.5 augustss hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */
2335 1.33 augustss for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2336 1.5 augustss hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
2337 1.5 augustss hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2338 1.5 augustss l = min(len, hubd.bDescLength);
2339 1.5 augustss totlen = l;
2340 1.5 augustss memcpy(buf, &hubd, l);
2341 1.5 augustss break;
2342 1.5 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2343 1.5 augustss if (len != 4) {
2344 1.5 augustss err = USBD_IOERROR;
2345 1.5 augustss goto ret;
2346 1.5 augustss }
2347 1.5 augustss memset(buf, 0, len); /* ? XXX */
2348 1.5 augustss totlen = len;
2349 1.5 augustss break;
2350 1.5 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2351 1.72 augustss DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n",
2352 1.5 augustss index));
2353 1.5 augustss if (index < 1 || index > sc->sc_noport) {
2354 1.5 augustss err = USBD_IOERROR;
2355 1.5 augustss goto ret;
2356 1.5 augustss }
2357 1.5 augustss if (len != 4) {
2358 1.5 augustss err = USBD_IOERROR;
2359 1.5 augustss goto ret;
2360 1.5 augustss }
2361 1.5 augustss v = EOREAD4(sc, EHCI_PORTSC(index));
2362 1.72 augustss DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n",
2363 1.5 augustss v));
2364 1.11 augustss i = UPS_HIGH_SPEED;
2365 1.5 augustss if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
2366 1.5 augustss if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
2367 1.5 augustss if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
2368 1.5 augustss if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
2369 1.5 augustss if (v & EHCI_PS_PR) i |= UPS_RESET;
2370 1.5 augustss if (v & EHCI_PS_PP) i |= UPS_PORT_POWER;
2371 1.5 augustss USETW(ps.wPortStatus, i);
2372 1.5 augustss i = 0;
2373 1.5 augustss if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
2374 1.5 augustss if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
2375 1.5 augustss if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
2376 1.106 augustss if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET;
2377 1.5 augustss USETW(ps.wPortChange, i);
2378 1.5 augustss l = min(len, sizeof ps);
2379 1.5 augustss memcpy(buf, &ps, l);
2380 1.5 augustss totlen = l;
2381 1.5 augustss break;
2382 1.5 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2383 1.5 augustss err = USBD_IOERROR;
2384 1.5 augustss goto ret;
2385 1.5 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2386 1.5 augustss break;
2387 1.5 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2388 1.5 augustss if (index < 1 || index > sc->sc_noport) {
2389 1.5 augustss err = USBD_IOERROR;
2390 1.5 augustss goto ret;
2391 1.5 augustss }
2392 1.5 augustss port = EHCI_PORTSC(index);
2393 1.106 augustss v = EOREAD4(sc, port);
2394 1.106 augustss DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v));
2395 1.106 augustss v &= ~EHCI_PS_CLEAR;
2396 1.5 augustss switch(value) {
2397 1.5 augustss case UHF_PORT_ENABLE:
2398 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_PE);
2399 1.5 augustss break;
2400 1.5 augustss case UHF_PORT_SUSPEND:
2401 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_SUSP);
2402 1.5 augustss break;
2403 1.5 augustss case UHF_PORT_RESET:
2404 1.72 augustss DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n",
2405 1.5 augustss index));
2406 1.6 augustss if (EHCI_PS_IS_LOWSPEED(v)) {
2407 1.6 augustss /* Low speed device, give up ownership. */
2408 1.6 augustss ehci_disown(sc, index, 1);
2409 1.6 augustss break;
2410 1.6 augustss }
2411 1.8 augustss /* Start reset sequence. */
2412 1.8 augustss v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
2413 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_PR);
2414 1.8 augustss /* Wait for reset to complete. */
2415 1.13 augustss usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
2416 1.17 augustss if (sc->sc_dying) {
2417 1.17 augustss err = USBD_IOERROR;
2418 1.17 augustss goto ret;
2419 1.17 augustss }
2420 1.8 augustss /* Terminate reset sequence. */
2421 1.8 augustss EOWRITE4(sc, port, v);
2422 1.8 augustss /* Wait for HC to complete reset. */
2423 1.13 augustss usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE);
2424 1.17 augustss if (sc->sc_dying) {
2425 1.17 augustss err = USBD_IOERROR;
2426 1.17 augustss goto ret;
2427 1.17 augustss }
2428 1.8 augustss v = EOREAD4(sc, port);
2429 1.8 augustss DPRINTF(("ehci after reset, status=0x%08x\n", v));
2430 1.8 augustss if (v & EHCI_PS_PR) {
2431 1.8 augustss printf("%s: port reset timeout\n",
2432 1.8 augustss USBDEVNAME(sc->sc_bus.bdev));
2433 1.8 augustss return (USBD_TIMEOUT);
2434 1.5 augustss }
2435 1.8 augustss if (!(v & EHCI_PS_PE)) {
2436 1.6 augustss /* Not a high speed device, give up ownership.*/
2437 1.6 augustss ehci_disown(sc, index, 0);
2438 1.6 augustss break;
2439 1.6 augustss }
2440 1.106 augustss sc->sc_isreset[index] = 1;
2441 1.8 augustss DPRINTF(("ehci port %d reset, status = 0x%08x\n",
2442 1.6 augustss index, v));
2443 1.5 augustss break;
2444 1.5 augustss case UHF_PORT_POWER:
2445 1.72 augustss DPRINTFN(2,("ehci_root_ctrl_start: set port power "
2446 1.106 augustss "%d (has PPC = %d)\n", index,
2447 1.106 augustss sc->sc_hasppc));
2448 1.106 augustss if (sc->sc_hasppc)
2449 1.106 augustss EOWRITE4(sc, port, v | EHCI_PS_PP);
2450 1.5 augustss break;
2451 1.11 augustss case UHF_PORT_TEST:
2452 1.72 augustss DPRINTFN(2,("ehci_root_ctrl_start: set port test "
2453 1.11 augustss "%d\n", index));
2454 1.11 augustss break;
2455 1.11 augustss case UHF_PORT_INDICATOR:
2456 1.72 augustss DPRINTFN(2,("ehci_root_ctrl_start: set port ind "
2457 1.11 augustss "%d\n", index));
2458 1.14 augustss EOWRITE4(sc, port, v | EHCI_PS_PIC);
2459 1.11 augustss break;
2460 1.5 augustss default:
2461 1.5 augustss err = USBD_IOERROR;
2462 1.5 augustss goto ret;
2463 1.5 augustss }
2464 1.5 augustss break;
2465 1.11 augustss case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
2466 1.11 augustss case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
2467 1.11 augustss case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
2468 1.11 augustss case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
2469 1.11 augustss break;
2470 1.5 augustss default:
2471 1.5 augustss err = USBD_IOERROR;
2472 1.5 augustss goto ret;
2473 1.5 augustss }
2474 1.5 augustss xfer->actlen = totlen;
2475 1.5 augustss err = USBD_NORMAL_COMPLETION;
2476 1.5 augustss ret:
2477 1.5 augustss xfer->status = err;
2478 1.5 augustss s = splusb();
2479 1.5 augustss usb_transfer_complete(xfer);
2480 1.5 augustss splx(s);
2481 1.5 augustss return (USBD_IN_PROGRESS);
2482 1.6 augustss }
2483 1.6 augustss
2484 1.6 augustss void
2485 1.115 christos ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
2486 1.6 augustss {
2487 1.24 augustss int port;
2488 1.6 augustss u_int32_t v;
2489 1.6 augustss
2490 1.6 augustss DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed));
2491 1.6 augustss #ifdef DIAGNOSTIC
2492 1.6 augustss if (sc->sc_npcomp != 0) {
2493 1.24 augustss int i = (index-1) / sc->sc_npcomp;
2494 1.6 augustss if (i >= sc->sc_ncomp)
2495 1.6 augustss printf("%s: strange port\n",
2496 1.6 augustss USBDEVNAME(sc->sc_bus.bdev));
2497 1.6 augustss else
2498 1.6 augustss printf("%s: handing over %s speed device on "
2499 1.6 augustss "port %d to %s\n",
2500 1.6 augustss USBDEVNAME(sc->sc_bus.bdev),
2501 1.6 augustss lowspeed ? "low" : "full",
2502 1.6 augustss index, USBDEVNAME(sc->sc_comps[i]->bdev));
2503 1.6 augustss } else {
2504 1.6 augustss printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev));
2505 1.6 augustss }
2506 1.6 augustss #endif
2507 1.6 augustss port = EHCI_PORTSC(index);
2508 1.6 augustss v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
2509 1.6 augustss EOWRITE4(sc, port, v | EHCI_PS_PO);
2510 1.5 augustss }
2511 1.5 augustss
2512 1.5 augustss /* Abort a root control request. */
2513 1.5 augustss Static void
2514 1.115 christos ehci_root_ctrl_abort(usbd_xfer_handle xfer)
2515 1.5 augustss {
2516 1.5 augustss /* Nothing to do, all transfers are synchronous. */
2517 1.5 augustss }
2518 1.5 augustss
2519 1.5 augustss /* Close the root pipe. */
2520 1.5 augustss Static void
2521 1.115 christos ehci_root_ctrl_close(usbd_pipe_handle pipe)
2522 1.5 augustss {
2523 1.5 augustss DPRINTF(("ehci_root_ctrl_close\n"));
2524 1.5 augustss /* Nothing to do. */
2525 1.5 augustss }
2526 1.5 augustss
2527 1.5 augustss void
2528 1.5 augustss ehci_root_intr_done(usbd_xfer_handle xfer)
2529 1.5 augustss {
2530 1.5 augustss }
2531 1.5 augustss
2532 1.5 augustss Static usbd_status
2533 1.5 augustss ehci_root_intr_transfer(usbd_xfer_handle xfer)
2534 1.5 augustss {
2535 1.123.12.1 itohy ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2536 1.5 augustss usbd_status err;
2537 1.5 augustss
2538 1.5 augustss /* Insert last in queue. */
2539 1.123.12.1 itohy err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag,
2540 1.123.12.1 itohy &EXFER(xfer)->dmabuf);
2541 1.5 augustss if (err)
2542 1.5 augustss return (err);
2543 1.5 augustss
2544 1.5 augustss /* Pipe isn't running, start first */
2545 1.5 augustss return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2546 1.5 augustss }
2547 1.5 augustss
2548 1.5 augustss Static usbd_status
2549 1.5 augustss ehci_root_intr_start(usbd_xfer_handle xfer)
2550 1.5 augustss {
2551 1.5 augustss usbd_pipe_handle pipe = xfer->pipe;
2552 1.5 augustss ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2553 1.5 augustss
2554 1.5 augustss if (sc->sc_dying)
2555 1.5 augustss return (USBD_IOERROR);
2556 1.5 augustss
2557 1.123.12.2 itohy if (xfer->rqflags & URQ_DEV_MAP_MBUF)
2558 1.123.12.2 itohy return (USBD_INVAL); /* mbuf transfer is not supported */
2559 1.123.12.2 itohy
2560 1.5 augustss sc->sc_intrxfer = xfer;
2561 1.5 augustss
2562 1.5 augustss return (USBD_IN_PROGRESS);
2563 1.5 augustss }
2564 1.5 augustss
2565 1.5 augustss /* Abort a root interrupt request. */
2566 1.5 augustss Static void
2567 1.5 augustss ehci_root_intr_abort(usbd_xfer_handle xfer)
2568 1.5 augustss {
2569 1.123.12.1 itohy ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2570 1.5 augustss int s;
2571 1.5 augustss
2572 1.5 augustss if (xfer->pipe->intrxfer == xfer) {
2573 1.5 augustss DPRINTF(("ehci_root_intr_abort: remove\n"));
2574 1.5 augustss xfer->pipe->intrxfer = NULL;
2575 1.5 augustss }
2576 1.5 augustss xfer->status = USBD_CANCELLED;
2577 1.5 augustss s = splusb();
2578 1.123.12.1 itohy usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf);
2579 1.5 augustss splx(s);
2580 1.5 augustss }
2581 1.5 augustss
2582 1.5 augustss /* Close the root pipe. */
2583 1.5 augustss Static void
2584 1.5 augustss ehci_root_intr_close(usbd_pipe_handle pipe)
2585 1.5 augustss {
2586 1.5 augustss ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2587 1.33 augustss
2588 1.5 augustss DPRINTF(("ehci_root_intr_close\n"));
2589 1.5 augustss
2590 1.5 augustss sc->sc_intrxfer = NULL;
2591 1.5 augustss }
2592 1.5 augustss
2593 1.5 augustss void
2594 1.5 augustss ehci_root_ctrl_done(usbd_xfer_handle xfer)
2595 1.5 augustss {
2596 1.9 augustss }
2597 1.9 augustss
2598 1.9 augustss /************************/
2599 1.9 augustss
2600 1.9 augustss ehci_soft_qh_t *
2601 1.9 augustss ehci_alloc_sqh(ehci_softc_t *sc)
2602 1.9 augustss {
2603 1.9 augustss ehci_soft_qh_t *sqh;
2604 1.123.12.1 itohy ehci_soft_qtd_t *sqtd;
2605 1.9 augustss usbd_status err;
2606 1.9 augustss int i, offs;
2607 1.9 augustss usb_dma_t dma;
2608 1.123.12.1 itohy struct ehci_mem_desc *em;
2609 1.9 augustss
2610 1.9 augustss if (sc->sc_freeqhs == NULL) {
2611 1.9 augustss DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n"));
2612 1.123.12.1 itohy err = usb_allocmem(&sc->sc_dmatag,
2613 1.123.12.1 itohy EHCI_SQH_SIZE*EHCI_SQH_CHUNK + sizeof(struct ehci_mem_desc),
2614 1.123.12.1 itohy EHCI_PAGE_SIZE, &dma);
2615 1.25 augustss #ifdef EHCI_DEBUG
2616 1.25 augustss if (err)
2617 1.25 augustss printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err);
2618 1.25 augustss #endif
2619 1.9 augustss if (err)
2620 1.11 augustss return (NULL);
2621 1.123.12.1 itohy em = KERNADDR(&dma, EHCI_SQH_SIZE * EHCI_SQH_CHUNK);
2622 1.123.12.1 itohy em->em_top = KERNADDR(&dma, 0);
2623 1.123.12.1 itohy em->em_topdma = DMAADDR(&dma, 0);
2624 1.123.12.1 itohy em->em_dma = dma;
2625 1.123.12.1 itohy SIMPLEQ_INSERT_HEAD(&sc->sc_sqh_chunks, em, em_next);
2626 1.9 augustss for(i = 0; i < EHCI_SQH_CHUNK; i++) {
2627 1.9 augustss offs = i * EHCI_SQH_SIZE;
2628 1.30 augustss sqh = KERNADDR(&dma, offs);
2629 1.123.12.1 itohy sqh->eh_mdesc = em;
2630 1.9 augustss sqh->next = sc->sc_freeqhs;
2631 1.9 augustss sc->sc_freeqhs = sqh;
2632 1.9 augustss }
2633 1.9 augustss }
2634 1.123.12.1 itohy /* Allocate the initial inactive sqtd. */
2635 1.123.12.1 itohy sqtd = ehci_alloc_sqtd_norsv(sc);
2636 1.123.12.1 itohy if (sqtd == NULL)
2637 1.123.12.1 itohy return (NULL);
2638 1.123.12.1 itohy sqtd->qtd.qtd_status = htole32(0);
2639 1.123.12.1 itohy sqtd->qtd.qtd_next = EHCI_NULL;
2640 1.123.12.1 itohy sqtd->qtd.qtd_altnext = EHCI_NULL;
2641 1.123.12.1 itohy
2642 1.9 augustss sqh = sc->sc_freeqhs;
2643 1.9 augustss sc->sc_freeqhs = sqh->next;
2644 1.123.12.1 itohy
2645 1.123.12.1 itohy /* The overlay QTD should begin zeroed. */
2646 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(sqtd));
2647 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
2648 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_status = 0;
2649 1.123.12.1 itohy for (i = 0; i < EHCI_QTD_NBUFFERS; i++) {
2650 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_buffer[i] = 0;
2651 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_buffer_hi[i] = 0;
2652 1.123.12.1 itohy }
2653 1.11 augustss sqh->next = NULL;
2654 1.123.12.1 itohy sqh->prev = NULL;
2655 1.123.12.1 itohy sqh->sqtd = sqtd;
2656 1.123.12.1 itohy sqh->inactivesqtd = sqtd;
2657 1.9 augustss return (sqh);
2658 1.9 augustss }
2659 1.9 augustss
2660 1.9 augustss void
2661 1.9 augustss ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
2662 1.9 augustss {
2663 1.123.12.1 itohy ehci_free_sqtd_norsv(sc, sqh->inactivesqtd);
2664 1.9 augustss sqh->next = sc->sc_freeqhs;
2665 1.9 augustss sc->sc_freeqhs = sqh;
2666 1.9 augustss }
2667 1.9 augustss
2668 1.123.12.1 itohy Static usbd_status
2669 1.123.12.1 itohy ehci_grow_sqtd(ehci_softc_t *sc)
2670 1.9 augustss {
2671 1.123.12.1 itohy usb_dma_t dma;
2672 1.123.12.1 itohy struct ehci_mem_desc *em;
2673 1.9 augustss ehci_soft_qtd_t *sqtd;
2674 1.9 augustss usbd_status err;
2675 1.123.12.1 itohy int i, s, offs;
2676 1.9 augustss
2677 1.123.12.1 itohy DPRINTFN(2, ("ehci_grow_sqtd: allocating chunk\n"));
2678 1.123.12.1 itohy err = usb_allocmem(&sc->sc_dmatag,
2679 1.123.12.1 itohy EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK + sizeof(struct ehci_mem_desc),
2680 1.123.12.1 itohy EHCI_PAGE_SIZE, &dma);
2681 1.25 augustss #ifdef EHCI_DEBUG
2682 1.123.12.1 itohy if (err)
2683 1.123.12.1 itohy printf("ehci_grow_sqtd: usb_allocmem()=%d\n", err);
2684 1.25 augustss #endif
2685 1.123.12.1 itohy if (err)
2686 1.123.12.1 itohy return (err);
2687 1.123.12.1 itohy em = KERNADDR(&dma, EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK);
2688 1.123.12.1 itohy em->em_top = KERNADDR(&dma, 0);
2689 1.123.12.1 itohy em->em_topdma = DMAADDR(&dma, 0);
2690 1.123.12.1 itohy em->em_dma = dma;
2691 1.123.12.1 itohy s = splusb();
2692 1.123.12.1 itohy SIMPLEQ_INSERT_HEAD(&sc->sc_sqtd_chunks, em, em_next);
2693 1.123.12.1 itohy for(i = 0; i < EHCI_SQTD_CHUNK; i++) {
2694 1.123.12.1 itohy offs = i * EHCI_SQTD_SIZE;
2695 1.123.12.1 itohy sqtd = KERNADDR(&dma, offs);
2696 1.123.12.1 itohy sqtd->et_mdesc = em;
2697 1.123.12.1 itohy sqtd->nextqtd = sc->sc_freeqtds;
2698 1.123.12.1 itohy sc->sc_freeqtds = sqtd;
2699 1.123.12.1 itohy sc->sc_nfreeqtds++;
2700 1.9 augustss }
2701 1.123.12.1 itohy splx(s);
2702 1.123.12.1 itohy
2703 1.123.12.1 itohy return (USBD_NORMAL_COMPLETION);
2704 1.123.12.1 itohy }
2705 1.123.12.1 itohy
2706 1.123.12.1 itohy ehci_soft_qtd_t *
2707 1.123.12.1 itohy ehci_alloc_sqtd(ehci_softc_t *sc)
2708 1.123.12.1 itohy {
2709 1.123.12.1 itohy ehci_soft_qtd_t *sqtd;
2710 1.123.12.1 itohy int i;
2711 1.123.12.1 itohy int s;
2712 1.9 augustss
2713 1.9 augustss s = splusb();
2714 1.123.12.1 itohy
2715 1.123.12.1 itohy #ifdef DIAGNOSTIC
2716 1.123.12.1 itohy if (sc->sc_freeqtds == NULL)
2717 1.123.12.1 itohy panic("ehci_alloc_sqtd: %p %d",
2718 1.123.12.1 itohy sc->sc_freeqtds, sc->sc_nfreeqtds);
2719 1.123.12.1 itohy #endif
2720 1.9 augustss sqtd = sc->sc_freeqtds;
2721 1.9 augustss sc->sc_freeqtds = sqtd->nextqtd;
2722 1.123.12.1 itohy splx(s);
2723 1.123.12.1 itohy sqtd->qtd.qtd_next = EHCI_NULL;
2724 1.123.12.1 itohy sqtd->qtd.qtd_altnext = EHCI_NULL;
2725 1.123.12.1 itohy sqtd->qtd.qtd_status = 0;
2726 1.123.12.1 itohy for (i = 0; i < EHCI_QTD_NBUFFERS; i++) {
2727 1.123.12.1 itohy sqtd->qtd.qtd_buffer[i] = 0;
2728 1.123.12.1 itohy sqtd->qtd.qtd_buffer_hi[i] = 0;
2729 1.123.12.1 itohy }
2730 1.9 augustss sqtd->nextqtd = NULL;
2731 1.9 augustss sqtd->xfer = NULL;
2732 1.9 augustss
2733 1.9 augustss return (sqtd);
2734 1.9 augustss }
2735 1.9 augustss
2736 1.123.12.1 itohy Static ehci_soft_qtd_t *
2737 1.123.12.1 itohy ehci_alloc_sqtd_norsv(ehci_softc_t *sc)
2738 1.123.12.1 itohy {
2739 1.123.12.1 itohy int s;
2740 1.123.12.1 itohy
2741 1.123.12.1 itohy s = splusb();
2742 1.123.12.1 itohy if (sc->sc_nfreeqtds < 1)
2743 1.123.12.1 itohy if (ehci_grow_sqtd(sc))
2744 1.123.12.1 itohy return (NULL);
2745 1.123.12.1 itohy sc->sc_nfreeqtds--;
2746 1.123.12.1 itohy splx(s);
2747 1.123.12.1 itohy return (ehci_alloc_sqtd(sc));
2748 1.123.12.1 itohy }
2749 1.123.12.1 itohy
2750 1.9 augustss void
2751 1.9 augustss ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
2752 1.9 augustss {
2753 1.9 augustss int s;
2754 1.9 augustss
2755 1.9 augustss s = splusb();
2756 1.9 augustss sqtd->nextqtd = sc->sc_freeqtds;
2757 1.9 augustss sc->sc_freeqtds = sqtd;
2758 1.9 augustss splx(s);
2759 1.9 augustss }
2760 1.9 augustss
2761 1.123.12.1 itohy Static void
2762 1.123.12.1 itohy ehci_free_sqtd_norsv(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
2763 1.123.12.1 itohy {
2764 1.123.12.1 itohy int s;
2765 1.123.12.1 itohy
2766 1.123.12.1 itohy ehci_free_sqtd(sc, sqtd);
2767 1.123.12.1 itohy s = splusb();
2768 1.123.12.1 itohy sc->sc_nfreeqtds++;
2769 1.123.12.1 itohy splx(s);
2770 1.123.12.1 itohy }
2771 1.123.12.1 itohy
2772 1.15 augustss usbd_status
2773 1.25 augustss ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc,
2774 1.123.12.1 itohy int alen, int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t *start,
2775 1.123.12.1 itohy ehci_soft_qtd_t *newinactive, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep)
2776 1.15 augustss {
2777 1.123.12.3 itohy usb_endpoint_descriptor_t *endpt;
2778 1.15 augustss ehci_soft_qtd_t *next, *cur;
2779 1.123.12.1 itohy ehci_physaddr_t dataphys, nextphys;
2780 1.15 augustss u_int32_t qtdstatus;
2781 1.123.12.1 itohy int adj, len, curlen, mps, offset, pagelen, seg, segoff;
2782 1.123.12.1 itohy int i, iscontrol, forceshort;
2783 1.123.12.1 itohy struct usb_buffer_dma *ub = &EXFER(xfer)->dmabuf;
2784 1.123.12.1 itohy bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub);
2785 1.123.12.1 itohy int nsegs = USB_BUFFER_NSEGS(ub);
2786 1.123.12.3 itohy #if 1
2787 1.123.12.3 itohy int needaux;
2788 1.123.12.3 itohy int isread;
2789 1.123.12.3 itohy union usb_bufptr bufptr;
2790 1.123.12.3 itohy struct aux_desc ad;
2791 1.123.12.3 itohy bus_addr_t auxdma;
2792 1.123.12.3 itohy #endif
2793 1.15 augustss
2794 1.25 augustss DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen));
2795 1.15 augustss
2796 1.123.12.1 itohy offset = 0;
2797 1.15 augustss len = alen;
2798 1.123.12.1 itohy iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) ==
2799 1.123.12.1 itohy UE_CONTROL;
2800 1.67 mycroft qtdstatus = EHCI_QTD_ACTIVE |
2801 1.15 augustss EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
2802 1.15 augustss EHCI_QTD_SET_CERR(3)
2803 1.15 augustss /* IOC set below */
2804 1.15 augustss /* BYTES set below */
2805 1.67 mycroft ;
2806 1.123.12.3 itohy endpt = epipe->pipe.endpoint->edesc;
2807 1.123.12.3 itohy mps = UE_MAXPKTSZ(endpt);
2808 1.123.12.1 itohy forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) &&
2809 1.123.12.1 itohy len % mps == 0;
2810 1.123.12.1 itohy /*
2811 1.123.12.1 itohy * The control transfer data stage always starts with a toggle of 1.
2812 1.123.12.1 itohy * For other transfers we let the hardware track the toggle state.
2813 1.123.12.1 itohy */
2814 1.123.12.1 itohy if (iscontrol)
2815 1.123.12.1 itohy qtdstatus |= EHCI_QTD_SET_TOGGLE(1);
2816 1.123.12.1 itohy
2817 1.123.12.3 itohy #if 1
2818 1.123.12.3 itohy /*
2819 1.123.12.3 itohy * aux memory is possibly required if
2820 1.123.12.3 itohy * buffer has more than one segments,
2821 1.123.12.3 itohy * the transfer direction is OUT,
2822 1.123.12.3 itohy * and
2823 1.123.12.3 itohy * buffer is an mbuf chain, or
2824 1.123.12.3 itohy * buffer is not mps aligned
2825 1.123.12.3 itohy */
2826 1.123.12.3 itohy isread = UE_GET_DIR(endpt->bEndpointAddress) == UE_DIR_IN;
2827 1.123.12.3 itohy needaux =
2828 1.123.12.3 itohy nsegs > 1 && !isread &&
2829 1.123.12.3 itohy ((xfer->rqflags & URQ_DEV_MAP_MBUF) ||
2830 1.123.12.3 itohy (mps & (mps - 1)) != 0 /* mps is not a power of 2 */ ||
2831 1.123.12.3 itohy (segs[0].ds_addr & (mps - 1)) != 0 /* buffer is unaligned */);
2832 1.123.12.3 itohy
2833 1.123.12.3 itohy if (needaux) {
2834 1.123.12.3 itohy usb_bufptr_init(&bufptr, xfer);
2835 1.123.12.3 itohy if (EXFER(xfer)->aux.aux_naux) {
2836 1.123.12.3 itohy /* sync previous aux (just in case, probably a no-op) */
2837 1.123.12.3 itohy ehci_aux_dma_sync(sc, &EXFER(xfer)->aux,
2838 1.123.12.3 itohy BUS_DMASYNC_POSTWRITE);
2839 1.123.12.3 itohy
2840 1.123.12.3 itohy ehci_aux_mem_init(&EXFER(xfer)->aux);
2841 1.123.12.3 itohy }
2842 1.123.12.3 itohy }
2843 1.123.12.3 itohy #endif
2844 1.123.12.3 itohy
2845 1.123.12.1 itohy if (start != NULL) {
2846 1.123.12.1 itohy /*
2847 1.123.12.1 itohy * If we are given a starting qTD, assume it is linked into
2848 1.123.12.1 itohy * an active QH so be careful not to mark it active.
2849 1.123.12.1 itohy */
2850 1.123.12.1 itohy cur = start;
2851 1.123.12.1 itohy *sp = cur;
2852 1.123.12.1 itohy qtdstatus &= ~EHCI_QTD_ACTIVE;
2853 1.123.12.1 itohy } else {
2854 1.123.12.1 itohy cur = ehci_alloc_sqtd(sc);
2855 1.123.12.1 itohy *sp = cur;
2856 1.123.12.1 itohy if (cur == NULL)
2857 1.123.12.1 itohy goto nomem;
2858 1.123.12.1 itohy }
2859 1.123.12.1 itohy seg = 0;
2860 1.123.12.1 itohy segoff = 0;
2861 1.15 augustss for (;;) {
2862 1.123.12.1 itohy curlen = 0;
2863 1.123.12.1 itohy
2864 1.26 augustss /* The EHCI hardware can handle at most 5 pages. */
2865 1.123.12.1 itohy for (i = 0; i < EHCI_QTD_NBUFFERS && curlen < len; i++) {
2866 1.123.12.1 itohy USB_KASSERT2(seg < nsegs,
2867 1.123.12.1 itohy ("ehci_alloc_sqtd_chain: overrun"));
2868 1.123.12.1 itohy dataphys = segs[seg].ds_addr + segoff;
2869 1.123.12.1 itohy pagelen = segs[seg].ds_len - segoff;
2870 1.123.12.1 itohy if (pagelen > len - curlen)
2871 1.123.12.1 itohy pagelen = len - curlen;
2872 1.123.12.1 itohy if (pagelen > EHCI_PAGE_SIZE -
2873 1.123.12.1 itohy EHCI_PAGE_OFFSET(dataphys))
2874 1.123.12.1 itohy pagelen = EHCI_PAGE_SIZE -
2875 1.123.12.1 itohy EHCI_PAGE_OFFSET(dataphys);
2876 1.123.12.1 itohy segoff += pagelen;
2877 1.123.12.1 itohy if (segoff >= segs[seg].ds_len) {
2878 1.123.12.1 itohy USB_KASSERT2(segoff == segs[seg].ds_len,
2879 1.123.12.1 itohy ("ehci_alloc_sqtd_chain: overlap"));
2880 1.123.12.1 itohy seg++;
2881 1.123.12.1 itohy segoff = 0;
2882 1.25 augustss }
2883 1.123.12.1 itohy
2884 1.123.12.1 itohy cur->qtd.qtd_buffer[i] = htole32(dataphys);
2885 1.123.12.1 itohy cur->qtd.qtd_buffer_hi[i] = 0;
2886 1.123.12.1 itohy curlen += pagelen;
2887 1.123.12.1 itohy
2888 1.123.12.1 itohy /*
2889 1.123.12.1 itohy * Must stop if there is any gap before or after
2890 1.123.12.1 itohy * the page boundary.
2891 1.123.12.1 itohy */
2892 1.123.12.1 itohy if (EHCI_PAGE_OFFSET(dataphys + pagelen) != 0)
2893 1.123.12.1 itohy break;
2894 1.123.12.1 itohy if (seg < nsegs && EHCI_PAGE_OFFSET(segoff +
2895 1.123.12.1 itohy segs[seg].ds_addr) != 0)
2896 1.123.12.1 itohy break;
2897 1.15 augustss }
2898 1.123.12.1 itohy /* Adjust down to a multiple of mps if not at the end. */
2899 1.123.12.3 itohy if (!isread && curlen < len && (adj = curlen % mps) != 0) {
2900 1.123.12.1 itohy curlen -= adj;
2901 1.123.12.3 itohy #if 1
2902 1.123.12.3 itohy if (curlen == 0) {
2903 1.123.12.3 itohy USB_KASSERT(needaux);
2904 1.123.12.3 itohy /* need aux -- a packet is not contiguous */
2905 1.123.12.3 itohy curlen = len < mps ? len : mps;
2906 1.123.12.3 itohy auxdma = ehci_aux_dma_alloc(&EXFER(xfer)->aux,
2907 1.123.12.3 itohy curlen, &ad);
2908 1.123.12.3 itohy
2909 1.123.12.3 itohy /* prepare aux DMA */
2910 1.123.12.3 itohy usb_bufptr_wr(&bufptr, ad.aux_kern, curlen,
2911 1.123.12.3 itohy xfer->rqflags & URQ_DEV_MAP_MBUF);
2912 1.123.12.3 itohy cur->qtd.qtd_buffer[i] = htole32(auxdma);
2913 1.123.12.3 itohy cur->qtd.qtd_buffer_hi[i] = 0;
2914 1.123.12.3 itohy
2915 1.123.12.3 itohy /* skip handled segments */
2916 1.123.12.3 itohy segoff += curlen - adj;
2917 1.123.12.3 itohy do {
2918 1.123.12.3 itohy segoff -= segs[seg].ds_len;
2919 1.123.12.3 itohy seg++;
2920 1.123.12.3 itohy } while (segoff > segs[seg].ds_len);
2921 1.123.12.3 itohy
2922 1.123.12.3 itohy } else {
2923 1.123.12.3 itohy #endif
2924 1.123.12.3 itohy #if 0
2925 1.123.12.1 itohy USB_KASSERT2(curlen > 0,
2926 1.123.12.1 itohy ("ehci_alloc_sqtd_chain: need to copy"));
2927 1.123.12.3 itohy #endif
2928 1.123.12.1 itohy segoff -= adj;
2929 1.123.12.1 itohy if (segoff < 0) {
2930 1.123.12.1 itohy seg--;
2931 1.123.12.1 itohy segoff += segs[seg].ds_len;
2932 1.123.12.1 itohy }
2933 1.123.12.1 itohy USB_KASSERT2(seg >= 0 && segoff >= 0,
2934 1.123.12.1 itohy ("ehci_alloc_sqtd_chain: adjust to mps"));
2935 1.123.12.3 itohy }
2936 1.123.12.1 itohy }
2937 1.123.12.1 itohy
2938 1.15 augustss len -= curlen;
2939 1.15 augustss
2940 1.123.12.1 itohy if (len != 0 || forceshort) {
2941 1.15 augustss next = ehci_alloc_sqtd(sc);
2942 1.15 augustss if (next == NULL)
2943 1.15 augustss goto nomem;
2944 1.123.12.1 itohy nextphys = htole32(EHCI_SQTD_DMAADDR(next));
2945 1.15 augustss } else {
2946 1.15 augustss next = NULL;
2947 1.15 augustss nextphys = EHCI_NULL;
2948 1.15 augustss }
2949 1.15 augustss
2950 1.15 augustss cur->nextqtd = next;
2951 1.123.12.1 itohy cur->qtd.qtd_next = nextphys;
2952 1.123.12.1 itohy /* Make sure to stop after a short transfer. */
2953 1.123.12.1 itohy cur->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive));
2954 1.15 augustss cur->qtd.qtd_status =
2955 1.67 mycroft htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen));
2956 1.15 augustss cur->xfer = xfer;
2957 1.18 augustss cur->len = curlen;
2958 1.123.12.1 itohy DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%d\n", curlen));
2959 1.123.12.1 itohy if (iscontrol) {
2960 1.123.12.1 itohy /*
2961 1.123.12.1 itohy * adjust the toggle based on the number of packets
2962 1.123.12.1 itohy * in this qtd
2963 1.123.12.1 itohy */
2964 1.123.12.1 itohy if ((((curlen + mps - 1) / mps) & 1) || curlen == 0)
2965 1.123.12.1 itohy qtdstatus ^= EHCI_QTD_TOGGLE_MASK;
2966 1.123.12.1 itohy }
2967 1.123.12.1 itohy qtdstatus |= EHCI_QTD_ACTIVE;
2968 1.123.12.1 itohy if (len == 0) {
2969 1.123.12.1 itohy if (!forceshort)
2970 1.123.12.1 itohy break;
2971 1.123.12.1 itohy forceshort = 0;
2972 1.55 mycroft }
2973 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, cur,
2974 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2975 1.25 augustss DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n"));
2976 1.123.12.1 itohy offset += curlen;
2977 1.15 augustss cur = next;
2978 1.123.12.3 itohy
2979 1.123.12.3 itohy #if 1
2980 1.123.12.3 itohy if (needaux)
2981 1.123.12.3 itohy usb_bufptr_advance(&bufptr, curlen,
2982 1.123.12.3 itohy xfer->rqflags & URQ_DEV_MAP_MBUF);
2983 1.123.12.3 itohy #endif
2984 1.15 augustss }
2985 1.15 augustss cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
2986 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, cur,
2987 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2988 1.123.12.3 itohy if (needaux)
2989 1.123.12.3 itohy ehci_aux_dma_sync(sc, &EXFER(xfer)->aux, BUS_DMASYNC_PREWRITE);
2990 1.123.12.3 itohy
2991 1.15 augustss *ep = cur;
2992 1.15 augustss
2993 1.29 augustss DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n",
2994 1.29 augustss *sp, *ep));
2995 1.29 augustss
2996 1.15 augustss return (USBD_NORMAL_COMPLETION);
2997 1.15 augustss
2998 1.15 augustss nomem:
2999 1.15 augustss /* XXX free chain */
3000 1.25 augustss DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n"));
3001 1.15 augustss return (USBD_NOMEM);
3002 1.15 augustss }
3003 1.15 augustss
3004 1.123.12.1 itohy /* Free the chain starting at sqtd and end at the qTD before sqtdend */
3005 1.18 augustss Static void
3006 1.123.12.1 itohy ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qh_t *sqh,
3007 1.123.12.1 itohy ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *sqtdend)
3008 1.18 augustss {
3009 1.123.12.1 itohy ehci_soft_qtd_t *p, **prevp;
3010 1.25 augustss int i;
3011 1.18 augustss
3012 1.29 augustss DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n",
3013 1.29 augustss sqtd, sqtdend));
3014 1.29 augustss
3015 1.123.12.1 itohy /* First unlink the chain from the QH's software qTD list. */
3016 1.123.12.1 itohy prevp = &sqh->sqtd;
3017 1.123.12.1 itohy for (p = sqh->sqtd; p != NULL; p = p->nextqtd) {
3018 1.123.12.1 itohy if (p == sqtd) {
3019 1.123.12.1 itohy *prevp = sqtdend;
3020 1.123.12.1 itohy break;
3021 1.123.12.1 itohy }
3022 1.123.12.1 itohy prevp = &p->nextqtd;
3023 1.123.12.1 itohy }
3024 1.123.12.1 itohy USB_KASSERT2(p != NULL, ("ehci_free_sqtd_chain: chain not found"));
3025 1.25 augustss for (i = 0; sqtd != sqtdend; sqtd = p, i++) {
3026 1.18 augustss p = sqtd->nextqtd;
3027 1.18 augustss ehci_free_sqtd(sc, sqtd);
3028 1.18 augustss }
3029 1.18 augustss }
3030 1.18 augustss
3031 1.15 augustss /****************/
3032 1.15 augustss
3033 1.9 augustss /*
3034 1.10 augustss * Close a reqular pipe.
3035 1.10 augustss * Assumes that there are no pending transactions.
3036 1.10 augustss */
3037 1.10 augustss void
3038 1.10 augustss ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head)
3039 1.10 augustss {
3040 1.10 augustss struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
3041 1.10 augustss ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
3042 1.10 augustss ehci_soft_qh_t *sqh = epipe->sqh;
3043 1.10 augustss int s;
3044 1.10 augustss
3045 1.10 augustss s = splusb();
3046 1.10 augustss ehci_rem_qh(sc, sqh, head);
3047 1.10 augustss splx(s);
3048 1.123.12.1 itohy pipe->endpoint->savedtoggle =
3049 1.123.12.1 itohy EHCI_QTD_GET_TOGGLE(le32toh(sqh->qh.qh_qtd.qtd_status));
3050 1.10 augustss ehci_free_sqh(sc, epipe->sqh);
3051 1.10 augustss }
3052 1.10 augustss
3053 1.33 augustss /*
3054 1.10 augustss * Abort a device request.
3055 1.10 augustss * If this routine is called at splusb() it guarantees that the request
3056 1.10 augustss * will be removed from the hardware scheduling and that the callback
3057 1.10 augustss * for it will be called with USBD_CANCELLED status.
3058 1.10 augustss * It's impossible to guarantee that the requested transfer will not
3059 1.10 augustss * have happened since the hardware runs concurrently.
3060 1.10 augustss * If the transaction has already happened we rely on the ordinary
3061 1.10 augustss * interrupt processing to process it.
3062 1.10 augustss */
3063 1.10 augustss void
3064 1.10 augustss ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
3065 1.10 augustss {
3066 1.26 augustss #define exfer EXFER(xfer)
3067 1.10 augustss struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3068 1.17 augustss ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
3069 1.26 augustss ehci_soft_qh_t *sqh = epipe->sqh;
3070 1.123.12.1 itohy ehci_soft_qtd_t *sqtd, *snext;
3071 1.123.12.1 itohy ehci_physaddr_t cur, us, next;
3072 1.11 augustss int s;
3073 1.123.12.1 itohy int hit, i;
3074 1.123.12.1 itohy /* int count = 0; */
3075 1.123.12.1 itohy ehci_soft_qh_t *psqh;
3076 1.10 augustss
3077 1.24 augustss DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe));
3078 1.10 augustss
3079 1.17 augustss if (sc->sc_dying) {
3080 1.17 augustss /* If we're dying, just do the software part. */
3081 1.17 augustss s = splusb();
3082 1.17 augustss xfer->status = status; /* make software ignore it */
3083 1.17 augustss usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer);
3084 1.123.12.1 itohy usb_rem_task(epipe->pipe.device, &exfer->abort_task);
3085 1.123.12.1 itohy usb_transfer_complete_dma(xfer, &sc->sc_dmatag,
3086 1.123.12.1 itohy &EXFER(xfer)->dmabuf);
3087 1.17 augustss splx(s);
3088 1.17 augustss return;
3089 1.17 augustss }
3090 1.17 augustss
3091 1.10 augustss if (xfer->device->bus->intr_context || !curproc)
3092 1.37 provos panic("ehci_abort_xfer: not in process context");
3093 1.10 augustss
3094 1.11 augustss /*
3095 1.96 augustss * If an abort is already in progress then just wait for it to
3096 1.96 augustss * complete and return.
3097 1.96 augustss */
3098 1.123.12.1 itohy if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) {
3099 1.96 augustss DPRINTFN(2, ("ehci_abort_xfer: already aborting\n"));
3100 1.123.12.1 itohy /* No need to wait if we're aborting from a timeout. */
3101 1.96 augustss if (status == USBD_TIMEOUT)
3102 1.123.12.1 itohy return;
3103 1.96 augustss /* Override the status which might be USBD_TIMEOUT. */
3104 1.96 augustss xfer->status = status;
3105 1.96 augustss DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n"));
3106 1.123.12.1 itohy exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT;
3107 1.123.12.1 itohy while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING)
3108 1.123.12.1 itohy tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciaw", 0);
3109 1.96 augustss return;
3110 1.96 augustss }
3111 1.96 augustss
3112 1.96 augustss /*
3113 1.123.12.1 itohy * Step 1: Make interrupt routine and timeouts ignore xfer.
3114 1.11 augustss */
3115 1.11 augustss s = splusb();
3116 1.123.12.1 itohy exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING;
3117 1.11 augustss xfer->status = status; /* make software ignore it */
3118 1.15 augustss usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer);
3119 1.123.12.1 itohy usb_rem_task(epipe->pipe.device, &exfer->abort_task);
3120 1.11 augustss splx(s);
3121 1.11 augustss
3122 1.33 augustss /*
3123 1.11 augustss * Step 2: Wait until we know hardware has finished any possible
3124 1.123.12.1 itohy * use of the xfer. We do this by removing the entire
3125 1.123.12.1 itohy * queue from the async schedule and waiting for the doorbell.
3126 1.123.12.1 itohy * Nothing else should be touching the queue now.
3127 1.123.12.1 itohy */
3128 1.123.12.1 itohy psqh = sqh->prev;
3129 1.123.12.1 itohy ehci_rem_qh(sc, sqh, psqh);
3130 1.123.12.1 itohy
3131 1.123.12.1 itohy /*
3132 1.123.12.1 itohy * Step 3: make sure the soft interrupt routine
3133 1.123.12.1 itohy * has run. This should remove any completed items off the queue.
3134 1.123.12.1 itohy * The hardware has no reference to completed items (TDs).
3135 1.123.12.1 itohy * It's safe to remove them at any time.
3136 1.11 augustss */
3137 1.29 augustss s = splusb();
3138 1.77 augustss #ifdef USB_USE_SOFTINTR
3139 1.29 augustss sc->sc_softwake = 1;
3140 1.77 augustss #endif /* USB_USE_SOFTINTR */
3141 1.29 augustss usb_schedsoftintr(&sc->sc_bus);
3142 1.77 augustss #ifdef USB_USE_SOFTINTR
3143 1.29 augustss tsleep(&sc->sc_softwake, PZERO, "ehciab", 0);
3144 1.77 augustss #endif /* USB_USE_SOFTINTR */
3145 1.33 augustss
3146 1.33 augustss /*
3147 1.123.12.1 itohy * Step 4: Remove any vestiges of the xfer from the hardware.
3148 1.11 augustss * The complication here is that the hardware may have executed
3149 1.123.12.1 itohy * into or even beyond the xfer we're trying to abort.
3150 1.123.12.1 itohy * So as we're scanning the TDs of this xfer we check if
3151 1.123.12.1 itohy * the hardware points to any of them.
3152 1.123.12.1 itohy *
3153 1.123.12.1 itohy * first we need to see if there are any transfers
3154 1.123.12.1 itohy * on this queue before the xfer we are aborting.. we need
3155 1.123.12.1 itohy * to update any pointers that point to us to point past
3156 1.123.12.1 itohy * the aborting xfer. (If there is something past us).
3157 1.123.12.1 itohy * Hardware and software.
3158 1.11 augustss */
3159 1.26 augustss cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd));
3160 1.26 augustss hit = 0;
3161 1.123.12.1 itohy
3162 1.123.12.1 itohy /* If they initially point here. */
3163 1.123.12.1 itohy us = EHCI_SQTD_DMAADDR(exfer->sqtdstart);
3164 1.123.12.1 itohy
3165 1.123.12.1 itohy /* We will change them to point here */
3166 1.123.12.1 itohy snext = exfer->sqtdend->nextqtd;
3167 1.123.12.1 itohy next = htole32(EHCI_SQTD_DMAADDR(snext));
3168 1.123.12.1 itohy
3169 1.123.12.1 itohy /*
3170 1.123.12.1 itohy * Now loop through any qTDs before us and keep track of the pointer
3171 1.123.12.1 itohy * that points to us for the end.
3172 1.123.12.1 itohy */
3173 1.123.12.1 itohy sqtd = sqh->sqtd;
3174 1.123.12.1 itohy while (sqtd && sqtd != exfer->sqtdstart) {
3175 1.123.12.1 itohy hit |= (cur == EHCI_SQTD_DMAADDR(sqtd));
3176 1.123.12.1 itohy if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_next)) == us) {
3177 1.123.12.1 itohy sqtd->qtd.qtd_next = next;
3178 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, sqtd,
3179 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3180 1.123.12.1 itohy }
3181 1.123.12.1 itohy if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_altnext)) == us) {
3182 1.123.12.1 itohy sqtd->qtd.qtd_altnext = next;
3183 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, sqtd,
3184 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3185 1.123.12.1 itohy }
3186 1.123.12.1 itohy sqtd = sqtd->nextqtd;
3187 1.26 augustss }
3188 1.11 augustss
3189 1.11 augustss /*
3190 1.123.12.1 itohy * If we already saw the active one then we are pretty much done.
3191 1.123.12.1 itohy * We've done all the relinking we need to do.
3192 1.123.12.1 itohy */
3193 1.123.12.1 itohy if (!hit) {
3194 1.123.12.1 itohy
3195 1.123.12.1 itohy /*
3196 1.123.12.1 itohy * Now reinitialise the QH to point to the next qTD
3197 1.123.12.1 itohy * (if there is one). We only need to do this if
3198 1.123.12.1 itohy * it was previously pointing to us.
3199 1.123.12.1 itohy */
3200 1.123.12.1 itohy for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
3201 1.123.12.1 itohy if (cur == EHCI_SQTD_DMAADDR(sqtd)) {
3202 1.123.12.1 itohy hit++;
3203 1.123.12.1 itohy }
3204 1.123.12.1 itohy if (sqtd == exfer->sqtdend)
3205 1.123.12.1 itohy break;
3206 1.123.12.1 itohy }
3207 1.123.12.1 itohy sqtd = sqtd->nextqtd;
3208 1.123.12.1 itohy /*
3209 1.123.12.1 itohy * Only need to alter the QH if it was pointing at a qTD
3210 1.123.12.1 itohy * that we are removing.
3211 1.123.12.1 itohy */
3212 1.123.12.1 itohy if (hit) {
3213 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_next =
3214 1.123.12.1 itohy htole32(EHCI_SQTD_DMAADDR(snext));
3215 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
3216 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_status &=
3217 1.123.12.1 itohy htole32(EHCI_QTD_TOGGLE_MASK);
3218 1.123.12.1 itohy for (i = 0; i < EHCI_QTD_NBUFFERS; i++) {
3219 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_buffer[i] = 0;
3220 1.123.12.1 itohy sqh->qh.qh_qtd.qtd_buffer_hi[i] = 0;
3221 1.123.12.1 itohy }
3222 1.123.12.1 itohy }
3223 1.123.12.1 itohy }
3224 1.123.12.1 itohy ehci_add_qh(sc, sqh, psqh);
3225 1.123.12.1 itohy /*
3226 1.123.12.1 itohy * Step 5: Execute callback.
3227 1.11 augustss */
3228 1.18 augustss #ifdef DIAGNOSTIC
3229 1.26 augustss exfer->isdone = 1;
3230 1.18 augustss #endif
3231 1.123.12.1 itohy /* Do the wakeup first to avoid touching the xfer after the callback. */
3232 1.123.12.1 itohy exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING;
3233 1.123.12.1 itohy if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) {
3234 1.123.12.1 itohy exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT;
3235 1.123.12.1 itohy wakeup(&exfer->ehci_xfer_flags);
3236 1.123.12.1 itohy }
3237 1.123.12.1 itohy usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf);
3238 1.11 augustss
3239 1.123.12.1 itohy /* printf("%s: %d TDs aborted\n", __func__, count); */
3240 1.11 augustss splx(s);
3241 1.26 augustss #undef exfer
3242 1.10 augustss }
3243 1.10 augustss
3244 1.15 augustss void
3245 1.15 augustss ehci_timeout(void *addr)
3246 1.15 augustss {
3247 1.15 augustss struct ehci_xfer *exfer = addr;
3248 1.17 augustss struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe;
3249 1.17 augustss ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
3250 1.15 augustss
3251 1.15 augustss DPRINTF(("ehci_timeout: exfer=%p\n", exfer));
3252 1.22 augustss #ifdef USB_DEBUG
3253 1.26 augustss if (ehcidebug > 1)
3254 1.22 augustss usbd_dump_pipe(exfer->xfer.pipe);
3255 1.22 augustss #endif
3256 1.15 augustss
3257 1.17 augustss if (sc->sc_dying) {
3258 1.17 augustss ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT);
3259 1.17 augustss return;
3260 1.17 augustss }
3261 1.17 augustss
3262 1.15 augustss /* Execute the abort in a process context. */
3263 1.114 joerg usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task,
3264 1.114 joerg USB_TASKQ_HC);
3265 1.15 augustss }
3266 1.15 augustss
3267 1.15 augustss void
3268 1.15 augustss ehci_timeout_task(void *addr)
3269 1.15 augustss {
3270 1.15 augustss usbd_xfer_handle xfer = addr;
3271 1.15 augustss int s;
3272 1.15 augustss
3273 1.15 augustss DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer));
3274 1.15 augustss
3275 1.15 augustss s = splusb();
3276 1.15 augustss ehci_abort_xfer(xfer, USBD_TIMEOUT);
3277 1.15 augustss splx(s);
3278 1.15 augustss }
3279 1.15 augustss
3280 1.123.12.1 itohy /*
3281 1.123.12.1 itohy * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing
3282 1.123.12.1 itohy * back the qTD status, or miss signalling occasionally under heavy load.
3283 1.123.12.1 itohy * If the host machine is too fast, we can miss transaction completion - when
3284 1.123.12.1 itohy * we scan the active list the transaction still seems to be active. This
3285 1.123.12.1 itohy * generally exhibits itself as a umass stall that never recovers.
3286 1.123.12.1 itohy *
3287 1.123.12.1 itohy * We work around this behaviour by setting up this callback after any softintr
3288 1.123.12.1 itohy * that completes with transactions still pending, giving us another chance to
3289 1.123.12.1 itohy * check for completion after the writeback has taken place.
3290 1.123.12.1 itohy */
3291 1.123.12.1 itohy void
3292 1.123.12.1 itohy ehci_intrlist_timeout(void *arg)
3293 1.123.12.1 itohy {
3294 1.123.12.1 itohy ehci_softc_t *sc = arg;
3295 1.123.12.1 itohy int s = splusb();
3296 1.123.12.1 itohy
3297 1.123.12.1 itohy DPRINTFN(3, ("ehci_intrlist_timeout\n"));
3298 1.123.12.1 itohy usb_schedsoftintr(&sc->sc_bus);
3299 1.123.12.1 itohy
3300 1.123.12.1 itohy splx(s);
3301 1.123.12.1 itohy }
3302 1.123.12.1 itohy
3303 1.5 augustss /************************/
3304 1.5 augustss
3305 1.10 augustss Static usbd_status
3306 1.10 augustss ehci_device_ctrl_transfer(usbd_xfer_handle xfer)
3307 1.10 augustss {
3308 1.123.12.1 itohy ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
3309 1.10 augustss usbd_status err;
3310 1.10 augustss
3311 1.10 augustss /* Insert last in queue. */
3312 1.123.12.1 itohy err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag,
3313 1.123.12.1 itohy &EXFER(xfer)->dmabuf);
3314 1.10 augustss if (err)
3315 1.10 augustss return (err);
3316 1.10 augustss
3317 1.10 augustss /* Pipe isn't running, start first */
3318 1.10 augustss return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3319 1.10 augustss }
3320 1.10 augustss
3321 1.12 augustss Static usbd_status
3322 1.12 augustss ehci_device_ctrl_start(usbd_xfer_handle xfer)
3323 1.12 augustss {
3324 1.15 augustss ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
3325 1.15 augustss usbd_status err;
3326 1.15 augustss
3327 1.15 augustss if (sc->sc_dying)
3328 1.15 augustss return (USBD_IOERROR);
3329 1.15 augustss
3330 1.15 augustss #ifdef DIAGNOSTIC
3331 1.15 augustss if (!(xfer->rqflags & URQ_REQUEST)) {
3332 1.15 augustss /* XXX panic */
3333 1.15 augustss printf("ehci_device_ctrl_transfer: not a request\n");
3334 1.15 augustss return (USBD_INVAL);
3335 1.15 augustss }
3336 1.15 augustss #endif
3337 1.15 augustss
3338 1.15 augustss err = ehci_device_request(xfer);
3339 1.15 augustss if (err)
3340 1.15 augustss return (err);
3341 1.15 augustss
3342 1.15 augustss if (sc->sc_bus.use_polling)
3343 1.15 augustss ehci_waitintr(sc, xfer);
3344 1.15 augustss return (USBD_IN_PROGRESS);
3345 1.12 augustss }
3346 1.10 augustss
3347 1.10 augustss void
3348 1.10 augustss ehci_device_ctrl_done(usbd_xfer_handle xfer)
3349 1.10 augustss {
3350 1.18 augustss struct ehci_xfer *ex = EXFER(xfer);
3351 1.18 augustss ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
3352 1.123.12.1 itohy struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3353 1.18 augustss
3354 1.10 augustss DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer));
3355 1.10 augustss
3356 1.10 augustss #ifdef DIAGNOSTIC
3357 1.10 augustss if (!(xfer->rqflags & URQ_REQUEST)) {
3358 1.37 provos panic("ehci_ctrl_done: not a request");
3359 1.10 augustss }
3360 1.10 augustss #endif
3361 1.18 augustss
3362 1.44 augustss if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
3363 1.25 augustss ehci_del_intr_list(ex); /* remove from active list */
3364 1.123.12.1 itohy ehci_free_sqtd_chain(sc, epipe->sqh, ex->sqtdstart,
3365 1.123.12.1 itohy ex->sqtdend->nextqtd);
3366 1.25 augustss }
3367 1.18 augustss
3368 1.25 augustss DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen));
3369 1.10 augustss }
3370 1.10 augustss
3371 1.10 augustss /* Abort a device control request. */
3372 1.10 augustss Static void
3373 1.10 augustss ehci_device_ctrl_abort(usbd_xfer_handle xfer)
3374 1.10 augustss {
3375 1.10 augustss DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer));
3376 1.10 augustss ehci_abort_xfer(xfer, USBD_CANCELLED);
3377 1.10 augustss }
3378 1.10 augustss
3379 1.10 augustss /* Close a device control pipe. */
3380 1.10 augustss Static void
3381 1.10 augustss ehci_device_ctrl_close(usbd_pipe_handle pipe)
3382 1.10 augustss {
3383 1.123.12.1 itohy struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
3384 1.10 augustss ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
3385 1.10 augustss
3386 1.10 augustss DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe));
3387 1.11 augustss ehci_close_pipe(pipe, sc->sc_async_head);
3388 1.123.12.1 itohy usb_freemem(&sc->sc_dmatag, &epipe->u.ctl.reqdma);
3389 1.15 augustss }
3390 1.15 augustss
3391 1.15 augustss usbd_status
3392 1.15 augustss ehci_device_request(usbd_xfer_handle xfer)
3393 1.15 augustss {
3394 1.18 augustss #define exfer EXFER(xfer)
3395 1.15 augustss struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3396 1.15 augustss usb_device_request_t *req = &xfer->request;
3397 1.15 augustss usbd_device_handle dev = epipe->pipe.device;
3398 1.15 augustss ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
3399 1.123.12.1 itohy ehci_soft_qtd_t *newinactive, *setup, *stat, *next;
3400 1.15 augustss ehci_soft_qh_t *sqh;
3401 1.15 augustss int isread;
3402 1.15 augustss int len;
3403 1.15 augustss usbd_status err;
3404 1.15 augustss int s;
3405 1.15 augustss
3406 1.15 augustss isread = req->bmRequestType & UT_READ;
3407 1.15 augustss len = UGETW(req->wLength);
3408 1.15 augustss
3409 1.72 augustss DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, "
3410 1.15 augustss "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
3411 1.15 augustss req->bmRequestType, req->bRequest, UGETW(req->wValue),
3412 1.123.12.1 itohy UGETW(req->wIndex), len, dev->address,
3413 1.15 augustss epipe->pipe.endpoint->edesc->bEndpointAddress));
3414 1.15 augustss
3415 1.123.12.1 itohy newinactive = ehci_alloc_sqtd(sc);
3416 1.123.12.1 itohy if (newinactive == NULL) {
3417 1.15 augustss err = USBD_NOMEM;
3418 1.15 augustss goto bad1;
3419 1.15 augustss }
3420 1.123.12.1 itohy newinactive->qtd.qtd_status = htole32(0);
3421 1.123.12.1 itohy newinactive->qtd.qtd_next = EHCI_NULL;
3422 1.123.12.1 itohy newinactive->qtd.qtd_altnext = EHCI_NULL;
3423 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, newinactive,
3424 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3425 1.15 augustss stat = ehci_alloc_sqtd(sc);
3426 1.15 augustss if (stat == NULL) {
3427 1.15 augustss err = USBD_NOMEM;
3428 1.15 augustss goto bad2;
3429 1.15 augustss }
3430 1.15 augustss
3431 1.15 augustss sqh = epipe->sqh;
3432 1.123.12.1 itohy setup = sqh->inactivesqtd;
3433 1.123.12.1 itohy sqh->inactivesqtd = newinactive;
3434 1.15 augustss epipe->u.ctl.length = len;
3435 1.15 augustss
3436 1.15 augustss /* Set up data transaction */
3437 1.15 augustss if (len != 0) {
3438 1.15 augustss ehci_soft_qtd_t *end;
3439 1.15 augustss
3440 1.25 augustss err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
3441 1.123.12.1 itohy NULL, newinactive, &next, &end);
3442 1.15 augustss if (err)
3443 1.15 augustss goto bad3;
3444 1.83 augustss end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC);
3445 1.15 augustss end->nextqtd = stat;
3446 1.123.12.1 itohy end->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(stat));
3447 1.123.12.1 itohy end->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive));
3448 1.15 augustss } else {
3449 1.15 augustss next = stat;
3450 1.15 augustss }
3451 1.15 augustss
3452 1.30 augustss memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req);
3453 1.15 augustss
3454 1.123.12.1 itohy /* Clear toggle, and do not activate until complete */
3455 1.15 augustss setup->qtd.qtd_status = htole32(
3456 1.15 augustss EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
3457 1.15 augustss EHCI_QTD_SET_CERR(3) |
3458 1.64 mycroft EHCI_QTD_SET_TOGGLE(0) |
3459 1.15 augustss EHCI_QTD_SET_BYTES(sizeof *req)
3460 1.15 augustss );
3461 1.31 augustss setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0));
3462 1.48 mycroft setup->qtd.qtd_buffer_hi[0] = 0;
3463 1.15 augustss setup->nextqtd = next;
3464 1.123.12.1 itohy setup->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(next));
3465 1.123.12.1 itohy setup->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive));
3466 1.15 augustss setup->xfer = xfer;
3467 1.18 augustss setup->len = sizeof *req;
3468 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, setup, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3469 1.15 augustss
3470 1.15 augustss stat->qtd.qtd_status = htole32(
3471 1.26 augustss EHCI_QTD_ACTIVE |
3472 1.15 augustss EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
3473 1.15 augustss EHCI_QTD_SET_CERR(3) |
3474 1.64 mycroft EHCI_QTD_SET_TOGGLE(1) |
3475 1.15 augustss EHCI_QTD_IOC
3476 1.15 augustss );
3477 1.15 augustss stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */
3478 1.48 mycroft stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */
3479 1.123.12.1 itohy stat->nextqtd = newinactive;
3480 1.123.12.1 itohy stat->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive));
3481 1.123.12.1 itohy stat->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive));
3482 1.15 augustss stat->xfer = xfer;
3483 1.18 augustss stat->len = 0;
3484 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, stat, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3485 1.15 augustss
3486 1.15 augustss #ifdef EHCI_DEBUG
3487 1.23 augustss if (ehcidebug > 5) {
3488 1.15 augustss DPRINTF(("ehci_device_request:\n"));
3489 1.15 augustss ehci_dump_sqh(sqh);
3490 1.15 augustss ehci_dump_sqtds(setup);
3491 1.15 augustss }
3492 1.15 augustss #endif
3493 1.15 augustss
3494 1.18 augustss exfer->sqtdstart = setup;
3495 1.18 augustss exfer->sqtdend = stat;
3496 1.18 augustss #ifdef DIAGNOSTIC
3497 1.18 augustss if (!exfer->isdone) {
3498 1.18 augustss printf("ehci_device_request: not done, exfer=%p\n", exfer);
3499 1.18 augustss }
3500 1.18 augustss exfer->isdone = 0;
3501 1.18 augustss #endif
3502 1.18 augustss
3503 1.123.12.1 itohy /* Activate the new qTD in the QH list. */
3504 1.15 augustss s = splusb();
3505 1.123.12.1 itohy ehci_activate_qh(sc, sqh, setup);
3506 1.15 augustss if (xfer->timeout && !sc->sc_bus.use_polling) {
3507 1.123.12.1 itohy usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
3508 1.15 augustss ehci_timeout, xfer);
3509 1.15 augustss }
3510 1.18 augustss ehci_add_intr_list(sc, exfer);
3511 1.18 augustss xfer->status = USBD_IN_PROGRESS;
3512 1.15 augustss splx(s);
3513 1.15 augustss
3514 1.17 augustss #ifdef EHCI_DEBUG
3515 1.15 augustss if (ehcidebug > 10) {
3516 1.15 augustss DPRINTF(("ehci_device_request: status=%x\n",
3517 1.15 augustss EOREAD4(sc, EHCI_USBSTS)));
3518 1.23 augustss delay(10000);
3519 1.18 augustss ehci_dump_regs(sc);
3520 1.15 augustss ehci_dump_sqh(sc->sc_async_head);
3521 1.15 augustss ehci_dump_sqh(sqh);
3522 1.15 augustss ehci_dump_sqtds(setup);
3523 1.15 augustss }
3524 1.15 augustss #endif
3525 1.15 augustss
3526 1.15 augustss return (USBD_NORMAL_COMPLETION);
3527 1.15 augustss
3528 1.15 augustss bad3:
3529 1.123.12.1 itohy sqh->inactivesqtd = setup;
3530 1.15 augustss ehci_free_sqtd(sc, stat);
3531 1.15 augustss bad2:
3532 1.123.12.1 itohy ehci_free_sqtd(sc, newinactive);
3533 1.15 augustss bad1:
3534 1.25 augustss DPRINTFN(-1,("ehci_device_request: no memory\n"));
3535 1.25 augustss xfer->status = err;
3536 1.123.12.1 itohy usb_transfer_complete_dma(xfer, &sc->sc_dmatag,
3537 1.123.12.1 itohy &EXFER(xfer)->dmabuf);
3538 1.15 augustss return (err);
3539 1.18 augustss #undef exfer
3540 1.10 augustss }
3541 1.10 augustss
3542 1.10 augustss /************************/
3543 1.5 augustss
3544 1.19 augustss Static usbd_status
3545 1.19 augustss ehci_device_bulk_transfer(usbd_xfer_handle xfer)
3546 1.19 augustss {
3547 1.123.12.1 itohy ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
3548 1.19 augustss usbd_status err;
3549 1.19 augustss
3550 1.19 augustss /* Insert last in queue. */
3551 1.123.12.1 itohy err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag,
3552 1.123.12.1 itohy &EXFER(xfer)->dmabuf);
3553 1.19 augustss if (err)
3554 1.19 augustss return (err);
3555 1.19 augustss
3556 1.19 augustss /* Pipe isn't running, start first */
3557 1.19 augustss return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3558 1.19 augustss }
3559 1.19 augustss
3560 1.19 augustss usbd_status
3561 1.19 augustss ehci_device_bulk_start(usbd_xfer_handle xfer)
3562 1.19 augustss {
3563 1.19 augustss #define exfer EXFER(xfer)
3564 1.19 augustss struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3565 1.19 augustss usbd_device_handle dev = epipe->pipe.device;
3566 1.19 augustss ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
3567 1.123.12.1 itohy ehci_soft_qtd_t *data, *dataend, *newinactive;
3568 1.19 augustss ehci_soft_qh_t *sqh;
3569 1.19 augustss usbd_status err;
3570 1.19 augustss int len, isread, endpt;
3571 1.19 augustss int s;
3572 1.19 augustss
3573 1.72 augustss DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n",
3574 1.19 augustss xfer, xfer->length, xfer->flags));
3575 1.19 augustss
3576 1.19 augustss if (sc->sc_dying)
3577 1.19 augustss return (USBD_IOERROR);
3578 1.19 augustss
3579 1.19 augustss #ifdef DIAGNOSTIC
3580 1.19 augustss if (xfer->rqflags & URQ_REQUEST)
3581 1.72 augustss panic("ehci_device_bulk_start: a request");
3582 1.19 augustss #endif
3583 1.19 augustss
3584 1.19 augustss len = xfer->length;
3585 1.19 augustss endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3586 1.19 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3587 1.19 augustss sqh = epipe->sqh;
3588 1.19 augustss
3589 1.19 augustss epipe->u.bulk.length = len;
3590 1.19 augustss
3591 1.123.12.1 itohy newinactive = ehci_alloc_sqtd(sc);
3592 1.123.12.1 itohy if (newinactive == NULL) {
3593 1.123.12.1 itohy DPRINTFN(-1,("ehci_device_bulk_start: no sqtd memory\n"));
3594 1.123.12.1 itohy err = USBD_NOMEM;
3595 1.123.12.1 itohy xfer->status = err;
3596 1.123.12.1 itohy usb_transfer_complete(xfer);
3597 1.123.12.1 itohy return (err);
3598 1.123.12.1 itohy }
3599 1.123.12.1 itohy newinactive->qtd.qtd_status = htole32(0);
3600 1.123.12.1 itohy newinactive->qtd.qtd_next = EHCI_NULL;
3601 1.123.12.1 itohy newinactive->qtd.qtd_altnext = EHCI_NULL;
3602 1.123.12.1 itohy err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
3603 1.123.12.1 itohy sqh->inactivesqtd, newinactive, &data, &dataend);
3604 1.25 augustss if (err) {
3605 1.123.12.1 itohy DPRINTFN(-1,("ehci_device_bulk_start: no memory\n"));
3606 1.123.12.1 itohy ehci_free_sqtd(sc, newinactive);
3607 1.25 augustss xfer->status = err;
3608 1.25 augustss usb_transfer_complete(xfer);
3609 1.19 augustss return (err);
3610 1.25 augustss }
3611 1.123.12.1 itohy dataend->nextqtd = newinactive;
3612 1.123.12.1 itohy dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive));
3613 1.123.12.1 itohy dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive));
3614 1.123.12.1 itohy sqh->inactivesqtd = newinactive;
3615 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, newinactive,
3616 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3617 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, dataend,
3618 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3619 1.19 augustss
3620 1.19 augustss #ifdef EHCI_DEBUG
3621 1.23 augustss if (ehcidebug > 5) {
3622 1.72 augustss DPRINTF(("ehci_device_bulk_start: data(1)\n"));
3623 1.23 augustss ehci_dump_sqh(sqh);
3624 1.19 augustss ehci_dump_sqtds(data);
3625 1.19 augustss }
3626 1.19 augustss #endif
3627 1.19 augustss
3628 1.19 augustss /* Set up interrupt info. */
3629 1.19 augustss exfer->sqtdstart = data;
3630 1.19 augustss exfer->sqtdend = dataend;
3631 1.19 augustss #ifdef DIAGNOSTIC
3632 1.19 augustss if (!exfer->isdone) {
3633 1.72 augustss printf("ehci_device_bulk_start: not done, ex=%p\n", exfer);
3634 1.19 augustss }
3635 1.19 augustss exfer->isdone = 0;
3636 1.19 augustss #endif
3637 1.19 augustss
3638 1.19 augustss s = splusb();
3639 1.123.12.1 itohy ehci_activate_qh(sc, sqh, data);
3640 1.19 augustss if (xfer->timeout && !sc->sc_bus.use_polling) {
3641 1.123.12.1 itohy usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
3642 1.19 augustss ehci_timeout, xfer);
3643 1.19 augustss }
3644 1.19 augustss ehci_add_intr_list(sc, exfer);
3645 1.19 augustss xfer->status = USBD_IN_PROGRESS;
3646 1.19 augustss splx(s);
3647 1.19 augustss
3648 1.19 augustss #ifdef EHCI_DEBUG
3649 1.19 augustss if (ehcidebug > 10) {
3650 1.72 augustss DPRINTF(("ehci_device_bulk_start: data(2)\n"));
3651 1.23 augustss delay(10000);
3652 1.72 augustss DPRINTF(("ehci_device_bulk_start: data(3)\n"));
3653 1.23 augustss ehci_dump_regs(sc);
3654 1.29 augustss #if 0
3655 1.29 augustss printf("async_head:\n");
3656 1.23 augustss ehci_dump_sqh(sc->sc_async_head);
3657 1.29 augustss #endif
3658 1.29 augustss printf("sqh:\n");
3659 1.23 augustss ehci_dump_sqh(sqh);
3660 1.19 augustss ehci_dump_sqtds(data);
3661 1.19 augustss }
3662 1.19 augustss #endif
3663 1.19 augustss
3664 1.19 augustss if (sc->sc_bus.use_polling)
3665 1.19 augustss ehci_waitintr(sc, xfer);
3666 1.19 augustss
3667 1.19 augustss return (USBD_IN_PROGRESS);
3668 1.19 augustss #undef exfer
3669 1.19 augustss }
3670 1.19 augustss
3671 1.19 augustss Static void
3672 1.19 augustss ehci_device_bulk_abort(usbd_xfer_handle xfer)
3673 1.19 augustss {
3674 1.19 augustss DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer));
3675 1.19 augustss ehci_abort_xfer(xfer, USBD_CANCELLED);
3676 1.19 augustss }
3677 1.19 augustss
3678 1.33 augustss /*
3679 1.19 augustss * Close a device bulk pipe.
3680 1.19 augustss */
3681 1.19 augustss Static void
3682 1.19 augustss ehci_device_bulk_close(usbd_pipe_handle pipe)
3683 1.19 augustss {
3684 1.19 augustss ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
3685 1.19 augustss
3686 1.19 augustss DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe));
3687 1.19 augustss ehci_close_pipe(pipe, sc->sc_async_head);
3688 1.19 augustss }
3689 1.19 augustss
3690 1.19 augustss void
3691 1.19 augustss ehci_device_bulk_done(usbd_xfer_handle xfer)
3692 1.19 augustss {
3693 1.19 augustss struct ehci_xfer *ex = EXFER(xfer);
3694 1.19 augustss ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
3695 1.123.12.1 itohy struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3696 1.19 augustss
3697 1.33 augustss DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n",
3698 1.19 augustss xfer, xfer->actlen));
3699 1.19 augustss
3700 1.44 augustss if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
3701 1.25 augustss ehci_del_intr_list(ex); /* remove from active list */
3702 1.123.12.1 itohy ehci_free_sqtd_chain(sc, epipe->sqh, ex->sqtdstart,
3703 1.123.12.1 itohy ex->sqtdend->nextqtd);
3704 1.25 augustss }
3705 1.19 augustss
3706 1.19 augustss DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen));
3707 1.19 augustss }
3708 1.5 augustss
3709 1.10 augustss /************************/
3710 1.10 augustss
3711 1.78 augustss Static usbd_status
3712 1.78 augustss ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival)
3713 1.78 augustss {
3714 1.78 augustss struct ehci_soft_islot *isp;
3715 1.78 augustss int islot, lev;
3716 1.78 augustss
3717 1.78 augustss /* Find a poll rate that is large enough. */
3718 1.78 augustss for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--)
3719 1.78 augustss if (EHCI_ILEV_IVAL(lev) <= ival)
3720 1.78 augustss break;
3721 1.78 augustss
3722 1.78 augustss /* Pick an interrupt slot at the right level. */
3723 1.123.12.1 itohy /* XXX could do better than picking at random. */
3724 1.123.12.1 itohy islot = EHCI_IQHIDX(lev, arc4random());
3725 1.78 augustss
3726 1.78 augustss sqh->islot = islot;
3727 1.78 augustss isp = &sc->sc_islots[islot];
3728 1.123.12.1 itohy ehci_add_qh(sc, sqh, isp->sqh);
3729 1.78 augustss
3730 1.78 augustss return (USBD_NORMAL_COMPLETION);
3731 1.78 augustss }
3732 1.78 augustss
3733 1.78 augustss Static usbd_status
3734 1.78 augustss ehci_device_intr_transfer(usbd_xfer_handle xfer)
3735 1.78 augustss {
3736 1.123.12.1 itohy ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
3737 1.78 augustss usbd_status err;
3738 1.78 augustss
3739 1.78 augustss /* Insert last in queue. */
3740 1.123.12.1 itohy err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag,
3741 1.123.12.1 itohy &EXFER(xfer)->dmabuf);
3742 1.78 augustss if (err)
3743 1.78 augustss return (err);
3744 1.78 augustss
3745 1.78 augustss /*
3746 1.78 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
3747 1.78 augustss * so start it first.
3748 1.78 augustss */
3749 1.78 augustss return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3750 1.78 augustss }
3751 1.78 augustss
3752 1.78 augustss Static usbd_status
3753 1.78 augustss ehci_device_intr_start(usbd_xfer_handle xfer)
3754 1.78 augustss {
3755 1.78 augustss #define exfer EXFER(xfer)
3756 1.78 augustss struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3757 1.78 augustss usbd_device_handle dev = xfer->pipe->device;
3758 1.78 augustss ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
3759 1.123.12.1 itohy ehci_soft_qtd_t *data, *dataend, *newinactive;
3760 1.78 augustss ehci_soft_qh_t *sqh;
3761 1.78 augustss usbd_status err;
3762 1.78 augustss int len, isread, endpt;
3763 1.78 augustss int s;
3764 1.78 augustss
3765 1.78 augustss DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n",
3766 1.78 augustss xfer, xfer->length, xfer->flags));
3767 1.78 augustss
3768 1.78 augustss if (sc->sc_dying)
3769 1.78 augustss return (USBD_IOERROR);
3770 1.78 augustss
3771 1.78 augustss #ifdef DIAGNOSTIC
3772 1.78 augustss if (xfer->rqflags & URQ_REQUEST)
3773 1.78 augustss panic("ehci_device_intr_start: a request");
3774 1.78 augustss #endif
3775 1.78 augustss
3776 1.78 augustss len = xfer->length;
3777 1.78 augustss endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3778 1.78 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3779 1.78 augustss sqh = epipe->sqh;
3780 1.78 augustss
3781 1.78 augustss epipe->u.intr.length = len;
3782 1.78 augustss
3783 1.123.12.1 itohy newinactive = ehci_alloc_sqtd(sc);
3784 1.123.12.1 itohy if (newinactive == NULL) {
3785 1.123.12.1 itohy DPRINTFN(-1,("ehci_device_intr_start: no sqtd memory\n"));
3786 1.123.12.1 itohy err = USBD_NOMEM;
3787 1.123.12.1 itohy xfer->status = err;
3788 1.123.12.1 itohy usb_transfer_complete(xfer);
3789 1.123.12.1 itohy return (err);
3790 1.123.12.1 itohy }
3791 1.123.12.1 itohy newinactive->qtd.qtd_status = htole32(0);
3792 1.123.12.1 itohy newinactive->qtd.qtd_next = EHCI_NULL;
3793 1.123.12.1 itohy newinactive->qtd.qtd_altnext = EHCI_NULL;
3794 1.123.12.1 itohy err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
3795 1.123.12.1 itohy sqh->inactivesqtd, newinactive, &data, &dataend);
3796 1.78 augustss if (err) {
3797 1.78 augustss DPRINTFN(-1, ("ehci_device_intr_start: no memory\n"));
3798 1.78 augustss xfer->status = err;
3799 1.78 augustss usb_transfer_complete(xfer);
3800 1.78 augustss return (err);
3801 1.78 augustss }
3802 1.123.12.1 itohy dataend->nextqtd = newinactive;
3803 1.123.12.1 itohy dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive));
3804 1.123.12.1 itohy dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive));
3805 1.123.12.1 itohy sqh->inactivesqtd = newinactive;
3806 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, newinactive,
3807 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3808 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, dataend,
3809 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3810 1.78 augustss
3811 1.78 augustss #ifdef EHCI_DEBUG
3812 1.78 augustss if (ehcidebug > 5) {
3813 1.78 augustss DPRINTF(("ehci_device_intr_start: data(1)\n"));
3814 1.78 augustss ehci_dump_sqh(sqh);
3815 1.78 augustss ehci_dump_sqtds(data);
3816 1.78 augustss }
3817 1.78 augustss #endif
3818 1.78 augustss
3819 1.78 augustss /* Set up interrupt info. */
3820 1.78 augustss exfer->sqtdstart = data;
3821 1.78 augustss exfer->sqtdend = dataend;
3822 1.78 augustss #ifdef DIAGNOSTIC
3823 1.78 augustss if (!exfer->isdone) {
3824 1.78 augustss printf("ehci_device_intr_start: not done, ex=%p\n", exfer);
3825 1.78 augustss }
3826 1.78 augustss exfer->isdone = 0;
3827 1.78 augustss #endif
3828 1.78 augustss
3829 1.78 augustss s = splusb();
3830 1.123.12.1 itohy ehci_activate_qh(sc, sqh, data);
3831 1.78 augustss if (xfer->timeout && !sc->sc_bus.use_polling) {
3832 1.123.12.1 itohy usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
3833 1.78 augustss ehci_timeout, xfer);
3834 1.78 augustss }
3835 1.78 augustss ehci_add_intr_list(sc, exfer);
3836 1.78 augustss xfer->status = USBD_IN_PROGRESS;
3837 1.78 augustss splx(s);
3838 1.78 augustss
3839 1.78 augustss #ifdef EHCI_DEBUG
3840 1.78 augustss if (ehcidebug > 10) {
3841 1.78 augustss DPRINTF(("ehci_device_intr_start: data(2)\n"));
3842 1.78 augustss delay(10000);
3843 1.78 augustss DPRINTF(("ehci_device_intr_start: data(3)\n"));
3844 1.78 augustss ehci_dump_regs(sc);
3845 1.78 augustss printf("sqh:\n");
3846 1.78 augustss ehci_dump_sqh(sqh);
3847 1.78 augustss ehci_dump_sqtds(data);
3848 1.78 augustss }
3849 1.78 augustss #endif
3850 1.78 augustss
3851 1.78 augustss if (sc->sc_bus.use_polling)
3852 1.78 augustss ehci_waitintr(sc, xfer);
3853 1.78 augustss
3854 1.78 augustss return (USBD_IN_PROGRESS);
3855 1.78 augustss #undef exfer
3856 1.78 augustss }
3857 1.78 augustss
3858 1.78 augustss Static void
3859 1.78 augustss ehci_device_intr_abort(usbd_xfer_handle xfer)
3860 1.78 augustss {
3861 1.78 augustss DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer));
3862 1.78 augustss if (xfer->pipe->intrxfer == xfer) {
3863 1.123.12.1 itohy DPRINTFN(1, ("ehci_device_intr_abort: remove\n"));
3864 1.78 augustss xfer->pipe->intrxfer = NULL;
3865 1.78 augustss }
3866 1.78 augustss ehci_abort_xfer(xfer, USBD_CANCELLED);
3867 1.78 augustss }
3868 1.78 augustss
3869 1.78 augustss Static void
3870 1.78 augustss ehci_device_intr_close(usbd_pipe_handle pipe)
3871 1.78 augustss {
3872 1.78 augustss ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
3873 1.78 augustss struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
3874 1.78 augustss struct ehci_soft_islot *isp;
3875 1.78 augustss
3876 1.78 augustss isp = &sc->sc_islots[epipe->sqh->islot];
3877 1.78 augustss ehci_close_pipe(pipe, isp->sqh);
3878 1.78 augustss }
3879 1.78 augustss
3880 1.78 augustss Static void
3881 1.78 augustss ehci_device_intr_done(usbd_xfer_handle xfer)
3882 1.78 augustss {
3883 1.78 augustss #define exfer EXFER(xfer)
3884 1.78 augustss struct ehci_xfer *ex = EXFER(xfer);
3885 1.78 augustss ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
3886 1.78 augustss struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3887 1.123.12.1 itohy ehci_soft_qtd_t *data, *dataend, *newinactive;
3888 1.78 augustss ehci_soft_qh_t *sqh;
3889 1.78 augustss usbd_status err;
3890 1.78 augustss int len, isread, endpt, s;
3891 1.78 augustss
3892 1.78 augustss DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n",
3893 1.78 augustss xfer, xfer->actlen));
3894 1.78 augustss
3895 1.123.12.1 itohy sqh = epipe->sqh;
3896 1.78 augustss if (xfer->pipe->repeat) {
3897 1.123.12.1 itohy ehci_free_sqtd_chain(sc, sqh, ex->sqtdstart,
3898 1.123.12.1 itohy ex->sqtdend->nextqtd);
3899 1.78 augustss
3900 1.78 augustss len = epipe->u.intr.length;
3901 1.78 augustss xfer->length = len;
3902 1.78 augustss endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3903 1.78 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3904 1.78 augustss
3905 1.123.12.1 itohy newinactive = ehci_alloc_sqtd(sc);
3906 1.123.12.1 itohy if (newinactive == NULL) {
3907 1.123.12.1 itohy DPRINTFN(-1,
3908 1.123.12.1 itohy ("ehci_device_intr_done: no sqtd memory\n"));
3909 1.123.12.1 itohy err = USBD_NOMEM;
3910 1.123.12.1 itohy xfer->status = err;
3911 1.123.12.1 itohy return;
3912 1.123.12.1 itohy }
3913 1.123.12.1 itohy newinactive->qtd.qtd_status = htole32(0);
3914 1.123.12.1 itohy newinactive->qtd.qtd_next = EHCI_NULL;
3915 1.123.12.1 itohy newinactive->qtd.qtd_altnext = EHCI_NULL;
3916 1.78 augustss err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
3917 1.123.12.1 itohy sqh->inactivesqtd, newinactive, &data, &dataend);
3918 1.78 augustss if (err) {
3919 1.78 augustss DPRINTFN(-1, ("ehci_device_intr_done: no memory\n"));
3920 1.78 augustss xfer->status = err;
3921 1.78 augustss return;
3922 1.78 augustss }
3923 1.123.12.1 itohy dataend->nextqtd = newinactive;
3924 1.123.12.1 itohy dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive));
3925 1.123.12.1 itohy dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive));
3926 1.123.12.1 itohy sqh->inactivesqtd = newinactive;
3927 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, newinactive,
3928 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3929 1.123.12.1 itohy EHCI_SQTD_SYNC(sc, dataend,
3930 1.123.12.1 itohy BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3931 1.78 augustss
3932 1.78 augustss /* Set up interrupt info. */
3933 1.78 augustss exfer->sqtdstart = data;
3934 1.78 augustss exfer->sqtdend = dataend;
3935 1.78 augustss #ifdef DIAGNOSTIC
3936 1.78 augustss if (!exfer->isdone) {
3937 1.78 augustss printf("ehci_device_intr_done: not done, ex=%p\n",
3938 1.78 augustss exfer);
3939 1.78 augustss }
3940 1.78 augustss exfer->isdone = 0;
3941 1.78 augustss #endif
3942 1.78 augustss
3943 1.78 augustss s = splusb();
3944 1.123.12.1 itohy ehci_activate_qh(sc, sqh, data);
3945 1.78 augustss if (xfer->timeout && !sc->sc_bus.use_polling) {
3946 1.78 augustss usb_callout(xfer->timeout_handle,
3947 1.123.12.1 itohy MS_TO_TICKS(xfer->timeout), ehci_timeout, xfer);
3948 1.78 augustss }
3949 1.78 augustss splx(s);
3950 1.78 augustss
3951 1.78 augustss xfer->status = USBD_IN_PROGRESS;
3952 1.78 augustss } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
3953 1.78 augustss ehci_del_intr_list(ex); /* remove from active list */
3954 1.123.12.1 itohy ehci_free_sqtd_chain(sc, sqh, ex->sqtdstart,
3955 1.123.12.1 itohy ex->sqtdend->nextqtd);
3956 1.78 augustss }
3957 1.78 augustss #undef exfer
3958 1.78 augustss }
3959 1.10 augustss
3960 1.10 augustss /************************/
3961 1.5 augustss
3962 1.113 christos Static usbd_status
3963 1.115 christos ehci_device_isoc_transfer(usbd_xfer_handle xfer)
3964 1.113 christos {
3965 1.113 christos return USBD_IOERROR;
3966 1.113 christos }
3967 1.113 christos Static usbd_status
3968 1.115 christos ehci_device_isoc_start(usbd_xfer_handle xfer)
3969 1.113 christos {
3970 1.113 christos return USBD_IOERROR;
3971 1.113 christos }
3972 1.113 christos Static void
3973 1.115 christos ehci_device_isoc_abort(usbd_xfer_handle xfer)
3974 1.113 christos {
3975 1.113 christos }
3976 1.113 christos Static void
3977 1.115 christos ehci_device_isoc_close(usbd_pipe_handle pipe)
3978 1.113 christos {
3979 1.113 christos }
3980 1.113 christos Static void
3981 1.115 christos ehci_device_isoc_done(usbd_xfer_handle xfer)
3982 1.113 christos {
3983 1.113 christos }
3984