ehci.c revision 1.2.4.10 1 1.2.4.6 nathanw /* $NetBSD: ehci.c,v 1.2.4.10 2002/12/11 06:38:49 thorpej Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.2.4.2 nathanw * TODO
5 1.2.4.2 nathanw * hold off explorations by companion controllers until ehci has started.
6 1.2.4.2 nathanw */
7 1.2.4.2 nathanw
8 1.2.4.2 nathanw /*
9 1.2.4.2 nathanw * Copyright (c) 2001 The NetBSD Foundation, Inc.
10 1.1 augustss * All rights reserved.
11 1.1 augustss *
12 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
13 1.1 augustss * by Lennart Augustsson (lennart (at) augustsson.net).
14 1.1 augustss *
15 1.1 augustss * Redistribution and use in source and binary forms, with or without
16 1.1 augustss * modification, are permitted provided that the following conditions
17 1.1 augustss * are met:
18 1.1 augustss * 1. Redistributions of source code must retain the above copyright
19 1.1 augustss * notice, this list of conditions and the following disclaimer.
20 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
21 1.1 augustss * notice, this list of conditions and the following disclaimer in the
22 1.1 augustss * documentation and/or other materials provided with the distribution.
23 1.1 augustss * 3. All advertising materials mentioning features or use of this software
24 1.1 augustss * must display the following acknowledgement:
25 1.1 augustss * This product includes software developed by the NetBSD
26 1.1 augustss * Foundation, Inc. and its contributors.
27 1.1 augustss * 4. Neither the name of The NetBSD Foundation nor the names of its
28 1.1 augustss * contributors may be used to endorse or promote products derived
29 1.1 augustss * from this software without specific prior written permission.
30 1.1 augustss *
31 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
32 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
33 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
34 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
35 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
36 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
37 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
38 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
39 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
40 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
42 1.1 augustss */
43 1.1 augustss
44 1.1 augustss /*
45 1.2.4.1 nathanw * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
46 1.1 augustss *
47 1.2.4.7 nathanw * The EHCI 1.0 spec can be found at
48 1.2.4.7 nathanw * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
49 1.2.4.2 nathanw * and the USB 2.0 spec at
50 1.2.4.2 nathanw * http://www.usb.org/developers/data/usb_20.zip
51 1.1 augustss *
52 1.1 augustss */
53 1.1 augustss
54 1.2.4.1 nathanw #include <sys/cdefs.h>
55 1.2.4.6 nathanw __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.2.4.10 2002/12/11 06:38:49 thorpej Exp $");
56 1.2.4.1 nathanw
57 1.1 augustss #include <sys/param.h>
58 1.1 augustss #include <sys/systm.h>
59 1.1 augustss #include <sys/kernel.h>
60 1.1 augustss #include <sys/malloc.h>
61 1.1 augustss #include <sys/device.h>
62 1.1 augustss #include <sys/select.h>
63 1.1 augustss #include <sys/proc.h>
64 1.1 augustss #include <sys/queue.h>
65 1.1 augustss
66 1.1 augustss #include <machine/bus.h>
67 1.1 augustss #include <machine/endian.h>
68 1.1 augustss
69 1.1 augustss #include <dev/usb/usb.h>
70 1.1 augustss #include <dev/usb/usbdi.h>
71 1.1 augustss #include <dev/usb/usbdivar.h>
72 1.1 augustss #include <dev/usb/usb_mem.h>
73 1.1 augustss #include <dev/usb/usb_quirks.h>
74 1.1 augustss
75 1.1 augustss #include <dev/usb/ehcireg.h>
76 1.1 augustss #include <dev/usb/ehcivar.h>
77 1.1 augustss
78 1.1 augustss #ifdef EHCI_DEBUG
79 1.1 augustss #define DPRINTF(x) if (ehcidebug) printf x
80 1.1 augustss #define DPRINTFN(n,x) if (ehcidebug>(n)) printf x
81 1.2.4.2 nathanw int ehcidebug = 0;
82 1.2.4.2 nathanw #ifndef __NetBSD__
83 1.1 augustss #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f))
84 1.2.4.2 nathanw #endif
85 1.1 augustss #else
86 1.1 augustss #define DPRINTF(x)
87 1.1 augustss #define DPRINTFN(n,x)
88 1.1 augustss #endif
89 1.1 augustss
90 1.2.4.2 nathanw struct ehci_pipe {
91 1.2.4.2 nathanw struct usbd_pipe pipe;
92 1.2.4.2 nathanw ehci_soft_qh_t *sqh;
93 1.2.4.2 nathanw union {
94 1.2.4.2 nathanw ehci_soft_qtd_t *qtd;
95 1.2.4.2 nathanw /* ehci_soft_itd_t *itd; */
96 1.2.4.2 nathanw } tail;
97 1.2.4.2 nathanw union {
98 1.2.4.2 nathanw /* Control pipe */
99 1.2.4.2 nathanw struct {
100 1.2.4.2 nathanw usb_dma_t reqdma;
101 1.2.4.2 nathanw u_int length;
102 1.2.4.2 nathanw /*ehci_soft_qtd_t *setup, *data, *stat;*/
103 1.2.4.2 nathanw } ctl;
104 1.2.4.2 nathanw /* Interrupt pipe */
105 1.2.4.2 nathanw /* XXX */
106 1.2.4.2 nathanw /* Bulk pipe */
107 1.2.4.2 nathanw struct {
108 1.2.4.2 nathanw u_int length;
109 1.2.4.2 nathanw } bulk;
110 1.2.4.2 nathanw /* Iso pipe */
111 1.2.4.2 nathanw /* XXX */
112 1.2.4.2 nathanw } u;
113 1.2.4.2 nathanw };
114 1.2.4.2 nathanw
115 1.2.4.2 nathanw Static void ehci_shutdown(void *);
116 1.2.4.2 nathanw Static void ehci_power(int, void *);
117 1.2.4.2 nathanw
118 1.2.4.2 nathanw Static usbd_status ehci_open(usbd_pipe_handle);
119 1.2.4.2 nathanw Static void ehci_poll(struct usbd_bus *);
120 1.2.4.2 nathanw Static void ehci_softintr(void *);
121 1.2.4.2 nathanw Static int ehci_intr1(ehci_softc_t *);
122 1.2.4.2 nathanw Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle);
123 1.2.4.2 nathanw Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *);
124 1.2.4.2 nathanw Static void ehci_idone(struct ehci_xfer *);
125 1.2.4.2 nathanw Static void ehci_timeout(void *);
126 1.2.4.2 nathanw Static void ehci_timeout_task(void *);
127 1.2.4.2 nathanw
128 1.2.4.2 nathanw Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t);
129 1.2.4.2 nathanw Static void ehci_freem(struct usbd_bus *, usb_dma_t *);
130 1.2.4.2 nathanw
131 1.2.4.2 nathanw Static usbd_xfer_handle ehci_allocx(struct usbd_bus *);
132 1.2.4.2 nathanw Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle);
133 1.2.4.2 nathanw
134 1.2.4.2 nathanw Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle);
135 1.2.4.2 nathanw Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle);
136 1.2.4.2 nathanw Static void ehci_root_ctrl_abort(usbd_xfer_handle);
137 1.2.4.2 nathanw Static void ehci_root_ctrl_close(usbd_pipe_handle);
138 1.2.4.2 nathanw Static void ehci_root_ctrl_done(usbd_xfer_handle);
139 1.2.4.2 nathanw
140 1.2.4.2 nathanw Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle);
141 1.2.4.2 nathanw Static usbd_status ehci_root_intr_start(usbd_xfer_handle);
142 1.2.4.2 nathanw Static void ehci_root_intr_abort(usbd_xfer_handle);
143 1.2.4.2 nathanw Static void ehci_root_intr_close(usbd_pipe_handle);
144 1.2.4.2 nathanw Static void ehci_root_intr_done(usbd_xfer_handle);
145 1.2.4.2 nathanw
146 1.2.4.2 nathanw Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle);
147 1.2.4.2 nathanw Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle);
148 1.2.4.2 nathanw Static void ehci_device_ctrl_abort(usbd_xfer_handle);
149 1.2.4.2 nathanw Static void ehci_device_ctrl_close(usbd_pipe_handle);
150 1.2.4.2 nathanw Static void ehci_device_ctrl_done(usbd_xfer_handle);
151 1.2.4.2 nathanw
152 1.2.4.2 nathanw Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle);
153 1.2.4.2 nathanw Static usbd_status ehci_device_bulk_start(usbd_xfer_handle);
154 1.2.4.2 nathanw Static void ehci_device_bulk_abort(usbd_xfer_handle);
155 1.2.4.2 nathanw Static void ehci_device_bulk_close(usbd_pipe_handle);
156 1.2.4.2 nathanw Static void ehci_device_bulk_done(usbd_xfer_handle);
157 1.2.4.2 nathanw
158 1.2.4.2 nathanw Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle);
159 1.2.4.2 nathanw Static usbd_status ehci_device_intr_start(usbd_xfer_handle);
160 1.2.4.2 nathanw Static void ehci_device_intr_abort(usbd_xfer_handle);
161 1.2.4.2 nathanw Static void ehci_device_intr_close(usbd_pipe_handle);
162 1.2.4.2 nathanw Static void ehci_device_intr_done(usbd_xfer_handle);
163 1.2.4.2 nathanw
164 1.2.4.2 nathanw Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle);
165 1.2.4.2 nathanw Static usbd_status ehci_device_isoc_start(usbd_xfer_handle);
166 1.2.4.2 nathanw Static void ehci_device_isoc_abort(usbd_xfer_handle);
167 1.2.4.2 nathanw Static void ehci_device_isoc_close(usbd_pipe_handle);
168 1.2.4.2 nathanw Static void ehci_device_isoc_done(usbd_xfer_handle);
169 1.2.4.2 nathanw
170 1.2.4.2 nathanw Static void ehci_device_clear_toggle(usbd_pipe_handle pipe);
171 1.2.4.2 nathanw Static void ehci_noop(usbd_pipe_handle pipe);
172 1.2.4.2 nathanw
173 1.2.4.2 nathanw Static int ehci_str(usb_string_descriptor_t *, int, char *);
174 1.2.4.2 nathanw Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle);
175 1.2.4.2 nathanw Static void ehci_pcd_able(ehci_softc_t *, int);
176 1.2.4.2 nathanw Static void ehci_pcd_enable(void *);
177 1.2.4.2 nathanw Static void ehci_disown(ehci_softc_t *, int, int);
178 1.2.4.2 nathanw
179 1.2.4.2 nathanw Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *);
180 1.2.4.2 nathanw Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
181 1.2.4.2 nathanw
182 1.2.4.2 nathanw Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
183 1.2.4.2 nathanw Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
184 1.2.4.2 nathanw Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *,
185 1.2.4.2 nathanw ehci_softc_t *, int, int, usbd_xfer_handle,
186 1.2.4.2 nathanw ehci_soft_qtd_t **, ehci_soft_qtd_t **);
187 1.2.4.2 nathanw Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *,
188 1.2.4.2 nathanw ehci_soft_qtd_t *);
189 1.2.4.2 nathanw
190 1.2.4.2 nathanw Static usbd_status ehci_device_request(usbd_xfer_handle xfer);
191 1.2.4.2 nathanw
192 1.2.4.2 nathanw Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *);
193 1.2.4.2 nathanw Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
194 1.2.4.2 nathanw ehci_soft_qh_t *);
195 1.2.4.2 nathanw Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *);
196 1.2.4.2 nathanw Static void ehci_sync_hc(ehci_softc_t *);
197 1.2.4.2 nathanw
198 1.2.4.2 nathanw Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *);
199 1.2.4.2 nathanw Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status);
200 1.2.4.2 nathanw
201 1.2.4.2 nathanw #ifdef EHCI_DEBUG
202 1.2.4.2 nathanw Static void ehci_dump_regs(ehci_softc_t *);
203 1.2.4.10 thorpej Static void ehci_dump(void);
204 1.2.4.2 nathanw Static ehci_softc_t *theehci;
205 1.2.4.2 nathanw Static void ehci_dump_link(ehci_link_t, int);
206 1.2.4.2 nathanw Static void ehci_dump_sqtds(ehci_soft_qtd_t *);
207 1.2.4.2 nathanw Static void ehci_dump_sqtd(ehci_soft_qtd_t *);
208 1.2.4.2 nathanw Static void ehci_dump_qtd(ehci_qtd_t *);
209 1.2.4.2 nathanw Static void ehci_dump_sqh(ehci_soft_qh_t *);
210 1.2.4.9 nathanw #ifdef DIAGNOSTIC
211 1.2.4.2 nathanw Static void ehci_dump_exfer(struct ehci_xfer *);
212 1.2.4.2 nathanw #endif
213 1.2.4.9 nathanw #endif
214 1.2.4.2 nathanw
215 1.2.4.2 nathanw #define MS_TO_TICKS(ms) ((ms) * hz / 1000)
216 1.2.4.2 nathanw
217 1.2.4.2 nathanw #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
218 1.2.4.2 nathanw
219 1.2.4.2 nathanw #define EHCI_INTR_ENDPT 1
220 1.2.4.2 nathanw
221 1.2.4.2 nathanw #define ehci_add_intr_list(sc, ex) \
222 1.2.4.2 nathanw LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext);
223 1.2.4.2 nathanw #define ehci_del_intr_list(ex) \
224 1.2.4.2 nathanw LIST_REMOVE((ex), inext)
225 1.2.4.2 nathanw
226 1.2.4.2 nathanw Static struct usbd_bus_methods ehci_bus_methods = {
227 1.2.4.2 nathanw ehci_open,
228 1.2.4.2 nathanw ehci_softintr,
229 1.2.4.2 nathanw ehci_poll,
230 1.2.4.2 nathanw ehci_allocm,
231 1.2.4.2 nathanw ehci_freem,
232 1.2.4.2 nathanw ehci_allocx,
233 1.2.4.2 nathanw ehci_freex,
234 1.2.4.2 nathanw };
235 1.2.4.2 nathanw
236 1.2.4.6 nathanw Static struct usbd_pipe_methods ehci_root_ctrl_methods = {
237 1.2.4.2 nathanw ehci_root_ctrl_transfer,
238 1.2.4.2 nathanw ehci_root_ctrl_start,
239 1.2.4.2 nathanw ehci_root_ctrl_abort,
240 1.2.4.2 nathanw ehci_root_ctrl_close,
241 1.2.4.2 nathanw ehci_noop,
242 1.2.4.2 nathanw ehci_root_ctrl_done,
243 1.2.4.2 nathanw };
244 1.2.4.2 nathanw
245 1.2.4.6 nathanw Static struct usbd_pipe_methods ehci_root_intr_methods = {
246 1.2.4.2 nathanw ehci_root_intr_transfer,
247 1.2.4.2 nathanw ehci_root_intr_start,
248 1.2.4.2 nathanw ehci_root_intr_abort,
249 1.2.4.2 nathanw ehci_root_intr_close,
250 1.2.4.2 nathanw ehci_noop,
251 1.2.4.2 nathanw ehci_root_intr_done,
252 1.2.4.2 nathanw };
253 1.2.4.2 nathanw
254 1.2.4.6 nathanw Static struct usbd_pipe_methods ehci_device_ctrl_methods = {
255 1.2.4.2 nathanw ehci_device_ctrl_transfer,
256 1.2.4.2 nathanw ehci_device_ctrl_start,
257 1.2.4.2 nathanw ehci_device_ctrl_abort,
258 1.2.4.2 nathanw ehci_device_ctrl_close,
259 1.2.4.2 nathanw ehci_noop,
260 1.2.4.2 nathanw ehci_device_ctrl_done,
261 1.2.4.2 nathanw };
262 1.2.4.2 nathanw
263 1.2.4.6 nathanw Static struct usbd_pipe_methods ehci_device_intr_methods = {
264 1.2.4.2 nathanw ehci_device_intr_transfer,
265 1.2.4.2 nathanw ehci_device_intr_start,
266 1.2.4.2 nathanw ehci_device_intr_abort,
267 1.2.4.2 nathanw ehci_device_intr_close,
268 1.2.4.2 nathanw ehci_device_clear_toggle,
269 1.2.4.2 nathanw ehci_device_intr_done,
270 1.2.4.2 nathanw };
271 1.2.4.2 nathanw
272 1.2.4.6 nathanw Static struct usbd_pipe_methods ehci_device_bulk_methods = {
273 1.2.4.2 nathanw ehci_device_bulk_transfer,
274 1.2.4.2 nathanw ehci_device_bulk_start,
275 1.2.4.2 nathanw ehci_device_bulk_abort,
276 1.2.4.2 nathanw ehci_device_bulk_close,
277 1.2.4.2 nathanw ehci_device_clear_toggle,
278 1.2.4.2 nathanw ehci_device_bulk_done,
279 1.2.4.2 nathanw };
280 1.2.4.2 nathanw
281 1.2.4.2 nathanw Static struct usbd_pipe_methods ehci_device_isoc_methods = {
282 1.2.4.2 nathanw ehci_device_isoc_transfer,
283 1.2.4.2 nathanw ehci_device_isoc_start,
284 1.2.4.2 nathanw ehci_device_isoc_abort,
285 1.2.4.2 nathanw ehci_device_isoc_close,
286 1.2.4.2 nathanw ehci_noop,
287 1.2.4.2 nathanw ehci_device_isoc_done,
288 1.2.4.2 nathanw };
289 1.2.4.2 nathanw
290 1.1 augustss usbd_status
291 1.1 augustss ehci_init(ehci_softc_t *sc)
292 1.1 augustss {
293 1.2.4.1 nathanw u_int32_t version, sparams, cparams, hcr;
294 1.2.4.1 nathanw u_int i;
295 1.2.4.1 nathanw usbd_status err;
296 1.2.4.2 nathanw ehci_soft_qh_t *sqh;
297 1.2.4.1 nathanw
298 1.2.4.1 nathanw DPRINTF(("ehci_init: start\n"));
299 1.2.4.2 nathanw #ifdef EHCI_DEBUG
300 1.2.4.2 nathanw theehci = sc;
301 1.2.4.2 nathanw #endif
302 1.2.4.1 nathanw
303 1.2.4.1 nathanw sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
304 1.2.4.1 nathanw
305 1.2.4.1 nathanw version = EREAD2(sc, EHCI_HCIVERSION);
306 1.2.4.1 nathanw printf("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev),
307 1.2.4.1 nathanw version >> 8, version & 0xff);
308 1.2.4.1 nathanw
309 1.2.4.1 nathanw sparams = EREAD4(sc, EHCI_HCSPARAMS);
310 1.2.4.1 nathanw DPRINTF(("ehci_init: sparams=0x%x\n", sparams));
311 1.2.4.2 nathanw sc->sc_npcomp = EHCI_HCS_N_PCC(sparams);
312 1.2.4.1 nathanw if (EHCI_HCS_N_CC(sparams) != sc->sc_ncomp) {
313 1.2.4.1 nathanw printf("%s: wrong number of companions (%d != %d)\n",
314 1.2.4.1 nathanw USBDEVNAME(sc->sc_bus.bdev),
315 1.2.4.1 nathanw EHCI_HCS_N_CC(sparams), sc->sc_ncomp);
316 1.2.4.1 nathanw return (USBD_IOERROR);
317 1.2.4.1 nathanw }
318 1.2.4.1 nathanw if (sc->sc_ncomp > 0) {
319 1.2.4.1 nathanw printf("%s: companion controller%s, %d port%s each:",
320 1.2.4.1 nathanw USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "",
321 1.2.4.1 nathanw EHCI_HCS_N_PCC(sparams),
322 1.2.4.1 nathanw EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "");
323 1.2.4.1 nathanw for (i = 0; i < sc->sc_ncomp; i++)
324 1.2.4.1 nathanw printf(" %s", USBDEVNAME(sc->sc_comps[i]->bdev));
325 1.2.4.1 nathanw printf("\n");
326 1.2.4.1 nathanw }
327 1.2.4.2 nathanw sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
328 1.2.4.1 nathanw cparams = EREAD4(sc, EHCI_HCCPARAMS);
329 1.2.4.1 nathanw DPRINTF(("ehci_init: cparams=0x%x\n", cparams));
330 1.2.4.6 nathanw
331 1.2.4.7 nathanw if (EHCI_HCC_64BIT(cparams)) {
332 1.2.4.7 nathanw /* MUST clear segment register if 64 bit capable. */
333 1.2.4.7 nathanw EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
334 1.2.4.7 nathanw }
335 1.2.4.7 nathanw
336 1.2.4.1 nathanw sc->sc_bus.usbrev = USBREV_2_0;
337 1.2.4.1 nathanw
338 1.2.4.1 nathanw /* Reset the controller */
339 1.2.4.1 nathanw DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev)));
340 1.2.4.1 nathanw EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
341 1.2.4.1 nathanw usb_delay_ms(&sc->sc_bus, 1);
342 1.2.4.1 nathanw EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
343 1.2.4.1 nathanw for (i = 0; i < 100; i++) {
344 1.2.4.7 nathanw usb_delay_ms(&sc->sc_bus, 1);
345 1.2.4.1 nathanw hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
346 1.2.4.1 nathanw if (!hcr)
347 1.2.4.1 nathanw break;
348 1.2.4.1 nathanw }
349 1.2.4.1 nathanw if (hcr) {
350 1.2.4.1 nathanw printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev));
351 1.2.4.1 nathanw return (USBD_IOERROR);
352 1.2.4.1 nathanw }
353 1.2.4.1 nathanw
354 1.2.4.1 nathanw /* frame list size at default, read back what we got and use that */
355 1.2.4.1 nathanw switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
356 1.2.4.1 nathanw case 0: sc->sc_flsize = 1024*4; break;
357 1.2.4.1 nathanw case 1: sc->sc_flsize = 512*4; break;
358 1.2.4.1 nathanw case 2: sc->sc_flsize = 256*4; break;
359 1.2.4.1 nathanw case 3: return (USBD_IOERROR);
360 1.2.4.1 nathanw }
361 1.2.4.1 nathanw err = usb_allocmem(&sc->sc_bus, sc->sc_flsize,
362 1.2.4.1 nathanw EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
363 1.2.4.1 nathanw if (err)
364 1.2.4.1 nathanw return (err);
365 1.2.4.1 nathanw DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize));
366 1.2.4.1 nathanw
367 1.2.4.2 nathanw /* Set up the bus struct. */
368 1.2.4.2 nathanw sc->sc_bus.methods = &ehci_bus_methods;
369 1.2.4.2 nathanw sc->sc_bus.pipe_size = sizeof(struct ehci_pipe);
370 1.2.4.2 nathanw
371 1.2.4.2 nathanw sc->sc_powerhook = powerhook_establish(ehci_power, sc);
372 1.2.4.2 nathanw sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc);
373 1.2.4.2 nathanw
374 1.2.4.2 nathanw sc->sc_eintrs = EHCI_NORMAL_INTRS;
375 1.2.4.2 nathanw
376 1.2.4.2 nathanw /* Allocate dummy QH that starts the async list. */
377 1.2.4.2 nathanw sqh = ehci_alloc_sqh(sc);
378 1.2.4.2 nathanw if (sqh == NULL) {
379 1.2.4.2 nathanw err = USBD_NOMEM;
380 1.2.4.2 nathanw goto bad1;
381 1.2.4.2 nathanw }
382 1.2.4.2 nathanw /* Fill the QH */
383 1.2.4.2 nathanw sqh->qh.qh_endp =
384 1.2.4.2 nathanw htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
385 1.2.4.2 nathanw sqh->qh.qh_link =
386 1.2.4.2 nathanw htole32(sqh->physaddr | EHCI_LINK_QH);
387 1.2.4.2 nathanw sqh->qh.qh_curqtd = EHCI_NULL;
388 1.2.4.2 nathanw sqh->next = NULL;
389 1.2.4.2 nathanw /* Fill the overlay qTD */
390 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
391 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
392 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
393 1.2.4.2 nathanw sqh->sqtd = NULL;
394 1.2.4.2 nathanw #ifdef EHCI_DEBUG
395 1.2.4.2 nathanw if (ehcidebug) {
396 1.2.4.2 nathanw ehci_dump_sqh(sqh);
397 1.2.4.2 nathanw }
398 1.2.4.2 nathanw #endif
399 1.2.4.2 nathanw
400 1.2.4.2 nathanw /* Point to async list */
401 1.2.4.2 nathanw sc->sc_async_head = sqh;
402 1.2.4.2 nathanw EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
403 1.2.4.2 nathanw
404 1.2.4.2 nathanw usb_callout_init(sc->sc_tmo_pcd);
405 1.2.4.2 nathanw
406 1.2.4.2 nathanw lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0);
407 1.2.4.2 nathanw
408 1.2.4.2 nathanw /* Enable interrupts */
409 1.2.4.2 nathanw EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
410 1.2.4.2 nathanw
411 1.2.4.2 nathanw /* Turn on controller */
412 1.2.4.2 nathanw EOWRITE4(sc, EHCI_USBCMD,
413 1.2.4.2 nathanw EHCI_CMD_ITC_8 | /* 8 microframes */
414 1.2.4.2 nathanw (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
415 1.2.4.2 nathanw EHCI_CMD_ASE |
416 1.2.4.2 nathanw /* EHCI_CMD_PSE | */
417 1.2.4.2 nathanw EHCI_CMD_RS);
418 1.2.4.2 nathanw
419 1.2.4.2 nathanw /* Take over port ownership */
420 1.2.4.2 nathanw EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
421 1.2.4.2 nathanw
422 1.2.4.2 nathanw for (i = 0; i < 100; i++) {
423 1.2.4.7 nathanw usb_delay_ms(&sc->sc_bus, 1);
424 1.2.4.2 nathanw hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
425 1.2.4.2 nathanw if (!hcr)
426 1.2.4.2 nathanw break;
427 1.2.4.2 nathanw }
428 1.2.4.2 nathanw if (hcr) {
429 1.2.4.2 nathanw printf("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev));
430 1.2.4.2 nathanw return (USBD_IOERROR);
431 1.2.4.2 nathanw }
432 1.2.4.2 nathanw
433 1.2.4.2 nathanw return (USBD_NORMAL_COMPLETION);
434 1.2.4.2 nathanw
435 1.2.4.2 nathanw #if 0
436 1.2.4.2 nathanw bad2:
437 1.2.4.2 nathanw ehci_free_sqh(sc, sc->sc_async_head);
438 1.2.4.2 nathanw #endif
439 1.2.4.2 nathanw bad1:
440 1.2.4.2 nathanw usb_freemem(&sc->sc_bus, &sc->sc_fldma);
441 1.2.4.2 nathanw return (err);
442 1.1 augustss }
443 1.1 augustss
444 1.1 augustss int
445 1.1 augustss ehci_intr(void *v)
446 1.1 augustss {
447 1.2.4.2 nathanw ehci_softc_t *sc = v;
448 1.2.4.2 nathanw
449 1.2.4.2 nathanw if (sc == NULL || sc->sc_dying)
450 1.2.4.2 nathanw return (0);
451 1.2.4.2 nathanw
452 1.2.4.2 nathanw /* If we get an interrupt while polling, then just ignore it. */
453 1.2.4.2 nathanw if (sc->sc_bus.use_polling) {
454 1.2.4.2 nathanw #ifdef DIAGNOSTIC
455 1.2.4.2 nathanw printf("ehci_intr: ignored interrupt while polling\n");
456 1.2.4.2 nathanw #endif
457 1.2.4.2 nathanw return (0);
458 1.2.4.2 nathanw }
459 1.2.4.2 nathanw
460 1.2.4.6 nathanw return (ehci_intr1(sc));
461 1.2.4.2 nathanw }
462 1.2.4.2 nathanw
463 1.2.4.2 nathanw Static int
464 1.2.4.2 nathanw ehci_intr1(ehci_softc_t *sc)
465 1.2.4.2 nathanw {
466 1.2.4.2 nathanw u_int32_t intrs, eintrs;
467 1.2.4.2 nathanw
468 1.2.4.2 nathanw DPRINTFN(20,("ehci_intr1: enter\n"));
469 1.2.4.2 nathanw
470 1.2.4.2 nathanw /* In case the interrupt occurs before initialization has completed. */
471 1.2.4.2 nathanw if (sc == NULL) {
472 1.2.4.2 nathanw #ifdef DIAGNOSTIC
473 1.2.4.2 nathanw printf("ehci_intr: sc == NULL\n");
474 1.2.4.2 nathanw #endif
475 1.2.4.2 nathanw return (0);
476 1.2.4.2 nathanw }
477 1.2.4.2 nathanw
478 1.2.4.2 nathanw intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
479 1.2.4.2 nathanw
480 1.2.4.2 nathanw if (!intrs)
481 1.2.4.2 nathanw return (0);
482 1.2.4.2 nathanw
483 1.2.4.2 nathanw EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
484 1.2.4.2 nathanw eintrs = intrs & sc->sc_eintrs;
485 1.2.4.6 nathanw DPRINTFN(7, ("ehci_intr: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n",
486 1.2.4.2 nathanw sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS),
487 1.2.4.2 nathanw (u_int)eintrs));
488 1.2.4.2 nathanw if (!eintrs)
489 1.2.4.2 nathanw return (0);
490 1.2.4.2 nathanw
491 1.2.4.2 nathanw sc->sc_bus.intr_context++;
492 1.2.4.2 nathanw sc->sc_bus.no_intrs++;
493 1.2.4.2 nathanw if (eintrs & EHCI_STS_IAA) {
494 1.2.4.2 nathanw DPRINTF(("ehci_intr1: door bell\n"));
495 1.2.4.2 nathanw wakeup(&sc->sc_async_head);
496 1.2.4.2 nathanw eintrs &= ~EHCI_STS_IAA;
497 1.2.4.2 nathanw }
498 1.2.4.2 nathanw if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
499 1.2.4.6 nathanw DPRINTF(("ehci_intr1: %s %s\n",
500 1.2.4.2 nathanw eintrs & EHCI_STS_INT ? "INT" : "",
501 1.2.4.2 nathanw eintrs & EHCI_STS_ERRINT ? "ERRINT" : ""));
502 1.2.4.2 nathanw usb_schedsoftintr(&sc->sc_bus);
503 1.2.4.2 nathanw eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
504 1.2.4.2 nathanw }
505 1.2.4.2 nathanw if (eintrs & EHCI_STS_HSE) {
506 1.2.4.2 nathanw printf("%s: unrecoverable error, controller halted\n",
507 1.2.4.2 nathanw USBDEVNAME(sc->sc_bus.bdev));
508 1.2.4.2 nathanw /* XXX what else */
509 1.2.4.2 nathanw }
510 1.2.4.2 nathanw if (eintrs & EHCI_STS_PCD) {
511 1.2.4.2 nathanw ehci_pcd(sc, sc->sc_intrxfer);
512 1.2.4.6 nathanw /*
513 1.2.4.2 nathanw * Disable PCD interrupt for now, because it will be
514 1.2.4.2 nathanw * on until the port has been reset.
515 1.2.4.2 nathanw */
516 1.2.4.2 nathanw ehci_pcd_able(sc, 0);
517 1.2.4.2 nathanw /* Do not allow RHSC interrupts > 1 per second */
518 1.2.4.2 nathanw usb_callout(sc->sc_tmo_pcd, hz, ehci_pcd_enable, sc);
519 1.2.4.2 nathanw eintrs &= ~EHCI_STS_PCD;
520 1.2.4.2 nathanw }
521 1.2.4.2 nathanw
522 1.2.4.2 nathanw sc->sc_bus.intr_context--;
523 1.2.4.2 nathanw
524 1.2.4.2 nathanw if (eintrs != 0) {
525 1.2.4.2 nathanw /* Block unprocessed interrupts. */
526 1.2.4.2 nathanw sc->sc_eintrs &= ~eintrs;
527 1.2.4.2 nathanw EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
528 1.2.4.2 nathanw printf("%s: blocking intrs 0x%x\n",
529 1.2.4.2 nathanw USBDEVNAME(sc->sc_bus.bdev), eintrs);
530 1.2.4.2 nathanw }
531 1.2.4.2 nathanw
532 1.2.4.2 nathanw return (1);
533 1.2.4.2 nathanw }
534 1.2.4.2 nathanw
535 1.2.4.2 nathanw void
536 1.2.4.2 nathanw ehci_pcd_able(ehci_softc_t *sc, int on)
537 1.2.4.2 nathanw {
538 1.2.4.2 nathanw DPRINTFN(4, ("ehci_pcd_able: on=%d\n", on));
539 1.2.4.2 nathanw if (on)
540 1.2.4.2 nathanw sc->sc_eintrs |= EHCI_STS_PCD;
541 1.2.4.2 nathanw else
542 1.2.4.2 nathanw sc->sc_eintrs &= ~EHCI_STS_PCD;
543 1.2.4.2 nathanw EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
544 1.2.4.2 nathanw }
545 1.2.4.2 nathanw
546 1.2.4.2 nathanw void
547 1.2.4.2 nathanw ehci_pcd_enable(void *v_sc)
548 1.2.4.2 nathanw {
549 1.2.4.2 nathanw ehci_softc_t *sc = v_sc;
550 1.2.4.2 nathanw
551 1.2.4.2 nathanw ehci_pcd_able(sc, 1);
552 1.2.4.2 nathanw }
553 1.2.4.2 nathanw
554 1.2.4.2 nathanw void
555 1.2.4.2 nathanw ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer)
556 1.2.4.2 nathanw {
557 1.2.4.2 nathanw usbd_pipe_handle pipe;
558 1.2.4.2 nathanw struct ehci_pipe *epipe;
559 1.2.4.2 nathanw u_char *p;
560 1.2.4.2 nathanw int i, m;
561 1.2.4.2 nathanw
562 1.2.4.2 nathanw if (xfer == NULL) {
563 1.2.4.2 nathanw /* Just ignore the change. */
564 1.2.4.2 nathanw return;
565 1.2.4.2 nathanw }
566 1.2.4.2 nathanw
567 1.2.4.2 nathanw pipe = xfer->pipe;
568 1.2.4.2 nathanw epipe = (struct ehci_pipe *)pipe;
569 1.2.4.2 nathanw
570 1.2.4.3 nathanw p = KERNADDR(&xfer->dmabuf, 0);
571 1.2.4.2 nathanw m = min(sc->sc_noport, xfer->length * 8 - 1);
572 1.2.4.2 nathanw memset(p, 0, xfer->length);
573 1.2.4.2 nathanw for (i = 1; i <= m; i++) {
574 1.2.4.2 nathanw /* Pick out CHANGE bits from the status reg. */
575 1.2.4.2 nathanw if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
576 1.2.4.2 nathanw p[i/8] |= 1 << (i%8);
577 1.2.4.2 nathanw }
578 1.2.4.2 nathanw DPRINTF(("ehci_pcd: change=0x%02x\n", *p));
579 1.2.4.2 nathanw xfer->actlen = xfer->length;
580 1.2.4.2 nathanw xfer->status = USBD_NORMAL_COMPLETION;
581 1.2.4.2 nathanw
582 1.2.4.2 nathanw usb_transfer_complete(xfer);
583 1.2.4.2 nathanw }
584 1.2.4.2 nathanw
585 1.2.4.2 nathanw void
586 1.2.4.2 nathanw ehci_softintr(void *v)
587 1.2.4.2 nathanw {
588 1.2.4.2 nathanw ehci_softc_t *sc = v;
589 1.2.4.2 nathanw struct ehci_xfer *ex;
590 1.2.4.2 nathanw
591 1.2.4.2 nathanw DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev),
592 1.2.4.2 nathanw sc->sc_bus.intr_context));
593 1.2.4.2 nathanw
594 1.2.4.2 nathanw sc->sc_bus.intr_context++;
595 1.2.4.2 nathanw
596 1.2.4.2 nathanw /*
597 1.2.4.2 nathanw * The only explanation I can think of for why EHCI is as brain dead
598 1.2.4.2 nathanw * as UHCI interrupt-wise is that Intel was involved in both.
599 1.2.4.2 nathanw * An interrupt just tells us that something is done, we have no
600 1.2.4.2 nathanw * clue what, so we need to scan through all active transfers. :-(
601 1.2.4.2 nathanw */
602 1.2.4.2 nathanw for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = LIST_NEXT(ex, inext))
603 1.2.4.2 nathanw ehci_check_intr(sc, ex);
604 1.2.4.2 nathanw
605 1.2.4.2 nathanw if (sc->sc_softwake) {
606 1.2.4.2 nathanw sc->sc_softwake = 0;
607 1.2.4.2 nathanw wakeup(&sc->sc_softwake);
608 1.2.4.2 nathanw }
609 1.2.4.2 nathanw
610 1.2.4.2 nathanw sc->sc_bus.intr_context--;
611 1.2.4.2 nathanw }
612 1.2.4.2 nathanw
613 1.2.4.2 nathanw /* Check for an interrupt. */
614 1.2.4.2 nathanw void
615 1.2.4.2 nathanw ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
616 1.2.4.2 nathanw {
617 1.2.4.2 nathanw ehci_soft_qtd_t *sqtd, *lsqtd;
618 1.2.4.2 nathanw u_int32_t status;
619 1.2.4.2 nathanw
620 1.2.4.2 nathanw DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex));
621 1.2.4.2 nathanw
622 1.2.4.2 nathanw if (ex->sqtdstart == NULL) {
623 1.2.4.2 nathanw printf("ehci_check_intr: sqtdstart=NULL\n");
624 1.2.4.2 nathanw return;
625 1.2.4.2 nathanw }
626 1.2.4.2 nathanw lsqtd = ex->sqtdend;
627 1.2.4.2 nathanw #ifdef DIAGNOSTIC
628 1.2.4.2 nathanw if (lsqtd == NULL) {
629 1.2.4.2 nathanw printf("ehci_check_intr: sqtd==0\n");
630 1.2.4.2 nathanw return;
631 1.2.4.2 nathanw }
632 1.2.4.2 nathanw #endif
633 1.2.4.6 nathanw /*
634 1.2.4.2 nathanw * If the last TD is still active we need to check whether there
635 1.2.4.2 nathanw * is a an error somewhere in the middle, or whether there was a
636 1.2.4.2 nathanw * short packet (SPD and not ACTIVE).
637 1.2.4.2 nathanw */
638 1.2.4.2 nathanw if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) {
639 1.2.4.2 nathanw DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex));
640 1.2.4.2 nathanw for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) {
641 1.2.4.2 nathanw status = le32toh(sqtd->qtd.qtd_status);
642 1.2.4.2 nathanw /* If there's an active QTD the xfer isn't done. */
643 1.2.4.2 nathanw if (status & EHCI_QTD_ACTIVE)
644 1.2.4.2 nathanw break;
645 1.2.4.2 nathanw /* Any kind of error makes the xfer done. */
646 1.2.4.2 nathanw if (status & EHCI_QTD_HALTED)
647 1.2.4.2 nathanw goto done;
648 1.2.4.2 nathanw /* We want short packets, and it is short: it's done */
649 1.2.4.2 nathanw if (EHCI_QTD_SET_BYTES(status) != 0)
650 1.2.4.2 nathanw goto done;
651 1.2.4.2 nathanw }
652 1.2.4.2 nathanw DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n",
653 1.2.4.2 nathanw ex, ex->sqtdstart));
654 1.2.4.2 nathanw return;
655 1.2.4.2 nathanw }
656 1.2.4.2 nathanw done:
657 1.2.4.2 nathanw DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex));
658 1.2.4.2 nathanw usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex);
659 1.2.4.2 nathanw ehci_idone(ex);
660 1.2.4.2 nathanw }
661 1.2.4.2 nathanw
662 1.2.4.2 nathanw void
663 1.2.4.2 nathanw ehci_idone(struct ehci_xfer *ex)
664 1.2.4.2 nathanw {
665 1.2.4.2 nathanw usbd_xfer_handle xfer = &ex->xfer;
666 1.2.4.2 nathanw #ifdef EHCI_DEBUG
667 1.2.4.2 nathanw struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
668 1.2.4.2 nathanw #endif
669 1.2.4.2 nathanw ehci_soft_qtd_t *sqtd;
670 1.2.4.2 nathanw u_int32_t status = 0, nstatus;
671 1.2.4.2 nathanw int actlen;
672 1.2.4.2 nathanw
673 1.2.4.2 nathanw DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex));
674 1.2.4.2 nathanw #ifdef DIAGNOSTIC
675 1.2.4.2 nathanw {
676 1.2.4.2 nathanw int s = splhigh();
677 1.2.4.2 nathanw if (ex->isdone) {
678 1.2.4.2 nathanw splx(s);
679 1.2.4.2 nathanw #ifdef EHCI_DEBUG
680 1.2.4.2 nathanw printf("ehci_idone: ex is done!\n ");
681 1.2.4.2 nathanw ehci_dump_exfer(ex);
682 1.2.4.2 nathanw #else
683 1.2.4.2 nathanw printf("ehci_idone: ex=%p is done!\n", ex);
684 1.2.4.2 nathanw #endif
685 1.2.4.2 nathanw return;
686 1.2.4.2 nathanw }
687 1.2.4.2 nathanw ex->isdone = 1;
688 1.2.4.2 nathanw splx(s);
689 1.2.4.2 nathanw }
690 1.2.4.2 nathanw #endif
691 1.2.4.2 nathanw
692 1.2.4.2 nathanw if (xfer->status == USBD_CANCELLED ||
693 1.2.4.2 nathanw xfer->status == USBD_TIMEOUT) {
694 1.2.4.2 nathanw DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer));
695 1.2.4.2 nathanw return;
696 1.2.4.2 nathanw }
697 1.2.4.2 nathanw
698 1.2.4.2 nathanw #ifdef EHCI_DEBUG
699 1.2.4.2 nathanw DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe));
700 1.2.4.2 nathanw if (ehcidebug > 10)
701 1.2.4.2 nathanw ehci_dump_sqtds(ex->sqtdstart);
702 1.2.4.2 nathanw #endif
703 1.2.4.2 nathanw
704 1.2.4.2 nathanw /* The transfer is done, compute actual length and status. */
705 1.2.4.2 nathanw actlen = 0;
706 1.2.4.2 nathanw for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) {
707 1.2.4.2 nathanw nstatus = le32toh(sqtd->qtd.qtd_status);
708 1.2.4.2 nathanw if (nstatus & EHCI_QTD_ACTIVE)
709 1.2.4.2 nathanw break;
710 1.2.4.2 nathanw
711 1.2.4.2 nathanw status = nstatus;
712 1.2.4.2 nathanw if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
713 1.2.4.2 nathanw actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
714 1.2.4.2 nathanw }
715 1.2.4.2 nathanw
716 1.2.4.2 nathanw /* If there are left over TDs we need to update the toggle. */
717 1.2.4.2 nathanw if (sqtd != NULL) {
718 1.2.4.2 nathanw if (!(xfer->rqflags & URQ_REQUEST))
719 1.2.4.2 nathanw printf("ehci_idone: need toggle update\n");
720 1.2.4.2 nathanw #if 0
721 1.2.4.2 nathanw epipe->nexttoggle = EHCI_TD_GET_DT(le32toh(std->td.td_token));
722 1.2.4.2 nathanw #endif
723 1.2.4.2 nathanw }
724 1.2.4.2 nathanw
725 1.2.4.2 nathanw status &= EHCI_QTD_STATERRS;
726 1.2.4.2 nathanw DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n",
727 1.2.4.2 nathanw xfer->length, actlen, status));
728 1.2.4.2 nathanw xfer->actlen = actlen;
729 1.2.4.2 nathanw if (status != 0) {
730 1.2.4.2 nathanw #ifdef EHCI_DEBUG
731 1.2.4.2 nathanw char sbuf[128];
732 1.2.4.2 nathanw
733 1.2.4.2 nathanw bitmask_snprintf((u_int32_t)status,
734 1.2.4.2 nathanw "\20\3MISSEDMICRO\4XACT\5BABBLE\6BABBLE"
735 1.2.4.2 nathanw "\7HALTED",
736 1.2.4.2 nathanw sbuf, sizeof(sbuf));
737 1.2.4.2 nathanw
738 1.2.4.2 nathanw DPRINTFN((status == EHCI_QTD_HALTED)*/*10*/2,
739 1.2.4.2 nathanw ("ehci_idone: error, addr=%d, endpt=0x%02x, "
740 1.2.4.2 nathanw "status 0x%s\n",
741 1.2.4.2 nathanw xfer->pipe->device->address,
742 1.2.4.2 nathanw xfer->pipe->endpoint->edesc->bEndpointAddress,
743 1.2.4.2 nathanw sbuf));
744 1.2.4.2 nathanw if (ehcidebug > 2) {
745 1.2.4.2 nathanw ehci_dump_sqh(epipe->sqh);
746 1.2.4.2 nathanw ehci_dump_sqtds(ex->sqtdstart);
747 1.2.4.2 nathanw }
748 1.2.4.2 nathanw #endif
749 1.2.4.2 nathanw if (status == EHCI_QTD_HALTED)
750 1.2.4.2 nathanw xfer->status = USBD_STALLED;
751 1.2.4.2 nathanw else
752 1.2.4.2 nathanw xfer->status = USBD_IOERROR; /* more info XXX */
753 1.2.4.2 nathanw } else {
754 1.2.4.2 nathanw xfer->status = USBD_NORMAL_COMPLETION;
755 1.2.4.2 nathanw }
756 1.2.4.2 nathanw
757 1.2.4.2 nathanw usb_transfer_complete(xfer);
758 1.2.4.2 nathanw DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex));
759 1.2.4.2 nathanw }
760 1.2.4.2 nathanw
761 1.2.4.2 nathanw /*
762 1.2.4.2 nathanw * Wait here until controller claims to have an interrupt.
763 1.2.4.2 nathanw * Then call ehci_intr and return. Use timeout to avoid waiting
764 1.2.4.2 nathanw * too long.
765 1.2.4.2 nathanw */
766 1.2.4.2 nathanw void
767 1.2.4.2 nathanw ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer)
768 1.2.4.2 nathanw {
769 1.2.4.2 nathanw int timo = xfer->timeout;
770 1.2.4.2 nathanw int usecs;
771 1.2.4.2 nathanw u_int32_t intrs;
772 1.2.4.2 nathanw
773 1.2.4.2 nathanw xfer->status = USBD_IN_PROGRESS;
774 1.2.4.2 nathanw for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) {
775 1.2.4.2 nathanw usb_delay_ms(&sc->sc_bus, 1);
776 1.2.4.2 nathanw if (sc->sc_dying)
777 1.2.4.2 nathanw break;
778 1.2.4.2 nathanw intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) &
779 1.2.4.2 nathanw sc->sc_eintrs;
780 1.2.4.2 nathanw DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs));
781 1.2.4.2 nathanw #ifdef OHCI_DEBUG
782 1.2.4.2 nathanw if (ehcidebug > 15)
783 1.2.4.2 nathanw ehci_dump_regs(sc);
784 1.2.4.2 nathanw #endif
785 1.2.4.2 nathanw if (intrs) {
786 1.2.4.2 nathanw ehci_intr1(sc);
787 1.2.4.2 nathanw if (xfer->status != USBD_IN_PROGRESS)
788 1.2.4.2 nathanw return;
789 1.2.4.2 nathanw }
790 1.2.4.2 nathanw }
791 1.2.4.2 nathanw
792 1.2.4.2 nathanw /* Timeout */
793 1.2.4.2 nathanw DPRINTF(("ehci_waitintr: timeout\n"));
794 1.2.4.2 nathanw xfer->status = USBD_TIMEOUT;
795 1.2.4.2 nathanw usb_transfer_complete(xfer);
796 1.2.4.2 nathanw /* XXX should free TD */
797 1.2.4.2 nathanw }
798 1.2.4.2 nathanw
799 1.2.4.2 nathanw void
800 1.2.4.2 nathanw ehci_poll(struct usbd_bus *bus)
801 1.2.4.2 nathanw {
802 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)bus;
803 1.2.4.2 nathanw #ifdef EHCI_DEBUG
804 1.2.4.2 nathanw static int last;
805 1.2.4.2 nathanw int new;
806 1.2.4.2 nathanw new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
807 1.2.4.2 nathanw if (new != last) {
808 1.2.4.2 nathanw DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new));
809 1.2.4.2 nathanw last = new;
810 1.2.4.2 nathanw }
811 1.2.4.2 nathanw #endif
812 1.2.4.2 nathanw
813 1.2.4.2 nathanw if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs)
814 1.2.4.2 nathanw ehci_intr1(sc);
815 1.1 augustss }
816 1.1 augustss
817 1.1 augustss int
818 1.1 augustss ehci_detach(struct ehci_softc *sc, int flags)
819 1.1 augustss {
820 1.1 augustss int rv = 0;
821 1.1 augustss
822 1.1 augustss if (sc->sc_child != NULL)
823 1.1 augustss rv = config_detach(sc->sc_child, flags);
824 1.2.4.6 nathanw
825 1.1 augustss if (rv != 0)
826 1.1 augustss return (rv);
827 1.1 augustss
828 1.2.4.2 nathanw usb_uncallout(sc->sc_tmo_pcd, ehci_pcd_enable, sc);
829 1.2.4.2 nathanw
830 1.1 augustss if (sc->sc_powerhook != NULL)
831 1.1 augustss powerhook_disestablish(sc->sc_powerhook);
832 1.1 augustss if (sc->sc_shutdownhook != NULL)
833 1.1 augustss shutdownhook_disestablish(sc->sc_shutdownhook);
834 1.1 augustss
835 1.2.4.2 nathanw usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
836 1.2.4.2 nathanw
837 1.1 augustss /* XXX free other data structures XXX */
838 1.1 augustss
839 1.1 augustss return (rv);
840 1.1 augustss }
841 1.1 augustss
842 1.1 augustss
843 1.1 augustss int
844 1.1 augustss ehci_activate(device_ptr_t self, enum devact act)
845 1.1 augustss {
846 1.1 augustss struct ehci_softc *sc = (struct ehci_softc *)self;
847 1.1 augustss int rv = 0;
848 1.1 augustss
849 1.1 augustss switch (act) {
850 1.1 augustss case DVACT_ACTIVATE:
851 1.1 augustss return (EOPNOTSUPP);
852 1.1 augustss break;
853 1.1 augustss
854 1.1 augustss case DVACT_DEACTIVATE:
855 1.1 augustss if (sc->sc_child != NULL)
856 1.1 augustss rv = config_deactivate(sc->sc_child);
857 1.2.4.2 nathanw sc->sc_dying = 1;
858 1.1 augustss break;
859 1.1 augustss }
860 1.1 augustss return (rv);
861 1.1 augustss }
862 1.1 augustss
863 1.2.4.2 nathanw /*
864 1.2.4.2 nathanw * Handle suspend/resume.
865 1.2.4.2 nathanw *
866 1.2.4.2 nathanw * We need to switch to polling mode here, because this routine is
867 1.2.4.2 nathanw * called from an intterupt context. This is all right since we
868 1.2.4.2 nathanw * are almost suspended anyway.
869 1.2.4.2 nathanw */
870 1.2.4.2 nathanw void
871 1.2.4.2 nathanw ehci_power(int why, void *v)
872 1.2.4.2 nathanw {
873 1.2.4.2 nathanw ehci_softc_t *sc = v;
874 1.2.4.2 nathanw //u_int32_t ctl;
875 1.2.4.2 nathanw int s;
876 1.2.4.2 nathanw
877 1.2.4.2 nathanw #ifdef EHCI_DEBUG
878 1.2.4.2 nathanw DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why));
879 1.2.4.2 nathanw ehci_dump_regs(sc);
880 1.2.4.2 nathanw #endif
881 1.2.4.2 nathanw
882 1.2.4.2 nathanw s = splhardusb();
883 1.2.4.2 nathanw switch (why) {
884 1.2.4.2 nathanw case PWR_SUSPEND:
885 1.2.4.2 nathanw case PWR_STANDBY:
886 1.2.4.2 nathanw sc->sc_bus.use_polling++;
887 1.2.4.2 nathanw #if 0
888 1.2.4.2 nathanw OOO
889 1.2.4.2 nathanw ctl = OREAD4(sc, EHCI_CONTROL) & ~EHCI_HCFS_MASK;
890 1.2.4.2 nathanw if (sc->sc_control == 0) {
891 1.2.4.2 nathanw /*
892 1.2.4.2 nathanw * Preserve register values, in case that APM BIOS
893 1.2.4.2 nathanw * does not recover them.
894 1.2.4.2 nathanw */
895 1.2.4.2 nathanw sc->sc_control = ctl;
896 1.2.4.2 nathanw sc->sc_intre = OREAD4(sc, EHCI_INTERRUPT_ENABLE);
897 1.2.4.2 nathanw }
898 1.2.4.2 nathanw ctl |= EHCI_HCFS_SUSPEND;
899 1.2.4.2 nathanw OWRITE4(sc, EHCI_CONTROL, ctl);
900 1.2.4.2 nathanw #endif
901 1.2.4.2 nathanw usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
902 1.2.4.2 nathanw sc->sc_bus.use_polling--;
903 1.2.4.2 nathanw break;
904 1.2.4.2 nathanw case PWR_RESUME:
905 1.2.4.2 nathanw sc->sc_bus.use_polling++;
906 1.2.4.2 nathanw #if 0
907 1.2.4.2 nathanw OOO
908 1.2.4.2 nathanw /* Some broken BIOSes do not recover these values */
909 1.2.4.3 nathanw OWRITE4(sc, EHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
910 1.2.4.2 nathanw OWRITE4(sc, EHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
911 1.2.4.2 nathanw OWRITE4(sc, EHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
912 1.2.4.2 nathanw if (sc->sc_intre)
913 1.2.4.2 nathanw OWRITE4(sc, EHCI_INTERRUPT_ENABLE,
914 1.2.4.2 nathanw sc->sc_intre & (EHCI_ALL_INTRS | EHCI_MIE));
915 1.2.4.2 nathanw if (sc->sc_control)
916 1.2.4.2 nathanw ctl = sc->sc_control;
917 1.2.4.2 nathanw else
918 1.2.4.2 nathanw ctl = OREAD4(sc, EHCI_CONTROL);
919 1.2.4.2 nathanw ctl |= EHCI_HCFS_RESUME;
920 1.2.4.2 nathanw OWRITE4(sc, EHCI_CONTROL, ctl);
921 1.2.4.2 nathanw usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
922 1.2.4.2 nathanw ctl = (ctl & ~EHCI_HCFS_MASK) | EHCI_HCFS_OPERATIONAL;
923 1.2.4.2 nathanw OWRITE4(sc, EHCI_CONTROL, ctl);
924 1.2.4.2 nathanw usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
925 1.2.4.2 nathanw sc->sc_control = sc->sc_intre = 0;
926 1.2.4.2 nathanw #endif
927 1.2.4.2 nathanw sc->sc_bus.use_polling--;
928 1.2.4.2 nathanw break;
929 1.2.4.2 nathanw case PWR_SOFTSUSPEND:
930 1.2.4.2 nathanw case PWR_SOFTSTANDBY:
931 1.2.4.2 nathanw case PWR_SOFTRESUME:
932 1.2.4.2 nathanw break;
933 1.2.4.2 nathanw }
934 1.2.4.2 nathanw splx(s);
935 1.2.4.2 nathanw }
936 1.2.4.2 nathanw
937 1.2.4.2 nathanw /*
938 1.2.4.2 nathanw * Shut down the controller when the system is going down.
939 1.2.4.2 nathanw */
940 1.2.4.2 nathanw void
941 1.2.4.2 nathanw ehci_shutdown(void *v)
942 1.2.4.2 nathanw {
943 1.2.4.2 nathanw ehci_softc_t *sc = v;
944 1.2.4.2 nathanw
945 1.2.4.2 nathanw DPRINTF(("ehci_shutdown: stopping the HC\n"));
946 1.2.4.2 nathanw EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
947 1.2.4.2 nathanw EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
948 1.2.4.2 nathanw }
949 1.2.4.2 nathanw
950 1.2.4.2 nathanw usbd_status
951 1.2.4.2 nathanw ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size)
952 1.2.4.2 nathanw {
953 1.2.4.2 nathanw struct ehci_softc *sc = (struct ehci_softc *)bus;
954 1.2.4.2 nathanw usbd_status err;
955 1.2.4.2 nathanw
956 1.2.4.2 nathanw err = usb_allocmem(&sc->sc_bus, size, 0, dma);
957 1.2.4.2 nathanw #ifdef EHCI_DEBUG
958 1.2.4.2 nathanw if (err)
959 1.2.4.2 nathanw printf("ehci_allocm: usb_allocmem()=%d\n", err);
960 1.2.4.2 nathanw #endif
961 1.2.4.2 nathanw return (err);
962 1.2.4.2 nathanw }
963 1.2.4.2 nathanw
964 1.2.4.2 nathanw void
965 1.2.4.2 nathanw ehci_freem(struct usbd_bus *bus, usb_dma_t *dma)
966 1.2.4.2 nathanw {
967 1.2.4.2 nathanw struct ehci_softc *sc = (struct ehci_softc *)bus;
968 1.2.4.2 nathanw
969 1.2.4.2 nathanw usb_freemem(&sc->sc_bus, dma);
970 1.2.4.2 nathanw }
971 1.2.4.2 nathanw
972 1.2.4.2 nathanw usbd_xfer_handle
973 1.2.4.2 nathanw ehci_allocx(struct usbd_bus *bus)
974 1.2.4.2 nathanw {
975 1.2.4.2 nathanw struct ehci_softc *sc = (struct ehci_softc *)bus;
976 1.2.4.2 nathanw usbd_xfer_handle xfer;
977 1.2.4.2 nathanw
978 1.2.4.2 nathanw xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers);
979 1.2.4.2 nathanw if (xfer != NULL) {
980 1.2.4.3 nathanw SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
981 1.2.4.2 nathanw #ifdef DIAGNOSTIC
982 1.2.4.2 nathanw if (xfer->busy_free != XFER_FREE) {
983 1.2.4.2 nathanw printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer,
984 1.2.4.2 nathanw xfer->busy_free);
985 1.2.4.2 nathanw }
986 1.2.4.2 nathanw #endif
987 1.2.4.2 nathanw } else {
988 1.2.4.2 nathanw xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT);
989 1.2.4.2 nathanw }
990 1.2.4.2 nathanw if (xfer != NULL) {
991 1.2.4.2 nathanw memset(xfer, 0, sizeof (struct ehci_xfer));
992 1.2.4.2 nathanw #ifdef DIAGNOSTIC
993 1.2.4.2 nathanw EXFER(xfer)->isdone = 1;
994 1.2.4.2 nathanw xfer->busy_free = XFER_BUSY;
995 1.2.4.2 nathanw #endif
996 1.2.4.2 nathanw }
997 1.2.4.2 nathanw return (xfer);
998 1.2.4.2 nathanw }
999 1.2.4.2 nathanw
1000 1.2.4.2 nathanw void
1001 1.2.4.2 nathanw ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
1002 1.2.4.2 nathanw {
1003 1.2.4.2 nathanw struct ehci_softc *sc = (struct ehci_softc *)bus;
1004 1.2.4.2 nathanw
1005 1.2.4.2 nathanw #ifdef DIAGNOSTIC
1006 1.2.4.2 nathanw if (xfer->busy_free != XFER_BUSY) {
1007 1.2.4.2 nathanw printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer,
1008 1.2.4.2 nathanw xfer->busy_free);
1009 1.2.4.2 nathanw return;
1010 1.2.4.2 nathanw }
1011 1.2.4.2 nathanw xfer->busy_free = XFER_FREE;
1012 1.2.4.2 nathanw if (!EXFER(xfer)->isdone) {
1013 1.2.4.2 nathanw printf("ehci_freex: !isdone\n");
1014 1.2.4.2 nathanw return;
1015 1.2.4.2 nathanw }
1016 1.2.4.2 nathanw #endif
1017 1.2.4.2 nathanw SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next);
1018 1.2.4.2 nathanw }
1019 1.2.4.2 nathanw
1020 1.2.4.2 nathanw Static void
1021 1.2.4.2 nathanw ehci_device_clear_toggle(usbd_pipe_handle pipe)
1022 1.2.4.2 nathanw {
1023 1.2.4.2 nathanw struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1024 1.2.4.2 nathanw
1025 1.2.4.2 nathanw DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n",
1026 1.2.4.2 nathanw epipe, epipe->sqh->qh.qh_qtd.qtd_status));
1027 1.2.4.2 nathanw #ifdef USB_DEBUG
1028 1.2.4.2 nathanw if (ehcidebug)
1029 1.2.4.2 nathanw usbd_dump_pipe(pipe);
1030 1.2.4.2 nathanw #endif
1031 1.2.4.2 nathanw epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE);
1032 1.2.4.2 nathanw }
1033 1.2.4.2 nathanw
1034 1.2.4.2 nathanw Static void
1035 1.2.4.2 nathanw ehci_noop(usbd_pipe_handle pipe)
1036 1.2.4.2 nathanw {
1037 1.2.4.2 nathanw }
1038 1.2.4.2 nathanw
1039 1.2.4.2 nathanw #ifdef EHCI_DEBUG
1040 1.2.4.2 nathanw void
1041 1.2.4.2 nathanw ehci_dump_regs(ehci_softc_t *sc)
1042 1.2.4.2 nathanw {
1043 1.2.4.2 nathanw int i;
1044 1.2.4.2 nathanw printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n",
1045 1.2.4.2 nathanw EOREAD4(sc, EHCI_USBCMD),
1046 1.2.4.2 nathanw EOREAD4(sc, EHCI_USBSTS),
1047 1.2.4.2 nathanw EOREAD4(sc, EHCI_USBINTR));
1048 1.2.4.2 nathanw printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
1049 1.2.4.2 nathanw EOREAD4(sc, EHCI_FRINDEX),
1050 1.2.4.2 nathanw EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1051 1.2.4.2 nathanw EOREAD4(sc, EHCI_PERIODICLISTBASE),
1052 1.2.4.2 nathanw EOREAD4(sc, EHCI_ASYNCLISTADDR));
1053 1.2.4.2 nathanw for (i = 1; i <= sc->sc_noport; i++)
1054 1.2.4.6 nathanw printf("port %d status=0x%08x\n", i,
1055 1.2.4.2 nathanw EOREAD4(sc, EHCI_PORTSC(i)));
1056 1.2.4.10 thorpej }
1057 1.2.4.10 thorpej
1058 1.2.4.10 thorpej /*
1059 1.2.4.10 thorpej * Unused function - this is meant to be called from a kernel
1060 1.2.4.10 thorpej * debugger.
1061 1.2.4.10 thorpej */
1062 1.2.4.10 thorpej void
1063 1.2.4.10 thorpej ehci_dump()
1064 1.2.4.10 thorpej {
1065 1.2.4.10 thorpej ehci_dump_regs(theehci);
1066 1.2.4.2 nathanw }
1067 1.2.4.2 nathanw
1068 1.2.4.2 nathanw void
1069 1.2.4.2 nathanw ehci_dump_link(ehci_link_t link, int type)
1070 1.2.4.2 nathanw {
1071 1.2.4.2 nathanw link = le32toh(link);
1072 1.2.4.2 nathanw printf("0x%08x", link);
1073 1.2.4.2 nathanw if (link & EHCI_LINK_TERMINATE)
1074 1.2.4.2 nathanw printf("<T>");
1075 1.2.4.2 nathanw else {
1076 1.2.4.2 nathanw printf("<");
1077 1.2.4.2 nathanw if (type) {
1078 1.2.4.2 nathanw switch (EHCI_LINK_TYPE(link)) {
1079 1.2.4.2 nathanw case EHCI_LINK_ITD: printf("ITD"); break;
1080 1.2.4.2 nathanw case EHCI_LINK_QH: printf("QH"); break;
1081 1.2.4.2 nathanw case EHCI_LINK_SITD: printf("SITD"); break;
1082 1.2.4.2 nathanw case EHCI_LINK_FSTN: printf("FSTN"); break;
1083 1.2.4.2 nathanw }
1084 1.2.4.2 nathanw }
1085 1.2.4.2 nathanw printf(">");
1086 1.2.4.2 nathanw }
1087 1.2.4.2 nathanw }
1088 1.2.4.2 nathanw
1089 1.2.4.2 nathanw void
1090 1.2.4.2 nathanw ehci_dump_sqtds(ehci_soft_qtd_t *sqtd)
1091 1.2.4.2 nathanw {
1092 1.2.4.2 nathanw int i;
1093 1.2.4.2 nathanw u_int32_t stop;
1094 1.2.4.2 nathanw
1095 1.2.4.2 nathanw stop = 0;
1096 1.2.4.2 nathanw for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) {
1097 1.2.4.2 nathanw ehci_dump_sqtd(sqtd);
1098 1.2.4.2 nathanw stop = sqtd->qtd.qtd_next & EHCI_LINK_TERMINATE;
1099 1.2.4.2 nathanw }
1100 1.2.4.2 nathanw if (sqtd)
1101 1.2.4.2 nathanw printf("dump aborted, too many TDs\n");
1102 1.2.4.2 nathanw }
1103 1.2.4.2 nathanw
1104 1.2.4.2 nathanw void
1105 1.2.4.2 nathanw ehci_dump_sqtd(ehci_soft_qtd_t *sqtd)
1106 1.2.4.2 nathanw {
1107 1.2.4.2 nathanw printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr);
1108 1.2.4.2 nathanw ehci_dump_qtd(&sqtd->qtd);
1109 1.2.4.2 nathanw }
1110 1.2.4.2 nathanw
1111 1.2.4.2 nathanw void
1112 1.2.4.2 nathanw ehci_dump_qtd(ehci_qtd_t *qtd)
1113 1.2.4.2 nathanw {
1114 1.2.4.2 nathanw u_int32_t s;
1115 1.2.4.2 nathanw char sbuf[128];
1116 1.2.4.2 nathanw
1117 1.2.4.2 nathanw printf(" next="); ehci_dump_link(qtd->qtd_next, 0);
1118 1.2.4.2 nathanw printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0);
1119 1.2.4.2 nathanw printf("\n");
1120 1.2.4.2 nathanw s = le32toh(qtd->qtd_status);
1121 1.2.4.2 nathanw bitmask_snprintf(EHCI_QTD_GET_STATUS(s),
1122 1.2.4.2 nathanw "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR"
1123 1.2.4.2 nathanw "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf));
1124 1.2.4.2 nathanw printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
1125 1.2.4.2 nathanw s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
1126 1.2.4.2 nathanw EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
1127 1.2.4.2 nathanw printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s),
1128 1.2.4.2 nathanw EHCI_QTD_GET_PID(s), sbuf);
1129 1.2.4.2 nathanw for (s = 0; s < 5; s++)
1130 1.2.4.2 nathanw printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s]));
1131 1.2.4.2 nathanw }
1132 1.2.4.2 nathanw
1133 1.2.4.2 nathanw void
1134 1.2.4.2 nathanw ehci_dump_sqh(ehci_soft_qh_t *sqh)
1135 1.2.4.2 nathanw {
1136 1.2.4.2 nathanw ehci_qh_t *qh = &sqh->qh;
1137 1.2.4.2 nathanw u_int32_t endp, endphub;
1138 1.2.4.2 nathanw
1139 1.2.4.2 nathanw printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr);
1140 1.2.4.2 nathanw printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n");
1141 1.2.4.2 nathanw endp = le32toh(qh->qh_endp);
1142 1.2.4.2 nathanw printf(" endp=0x%08x\n", endp);
1143 1.2.4.2 nathanw printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
1144 1.2.4.2 nathanw EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
1145 1.2.4.2 nathanw EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
1146 1.2.4.2 nathanw EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
1147 1.2.4.2 nathanw printf(" mpl=0x%x ctl=%d nrl=%d\n",
1148 1.2.4.2 nathanw EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
1149 1.2.4.2 nathanw EHCI_QH_GET_NRL(endp));
1150 1.2.4.2 nathanw endphub = le32toh(qh->qh_endphub);
1151 1.2.4.2 nathanw printf(" endphub=0x%08x\n", endphub);
1152 1.2.4.2 nathanw printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
1153 1.2.4.2 nathanw EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
1154 1.2.4.2 nathanw EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
1155 1.2.4.2 nathanw EHCI_QH_GET_MULT(endphub));
1156 1.2.4.2 nathanw printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n");
1157 1.2.4.2 nathanw printf("Overlay qTD:\n");
1158 1.2.4.2 nathanw ehci_dump_qtd(&qh->qh_qtd);
1159 1.2.4.2 nathanw }
1160 1.2.4.2 nathanw
1161 1.2.4.9 nathanw #ifdef DIAGNOSTIC
1162 1.2.4.2 nathanw Static void
1163 1.2.4.2 nathanw ehci_dump_exfer(struct ehci_xfer *ex)
1164 1.2.4.2 nathanw {
1165 1.2.4.2 nathanw printf("ehci_dump_exfer: ex=%p\n", ex);
1166 1.2.4.2 nathanw }
1167 1.2.4.9 nathanw #endif
1168 1.2.4.2 nathanw #endif
1169 1.2.4.2 nathanw
1170 1.2.4.2 nathanw usbd_status
1171 1.2.4.2 nathanw ehci_open(usbd_pipe_handle pipe)
1172 1.2.4.2 nathanw {
1173 1.2.4.2 nathanw usbd_device_handle dev = pipe->device;
1174 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
1175 1.2.4.2 nathanw usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1176 1.2.4.2 nathanw u_int8_t addr = dev->address;
1177 1.2.4.2 nathanw u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
1178 1.2.4.2 nathanw struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1179 1.2.4.2 nathanw ehci_soft_qh_t *sqh;
1180 1.2.4.2 nathanw usbd_status err;
1181 1.2.4.2 nathanw int s;
1182 1.2.4.2 nathanw int speed, naks;
1183 1.2.4.2 nathanw
1184 1.2.4.2 nathanw DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1185 1.2.4.2 nathanw pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1186 1.2.4.2 nathanw
1187 1.2.4.2 nathanw if (sc->sc_dying)
1188 1.2.4.2 nathanw return (USBD_IOERROR);
1189 1.2.4.2 nathanw
1190 1.2.4.2 nathanw if (addr == sc->sc_addr) {
1191 1.2.4.2 nathanw switch (ed->bEndpointAddress) {
1192 1.2.4.2 nathanw case USB_CONTROL_ENDPOINT:
1193 1.2.4.2 nathanw pipe->methods = &ehci_root_ctrl_methods;
1194 1.2.4.2 nathanw break;
1195 1.2.4.2 nathanw case UE_DIR_IN | EHCI_INTR_ENDPT:
1196 1.2.4.2 nathanw pipe->methods = &ehci_root_intr_methods;
1197 1.2.4.2 nathanw break;
1198 1.2.4.2 nathanw default:
1199 1.2.4.2 nathanw return (USBD_INVAL);
1200 1.2.4.2 nathanw }
1201 1.2.4.2 nathanw return (USBD_NORMAL_COMPLETION);
1202 1.2.4.2 nathanw }
1203 1.2.4.2 nathanw
1204 1.2.4.2 nathanw /* XXX All this stuff is only valid for async. */
1205 1.2.4.2 nathanw switch (dev->speed) {
1206 1.2.4.2 nathanw case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break;
1207 1.2.4.2 nathanw case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break;
1208 1.2.4.2 nathanw case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break;
1209 1.2.4.8 nathanw default: panic("ehci_open: bad device speed %d", dev->speed);
1210 1.2.4.2 nathanw }
1211 1.2.4.2 nathanw naks = 8; /* XXX */
1212 1.2.4.2 nathanw sqh = ehci_alloc_sqh(sc);
1213 1.2.4.2 nathanw if (sqh == NULL)
1214 1.2.4.2 nathanw goto bad0;
1215 1.2.4.2 nathanw /* qh_link filled when the QH is added */
1216 1.2.4.2 nathanw sqh->qh.qh_endp = htole32(
1217 1.2.4.2 nathanw EHCI_QH_SET_ADDR(addr) |
1218 1.2.4.2 nathanw EHCI_QH_SET_ENDPT(ed->bEndpointAddress) |
1219 1.2.4.2 nathanw EHCI_QH_SET_EPS(speed) | /* XXX */
1220 1.2.4.2 nathanw /* XXX EHCI_QH_DTC ? */
1221 1.2.4.2 nathanw EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) |
1222 1.2.4.2 nathanw (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ?
1223 1.2.4.2 nathanw EHCI_QH_CTL : 0) |
1224 1.2.4.2 nathanw EHCI_QH_SET_NRL(naks)
1225 1.2.4.2 nathanw );
1226 1.2.4.2 nathanw sqh->qh.qh_endphub = htole32(
1227 1.2.4.2 nathanw EHCI_QH_SET_MULT(1)
1228 1.2.4.2 nathanw /* XXX TT stuff */
1229 1.2.4.2 nathanw /* XXX interrupt mask */
1230 1.2.4.2 nathanw );
1231 1.2.4.2 nathanw sqh->qh.qh_curqtd = EHCI_NULL;
1232 1.2.4.2 nathanw /* Fill the overlay qTD */
1233 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
1234 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1235 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_status = htole32(0);
1236 1.2.4.2 nathanw
1237 1.2.4.2 nathanw epipe->sqh = sqh;
1238 1.2.4.2 nathanw
1239 1.2.4.2 nathanw switch (xfertype) {
1240 1.2.4.2 nathanw case UE_CONTROL:
1241 1.2.4.6 nathanw err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
1242 1.2.4.2 nathanw 0, &epipe->u.ctl.reqdma);
1243 1.2.4.2 nathanw #ifdef EHCI_DEBUG
1244 1.2.4.2 nathanw if (err)
1245 1.2.4.2 nathanw printf("ehci_open: usb_allocmem()=%d\n", err);
1246 1.2.4.2 nathanw #endif
1247 1.2.4.2 nathanw if (err)
1248 1.2.4.2 nathanw goto bad1;
1249 1.2.4.2 nathanw pipe->methods = &ehci_device_ctrl_methods;
1250 1.2.4.2 nathanw s = splusb();
1251 1.2.4.2 nathanw ehci_add_qh(sqh, sc->sc_async_head);
1252 1.2.4.2 nathanw splx(s);
1253 1.2.4.2 nathanw break;
1254 1.2.4.2 nathanw case UE_BULK:
1255 1.2.4.2 nathanw pipe->methods = &ehci_device_bulk_methods;
1256 1.2.4.2 nathanw s = splusb();
1257 1.2.4.2 nathanw ehci_add_qh(sqh, sc->sc_async_head);
1258 1.2.4.2 nathanw splx(s);
1259 1.2.4.2 nathanw break;
1260 1.2.4.2 nathanw case UE_INTERRUPT:
1261 1.2.4.2 nathanw pipe->methods = &ehci_device_intr_methods;
1262 1.2.4.2 nathanw return (USBD_INVAL);
1263 1.2.4.2 nathanw case UE_ISOCHRONOUS:
1264 1.2.4.2 nathanw pipe->methods = &ehci_device_isoc_methods;
1265 1.2.4.2 nathanw return (USBD_INVAL);
1266 1.2.4.2 nathanw default:
1267 1.2.4.2 nathanw return (USBD_INVAL);
1268 1.2.4.2 nathanw }
1269 1.2.4.2 nathanw return (USBD_NORMAL_COMPLETION);
1270 1.2.4.2 nathanw
1271 1.2.4.2 nathanw bad1:
1272 1.2.4.2 nathanw ehci_free_sqh(sc, sqh);
1273 1.2.4.2 nathanw bad0:
1274 1.2.4.2 nathanw return (USBD_NOMEM);
1275 1.2.4.2 nathanw }
1276 1.2.4.2 nathanw
1277 1.2.4.2 nathanw /*
1278 1.2.4.2 nathanw * Add an ED to the schedule. Called at splusb().
1279 1.2.4.2 nathanw */
1280 1.2.4.2 nathanw void
1281 1.2.4.2 nathanw ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1282 1.2.4.2 nathanw {
1283 1.2.4.2 nathanw SPLUSBCHECK;
1284 1.2.4.2 nathanw
1285 1.2.4.2 nathanw sqh->next = head->next;
1286 1.2.4.2 nathanw sqh->qh.qh_link = head->qh.qh_link;
1287 1.2.4.2 nathanw head->next = sqh;
1288 1.2.4.2 nathanw head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH);
1289 1.2.4.2 nathanw
1290 1.2.4.2 nathanw #ifdef EHCI_DEBUG
1291 1.2.4.2 nathanw if (ehcidebug > 5) {
1292 1.2.4.2 nathanw printf("ehci_add_qh:\n");
1293 1.2.4.2 nathanw ehci_dump_sqh(sqh);
1294 1.2.4.2 nathanw }
1295 1.2.4.2 nathanw #endif
1296 1.2.4.2 nathanw }
1297 1.2.4.2 nathanw
1298 1.2.4.2 nathanw /*
1299 1.2.4.2 nathanw * Remove an ED from the schedule. Called at splusb().
1300 1.2.4.2 nathanw */
1301 1.2.4.2 nathanw void
1302 1.2.4.2 nathanw ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1303 1.2.4.2 nathanw {
1304 1.2.4.6 nathanw ehci_soft_qh_t *p;
1305 1.2.4.2 nathanw
1306 1.2.4.2 nathanw SPLUSBCHECK;
1307 1.2.4.2 nathanw /* XXX */
1308 1.2.4.2 nathanw for (p = head; p == NULL && p->next != sqh; p = p->next)
1309 1.2.4.2 nathanw ;
1310 1.2.4.2 nathanw if (p == NULL)
1311 1.2.4.8 nathanw panic("ehci_rem_qh: ED not found");
1312 1.2.4.2 nathanw p->next = sqh->next;
1313 1.2.4.2 nathanw p->qh.qh_link = sqh->qh.qh_link;
1314 1.2.4.2 nathanw
1315 1.2.4.2 nathanw ehci_sync_hc(sc);
1316 1.2.4.2 nathanw }
1317 1.2.4.2 nathanw
1318 1.2.4.2 nathanw void
1319 1.2.4.2 nathanw ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd)
1320 1.2.4.2 nathanw {
1321 1.2.4.2 nathanw /* Halt while we are messing. */
1322 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_status |= htole32(EHCI_QTD_HALTED);
1323 1.2.4.2 nathanw sqh->qh.qh_curqtd = 0;
1324 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr);
1325 1.2.4.2 nathanw sqh->sqtd = sqtd;
1326 1.2.4.2 nathanw /* Keep toggle, clear the rest, including length. */
1327 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_status &= htole32(EHCI_QTD_TOGGLE);
1328 1.2.4.2 nathanw }
1329 1.2.4.2 nathanw
1330 1.2.4.2 nathanw /*
1331 1.2.4.2 nathanw * Ensure that the HC has released all references to the QH. We do this
1332 1.2.4.2 nathanw * by asking for a Async Advance Doorbell interrupt and then we wait for
1333 1.2.4.2 nathanw * the interrupt.
1334 1.2.4.2 nathanw * To make this easier we first obtain exclusive use of the doorbell.
1335 1.2.4.2 nathanw */
1336 1.2.4.2 nathanw void
1337 1.2.4.2 nathanw ehci_sync_hc(ehci_softc_t *sc)
1338 1.2.4.2 nathanw {
1339 1.2.4.2 nathanw int s, error;
1340 1.2.4.2 nathanw
1341 1.2.4.2 nathanw if (sc->sc_dying) {
1342 1.2.4.2 nathanw DPRINTFN(2,("ehci_sync_hc: dying\n"));
1343 1.2.4.2 nathanw return;
1344 1.2.4.2 nathanw }
1345 1.2.4.2 nathanw DPRINTFN(2,("ehci_sync_hc: enter\n"));
1346 1.2.4.2 nathanw lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); /* get doorbell */
1347 1.2.4.2 nathanw s = splhardusb();
1348 1.2.4.2 nathanw /* ask for doorbell */
1349 1.2.4.2 nathanw EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD);
1350 1.2.4.2 nathanw DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1351 1.2.4.2 nathanw EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1352 1.2.4.2 nathanw error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */
1353 1.2.4.2 nathanw DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1354 1.2.4.2 nathanw EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1355 1.2.4.2 nathanw splx(s);
1356 1.2.4.2 nathanw lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); /* release doorbell */
1357 1.2.4.2 nathanw #ifdef DIAGNOSTIC
1358 1.2.4.2 nathanw if (error)
1359 1.2.4.2 nathanw printf("ehci_sync_hc: tsleep() = %d\n", error);
1360 1.2.4.2 nathanw #endif
1361 1.2.4.2 nathanw DPRINTFN(2,("ehci_sync_hc: exit\n"));
1362 1.2.4.2 nathanw }
1363 1.2.4.2 nathanw
1364 1.2.4.2 nathanw /***********/
1365 1.2.4.2 nathanw
1366 1.2.4.2 nathanw /*
1367 1.2.4.2 nathanw * Data structures and routines to emulate the root hub.
1368 1.2.4.2 nathanw */
1369 1.2.4.2 nathanw Static usb_device_descriptor_t ehci_devd = {
1370 1.2.4.2 nathanw USB_DEVICE_DESCRIPTOR_SIZE,
1371 1.2.4.2 nathanw UDESC_DEVICE, /* type */
1372 1.2.4.2 nathanw {0x00, 0x02}, /* USB version */
1373 1.2.4.2 nathanw UDCLASS_HUB, /* class */
1374 1.2.4.2 nathanw UDSUBCLASS_HUB, /* subclass */
1375 1.2.4.2 nathanw UDPROTO_HSHUBSTT, /* protocol */
1376 1.2.4.2 nathanw 64, /* max packet */
1377 1.2.4.2 nathanw {0},{0},{0x00,0x01}, /* device id */
1378 1.2.4.2 nathanw 1,2,0, /* string indicies */
1379 1.2.4.2 nathanw 1 /* # of configurations */
1380 1.2.4.2 nathanw };
1381 1.2.4.2 nathanw
1382 1.2.4.2 nathanw Static usb_device_qualifier_t ehci_odevd = {
1383 1.2.4.2 nathanw USB_DEVICE_DESCRIPTOR_SIZE,
1384 1.2.4.2 nathanw UDESC_DEVICE_QUALIFIER, /* type */
1385 1.2.4.2 nathanw {0x00, 0x02}, /* USB version */
1386 1.2.4.2 nathanw UDCLASS_HUB, /* class */
1387 1.2.4.2 nathanw UDSUBCLASS_HUB, /* subclass */
1388 1.2.4.2 nathanw UDPROTO_FSHUB, /* protocol */
1389 1.2.4.2 nathanw 64, /* max packet */
1390 1.2.4.2 nathanw 1, /* # of configurations */
1391 1.2.4.2 nathanw 0
1392 1.2.4.2 nathanw };
1393 1.2.4.2 nathanw
1394 1.2.4.2 nathanw Static usb_config_descriptor_t ehci_confd = {
1395 1.2.4.2 nathanw USB_CONFIG_DESCRIPTOR_SIZE,
1396 1.2.4.2 nathanw UDESC_CONFIG,
1397 1.2.4.2 nathanw {USB_CONFIG_DESCRIPTOR_SIZE +
1398 1.2.4.2 nathanw USB_INTERFACE_DESCRIPTOR_SIZE +
1399 1.2.4.2 nathanw USB_ENDPOINT_DESCRIPTOR_SIZE},
1400 1.2.4.2 nathanw 1,
1401 1.2.4.2 nathanw 1,
1402 1.2.4.2 nathanw 0,
1403 1.2.4.2 nathanw UC_SELF_POWERED,
1404 1.2.4.2 nathanw 0 /* max power */
1405 1.2.4.2 nathanw };
1406 1.2.4.2 nathanw
1407 1.2.4.2 nathanw Static usb_interface_descriptor_t ehci_ifcd = {
1408 1.2.4.2 nathanw USB_INTERFACE_DESCRIPTOR_SIZE,
1409 1.2.4.2 nathanw UDESC_INTERFACE,
1410 1.2.4.2 nathanw 0,
1411 1.2.4.2 nathanw 0,
1412 1.2.4.2 nathanw 1,
1413 1.2.4.2 nathanw UICLASS_HUB,
1414 1.2.4.2 nathanw UISUBCLASS_HUB,
1415 1.2.4.2 nathanw UIPROTO_HSHUBSTT,
1416 1.2.4.2 nathanw 0
1417 1.2.4.2 nathanw };
1418 1.2.4.2 nathanw
1419 1.2.4.2 nathanw Static usb_endpoint_descriptor_t ehci_endpd = {
1420 1.2.4.2 nathanw USB_ENDPOINT_DESCRIPTOR_SIZE,
1421 1.2.4.2 nathanw UDESC_ENDPOINT,
1422 1.2.4.2 nathanw UE_DIR_IN | EHCI_INTR_ENDPT,
1423 1.2.4.2 nathanw UE_INTERRUPT,
1424 1.2.4.2 nathanw {8, 0}, /* max packet */
1425 1.2.4.2 nathanw 255
1426 1.2.4.2 nathanw };
1427 1.2.4.2 nathanw
1428 1.2.4.2 nathanw Static usb_hub_descriptor_t ehci_hubd = {
1429 1.2.4.2 nathanw USB_HUB_DESCRIPTOR_SIZE,
1430 1.2.4.2 nathanw UDESC_HUB,
1431 1.2.4.2 nathanw 0,
1432 1.2.4.2 nathanw {0,0},
1433 1.2.4.2 nathanw 0,
1434 1.2.4.2 nathanw 0,
1435 1.2.4.2 nathanw {0},
1436 1.2.4.2 nathanw };
1437 1.2.4.2 nathanw
1438 1.2.4.2 nathanw Static int
1439 1.2.4.2 nathanw ehci_str(p, l, s)
1440 1.2.4.2 nathanw usb_string_descriptor_t *p;
1441 1.2.4.2 nathanw int l;
1442 1.2.4.2 nathanw char *s;
1443 1.2.4.2 nathanw {
1444 1.2.4.2 nathanw int i;
1445 1.2.4.2 nathanw
1446 1.2.4.2 nathanw if (l == 0)
1447 1.2.4.2 nathanw return (0);
1448 1.2.4.2 nathanw p->bLength = 2 * strlen(s) + 2;
1449 1.2.4.2 nathanw if (l == 1)
1450 1.2.4.2 nathanw return (1);
1451 1.2.4.2 nathanw p->bDescriptorType = UDESC_STRING;
1452 1.2.4.2 nathanw l -= 2;
1453 1.2.4.2 nathanw for (i = 0; s[i] && l > 1; i++, l -= 2)
1454 1.2.4.2 nathanw USETW2(p->bString[i], 0, s[i]);
1455 1.2.4.2 nathanw return (2*i+2);
1456 1.2.4.2 nathanw }
1457 1.2.4.2 nathanw
1458 1.2.4.2 nathanw /*
1459 1.2.4.2 nathanw * Simulate a hardware hub by handling all the necessary requests.
1460 1.2.4.2 nathanw */
1461 1.2.4.2 nathanw Static usbd_status
1462 1.2.4.2 nathanw ehci_root_ctrl_transfer(usbd_xfer_handle xfer)
1463 1.2.4.2 nathanw {
1464 1.2.4.2 nathanw usbd_status err;
1465 1.2.4.2 nathanw
1466 1.2.4.2 nathanw /* Insert last in queue. */
1467 1.2.4.2 nathanw err = usb_insert_transfer(xfer);
1468 1.2.4.2 nathanw if (err)
1469 1.2.4.2 nathanw return (err);
1470 1.2.4.2 nathanw
1471 1.2.4.2 nathanw /* Pipe isn't running, start first */
1472 1.2.4.2 nathanw return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
1473 1.2.4.2 nathanw }
1474 1.2.4.2 nathanw
1475 1.2.4.2 nathanw Static usbd_status
1476 1.2.4.2 nathanw ehci_root_ctrl_start(usbd_xfer_handle xfer)
1477 1.2.4.2 nathanw {
1478 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
1479 1.2.4.2 nathanw usb_device_request_t *req;
1480 1.2.4.2 nathanw void *buf = NULL;
1481 1.2.4.2 nathanw int port, i;
1482 1.2.4.2 nathanw int s, len, value, index, l, totlen = 0;
1483 1.2.4.2 nathanw usb_port_status_t ps;
1484 1.2.4.2 nathanw usb_hub_descriptor_t hubd;
1485 1.2.4.2 nathanw usbd_status err;
1486 1.2.4.2 nathanw u_int32_t v;
1487 1.2.4.2 nathanw
1488 1.2.4.2 nathanw if (sc->sc_dying)
1489 1.2.4.2 nathanw return (USBD_IOERROR);
1490 1.2.4.2 nathanw
1491 1.2.4.2 nathanw #ifdef DIAGNOSTIC
1492 1.2.4.2 nathanw if (!(xfer->rqflags & URQ_REQUEST))
1493 1.2.4.2 nathanw /* XXX panic */
1494 1.2.4.2 nathanw return (USBD_INVAL);
1495 1.2.4.2 nathanw #endif
1496 1.2.4.2 nathanw req = &xfer->request;
1497 1.2.4.2 nathanw
1498 1.2.4.6 nathanw DPRINTFN(4,("ehci_root_ctrl_control type=0x%02x request=%02x\n",
1499 1.2.4.2 nathanw req->bmRequestType, req->bRequest));
1500 1.2.4.2 nathanw
1501 1.2.4.2 nathanw len = UGETW(req->wLength);
1502 1.2.4.2 nathanw value = UGETW(req->wValue);
1503 1.2.4.2 nathanw index = UGETW(req->wIndex);
1504 1.2.4.2 nathanw
1505 1.2.4.2 nathanw if (len != 0)
1506 1.2.4.3 nathanw buf = KERNADDR(&xfer->dmabuf, 0);
1507 1.2.4.2 nathanw
1508 1.2.4.2 nathanw #define C(x,y) ((x) | ((y) << 8))
1509 1.2.4.2 nathanw switch(C(req->bRequest, req->bmRequestType)) {
1510 1.2.4.2 nathanw case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
1511 1.2.4.2 nathanw case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
1512 1.2.4.2 nathanw case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1513 1.2.4.6 nathanw /*
1514 1.2.4.2 nathanw * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
1515 1.2.4.2 nathanw * for the integrated root hub.
1516 1.2.4.2 nathanw */
1517 1.2.4.2 nathanw break;
1518 1.2.4.2 nathanw case C(UR_GET_CONFIG, UT_READ_DEVICE):
1519 1.2.4.2 nathanw if (len > 0) {
1520 1.2.4.2 nathanw *(u_int8_t *)buf = sc->sc_conf;
1521 1.2.4.2 nathanw totlen = 1;
1522 1.2.4.2 nathanw }
1523 1.2.4.2 nathanw break;
1524 1.2.4.2 nathanw case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1525 1.2.4.2 nathanw DPRINTFN(8,("ehci_root_ctrl_control wValue=0x%04x\n", value));
1526 1.2.4.2 nathanw switch(value >> 8) {
1527 1.2.4.2 nathanw case UDESC_DEVICE:
1528 1.2.4.2 nathanw if ((value & 0xff) != 0) {
1529 1.2.4.2 nathanw err = USBD_IOERROR;
1530 1.2.4.2 nathanw goto ret;
1531 1.2.4.2 nathanw }
1532 1.2.4.2 nathanw totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1533 1.2.4.2 nathanw USETW(ehci_devd.idVendor, sc->sc_id_vendor);
1534 1.2.4.2 nathanw memcpy(buf, &ehci_devd, l);
1535 1.2.4.2 nathanw break;
1536 1.2.4.6 nathanw /*
1537 1.2.4.2 nathanw * We can't really operate at another speed, but the spec says
1538 1.2.4.2 nathanw * we need this descriptor.
1539 1.2.4.2 nathanw */
1540 1.2.4.2 nathanw case UDESC_DEVICE_QUALIFIER:
1541 1.2.4.2 nathanw if ((value & 0xff) != 0) {
1542 1.2.4.2 nathanw err = USBD_IOERROR;
1543 1.2.4.2 nathanw goto ret;
1544 1.2.4.2 nathanw }
1545 1.2.4.2 nathanw totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1546 1.2.4.2 nathanw memcpy(buf, &ehci_odevd, l);
1547 1.2.4.2 nathanw break;
1548 1.2.4.6 nathanw /*
1549 1.2.4.2 nathanw * We can't really operate at another speed, but the spec says
1550 1.2.4.2 nathanw * we need this descriptor.
1551 1.2.4.2 nathanw */
1552 1.2.4.2 nathanw case UDESC_OTHER_SPEED_CONFIGURATION:
1553 1.2.4.2 nathanw case UDESC_CONFIG:
1554 1.2.4.2 nathanw if ((value & 0xff) != 0) {
1555 1.2.4.2 nathanw err = USBD_IOERROR;
1556 1.2.4.2 nathanw goto ret;
1557 1.2.4.2 nathanw }
1558 1.2.4.2 nathanw totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
1559 1.2.4.2 nathanw memcpy(buf, &ehci_confd, l);
1560 1.2.4.2 nathanw ((usb_config_descriptor_t *)buf)->bDescriptorType =
1561 1.2.4.2 nathanw value >> 8;
1562 1.2.4.2 nathanw buf = (char *)buf + l;
1563 1.2.4.2 nathanw len -= l;
1564 1.2.4.2 nathanw l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
1565 1.2.4.2 nathanw totlen += l;
1566 1.2.4.2 nathanw memcpy(buf, &ehci_ifcd, l);
1567 1.2.4.2 nathanw buf = (char *)buf + l;
1568 1.2.4.2 nathanw len -= l;
1569 1.2.4.2 nathanw l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
1570 1.2.4.2 nathanw totlen += l;
1571 1.2.4.2 nathanw memcpy(buf, &ehci_endpd, l);
1572 1.2.4.2 nathanw break;
1573 1.2.4.2 nathanw case UDESC_STRING:
1574 1.2.4.2 nathanw if (len == 0)
1575 1.2.4.2 nathanw break;
1576 1.2.4.2 nathanw *(u_int8_t *)buf = 0;
1577 1.2.4.2 nathanw totlen = 1;
1578 1.2.4.2 nathanw switch (value & 0xff) {
1579 1.2.4.2 nathanw case 1: /* Vendor */
1580 1.2.4.2 nathanw totlen = ehci_str(buf, len, sc->sc_vendor);
1581 1.2.4.2 nathanw break;
1582 1.2.4.2 nathanw case 2: /* Product */
1583 1.2.4.2 nathanw totlen = ehci_str(buf, len, "EHCI root hub");
1584 1.2.4.2 nathanw break;
1585 1.2.4.2 nathanw }
1586 1.2.4.2 nathanw break;
1587 1.2.4.2 nathanw default:
1588 1.2.4.2 nathanw err = USBD_IOERROR;
1589 1.2.4.2 nathanw goto ret;
1590 1.2.4.2 nathanw }
1591 1.2.4.2 nathanw break;
1592 1.2.4.2 nathanw case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
1593 1.2.4.2 nathanw if (len > 0) {
1594 1.2.4.2 nathanw *(u_int8_t *)buf = 0;
1595 1.2.4.2 nathanw totlen = 1;
1596 1.2.4.2 nathanw }
1597 1.2.4.2 nathanw break;
1598 1.2.4.2 nathanw case C(UR_GET_STATUS, UT_READ_DEVICE):
1599 1.2.4.2 nathanw if (len > 1) {
1600 1.2.4.2 nathanw USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
1601 1.2.4.2 nathanw totlen = 2;
1602 1.2.4.2 nathanw }
1603 1.2.4.2 nathanw break;
1604 1.2.4.2 nathanw case C(UR_GET_STATUS, UT_READ_INTERFACE):
1605 1.2.4.2 nathanw case C(UR_GET_STATUS, UT_READ_ENDPOINT):
1606 1.2.4.2 nathanw if (len > 1) {
1607 1.2.4.2 nathanw USETW(((usb_status_t *)buf)->wStatus, 0);
1608 1.2.4.2 nathanw totlen = 2;
1609 1.2.4.2 nathanw }
1610 1.2.4.2 nathanw break;
1611 1.2.4.2 nathanw case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
1612 1.2.4.2 nathanw if (value >= USB_MAX_DEVICES) {
1613 1.2.4.2 nathanw err = USBD_IOERROR;
1614 1.2.4.2 nathanw goto ret;
1615 1.2.4.2 nathanw }
1616 1.2.4.2 nathanw sc->sc_addr = value;
1617 1.2.4.2 nathanw break;
1618 1.2.4.2 nathanw case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
1619 1.2.4.2 nathanw if (value != 0 && value != 1) {
1620 1.2.4.2 nathanw err = USBD_IOERROR;
1621 1.2.4.2 nathanw goto ret;
1622 1.2.4.2 nathanw }
1623 1.2.4.2 nathanw sc->sc_conf = value;
1624 1.2.4.2 nathanw break;
1625 1.2.4.2 nathanw case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
1626 1.2.4.2 nathanw break;
1627 1.2.4.2 nathanw case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
1628 1.2.4.2 nathanw case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
1629 1.2.4.2 nathanw case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
1630 1.2.4.2 nathanw err = USBD_IOERROR;
1631 1.2.4.2 nathanw goto ret;
1632 1.2.4.2 nathanw case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
1633 1.2.4.2 nathanw break;
1634 1.2.4.2 nathanw case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
1635 1.2.4.2 nathanw break;
1636 1.2.4.2 nathanw /* Hub requests */
1637 1.2.4.2 nathanw case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
1638 1.2.4.2 nathanw break;
1639 1.2.4.2 nathanw case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1640 1.2.4.2 nathanw DPRINTFN(8, ("ehci_root_ctrl_control: UR_CLEAR_PORT_FEATURE "
1641 1.2.4.2 nathanw "port=%d feature=%d\n",
1642 1.2.4.2 nathanw index, value));
1643 1.2.4.2 nathanw if (index < 1 || index > sc->sc_noport) {
1644 1.2.4.2 nathanw err = USBD_IOERROR;
1645 1.2.4.2 nathanw goto ret;
1646 1.2.4.2 nathanw }
1647 1.2.4.2 nathanw port = EHCI_PORTSC(index);
1648 1.2.4.2 nathanw v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1649 1.2.4.2 nathanw switch(value) {
1650 1.2.4.2 nathanw case UHF_PORT_ENABLE:
1651 1.2.4.2 nathanw EOWRITE4(sc, port, v &~ EHCI_PS_PE);
1652 1.2.4.2 nathanw break;
1653 1.2.4.2 nathanw case UHF_PORT_SUSPEND:
1654 1.2.4.2 nathanw EOWRITE4(sc, port, v &~ EHCI_PS_SUSP);
1655 1.2.4.2 nathanw break;
1656 1.2.4.2 nathanw case UHF_PORT_POWER:
1657 1.2.4.2 nathanw EOWRITE4(sc, port, v &~ EHCI_PS_PP);
1658 1.2.4.2 nathanw break;
1659 1.2.4.2 nathanw case UHF_PORT_TEST:
1660 1.2.4.2 nathanw DPRINTFN(2,("ehci_root_ctrl_transfer: clear port test "
1661 1.2.4.2 nathanw "%d\n", index));
1662 1.2.4.2 nathanw break;
1663 1.2.4.2 nathanw case UHF_PORT_INDICATOR:
1664 1.2.4.2 nathanw DPRINTFN(2,("ehci_root_ctrl_transfer: clear port ind "
1665 1.2.4.2 nathanw "%d\n", index));
1666 1.2.4.2 nathanw EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
1667 1.2.4.2 nathanw break;
1668 1.2.4.2 nathanw case UHF_C_PORT_CONNECTION:
1669 1.2.4.2 nathanw EOWRITE4(sc, port, v | EHCI_PS_CSC);
1670 1.2.4.2 nathanw break;
1671 1.2.4.2 nathanw case UHF_C_PORT_ENABLE:
1672 1.2.4.2 nathanw EOWRITE4(sc, port, v | EHCI_PS_PEC);
1673 1.2.4.2 nathanw break;
1674 1.2.4.2 nathanw case UHF_C_PORT_SUSPEND:
1675 1.2.4.2 nathanw /* how? */
1676 1.2.4.2 nathanw break;
1677 1.2.4.2 nathanw case UHF_C_PORT_OVER_CURRENT:
1678 1.2.4.2 nathanw EOWRITE4(sc, port, v | EHCI_PS_OCC);
1679 1.2.4.2 nathanw break;
1680 1.2.4.2 nathanw case UHF_C_PORT_RESET:
1681 1.2.4.2 nathanw sc->sc_isreset = 0;
1682 1.2.4.2 nathanw break;
1683 1.2.4.2 nathanw default:
1684 1.2.4.2 nathanw err = USBD_IOERROR;
1685 1.2.4.2 nathanw goto ret;
1686 1.2.4.2 nathanw }
1687 1.2.4.2 nathanw #if 0
1688 1.2.4.2 nathanw switch(value) {
1689 1.2.4.2 nathanw case UHF_C_PORT_CONNECTION:
1690 1.2.4.2 nathanw case UHF_C_PORT_ENABLE:
1691 1.2.4.2 nathanw case UHF_C_PORT_SUSPEND:
1692 1.2.4.2 nathanw case UHF_C_PORT_OVER_CURRENT:
1693 1.2.4.2 nathanw case UHF_C_PORT_RESET:
1694 1.2.4.2 nathanw /* Enable RHSC interrupt if condition is cleared. */
1695 1.2.4.2 nathanw if ((OREAD4(sc, port) >> 16) == 0)
1696 1.2.4.2 nathanw ehci_pcd_able(sc, 1);
1697 1.2.4.2 nathanw break;
1698 1.2.4.2 nathanw default:
1699 1.2.4.2 nathanw break;
1700 1.2.4.2 nathanw }
1701 1.2.4.2 nathanw #endif
1702 1.2.4.2 nathanw break;
1703 1.2.4.2 nathanw case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1704 1.2.4.2 nathanw if (value != 0) {
1705 1.2.4.2 nathanw err = USBD_IOERROR;
1706 1.2.4.2 nathanw goto ret;
1707 1.2.4.2 nathanw }
1708 1.2.4.2 nathanw hubd = ehci_hubd;
1709 1.2.4.2 nathanw hubd.bNbrPorts = sc->sc_noport;
1710 1.2.4.2 nathanw v = EOREAD4(sc, EHCI_HCSPARAMS);
1711 1.2.4.2 nathanw USETW(hubd.wHubCharacteristics,
1712 1.2.4.2 nathanw EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH |
1713 1.2.4.2 nathanw EHCI_HCS_P_INCICATOR(EREAD4(sc, EHCI_HCSPARAMS))
1714 1.2.4.2 nathanw ? UHD_PORT_IND : 0);
1715 1.2.4.2 nathanw hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */
1716 1.2.4.6 nathanw for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
1717 1.2.4.2 nathanw hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
1718 1.2.4.2 nathanw hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
1719 1.2.4.2 nathanw l = min(len, hubd.bDescLength);
1720 1.2.4.2 nathanw totlen = l;
1721 1.2.4.2 nathanw memcpy(buf, &hubd, l);
1722 1.2.4.2 nathanw break;
1723 1.2.4.2 nathanw case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
1724 1.2.4.2 nathanw if (len != 4) {
1725 1.2.4.2 nathanw err = USBD_IOERROR;
1726 1.2.4.2 nathanw goto ret;
1727 1.2.4.2 nathanw }
1728 1.2.4.2 nathanw memset(buf, 0, len); /* ? XXX */
1729 1.2.4.2 nathanw totlen = len;
1730 1.2.4.2 nathanw break;
1731 1.2.4.2 nathanw case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1732 1.2.4.2 nathanw DPRINTFN(8,("ehci_root_ctrl_transfer: get port status i=%d\n",
1733 1.2.4.2 nathanw index));
1734 1.2.4.2 nathanw if (index < 1 || index > sc->sc_noport) {
1735 1.2.4.2 nathanw err = USBD_IOERROR;
1736 1.2.4.2 nathanw goto ret;
1737 1.2.4.2 nathanw }
1738 1.2.4.2 nathanw if (len != 4) {
1739 1.2.4.2 nathanw err = USBD_IOERROR;
1740 1.2.4.2 nathanw goto ret;
1741 1.2.4.2 nathanw }
1742 1.2.4.2 nathanw v = EOREAD4(sc, EHCI_PORTSC(index));
1743 1.2.4.2 nathanw DPRINTFN(8,("ehci_root_ctrl_transfer: port status=0x%04x\n",
1744 1.2.4.2 nathanw v));
1745 1.2.4.2 nathanw i = UPS_HIGH_SPEED;
1746 1.2.4.2 nathanw if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
1747 1.2.4.2 nathanw if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
1748 1.2.4.2 nathanw if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
1749 1.2.4.2 nathanw if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
1750 1.2.4.2 nathanw if (v & EHCI_PS_PR) i |= UPS_RESET;
1751 1.2.4.2 nathanw if (v & EHCI_PS_PP) i |= UPS_PORT_POWER;
1752 1.2.4.2 nathanw USETW(ps.wPortStatus, i);
1753 1.2.4.2 nathanw i = 0;
1754 1.2.4.2 nathanw if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
1755 1.2.4.2 nathanw if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
1756 1.2.4.2 nathanw if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
1757 1.2.4.2 nathanw if (sc->sc_isreset) i |= UPS_C_PORT_RESET;
1758 1.2.4.2 nathanw USETW(ps.wPortChange, i);
1759 1.2.4.2 nathanw l = min(len, sizeof ps);
1760 1.2.4.2 nathanw memcpy(buf, &ps, l);
1761 1.2.4.2 nathanw totlen = l;
1762 1.2.4.2 nathanw break;
1763 1.2.4.2 nathanw case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1764 1.2.4.2 nathanw err = USBD_IOERROR;
1765 1.2.4.2 nathanw goto ret;
1766 1.2.4.2 nathanw case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
1767 1.2.4.2 nathanw break;
1768 1.2.4.2 nathanw case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
1769 1.2.4.2 nathanw if (index < 1 || index > sc->sc_noport) {
1770 1.2.4.2 nathanw err = USBD_IOERROR;
1771 1.2.4.2 nathanw goto ret;
1772 1.2.4.2 nathanw }
1773 1.2.4.2 nathanw port = EHCI_PORTSC(index);
1774 1.2.4.2 nathanw v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1775 1.2.4.2 nathanw switch(value) {
1776 1.2.4.2 nathanw case UHF_PORT_ENABLE:
1777 1.2.4.2 nathanw EOWRITE4(sc, port, v | EHCI_PS_PE);
1778 1.2.4.2 nathanw break;
1779 1.2.4.2 nathanw case UHF_PORT_SUSPEND:
1780 1.2.4.2 nathanw EOWRITE4(sc, port, v | EHCI_PS_SUSP);
1781 1.2.4.2 nathanw break;
1782 1.2.4.2 nathanw case UHF_PORT_RESET:
1783 1.2.4.2 nathanw DPRINTFN(5,("ehci_root_ctrl_transfer: reset port %d\n",
1784 1.2.4.2 nathanw index));
1785 1.2.4.2 nathanw if (EHCI_PS_IS_LOWSPEED(v)) {
1786 1.2.4.2 nathanw /* Low speed device, give up ownership. */
1787 1.2.4.2 nathanw ehci_disown(sc, index, 1);
1788 1.2.4.2 nathanw break;
1789 1.2.4.2 nathanw }
1790 1.2.4.2 nathanw /* Start reset sequence. */
1791 1.2.4.2 nathanw v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
1792 1.2.4.2 nathanw EOWRITE4(sc, port, v | EHCI_PS_PR);
1793 1.2.4.2 nathanw /* Wait for reset to complete. */
1794 1.2.4.2 nathanw usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
1795 1.2.4.2 nathanw if (sc->sc_dying) {
1796 1.2.4.2 nathanw err = USBD_IOERROR;
1797 1.2.4.2 nathanw goto ret;
1798 1.2.4.2 nathanw }
1799 1.2.4.2 nathanw /* Terminate reset sequence. */
1800 1.2.4.2 nathanw EOWRITE4(sc, port, v);
1801 1.2.4.2 nathanw /* Wait for HC to complete reset. */
1802 1.2.4.2 nathanw usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE);
1803 1.2.4.2 nathanw if (sc->sc_dying) {
1804 1.2.4.2 nathanw err = USBD_IOERROR;
1805 1.2.4.2 nathanw goto ret;
1806 1.2.4.2 nathanw }
1807 1.2.4.2 nathanw v = EOREAD4(sc, port);
1808 1.2.4.2 nathanw DPRINTF(("ehci after reset, status=0x%08x\n", v));
1809 1.2.4.2 nathanw if (v & EHCI_PS_PR) {
1810 1.2.4.2 nathanw printf("%s: port reset timeout\n",
1811 1.2.4.2 nathanw USBDEVNAME(sc->sc_bus.bdev));
1812 1.2.4.2 nathanw return (USBD_TIMEOUT);
1813 1.2.4.2 nathanw }
1814 1.2.4.2 nathanw if (!(v & EHCI_PS_PE)) {
1815 1.2.4.2 nathanw /* Not a high speed device, give up ownership.*/
1816 1.2.4.2 nathanw ehci_disown(sc, index, 0);
1817 1.2.4.2 nathanw break;
1818 1.2.4.2 nathanw }
1819 1.2.4.2 nathanw sc->sc_isreset = 1;
1820 1.2.4.2 nathanw DPRINTF(("ehci port %d reset, status = 0x%08x\n",
1821 1.2.4.2 nathanw index, v));
1822 1.2.4.2 nathanw break;
1823 1.2.4.2 nathanw case UHF_PORT_POWER:
1824 1.2.4.2 nathanw DPRINTFN(2,("ehci_root_ctrl_transfer: set port power "
1825 1.2.4.2 nathanw "%d\n", index));
1826 1.2.4.2 nathanw EOWRITE4(sc, port, v | EHCI_PS_PP);
1827 1.2.4.2 nathanw break;
1828 1.2.4.2 nathanw case UHF_PORT_TEST:
1829 1.2.4.2 nathanw DPRINTFN(2,("ehci_root_ctrl_transfer: set port test "
1830 1.2.4.2 nathanw "%d\n", index));
1831 1.2.4.2 nathanw break;
1832 1.2.4.2 nathanw case UHF_PORT_INDICATOR:
1833 1.2.4.2 nathanw DPRINTFN(2,("ehci_root_ctrl_transfer: set port ind "
1834 1.2.4.2 nathanw "%d\n", index));
1835 1.2.4.2 nathanw EOWRITE4(sc, port, v | EHCI_PS_PIC);
1836 1.2.4.2 nathanw break;
1837 1.2.4.2 nathanw default:
1838 1.2.4.2 nathanw err = USBD_IOERROR;
1839 1.2.4.2 nathanw goto ret;
1840 1.2.4.2 nathanw }
1841 1.2.4.2 nathanw break;
1842 1.2.4.2 nathanw case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
1843 1.2.4.2 nathanw case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
1844 1.2.4.2 nathanw case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
1845 1.2.4.2 nathanw case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
1846 1.2.4.2 nathanw break;
1847 1.2.4.2 nathanw default:
1848 1.2.4.2 nathanw err = USBD_IOERROR;
1849 1.2.4.2 nathanw goto ret;
1850 1.2.4.2 nathanw }
1851 1.2.4.2 nathanw xfer->actlen = totlen;
1852 1.2.4.2 nathanw err = USBD_NORMAL_COMPLETION;
1853 1.2.4.2 nathanw ret:
1854 1.2.4.2 nathanw xfer->status = err;
1855 1.2.4.2 nathanw s = splusb();
1856 1.2.4.2 nathanw usb_transfer_complete(xfer);
1857 1.2.4.2 nathanw splx(s);
1858 1.2.4.2 nathanw return (USBD_IN_PROGRESS);
1859 1.2.4.2 nathanw }
1860 1.2.4.2 nathanw
1861 1.2.4.2 nathanw void
1862 1.2.4.2 nathanw ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
1863 1.2.4.2 nathanw {
1864 1.2.4.2 nathanw int port;
1865 1.2.4.2 nathanw u_int32_t v;
1866 1.2.4.2 nathanw
1867 1.2.4.2 nathanw DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed));
1868 1.2.4.2 nathanw #ifdef DIAGNOSTIC
1869 1.2.4.2 nathanw if (sc->sc_npcomp != 0) {
1870 1.2.4.2 nathanw int i = (index-1) / sc->sc_npcomp;
1871 1.2.4.2 nathanw if (i >= sc->sc_ncomp)
1872 1.2.4.2 nathanw printf("%s: strange port\n",
1873 1.2.4.2 nathanw USBDEVNAME(sc->sc_bus.bdev));
1874 1.2.4.2 nathanw else
1875 1.2.4.2 nathanw printf("%s: handing over %s speed device on "
1876 1.2.4.2 nathanw "port %d to %s\n",
1877 1.2.4.2 nathanw USBDEVNAME(sc->sc_bus.bdev),
1878 1.2.4.2 nathanw lowspeed ? "low" : "full",
1879 1.2.4.2 nathanw index, USBDEVNAME(sc->sc_comps[i]->bdev));
1880 1.2.4.2 nathanw } else {
1881 1.2.4.2 nathanw printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev));
1882 1.2.4.2 nathanw }
1883 1.2.4.2 nathanw #endif
1884 1.2.4.2 nathanw port = EHCI_PORTSC(index);
1885 1.2.4.2 nathanw v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1886 1.2.4.2 nathanw EOWRITE4(sc, port, v | EHCI_PS_PO);
1887 1.2.4.2 nathanw }
1888 1.2.4.2 nathanw
1889 1.2.4.2 nathanw /* Abort a root control request. */
1890 1.2.4.2 nathanw Static void
1891 1.2.4.2 nathanw ehci_root_ctrl_abort(usbd_xfer_handle xfer)
1892 1.2.4.2 nathanw {
1893 1.2.4.2 nathanw /* Nothing to do, all transfers are synchronous. */
1894 1.2.4.2 nathanw }
1895 1.2.4.2 nathanw
1896 1.2.4.2 nathanw /* Close the root pipe. */
1897 1.2.4.2 nathanw Static void
1898 1.2.4.2 nathanw ehci_root_ctrl_close(usbd_pipe_handle pipe)
1899 1.2.4.2 nathanw {
1900 1.2.4.2 nathanw DPRINTF(("ehci_root_ctrl_close\n"));
1901 1.2.4.2 nathanw /* Nothing to do. */
1902 1.2.4.2 nathanw }
1903 1.2.4.2 nathanw
1904 1.2.4.2 nathanw void
1905 1.2.4.2 nathanw ehci_root_intr_done(usbd_xfer_handle xfer)
1906 1.2.4.2 nathanw {
1907 1.2.4.2 nathanw xfer->hcpriv = NULL;
1908 1.2.4.2 nathanw }
1909 1.2.4.2 nathanw
1910 1.2.4.2 nathanw Static usbd_status
1911 1.2.4.2 nathanw ehci_root_intr_transfer(usbd_xfer_handle xfer)
1912 1.2.4.2 nathanw {
1913 1.2.4.2 nathanw usbd_status err;
1914 1.2.4.2 nathanw
1915 1.2.4.2 nathanw /* Insert last in queue. */
1916 1.2.4.2 nathanw err = usb_insert_transfer(xfer);
1917 1.2.4.2 nathanw if (err)
1918 1.2.4.2 nathanw return (err);
1919 1.2.4.2 nathanw
1920 1.2.4.2 nathanw /* Pipe isn't running, start first */
1921 1.2.4.2 nathanw return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
1922 1.2.4.2 nathanw }
1923 1.2.4.2 nathanw
1924 1.2.4.2 nathanw Static usbd_status
1925 1.2.4.2 nathanw ehci_root_intr_start(usbd_xfer_handle xfer)
1926 1.2.4.2 nathanw {
1927 1.2.4.2 nathanw usbd_pipe_handle pipe = xfer->pipe;
1928 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
1929 1.2.4.2 nathanw
1930 1.2.4.2 nathanw if (sc->sc_dying)
1931 1.2.4.2 nathanw return (USBD_IOERROR);
1932 1.2.4.2 nathanw
1933 1.2.4.2 nathanw sc->sc_intrxfer = xfer;
1934 1.2.4.2 nathanw
1935 1.2.4.2 nathanw return (USBD_IN_PROGRESS);
1936 1.2.4.2 nathanw }
1937 1.2.4.2 nathanw
1938 1.2.4.2 nathanw /* Abort a root interrupt request. */
1939 1.2.4.2 nathanw Static void
1940 1.2.4.2 nathanw ehci_root_intr_abort(usbd_xfer_handle xfer)
1941 1.2.4.2 nathanw {
1942 1.2.4.2 nathanw int s;
1943 1.2.4.2 nathanw
1944 1.2.4.2 nathanw if (xfer->pipe->intrxfer == xfer) {
1945 1.2.4.2 nathanw DPRINTF(("ehci_root_intr_abort: remove\n"));
1946 1.2.4.2 nathanw xfer->pipe->intrxfer = NULL;
1947 1.2.4.2 nathanw }
1948 1.2.4.2 nathanw xfer->status = USBD_CANCELLED;
1949 1.2.4.2 nathanw s = splusb();
1950 1.2.4.2 nathanw usb_transfer_complete(xfer);
1951 1.2.4.2 nathanw splx(s);
1952 1.2.4.2 nathanw }
1953 1.2.4.2 nathanw
1954 1.2.4.2 nathanw /* Close the root pipe. */
1955 1.2.4.2 nathanw Static void
1956 1.2.4.2 nathanw ehci_root_intr_close(usbd_pipe_handle pipe)
1957 1.2.4.2 nathanw {
1958 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
1959 1.2.4.6 nathanw
1960 1.2.4.2 nathanw DPRINTF(("ehci_root_intr_close\n"));
1961 1.2.4.2 nathanw
1962 1.2.4.2 nathanw sc->sc_intrxfer = NULL;
1963 1.2.4.2 nathanw }
1964 1.2.4.2 nathanw
1965 1.2.4.2 nathanw void
1966 1.2.4.2 nathanw ehci_root_ctrl_done(usbd_xfer_handle xfer)
1967 1.2.4.2 nathanw {
1968 1.2.4.2 nathanw xfer->hcpriv = NULL;
1969 1.2.4.2 nathanw }
1970 1.2.4.2 nathanw
1971 1.2.4.2 nathanw /************************/
1972 1.2.4.2 nathanw
1973 1.2.4.2 nathanw ehci_soft_qh_t *
1974 1.2.4.2 nathanw ehci_alloc_sqh(ehci_softc_t *sc)
1975 1.2.4.2 nathanw {
1976 1.2.4.2 nathanw ehci_soft_qh_t *sqh;
1977 1.2.4.2 nathanw usbd_status err;
1978 1.2.4.2 nathanw int i, offs;
1979 1.2.4.2 nathanw usb_dma_t dma;
1980 1.2.4.2 nathanw
1981 1.2.4.2 nathanw if (sc->sc_freeqhs == NULL) {
1982 1.2.4.2 nathanw DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n"));
1983 1.2.4.2 nathanw err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK,
1984 1.2.4.2 nathanw EHCI_PAGE_SIZE, &dma);
1985 1.2.4.2 nathanw #ifdef EHCI_DEBUG
1986 1.2.4.2 nathanw if (err)
1987 1.2.4.2 nathanw printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err);
1988 1.2.4.2 nathanw #endif
1989 1.2.4.2 nathanw if (err)
1990 1.2.4.2 nathanw return (NULL);
1991 1.2.4.2 nathanw for(i = 0; i < EHCI_SQH_CHUNK; i++) {
1992 1.2.4.2 nathanw offs = i * EHCI_SQH_SIZE;
1993 1.2.4.3 nathanw sqh = KERNADDR(&dma, offs);
1994 1.2.4.3 nathanw sqh->physaddr = DMAADDR(&dma, offs);
1995 1.2.4.2 nathanw sqh->next = sc->sc_freeqhs;
1996 1.2.4.2 nathanw sc->sc_freeqhs = sqh;
1997 1.2.4.2 nathanw }
1998 1.2.4.2 nathanw }
1999 1.2.4.2 nathanw sqh = sc->sc_freeqhs;
2000 1.2.4.2 nathanw sc->sc_freeqhs = sqh->next;
2001 1.2.4.2 nathanw memset(&sqh->qh, 0, sizeof(ehci_qh_t));
2002 1.2.4.2 nathanw sqh->next = NULL;
2003 1.2.4.2 nathanw return (sqh);
2004 1.2.4.2 nathanw }
2005 1.2.4.2 nathanw
2006 1.2.4.2 nathanw void
2007 1.2.4.2 nathanw ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
2008 1.2.4.2 nathanw {
2009 1.2.4.2 nathanw sqh->next = sc->sc_freeqhs;
2010 1.2.4.2 nathanw sc->sc_freeqhs = sqh;
2011 1.2.4.2 nathanw }
2012 1.2.4.2 nathanw
2013 1.2.4.2 nathanw ehci_soft_qtd_t *
2014 1.2.4.2 nathanw ehci_alloc_sqtd(ehci_softc_t *sc)
2015 1.2.4.2 nathanw {
2016 1.2.4.2 nathanw ehci_soft_qtd_t *sqtd;
2017 1.2.4.2 nathanw usbd_status err;
2018 1.2.4.2 nathanw int i, offs;
2019 1.2.4.2 nathanw usb_dma_t dma;
2020 1.2.4.2 nathanw int s;
2021 1.2.4.2 nathanw
2022 1.2.4.2 nathanw if (sc->sc_freeqtds == NULL) {
2023 1.2.4.2 nathanw DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n"));
2024 1.2.4.2 nathanw err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK,
2025 1.2.4.2 nathanw EHCI_PAGE_SIZE, &dma);
2026 1.2.4.2 nathanw #ifdef EHCI_DEBUG
2027 1.2.4.2 nathanw if (err)
2028 1.2.4.2 nathanw printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err);
2029 1.2.4.2 nathanw #endif
2030 1.2.4.2 nathanw if (err)
2031 1.2.4.2 nathanw return (NULL);
2032 1.2.4.2 nathanw s = splusb();
2033 1.2.4.2 nathanw for(i = 0; i < EHCI_SQTD_CHUNK; i++) {
2034 1.2.4.2 nathanw offs = i * EHCI_SQTD_SIZE;
2035 1.2.4.3 nathanw sqtd = KERNADDR(&dma, offs);
2036 1.2.4.3 nathanw sqtd->physaddr = DMAADDR(&dma, offs);
2037 1.2.4.2 nathanw sqtd->nextqtd = sc->sc_freeqtds;
2038 1.2.4.2 nathanw sc->sc_freeqtds = sqtd;
2039 1.2.4.2 nathanw }
2040 1.2.4.2 nathanw splx(s);
2041 1.2.4.2 nathanw }
2042 1.2.4.2 nathanw
2043 1.2.4.2 nathanw s = splusb();
2044 1.2.4.2 nathanw sqtd = sc->sc_freeqtds;
2045 1.2.4.2 nathanw sc->sc_freeqtds = sqtd->nextqtd;
2046 1.2.4.2 nathanw memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t));
2047 1.2.4.2 nathanw sqtd->nextqtd = NULL;
2048 1.2.4.2 nathanw sqtd->xfer = NULL;
2049 1.2.4.2 nathanw splx(s);
2050 1.2.4.2 nathanw
2051 1.2.4.2 nathanw return (sqtd);
2052 1.2.4.2 nathanw }
2053 1.2.4.2 nathanw
2054 1.2.4.2 nathanw void
2055 1.2.4.2 nathanw ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
2056 1.2.4.2 nathanw {
2057 1.2.4.2 nathanw int s;
2058 1.2.4.2 nathanw
2059 1.2.4.2 nathanw s = splusb();
2060 1.2.4.2 nathanw sqtd->nextqtd = sc->sc_freeqtds;
2061 1.2.4.2 nathanw sc->sc_freeqtds = sqtd;
2062 1.2.4.2 nathanw splx(s);
2063 1.2.4.2 nathanw }
2064 1.2.4.2 nathanw
2065 1.2.4.2 nathanw usbd_status
2066 1.2.4.2 nathanw ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc,
2067 1.2.4.2 nathanw int alen, int rd, usbd_xfer_handle xfer,
2068 1.2.4.2 nathanw ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep)
2069 1.2.4.2 nathanw {
2070 1.2.4.2 nathanw ehci_soft_qtd_t *next, *cur;
2071 1.2.4.2 nathanw ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys;
2072 1.2.4.2 nathanw u_int32_t qtdstatus;
2073 1.2.4.2 nathanw int len, curlen;
2074 1.2.4.2 nathanw int i;
2075 1.2.4.2 nathanw usb_dma_t *dma = &xfer->dmabuf;
2076 1.2.4.2 nathanw
2077 1.2.4.2 nathanw DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen));
2078 1.2.4.2 nathanw
2079 1.2.4.2 nathanw len = alen;
2080 1.2.4.3 nathanw dataphys = DMAADDR(dma, 0);
2081 1.2.4.2 nathanw dataphyslastpage = EHCI_PAGE(dataphys + len - 1);
2082 1.2.4.2 nathanw qtdstatus = htole32(
2083 1.2.4.2 nathanw EHCI_QTD_ACTIVE |
2084 1.2.4.2 nathanw EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
2085 1.2.4.2 nathanw EHCI_QTD_SET_CERR(3)
2086 1.2.4.2 nathanw /* IOC set below */
2087 1.2.4.2 nathanw /* BYTES set below */
2088 1.2.4.2 nathanw /* XXX Data toggle */
2089 1.2.4.2 nathanw );
2090 1.2.4.2 nathanw
2091 1.2.4.2 nathanw cur = ehci_alloc_sqtd(sc);
2092 1.2.4.2 nathanw *sp = cur;
2093 1.2.4.2 nathanw if (cur == NULL)
2094 1.2.4.2 nathanw goto nomem;
2095 1.2.4.2 nathanw for (;;) {
2096 1.2.4.2 nathanw dataphyspage = EHCI_PAGE(dataphys);
2097 1.2.4.2 nathanw /* The EHCI hardware can handle at most 5 pages. */
2098 1.2.4.6 nathanw if (dataphyslastpage - dataphyspage <
2099 1.2.4.2 nathanw EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) {
2100 1.2.4.2 nathanw /* we can handle it in this QTD */
2101 1.2.4.2 nathanw curlen = len;
2102 1.2.4.2 nathanw } else {
2103 1.2.4.2 nathanw /* must use multiple TDs, fill as much as possible. */
2104 1.2.4.6 nathanw curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE -
2105 1.2.4.2 nathanw EHCI_PAGE_OFFSET(dataphys);
2106 1.2.4.2 nathanw #ifdef DIAGNOSTIC
2107 1.2.4.2 nathanw if (curlen > len) {
2108 1.2.4.2 nathanw printf("ehci_alloc_sqtd_chain: curlen=0x%x "
2109 1.2.4.2 nathanw "len=0x%x offs=0x%x\n", curlen, len,
2110 1.2.4.2 nathanw EHCI_PAGE_OFFSET(dataphys));
2111 1.2.4.2 nathanw printf("lastpage=0x%x page=0x%x phys=0x%x\n",
2112 1.2.4.2 nathanw dataphyslastpage, dataphyspage,
2113 1.2.4.2 nathanw dataphys);
2114 1.2.4.2 nathanw curlen = len;
2115 1.2.4.2 nathanw }
2116 1.2.4.2 nathanw #endif
2117 1.2.4.2 nathanw
2118 1.2.4.2 nathanw /* XXX true for EHCI? */
2119 1.2.4.2 nathanw /* the length must be a multiple of the max size */
2120 1.2.4.2 nathanw curlen -= curlen % UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize);
2121 1.2.4.2 nathanw DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, "
2122 1.2.4.2 nathanw "curlen=%d\n", curlen));
2123 1.2.4.2 nathanw #ifdef DIAGNOSTIC
2124 1.2.4.2 nathanw if (curlen == 0)
2125 1.2.4.8 nathanw panic("ehci_alloc_std: curlen == 0");
2126 1.2.4.2 nathanw #endif
2127 1.2.4.2 nathanw }
2128 1.2.4.2 nathanw DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x "
2129 1.2.4.2 nathanw "dataphyslastpage=0x%08x len=%d curlen=%d\n",
2130 1.2.4.2 nathanw dataphys, dataphyslastpage,
2131 1.2.4.2 nathanw len, curlen));
2132 1.2.4.2 nathanw len -= curlen;
2133 1.2.4.2 nathanw
2134 1.2.4.2 nathanw if (len != 0) {
2135 1.2.4.2 nathanw next = ehci_alloc_sqtd(sc);
2136 1.2.4.2 nathanw if (next == NULL)
2137 1.2.4.2 nathanw goto nomem;
2138 1.2.4.2 nathanw nextphys = next->physaddr;
2139 1.2.4.2 nathanw } else {
2140 1.2.4.2 nathanw next = NULL;
2141 1.2.4.2 nathanw nextphys = EHCI_NULL;
2142 1.2.4.2 nathanw }
2143 1.2.4.2 nathanw
2144 1.2.4.2 nathanw for (i = 0; i * EHCI_PAGE_SIZE < curlen; i++) {
2145 1.2.4.2 nathanw ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE;
2146 1.2.4.2 nathanw if (i != 0) /* use offset only in first buffer */
2147 1.2.4.2 nathanw a = EHCI_PAGE(a);
2148 1.2.4.2 nathanw cur->qtd.qtd_buffer[i] = htole32(a);
2149 1.2.4.2 nathanw #ifdef DIAGNOSTIC
2150 1.2.4.2 nathanw if (i >= EHCI_QTD_NBUFFERS) {
2151 1.2.4.2 nathanw printf("ehci_alloc_sqtd_chain: i=%d\n", i);
2152 1.2.4.2 nathanw goto nomem;
2153 1.2.4.2 nathanw }
2154 1.2.4.2 nathanw #endif
2155 1.2.4.2 nathanw }
2156 1.2.4.2 nathanw cur->nextqtd = next;
2157 1.2.4.2 nathanw cur->qtd.qtd_next = cur->qtd.qtd_altnext = htole32(nextphys);
2158 1.2.4.2 nathanw cur->qtd.qtd_status =
2159 1.2.4.2 nathanw qtdstatus | htole32(EHCI_QTD_SET_BYTES(curlen));
2160 1.2.4.2 nathanw cur->xfer = xfer;
2161 1.2.4.2 nathanw cur->len = curlen;
2162 1.2.4.2 nathanw DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n",
2163 1.2.4.2 nathanw dataphys, dataphys + curlen));
2164 1.2.4.2 nathanw if (len == 0)
2165 1.2.4.2 nathanw break;
2166 1.2.4.2 nathanw DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n"));
2167 1.2.4.2 nathanw dataphys += curlen;
2168 1.2.4.2 nathanw cur = next;
2169 1.2.4.2 nathanw }
2170 1.2.4.2 nathanw cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
2171 1.2.4.2 nathanw *ep = cur;
2172 1.2.4.2 nathanw
2173 1.2.4.2 nathanw DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n",
2174 1.2.4.2 nathanw *sp, *ep));
2175 1.2.4.2 nathanw
2176 1.2.4.2 nathanw return (USBD_NORMAL_COMPLETION);
2177 1.2.4.2 nathanw
2178 1.2.4.2 nathanw nomem:
2179 1.2.4.2 nathanw /* XXX free chain */
2180 1.2.4.2 nathanw DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n"));
2181 1.2.4.2 nathanw return (USBD_NOMEM);
2182 1.2.4.2 nathanw }
2183 1.2.4.2 nathanw
2184 1.2.4.2 nathanw Static void
2185 1.2.4.2 nathanw ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd,
2186 1.2.4.2 nathanw ehci_soft_qtd_t *sqtdend)
2187 1.2.4.2 nathanw {
2188 1.2.4.2 nathanw ehci_soft_qtd_t *p;
2189 1.2.4.2 nathanw int i;
2190 1.2.4.2 nathanw
2191 1.2.4.2 nathanw DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n",
2192 1.2.4.2 nathanw sqtd, sqtdend));
2193 1.2.4.2 nathanw
2194 1.2.4.2 nathanw for (i = 0; sqtd != sqtdend; sqtd = p, i++) {
2195 1.2.4.2 nathanw p = sqtd->nextqtd;
2196 1.2.4.2 nathanw ehci_free_sqtd(sc, sqtd);
2197 1.2.4.2 nathanw }
2198 1.2.4.2 nathanw }
2199 1.2.4.2 nathanw
2200 1.2.4.2 nathanw /****************/
2201 1.2.4.2 nathanw
2202 1.2.4.2 nathanw /*
2203 1.2.4.2 nathanw * Close a reqular pipe.
2204 1.2.4.2 nathanw * Assumes that there are no pending transactions.
2205 1.2.4.2 nathanw */
2206 1.2.4.2 nathanw void
2207 1.2.4.2 nathanw ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head)
2208 1.2.4.2 nathanw {
2209 1.2.4.2 nathanw struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
2210 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2211 1.2.4.2 nathanw ehci_soft_qh_t *sqh = epipe->sqh;
2212 1.2.4.2 nathanw int s;
2213 1.2.4.2 nathanw
2214 1.2.4.2 nathanw s = splusb();
2215 1.2.4.2 nathanw ehci_rem_qh(sc, sqh, head);
2216 1.2.4.2 nathanw splx(s);
2217 1.2.4.2 nathanw ehci_free_sqh(sc, epipe->sqh);
2218 1.2.4.2 nathanw }
2219 1.2.4.2 nathanw
2220 1.2.4.6 nathanw /*
2221 1.2.4.2 nathanw * Abort a device request.
2222 1.2.4.2 nathanw * If this routine is called at splusb() it guarantees that the request
2223 1.2.4.2 nathanw * will be removed from the hardware scheduling and that the callback
2224 1.2.4.2 nathanw * for it will be called with USBD_CANCELLED status.
2225 1.2.4.2 nathanw * It's impossible to guarantee that the requested transfer will not
2226 1.2.4.2 nathanw * have happened since the hardware runs concurrently.
2227 1.2.4.2 nathanw * If the transaction has already happened we rely on the ordinary
2228 1.2.4.2 nathanw * interrupt processing to process it.
2229 1.2.4.2 nathanw * XXX This is most probably wrong.
2230 1.2.4.2 nathanw */
2231 1.2.4.2 nathanw void
2232 1.2.4.2 nathanw ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2233 1.2.4.2 nathanw {
2234 1.2.4.2 nathanw #define exfer EXFER(xfer)
2235 1.2.4.2 nathanw struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2236 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
2237 1.2.4.2 nathanw ehci_soft_qh_t *sqh = epipe->sqh;
2238 1.2.4.2 nathanw ehci_soft_qtd_t *sqtd;
2239 1.2.4.2 nathanw ehci_physaddr_t cur;
2240 1.2.4.2 nathanw u_int32_t qhstatus;
2241 1.2.4.2 nathanw int s;
2242 1.2.4.2 nathanw int hit;
2243 1.2.4.2 nathanw
2244 1.2.4.2 nathanw DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe));
2245 1.2.4.2 nathanw
2246 1.2.4.2 nathanw if (sc->sc_dying) {
2247 1.2.4.2 nathanw /* If we're dying, just do the software part. */
2248 1.2.4.2 nathanw s = splusb();
2249 1.2.4.2 nathanw xfer->status = status; /* make software ignore it */
2250 1.2.4.2 nathanw usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer);
2251 1.2.4.2 nathanw usb_transfer_complete(xfer);
2252 1.2.4.2 nathanw splx(s);
2253 1.2.4.2 nathanw return;
2254 1.2.4.2 nathanw }
2255 1.2.4.2 nathanw
2256 1.2.4.5 nathanw if (xfer->device->bus->intr_context || !curproc)
2257 1.2.4.8 nathanw panic("ehci_abort_xfer: not in process context");
2258 1.2.4.2 nathanw
2259 1.2.4.2 nathanw /*
2260 1.2.4.2 nathanw * Step 1: Make interrupt routine and hardware ignore xfer.
2261 1.2.4.2 nathanw */
2262 1.2.4.2 nathanw s = splusb();
2263 1.2.4.2 nathanw xfer->status = status; /* make software ignore it */
2264 1.2.4.2 nathanw usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer);
2265 1.2.4.2 nathanw qhstatus = sqh->qh.qh_qtd.qtd_status;
2266 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED);
2267 1.2.4.2 nathanw for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
2268 1.2.4.2 nathanw sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED);
2269 1.2.4.2 nathanw if (sqtd == exfer->sqtdend)
2270 1.2.4.2 nathanw break;
2271 1.2.4.2 nathanw }
2272 1.2.4.2 nathanw splx(s);
2273 1.2.4.2 nathanw
2274 1.2.4.6 nathanw /*
2275 1.2.4.2 nathanw * Step 2: Wait until we know hardware has finished any possible
2276 1.2.4.2 nathanw * use of the xfer. Also make sure the soft interrupt routine
2277 1.2.4.2 nathanw * has run.
2278 1.2.4.2 nathanw */
2279 1.2.4.2 nathanw ehci_sync_hc(sc);
2280 1.2.4.2 nathanw s = splusb();
2281 1.2.4.2 nathanw sc->sc_softwake = 1;
2282 1.2.4.2 nathanw usb_schedsoftintr(&sc->sc_bus);
2283 1.2.4.2 nathanw tsleep(&sc->sc_softwake, PZERO, "ehciab", 0);
2284 1.2.4.2 nathanw splx(s);
2285 1.2.4.6 nathanw
2286 1.2.4.6 nathanw /*
2287 1.2.4.2 nathanw * Step 3: Remove any vestiges of the xfer from the hardware.
2288 1.2.4.2 nathanw * The complication here is that the hardware may have executed
2289 1.2.4.2 nathanw * beyond the xfer we're trying to abort. So as we're scanning
2290 1.2.4.2 nathanw * the TDs of this xfer we check if the hardware points to
2291 1.2.4.2 nathanw * any of them.
2292 1.2.4.2 nathanw */
2293 1.2.4.2 nathanw s = splusb(); /* XXX why? */
2294 1.2.4.2 nathanw cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd));
2295 1.2.4.2 nathanw hit = 0;
2296 1.2.4.2 nathanw for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
2297 1.2.4.2 nathanw hit |= cur == sqtd->physaddr;
2298 1.2.4.2 nathanw if (sqtd == exfer->sqtdend)
2299 1.2.4.2 nathanw break;
2300 1.2.4.2 nathanw }
2301 1.2.4.2 nathanw sqtd = sqtd->nextqtd;
2302 1.2.4.2 nathanw /* Zap curqtd register if hardware pointed inside the xfer. */
2303 1.2.4.2 nathanw if (hit && sqtd != NULL) {
2304 1.2.4.2 nathanw DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr));
2305 1.2.4.2 nathanw sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */
2306 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_status = qhstatus;
2307 1.2.4.2 nathanw } else {
2308 1.2.4.2 nathanw DPRINTFN(1,("ehci_abort_xfer: no hit\n"));
2309 1.2.4.2 nathanw }
2310 1.2.4.2 nathanw
2311 1.2.4.2 nathanw /*
2312 1.2.4.2 nathanw * Step 4: Execute callback.
2313 1.2.4.2 nathanw */
2314 1.2.4.2 nathanw #ifdef DIAGNOSTIC
2315 1.2.4.2 nathanw exfer->isdone = 1;
2316 1.2.4.2 nathanw #endif
2317 1.2.4.2 nathanw usb_transfer_complete(xfer);
2318 1.2.4.2 nathanw
2319 1.2.4.2 nathanw splx(s);
2320 1.2.4.2 nathanw #undef exfer
2321 1.2.4.2 nathanw }
2322 1.2.4.2 nathanw
2323 1.2.4.2 nathanw void
2324 1.2.4.2 nathanw ehci_timeout(void *addr)
2325 1.2.4.2 nathanw {
2326 1.2.4.2 nathanw struct ehci_xfer *exfer = addr;
2327 1.2.4.2 nathanw struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe;
2328 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
2329 1.2.4.2 nathanw
2330 1.2.4.2 nathanw DPRINTF(("ehci_timeout: exfer=%p\n", exfer));
2331 1.2.4.2 nathanw #ifdef USB_DEBUG
2332 1.2.4.2 nathanw if (ehcidebug > 1)
2333 1.2.4.2 nathanw usbd_dump_pipe(exfer->xfer.pipe);
2334 1.2.4.2 nathanw #endif
2335 1.2.4.2 nathanw
2336 1.2.4.2 nathanw if (sc->sc_dying) {
2337 1.2.4.2 nathanw ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT);
2338 1.2.4.2 nathanw return;
2339 1.2.4.2 nathanw }
2340 1.2.4.2 nathanw
2341 1.2.4.2 nathanw /* Execute the abort in a process context. */
2342 1.2.4.2 nathanw usb_init_task(&exfer->abort_task, ehci_timeout_task, addr);
2343 1.2.4.2 nathanw usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task);
2344 1.2.4.2 nathanw }
2345 1.2.4.2 nathanw
2346 1.2.4.2 nathanw void
2347 1.2.4.2 nathanw ehci_timeout_task(void *addr)
2348 1.2.4.2 nathanw {
2349 1.2.4.2 nathanw usbd_xfer_handle xfer = addr;
2350 1.2.4.2 nathanw int s;
2351 1.2.4.2 nathanw
2352 1.2.4.2 nathanw DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer));
2353 1.2.4.2 nathanw
2354 1.2.4.2 nathanw s = splusb();
2355 1.2.4.2 nathanw ehci_abort_xfer(xfer, USBD_TIMEOUT);
2356 1.2.4.2 nathanw splx(s);
2357 1.2.4.2 nathanw }
2358 1.2.4.2 nathanw
2359 1.2.4.2 nathanw /************************/
2360 1.2.4.2 nathanw
2361 1.2.4.2 nathanw Static usbd_status
2362 1.2.4.2 nathanw ehci_device_ctrl_transfer(usbd_xfer_handle xfer)
2363 1.2.4.2 nathanw {
2364 1.2.4.2 nathanw usbd_status err;
2365 1.2.4.2 nathanw
2366 1.2.4.2 nathanw /* Insert last in queue. */
2367 1.2.4.2 nathanw err = usb_insert_transfer(xfer);
2368 1.2.4.2 nathanw if (err)
2369 1.2.4.2 nathanw return (err);
2370 1.2.4.2 nathanw
2371 1.2.4.2 nathanw /* Pipe isn't running, start first */
2372 1.2.4.2 nathanw return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2373 1.2.4.2 nathanw }
2374 1.2.4.2 nathanw
2375 1.2.4.2 nathanw Static usbd_status
2376 1.2.4.2 nathanw ehci_device_ctrl_start(usbd_xfer_handle xfer)
2377 1.2.4.2 nathanw {
2378 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2379 1.2.4.2 nathanw usbd_status err;
2380 1.2.4.2 nathanw
2381 1.2.4.2 nathanw if (sc->sc_dying)
2382 1.2.4.2 nathanw return (USBD_IOERROR);
2383 1.2.4.2 nathanw
2384 1.2.4.2 nathanw #ifdef DIAGNOSTIC
2385 1.2.4.2 nathanw if (!(xfer->rqflags & URQ_REQUEST)) {
2386 1.2.4.2 nathanw /* XXX panic */
2387 1.2.4.2 nathanw printf("ehci_device_ctrl_transfer: not a request\n");
2388 1.2.4.2 nathanw return (USBD_INVAL);
2389 1.2.4.2 nathanw }
2390 1.2.4.2 nathanw #endif
2391 1.2.4.2 nathanw
2392 1.2.4.2 nathanw err = ehci_device_request(xfer);
2393 1.2.4.2 nathanw if (err)
2394 1.2.4.2 nathanw return (err);
2395 1.2.4.2 nathanw
2396 1.2.4.2 nathanw if (sc->sc_bus.use_polling)
2397 1.2.4.2 nathanw ehci_waitintr(sc, xfer);
2398 1.2.4.2 nathanw return (USBD_IN_PROGRESS);
2399 1.2.4.2 nathanw }
2400 1.2.4.2 nathanw
2401 1.2.4.2 nathanw void
2402 1.2.4.2 nathanw ehci_device_ctrl_done(usbd_xfer_handle xfer)
2403 1.2.4.2 nathanw {
2404 1.2.4.2 nathanw struct ehci_xfer *ex = EXFER(xfer);
2405 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2406 1.2.4.2 nathanw /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/
2407 1.2.4.2 nathanw
2408 1.2.4.2 nathanw DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer));
2409 1.2.4.2 nathanw
2410 1.2.4.2 nathanw #ifdef DIAGNOSTIC
2411 1.2.4.2 nathanw if (!(xfer->rqflags & URQ_REQUEST)) {
2412 1.2.4.8 nathanw panic("ehci_ctrl_done: not a request");
2413 1.2.4.2 nathanw }
2414 1.2.4.2 nathanw #endif
2415 1.2.4.2 nathanw
2416 1.2.4.2 nathanw if (xfer->status != USBD_NOMEM) {
2417 1.2.4.2 nathanw ehci_del_intr_list(ex); /* remove from active list */
2418 1.2.4.2 nathanw ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
2419 1.2.4.2 nathanw }
2420 1.2.4.2 nathanw
2421 1.2.4.2 nathanw DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen));
2422 1.2.4.2 nathanw }
2423 1.2.4.2 nathanw
2424 1.2.4.2 nathanw /* Abort a device control request. */
2425 1.2.4.2 nathanw Static void
2426 1.2.4.2 nathanw ehci_device_ctrl_abort(usbd_xfer_handle xfer)
2427 1.2.4.2 nathanw {
2428 1.2.4.2 nathanw DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer));
2429 1.2.4.2 nathanw ehci_abort_xfer(xfer, USBD_CANCELLED);
2430 1.2.4.2 nathanw }
2431 1.2.4.2 nathanw
2432 1.2.4.2 nathanw /* Close a device control pipe. */
2433 1.2.4.2 nathanw Static void
2434 1.2.4.2 nathanw ehci_device_ctrl_close(usbd_pipe_handle pipe)
2435 1.2.4.2 nathanw {
2436 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2437 1.2.4.2 nathanw /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/
2438 1.2.4.2 nathanw
2439 1.2.4.2 nathanw DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe));
2440 1.2.4.2 nathanw ehci_close_pipe(pipe, sc->sc_async_head);
2441 1.2.4.2 nathanw }
2442 1.2.4.2 nathanw
2443 1.2.4.2 nathanw usbd_status
2444 1.2.4.2 nathanw ehci_device_request(usbd_xfer_handle xfer)
2445 1.2.4.2 nathanw {
2446 1.2.4.2 nathanw #define exfer EXFER(xfer)
2447 1.2.4.2 nathanw struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2448 1.2.4.2 nathanw usb_device_request_t *req = &xfer->request;
2449 1.2.4.2 nathanw usbd_device_handle dev = epipe->pipe.device;
2450 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2451 1.2.4.2 nathanw int addr = dev->address;
2452 1.2.4.2 nathanw ehci_soft_qtd_t *setup, *stat, *next;
2453 1.2.4.2 nathanw ehci_soft_qh_t *sqh;
2454 1.2.4.2 nathanw int isread;
2455 1.2.4.2 nathanw int len;
2456 1.2.4.2 nathanw usbd_status err;
2457 1.2.4.2 nathanw int s;
2458 1.2.4.2 nathanw
2459 1.2.4.2 nathanw isread = req->bmRequestType & UT_READ;
2460 1.2.4.2 nathanw len = UGETW(req->wLength);
2461 1.2.4.2 nathanw
2462 1.2.4.2 nathanw DPRINTFN(3,("ehci_device_control type=0x%02x, request=0x%02x, "
2463 1.2.4.2 nathanw "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
2464 1.2.4.2 nathanw req->bmRequestType, req->bRequest, UGETW(req->wValue),
2465 1.2.4.6 nathanw UGETW(req->wIndex), len, addr,
2466 1.2.4.2 nathanw epipe->pipe.endpoint->edesc->bEndpointAddress));
2467 1.2.4.2 nathanw
2468 1.2.4.2 nathanw setup = ehci_alloc_sqtd(sc);
2469 1.2.4.2 nathanw if (setup == NULL) {
2470 1.2.4.2 nathanw err = USBD_NOMEM;
2471 1.2.4.2 nathanw goto bad1;
2472 1.2.4.2 nathanw }
2473 1.2.4.2 nathanw stat = ehci_alloc_sqtd(sc);
2474 1.2.4.2 nathanw if (stat == NULL) {
2475 1.2.4.2 nathanw err = USBD_NOMEM;
2476 1.2.4.2 nathanw goto bad2;
2477 1.2.4.2 nathanw }
2478 1.2.4.2 nathanw
2479 1.2.4.2 nathanw sqh = epipe->sqh;
2480 1.2.4.2 nathanw epipe->u.ctl.length = len;
2481 1.2.4.2 nathanw
2482 1.2.4.6 nathanw /* XXX
2483 1.2.4.2 nathanw * Since we're messing with the QH we must know the HC is in sync.
2484 1.2.4.2 nathanw * This needs to go away since it slows down control transfers.
2485 1.2.4.2 nathanw * Removing it entails:
2486 1.2.4.2 nathanw * - fill the QH only once with addr & wMaxPacketSize
2487 1.2.4.2 nathanw * - put the correct data toggles in the qtds and set DTC
2488 1.2.4.2 nathanw */
2489 1.2.4.2 nathanw /* ehci_sync_hc(sc); */
2490 1.2.4.2 nathanw /* Update device address and length since they may have changed. */
2491 1.2.4.2 nathanw /* XXX This only needs to be done once, but it's too early in open. */
2492 1.2.4.2 nathanw /* XXXX Should not touch ED here! */
2493 1.2.4.6 nathanw sqh->qh.qh_endp =
2494 1.2.4.2 nathanw (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QG_MPLMASK))) |
2495 1.2.4.2 nathanw htole32(
2496 1.2.4.2 nathanw EHCI_QH_SET_ADDR(addr) |
2497 1.2.4.2 nathanw /* EHCI_QH_DTC | */
2498 1.2.4.2 nathanw EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize))
2499 1.2.4.2 nathanw );
2500 1.2.4.2 nathanw /* Clear toggle */
2501 1.2.4.2 nathanw sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE);
2502 1.2.4.2 nathanw
2503 1.2.4.2 nathanw /* Set up data transaction */
2504 1.2.4.2 nathanw if (len != 0) {
2505 1.2.4.2 nathanw ehci_soft_qtd_t *end;
2506 1.2.4.2 nathanw
2507 1.2.4.2 nathanw err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
2508 1.2.4.2 nathanw &next, &end);
2509 1.2.4.2 nathanw if (err)
2510 1.2.4.2 nathanw goto bad3;
2511 1.2.4.2 nathanw end->nextqtd = stat;
2512 1.2.4.6 nathanw end->qtd.qtd_next =
2513 1.2.4.2 nathanw end->qtd.qtd_altnext = htole32(stat->physaddr);
2514 1.2.4.2 nathanw /* Start toggle at 1. */
2515 1.2.4.2 nathanw /*next->qtd.td_flags |= htole32(EHCI_QTD_TOGGLE);*/
2516 1.2.4.2 nathanw } else {
2517 1.2.4.2 nathanw next = stat;
2518 1.2.4.2 nathanw }
2519 1.2.4.2 nathanw
2520 1.2.4.3 nathanw memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req);
2521 1.2.4.2 nathanw
2522 1.2.4.2 nathanw setup->qtd.qtd_status = htole32(
2523 1.2.4.2 nathanw EHCI_QTD_ACTIVE |
2524 1.2.4.2 nathanw EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
2525 1.2.4.2 nathanw EHCI_QTD_SET_CERR(3) |
2526 1.2.4.2 nathanw EHCI_QTD_SET_BYTES(sizeof *req)
2527 1.2.4.2 nathanw );
2528 1.2.4.3 nathanw setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0));
2529 1.2.4.2 nathanw setup->nextqtd = next;
2530 1.2.4.2 nathanw setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
2531 1.2.4.2 nathanw setup->xfer = xfer;
2532 1.2.4.2 nathanw setup->len = sizeof *req;
2533 1.2.4.2 nathanw
2534 1.2.4.2 nathanw stat->qtd.qtd_status = htole32(
2535 1.2.4.2 nathanw EHCI_QTD_ACTIVE |
2536 1.2.4.2 nathanw EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
2537 1.2.4.2 nathanw EHCI_QTD_SET_CERR(3) |
2538 1.2.4.2 nathanw EHCI_QTD_IOC
2539 1.2.4.2 nathanw );
2540 1.2.4.2 nathanw stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */
2541 1.2.4.2 nathanw stat->nextqtd = NULL;
2542 1.2.4.2 nathanw stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL;
2543 1.2.4.2 nathanw stat->xfer = xfer;
2544 1.2.4.2 nathanw stat->len = 0;
2545 1.2.4.2 nathanw
2546 1.2.4.2 nathanw #ifdef EHCI_DEBUG
2547 1.2.4.2 nathanw if (ehcidebug > 5) {
2548 1.2.4.2 nathanw DPRINTF(("ehci_device_request:\n"));
2549 1.2.4.2 nathanw ehci_dump_sqh(sqh);
2550 1.2.4.2 nathanw ehci_dump_sqtds(setup);
2551 1.2.4.2 nathanw }
2552 1.2.4.2 nathanw #endif
2553 1.2.4.2 nathanw
2554 1.2.4.2 nathanw exfer->sqtdstart = setup;
2555 1.2.4.2 nathanw exfer->sqtdend = stat;
2556 1.2.4.2 nathanw #ifdef DIAGNOSTIC
2557 1.2.4.2 nathanw if (!exfer->isdone) {
2558 1.2.4.2 nathanw printf("ehci_device_request: not done, exfer=%p\n", exfer);
2559 1.2.4.2 nathanw }
2560 1.2.4.2 nathanw exfer->isdone = 0;
2561 1.2.4.2 nathanw #endif
2562 1.2.4.2 nathanw
2563 1.2.4.2 nathanw /* Insert qTD in QH list. */
2564 1.2.4.2 nathanw s = splusb();
2565 1.2.4.2 nathanw ehci_set_qh_qtd(sqh, setup);
2566 1.2.4.2 nathanw if (xfer->timeout && !sc->sc_bus.use_polling) {
2567 1.2.4.2 nathanw usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
2568 1.2.4.2 nathanw ehci_timeout, xfer);
2569 1.2.4.2 nathanw }
2570 1.2.4.2 nathanw ehci_add_intr_list(sc, exfer);
2571 1.2.4.2 nathanw xfer->status = USBD_IN_PROGRESS;
2572 1.2.4.2 nathanw splx(s);
2573 1.2.4.2 nathanw
2574 1.2.4.2 nathanw #ifdef EHCI_DEBUG
2575 1.2.4.2 nathanw if (ehcidebug > 10) {
2576 1.2.4.2 nathanw DPRINTF(("ehci_device_request: status=%x\n",
2577 1.2.4.2 nathanw EOREAD4(sc, EHCI_USBSTS)));
2578 1.2.4.2 nathanw delay(10000);
2579 1.2.4.2 nathanw ehci_dump_regs(sc);
2580 1.2.4.2 nathanw ehci_dump_sqh(sc->sc_async_head);
2581 1.2.4.2 nathanw ehci_dump_sqh(sqh);
2582 1.2.4.2 nathanw ehci_dump_sqtds(setup);
2583 1.2.4.2 nathanw }
2584 1.2.4.2 nathanw #endif
2585 1.2.4.2 nathanw
2586 1.2.4.2 nathanw return (USBD_NORMAL_COMPLETION);
2587 1.2.4.2 nathanw
2588 1.2.4.2 nathanw bad3:
2589 1.2.4.2 nathanw ehci_free_sqtd(sc, stat);
2590 1.2.4.2 nathanw bad2:
2591 1.2.4.2 nathanw ehci_free_sqtd(sc, setup);
2592 1.2.4.2 nathanw bad1:
2593 1.2.4.2 nathanw DPRINTFN(-1,("ehci_device_request: no memory\n"));
2594 1.2.4.2 nathanw xfer->status = err;
2595 1.2.4.2 nathanw usb_transfer_complete(xfer);
2596 1.2.4.2 nathanw return (err);
2597 1.2.4.2 nathanw #undef exfer
2598 1.2.4.2 nathanw }
2599 1.2.4.2 nathanw
2600 1.2.4.2 nathanw /************************/
2601 1.2.4.2 nathanw
2602 1.2.4.2 nathanw Static usbd_status
2603 1.2.4.2 nathanw ehci_device_bulk_transfer(usbd_xfer_handle xfer)
2604 1.2.4.2 nathanw {
2605 1.2.4.2 nathanw usbd_status err;
2606 1.2.4.2 nathanw
2607 1.2.4.2 nathanw /* Insert last in queue. */
2608 1.2.4.2 nathanw err = usb_insert_transfer(xfer);
2609 1.2.4.2 nathanw if (err)
2610 1.2.4.2 nathanw return (err);
2611 1.2.4.2 nathanw
2612 1.2.4.2 nathanw /* Pipe isn't running, start first */
2613 1.2.4.2 nathanw return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2614 1.2.4.2 nathanw }
2615 1.2.4.2 nathanw
2616 1.2.4.2 nathanw usbd_status
2617 1.2.4.2 nathanw ehci_device_bulk_start(usbd_xfer_handle xfer)
2618 1.2.4.2 nathanw {
2619 1.2.4.2 nathanw #define exfer EXFER(xfer)
2620 1.2.4.2 nathanw struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2621 1.2.4.2 nathanw usbd_device_handle dev = epipe->pipe.device;
2622 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2623 1.2.4.2 nathanw ehci_soft_qtd_t *data, *dataend;
2624 1.2.4.2 nathanw ehci_soft_qh_t *sqh;
2625 1.2.4.2 nathanw usbd_status err;
2626 1.2.4.2 nathanw int len, isread, endpt;
2627 1.2.4.2 nathanw int s;
2628 1.2.4.2 nathanw
2629 1.2.4.2 nathanw DPRINTFN(2, ("ehci_device_bulk_transfer: xfer=%p len=%d flags=%d\n",
2630 1.2.4.2 nathanw xfer, xfer->length, xfer->flags));
2631 1.2.4.2 nathanw
2632 1.2.4.2 nathanw if (sc->sc_dying)
2633 1.2.4.2 nathanw return (USBD_IOERROR);
2634 1.2.4.2 nathanw
2635 1.2.4.2 nathanw #ifdef DIAGNOSTIC
2636 1.2.4.2 nathanw if (xfer->rqflags & URQ_REQUEST)
2637 1.2.4.8 nathanw panic("ehci_device_bulk_transfer: a request");
2638 1.2.4.2 nathanw #endif
2639 1.2.4.2 nathanw
2640 1.2.4.2 nathanw len = xfer->length;
2641 1.2.4.2 nathanw endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
2642 1.2.4.2 nathanw isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2643 1.2.4.2 nathanw sqh = epipe->sqh;
2644 1.2.4.2 nathanw
2645 1.2.4.2 nathanw epipe->u.bulk.length = len;
2646 1.2.4.2 nathanw
2647 1.2.4.2 nathanw err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
2648 1.2.4.2 nathanw &dataend);
2649 1.2.4.2 nathanw if (err) {
2650 1.2.4.2 nathanw DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n"));
2651 1.2.4.2 nathanw xfer->status = err;
2652 1.2.4.2 nathanw usb_transfer_complete(xfer);
2653 1.2.4.2 nathanw return (err);
2654 1.2.4.2 nathanw }
2655 1.2.4.2 nathanw
2656 1.2.4.2 nathanw #ifdef EHCI_DEBUG
2657 1.2.4.2 nathanw if (ehcidebug > 5) {
2658 1.2.4.2 nathanw DPRINTF(("ehci_device_bulk_transfer: data(1)\n"));
2659 1.2.4.2 nathanw ehci_dump_sqh(sqh);
2660 1.2.4.2 nathanw ehci_dump_sqtds(data);
2661 1.2.4.2 nathanw }
2662 1.2.4.2 nathanw #endif
2663 1.2.4.2 nathanw
2664 1.2.4.2 nathanw /* Set up interrupt info. */
2665 1.2.4.2 nathanw exfer->sqtdstart = data;
2666 1.2.4.2 nathanw exfer->sqtdend = dataend;
2667 1.2.4.2 nathanw #ifdef DIAGNOSTIC
2668 1.2.4.2 nathanw if (!exfer->isdone) {
2669 1.2.4.2 nathanw printf("ehci_device_bulk_transfer: not done, ex=%p\n", exfer);
2670 1.2.4.2 nathanw }
2671 1.2.4.2 nathanw exfer->isdone = 0;
2672 1.2.4.2 nathanw #endif
2673 1.2.4.2 nathanw
2674 1.2.4.2 nathanw s = splusb();
2675 1.2.4.2 nathanw ehci_set_qh_qtd(sqh, data);
2676 1.2.4.2 nathanw if (xfer->timeout && !sc->sc_bus.use_polling) {
2677 1.2.4.2 nathanw usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
2678 1.2.4.2 nathanw ehci_timeout, xfer);
2679 1.2.4.2 nathanw }
2680 1.2.4.2 nathanw ehci_add_intr_list(sc, exfer);
2681 1.2.4.2 nathanw xfer->status = USBD_IN_PROGRESS;
2682 1.2.4.2 nathanw splx(s);
2683 1.2.4.2 nathanw
2684 1.2.4.2 nathanw #ifdef EHCI_DEBUG
2685 1.2.4.2 nathanw if (ehcidebug > 10) {
2686 1.2.4.2 nathanw DPRINTF(("ehci_device_bulk_transfer: data(2)\n"));
2687 1.2.4.2 nathanw delay(10000);
2688 1.2.4.2 nathanw DPRINTF(("ehci_device_bulk_transfer: data(3)\n"));
2689 1.2.4.2 nathanw ehci_dump_regs(sc);
2690 1.2.4.2 nathanw #if 0
2691 1.2.4.2 nathanw printf("async_head:\n");
2692 1.2.4.2 nathanw ehci_dump_sqh(sc->sc_async_head);
2693 1.2.4.2 nathanw #endif
2694 1.2.4.2 nathanw printf("sqh:\n");
2695 1.2.4.2 nathanw ehci_dump_sqh(sqh);
2696 1.2.4.2 nathanw ehci_dump_sqtds(data);
2697 1.2.4.2 nathanw }
2698 1.2.4.2 nathanw #endif
2699 1.2.4.2 nathanw
2700 1.2.4.2 nathanw if (sc->sc_bus.use_polling)
2701 1.2.4.2 nathanw ehci_waitintr(sc, xfer);
2702 1.2.4.2 nathanw
2703 1.2.4.2 nathanw return (USBD_IN_PROGRESS);
2704 1.2.4.2 nathanw #undef exfer
2705 1.2.4.2 nathanw }
2706 1.2.4.2 nathanw
2707 1.2.4.2 nathanw Static void
2708 1.2.4.2 nathanw ehci_device_bulk_abort(usbd_xfer_handle xfer)
2709 1.2.4.2 nathanw {
2710 1.2.4.2 nathanw DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer));
2711 1.2.4.2 nathanw ehci_abort_xfer(xfer, USBD_CANCELLED);
2712 1.2.4.2 nathanw }
2713 1.2.4.2 nathanw
2714 1.2.4.6 nathanw /*
2715 1.2.4.2 nathanw * Close a device bulk pipe.
2716 1.2.4.2 nathanw */
2717 1.2.4.2 nathanw Static void
2718 1.2.4.2 nathanw ehci_device_bulk_close(usbd_pipe_handle pipe)
2719 1.2.4.2 nathanw {
2720 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2721 1.2.4.2 nathanw
2722 1.2.4.2 nathanw DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe));
2723 1.2.4.2 nathanw ehci_close_pipe(pipe, sc->sc_async_head);
2724 1.2.4.2 nathanw }
2725 1.2.4.2 nathanw
2726 1.2.4.2 nathanw void
2727 1.2.4.2 nathanw ehci_device_bulk_done(usbd_xfer_handle xfer)
2728 1.2.4.2 nathanw {
2729 1.2.4.2 nathanw struct ehci_xfer *ex = EXFER(xfer);
2730 1.2.4.2 nathanw ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2731 1.2.4.2 nathanw /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/
2732 1.2.4.2 nathanw
2733 1.2.4.6 nathanw DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n",
2734 1.2.4.2 nathanw xfer, xfer->actlen));
2735 1.2.4.2 nathanw
2736 1.2.4.2 nathanw if (xfer->status != USBD_NOMEM) {
2737 1.2.4.2 nathanw ehci_del_intr_list(ex); /* remove from active list */
2738 1.2.4.2 nathanw ehci_free_sqtd_chain(sc, ex->sqtdstart, 0);
2739 1.2.4.2 nathanw }
2740 1.2.4.2 nathanw
2741 1.2.4.2 nathanw DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen));
2742 1.2.4.2 nathanw }
2743 1.2.4.2 nathanw
2744 1.2.4.2 nathanw /************************/
2745 1.2.4.2 nathanw
2746 1.2.4.2 nathanw Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; }
2747 1.2.4.2 nathanw Static usbd_status ehci_device_intr_start(usbd_xfer_handle xfer) { return USBD_IOERROR; }
2748 1.2.4.2 nathanw Static void ehci_device_intr_abort(usbd_xfer_handle xfer) { }
2749 1.2.4.2 nathanw Static void ehci_device_intr_close(usbd_pipe_handle pipe) { }
2750 1.2.4.2 nathanw Static void ehci_device_intr_done(usbd_xfer_handle xfer) { }
2751 1.2.4.2 nathanw
2752 1.2.4.2 nathanw /************************/
2753 1.2.4.2 nathanw
2754 1.2.4.2 nathanw Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; }
2755 1.2.4.2 nathanw Static usbd_status ehci_device_isoc_start(usbd_xfer_handle xfer) { return USBD_IOERROR; }
2756 1.2.4.2 nathanw Static void ehci_device_isoc_abort(usbd_xfer_handle xfer) { }
2757 1.2.4.2 nathanw Static void ehci_device_isoc_close(usbd_pipe_handle pipe) { }
2758 1.2.4.2 nathanw Static void ehci_device_isoc_done(usbd_xfer_handle xfer) { }
2759