ehci.c revision 1.318 1 1.318 riastrad /* $NetBSD: ehci.c,v 1.318 2023/10/28 21:18:15 riastradh Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.281 skrll * Copyright (c) 2004-2012,2016,2020 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.190 mrg * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum,
9 1.190 mrg * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill
10 1.281 skrll * (jmcneill (at) invisible.ca). Matthew R. Green (mrg (at) eterna.com.au), and
11 1.281 skrll * Nick Hudson .
12 1.1 augustss *
13 1.1 augustss * Redistribution and use in source and binary forms, with or without
14 1.1 augustss * modification, are permitted provided that the following conditions
15 1.1 augustss * are met:
16 1.1 augustss * 1. Redistributions of source code must retain the above copyright
17 1.1 augustss * notice, this list of conditions and the following disclaimer.
18 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
19 1.1 augustss * notice, this list of conditions and the following disclaimer in the
20 1.1 augustss * documentation and/or other materials provided with the distribution.
21 1.1 augustss *
22 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
23 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
26 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
33 1.1 augustss */
34 1.1 augustss
35 1.1 augustss /*
36 1.3 augustss * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
37 1.1 augustss *
38 1.35 enami * The EHCI 1.0 spec can be found at
39 1.160 uebayasi * http://www.intel.com/technology/usb/spec.htm
40 1.7 augustss * and the USB 2.0 spec at
41 1.160 uebayasi * http://www.usb.org/developers/docs/
42 1.1 augustss *
43 1.1 augustss */
44 1.4 lukem
45 1.52 jdolecek /*
46 1.52 jdolecek * TODO:
47 1.52 jdolecek * 1) hold off explorations by companion controllers until ehci has started.
48 1.52 jdolecek *
49 1.148 cegger * 2) The hub driver needs to handle and schedule the transaction translator,
50 1.100 augustss * to assign place in frame where different devices get to go. See chapter
51 1.91 perry * on hubs in USB 2.0 for details.
52 1.52 jdolecek *
53 1.164 uebayasi * 3) Command failures are not recovered correctly.
54 1.148 cegger */
55 1.52 jdolecek
56 1.4 lukem #include <sys/cdefs.h>
57 1.318 riastrad __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.318 2023/10/28 21:18:15 riastradh Exp $");
58 1.47 augustss
59 1.47 augustss #include "ohci.h"
60 1.47 augustss #include "uhci.h"
61 1.244 pooka
62 1.244 pooka #ifdef _KERNEL_OPT
63 1.229 skrll #include "opt_usb.h"
64 1.244 pooka #endif
65 1.1 augustss
66 1.1 augustss #include <sys/param.h>
67 1.229 skrll
68 1.229 skrll #include <sys/bus.h>
69 1.229 skrll #include <sys/cpu.h>
70 1.229 skrll #include <sys/device.h>
71 1.1 augustss #include <sys/kernel.h>
72 1.190 mrg #include <sys/kmem.h>
73 1.229 skrll #include <sys/mutex.h>
74 1.1 augustss #include <sys/proc.h>
75 1.1 augustss #include <sys/queue.h>
76 1.229 skrll #include <sys/select.h>
77 1.229 skrll #include <sys/sysctl.h>
78 1.229 skrll #include <sys/systm.h>
79 1.265 mrg #include <sys/reboot.h>
80 1.1 augustss
81 1.1 augustss #include <machine/endian.h>
82 1.1 augustss
83 1.1 augustss #include <dev/usb/usb.h>
84 1.1 augustss #include <dev/usb/usbdi.h>
85 1.1 augustss #include <dev/usb/usbdivar.h>
86 1.229 skrll #include <dev/usb/usbhist.h>
87 1.1 augustss #include <dev/usb/usb_mem.h>
88 1.1 augustss #include <dev/usb/usb_quirks.h>
89 1.1 augustss
90 1.1 augustss #include <dev/usb/ehcireg.h>
91 1.1 augustss #include <dev/usb/ehcivar.h>
92 1.249 skrll #include <dev/usb/usbroothub.h>
93 1.1 augustss
94 1.230 skrll #ifdef USB_DEBUG
95 1.230 skrll #ifndef EHCI_DEBUG
96 1.230 skrll #define ehcidebug 0
97 1.230 skrll #else
98 1.316 mrg
99 1.316 mrg #ifndef EHCI_DEBUG_DEFAULT
100 1.316 mrg #define EHCI_DEBUG_DEFAULT 0
101 1.316 mrg #endif
102 1.316 mrg
103 1.316 mrg static int ehcidebug = EHCI_DEBUG_DEFAULT;
104 1.229 skrll
105 1.229 skrll SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup")
106 1.190 mrg {
107 1.229 skrll int err;
108 1.229 skrll const struct sysctlnode *rnode;
109 1.229 skrll const struct sysctlnode *cnode;
110 1.229 skrll
111 1.229 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
112 1.229 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci",
113 1.229 skrll SYSCTL_DESCR("ehci global controls"),
114 1.229 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
115 1.229 skrll
116 1.229 skrll if (err)
117 1.229 skrll goto fail;
118 1.190 mrg
119 1.229 skrll /* control debugging printfs */
120 1.229 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
121 1.229 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
122 1.229 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
123 1.229 skrll NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL);
124 1.229 skrll if (err)
125 1.229 skrll goto fail;
126 1.229 skrll
127 1.229 skrll return;
128 1.229 skrll fail:
129 1.229 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
130 1.190 mrg }
131 1.190 mrg
132 1.229 skrll #endif /* EHCI_DEBUG */
133 1.230 skrll #endif /* USB_DEBUG */
134 1.1 augustss
135 1.249 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D)
136 1.249 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D)
137 1.249 skrll #define EHCIHIST_FUNC() USBHIST_FUNC()
138 1.249 skrll #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug)
139 1.249 skrll
140 1.5 augustss struct ehci_pipe {
141 1.5 augustss struct usbd_pipe pipe;
142 1.55 mycroft int nexttoggle;
143 1.55 mycroft
144 1.10 augustss ehci_soft_qh_t *sqh;
145 1.10 augustss union {
146 1.10 augustss /* Control pipe */
147 1.10 augustss struct {
148 1.10 augustss usb_dma_t reqdma;
149 1.249 skrll } ctrl;
150 1.10 augustss /* Interrupt pipe */
151 1.78 augustss struct {
152 1.78 augustss u_int length;
153 1.78 augustss } intr;
154 1.10 augustss /* Iso pipe */
155 1.139 jmcneill struct {
156 1.139 jmcneill u_int next_frame;
157 1.139 jmcneill u_int cur_xfers;
158 1.139 jmcneill } isoc;
159 1.249 skrll };
160 1.5 augustss };
161 1.5 augustss
162 1.249 skrll typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t;
163 1.249 skrll
164 1.249 skrll Static usbd_status ehci_open(struct usbd_pipe *);
165 1.5 augustss Static void ehci_poll(struct usbd_bus *);
166 1.5 augustss Static void ehci_softintr(void *);
167 1.11 augustss Static int ehci_intr1(ehci_softc_t *);
168 1.249 skrll Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *,
169 1.249 skrll ex_completeq_t *);
170 1.249 skrll Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *,
171 1.249 skrll ex_completeq_t *);
172 1.249 skrll Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *,
173 1.249 skrll ex_completeq_t *);
174 1.249 skrll Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *);
175 1.108 xtraeme Static void ehci_intrlist_timeout(void *);
176 1.190 mrg Static void ehci_doorbell(void *);
177 1.190 mrg Static void ehci_pcd(void *);
178 1.5 augustss
179 1.249 skrll Static struct usbd_xfer *
180 1.249 skrll ehci_allocx(struct usbd_bus *, unsigned int);
181 1.249 skrll Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *);
182 1.5 augustss
183 1.190 mrg Static void ehci_get_lock(struct usbd_bus *, kmutex_t **);
184 1.271 riastrad Static bool ehci_dying(struct usbd_bus *);
185 1.249 skrll Static int ehci_roothub_ctrl(struct usbd_bus *,
186 1.249 skrll usb_device_request_t *, void *, int);
187 1.5 augustss
188 1.249 skrll Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *);
189 1.249 skrll Static usbd_status ehci_root_intr_start(struct usbd_xfer *);
190 1.249 skrll Static void ehci_root_intr_abort(struct usbd_xfer *);
191 1.249 skrll Static void ehci_root_intr_close(struct usbd_pipe *);
192 1.249 skrll Static void ehci_root_intr_done(struct usbd_xfer *);
193 1.249 skrll
194 1.249 skrll Static int ehci_device_ctrl_init(struct usbd_xfer *);
195 1.249 skrll Static void ehci_device_ctrl_fini(struct usbd_xfer *);
196 1.249 skrll Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *);
197 1.249 skrll Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *);
198 1.249 skrll Static void ehci_device_ctrl_abort(struct usbd_xfer *);
199 1.249 skrll Static void ehci_device_ctrl_close(struct usbd_pipe *);
200 1.249 skrll Static void ehci_device_ctrl_done(struct usbd_xfer *);
201 1.249 skrll
202 1.249 skrll Static int ehci_device_bulk_init(struct usbd_xfer *);
203 1.249 skrll Static void ehci_device_bulk_fini(struct usbd_xfer *);
204 1.249 skrll Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *);
205 1.249 skrll Static usbd_status ehci_device_bulk_start(struct usbd_xfer *);
206 1.249 skrll Static void ehci_device_bulk_abort(struct usbd_xfer *);
207 1.249 skrll Static void ehci_device_bulk_close(struct usbd_pipe *);
208 1.249 skrll Static void ehci_device_bulk_done(struct usbd_xfer *);
209 1.249 skrll
210 1.249 skrll Static int ehci_device_intr_init(struct usbd_xfer *);
211 1.249 skrll Static void ehci_device_intr_fini(struct usbd_xfer *);
212 1.249 skrll Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *);
213 1.249 skrll Static usbd_status ehci_device_intr_start(struct usbd_xfer *);
214 1.249 skrll Static void ehci_device_intr_abort(struct usbd_xfer *);
215 1.249 skrll Static void ehci_device_intr_close(struct usbd_pipe *);
216 1.249 skrll Static void ehci_device_intr_done(struct usbd_xfer *);
217 1.249 skrll
218 1.249 skrll Static int ehci_device_isoc_init(struct usbd_xfer *);
219 1.249 skrll Static void ehci_device_isoc_fini(struct usbd_xfer *);
220 1.249 skrll Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *);
221 1.249 skrll Static void ehci_device_isoc_abort(struct usbd_xfer *);
222 1.249 skrll Static void ehci_device_isoc_close(struct usbd_pipe *);
223 1.249 skrll Static void ehci_device_isoc_done(struct usbd_xfer *);
224 1.249 skrll
225 1.249 skrll Static int ehci_device_fs_isoc_init(struct usbd_xfer *);
226 1.249 skrll Static void ehci_device_fs_isoc_fini(struct usbd_xfer *);
227 1.249 skrll Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *);
228 1.249 skrll Static void ehci_device_fs_isoc_abort(struct usbd_xfer *);
229 1.249 skrll Static void ehci_device_fs_isoc_close(struct usbd_pipe *);
230 1.249 skrll Static void ehci_device_fs_isoc_done(struct usbd_xfer *);
231 1.5 augustss
232 1.249 skrll Static void ehci_device_clear_toggle(struct usbd_pipe *);
233 1.249 skrll Static void ehci_noop(struct usbd_pipe *);
234 1.5 augustss
235 1.6 augustss Static void ehci_disown(ehci_softc_t *, int, int);
236 1.5 augustss
237 1.249 skrll Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *);
238 1.9 augustss Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
239 1.9 augustss
240 1.249 skrll Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
241 1.9 augustss Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
242 1.249 skrll Static int ehci_alloc_sqtd_chain(ehci_softc_t *,
243 1.249 skrll struct usbd_xfer *, int, int, ehci_soft_qtd_t **);
244 1.249 skrll Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *);
245 1.249 skrll
246 1.249 skrll Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *,
247 1.249 skrll int, int, int *, ehci_soft_qtd_t **);
248 1.249 skrll Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *);
249 1.249 skrll
250 1.249 skrll Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *);
251 1.249 skrll Static ehci_soft_sitd_t *
252 1.249 skrll ehci_alloc_sitd(ehci_softc_t *);
253 1.249 skrll
254 1.249 skrll Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *);
255 1.249 skrll Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *);
256 1.249 skrll Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *);
257 1.249 skrll Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *);
258 1.249 skrll
259 1.249 skrll static inline void
260 1.249 skrll ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd)
261 1.249 skrll {
262 1.249 skrll
263 1.249 skrll LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list);
264 1.249 skrll }
265 1.249 skrll
266 1.249 skrll static inline void
267 1.249 skrll ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd)
268 1.249 skrll {
269 1.249 skrll
270 1.249 skrll LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list);
271 1.249 skrll }
272 1.139 jmcneill
273 1.249 skrll Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status);
274 1.9 augustss
275 1.78 augustss Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *,
276 1.249 skrll int);
277 1.78 augustss
278 1.190 mrg Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *,
279 1.190 mrg ehci_soft_qh_t *);
280 1.10 augustss Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
281 1.10 augustss ehci_soft_qh_t *);
282 1.23 augustss Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *);
283 1.11 augustss Static void ehci_sync_hc(ehci_softc_t *);
284 1.10 augustss
285 1.249 skrll Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *);
286 1.271 riastrad Static void ehci_abortx(struct usbd_xfer *);
287 1.9 augustss
288 1.5 augustss #ifdef EHCI_DEBUG
289 1.229 skrll Static ehci_softc_t *theehci;
290 1.229 skrll void ehci_dump(void);
291 1.229 skrll #endif
292 1.229 skrll
293 1.229 skrll #ifdef EHCI_DEBUG
294 1.18 augustss Static void ehci_dump_regs(ehci_softc_t *);
295 1.15 augustss Static void ehci_dump_sqtds(ehci_soft_qtd_t *);
296 1.9 augustss Static void ehci_dump_sqtd(ehci_soft_qtd_t *);
297 1.9 augustss Static void ehci_dump_qtd(ehci_qtd_t *);
298 1.9 augustss Static void ehci_dump_sqh(ehci_soft_qh_t *);
299 1.249 skrll Static void ehci_dump_sitd(struct ehci_soft_itd *);
300 1.249 skrll Static void ehci_dump_itds(ehci_soft_itd_t *);
301 1.139 jmcneill Static void ehci_dump_itd(struct ehci_soft_itd *);
302 1.141 cegger Static void ehci_dump_exfer(struct ehci_xfer *);
303 1.5 augustss #endif
304 1.5 augustss
305 1.11 augustss #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
306 1.11 augustss
307 1.249 skrll static inline void
308 1.249 skrll ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex)
309 1.249 skrll {
310 1.249 skrll
311 1.249 skrll TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next);
312 1.249 skrll }
313 1.249 skrll
314 1.249 skrll static inline void
315 1.249 skrll ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex)
316 1.249 skrll {
317 1.5 augustss
318 1.249 skrll TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next);
319 1.249 skrll }
320 1.18 augustss
321 1.123 drochner Static const struct usbd_bus_methods ehci_bus_methods = {
322 1.249 skrll .ubm_open = ehci_open,
323 1.249 skrll .ubm_softint = ehci_softintr,
324 1.249 skrll .ubm_dopoll = ehci_poll,
325 1.249 skrll .ubm_allocx = ehci_allocx,
326 1.249 skrll .ubm_freex = ehci_freex,
327 1.271 riastrad .ubm_abortx = ehci_abortx,
328 1.271 riastrad .ubm_dying = ehci_dying,
329 1.249 skrll .ubm_getlock = ehci_get_lock,
330 1.249 skrll .ubm_rhctrl = ehci_roothub_ctrl,
331 1.5 augustss };
332 1.5 augustss
333 1.123 drochner Static const struct usbd_pipe_methods ehci_root_intr_methods = {
334 1.249 skrll .upm_transfer = ehci_root_intr_transfer,
335 1.249 skrll .upm_start = ehci_root_intr_start,
336 1.249 skrll .upm_abort = ehci_root_intr_abort,
337 1.249 skrll .upm_close = ehci_root_intr_close,
338 1.249 skrll .upm_cleartoggle = ehci_noop,
339 1.249 skrll .upm_done = ehci_root_intr_done,
340 1.5 augustss };
341 1.5 augustss
342 1.123 drochner Static const struct usbd_pipe_methods ehci_device_ctrl_methods = {
343 1.249 skrll .upm_init = ehci_device_ctrl_init,
344 1.249 skrll .upm_fini = ehci_device_ctrl_fini,
345 1.249 skrll .upm_transfer = ehci_device_ctrl_transfer,
346 1.249 skrll .upm_start = ehci_device_ctrl_start,
347 1.249 skrll .upm_abort = ehci_device_ctrl_abort,
348 1.249 skrll .upm_close = ehci_device_ctrl_close,
349 1.249 skrll .upm_cleartoggle = ehci_noop,
350 1.249 skrll .upm_done = ehci_device_ctrl_done,
351 1.5 augustss };
352 1.5 augustss
353 1.123 drochner Static const struct usbd_pipe_methods ehci_device_intr_methods = {
354 1.249 skrll .upm_init = ehci_device_intr_init,
355 1.249 skrll .upm_fini = ehci_device_intr_fini,
356 1.249 skrll .upm_transfer = ehci_device_intr_transfer,
357 1.249 skrll .upm_start = ehci_device_intr_start,
358 1.249 skrll .upm_abort = ehci_device_intr_abort,
359 1.249 skrll .upm_close = ehci_device_intr_close,
360 1.249 skrll .upm_cleartoggle = ehci_device_clear_toggle,
361 1.249 skrll .upm_done = ehci_device_intr_done,
362 1.5 augustss };
363 1.5 augustss
364 1.123 drochner Static const struct usbd_pipe_methods ehci_device_bulk_methods = {
365 1.249 skrll .upm_init = ehci_device_bulk_init,
366 1.249 skrll .upm_fini = ehci_device_bulk_fini,
367 1.249 skrll .upm_transfer = ehci_device_bulk_transfer,
368 1.249 skrll .upm_start = ehci_device_bulk_start,
369 1.249 skrll .upm_abort = ehci_device_bulk_abort,
370 1.249 skrll .upm_close = ehci_device_bulk_close,
371 1.249 skrll .upm_cleartoggle = ehci_device_clear_toggle,
372 1.249 skrll .upm_done = ehci_device_bulk_done,
373 1.5 augustss };
374 1.5 augustss
375 1.123 drochner Static const struct usbd_pipe_methods ehci_device_isoc_methods = {
376 1.249 skrll .upm_init = ehci_device_isoc_init,
377 1.249 skrll .upm_fini = ehci_device_isoc_fini,
378 1.249 skrll .upm_transfer = ehci_device_isoc_transfer,
379 1.249 skrll .upm_abort = ehci_device_isoc_abort,
380 1.249 skrll .upm_close = ehci_device_isoc_close,
381 1.249 skrll .upm_cleartoggle = ehci_noop,
382 1.249 skrll .upm_done = ehci_device_isoc_done,
383 1.249 skrll };
384 1.249 skrll
385 1.249 skrll Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = {
386 1.249 skrll .upm_init = ehci_device_fs_isoc_init,
387 1.249 skrll .upm_fini = ehci_device_fs_isoc_fini,
388 1.249 skrll .upm_transfer = ehci_device_fs_isoc_transfer,
389 1.249 skrll .upm_abort = ehci_device_fs_isoc_abort,
390 1.249 skrll .upm_close = ehci_device_fs_isoc_close,
391 1.249 skrll .upm_cleartoggle = ehci_noop,
392 1.249 skrll .upm_done = ehci_device_fs_isoc_done,
393 1.5 augustss };
394 1.5 augustss
395 1.123 drochner static const uint8_t revbits[EHCI_MAX_POLLRATE] = {
396 1.95 augustss 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78,
397 1.95 augustss 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c,
398 1.95 augustss 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a,
399 1.95 augustss 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e,
400 1.95 augustss 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79,
401 1.95 augustss 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d,
402 1.95 augustss 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b,
403 1.95 augustss 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f,
404 1.94 augustss };
405 1.94 augustss
406 1.249 skrll int
407 1.1 augustss ehci_init(ehci_softc_t *sc)
408 1.1 augustss {
409 1.290 skrll uint32_t vers, hcr;
410 1.3 augustss u_int i;
411 1.289 skrll int err;
412 1.11 augustss ehci_soft_qh_t *sqh;
413 1.89 augustss u_int ncomp;
414 1.3 augustss
415 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
416 1.6 augustss #ifdef EHCI_DEBUG
417 1.6 augustss theehci = sc;
418 1.6 augustss #endif
419 1.3 augustss
420 1.309 riastrad mutex_init(&sc->sc_rhlock, MUTEX_DEFAULT, IPL_NONE);
421 1.190 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
422 1.243 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
423 1.260 mrg cv_init(&sc->sc_doorbell, "ehcidb");
424 1.190 mrg
425 1.204 christos sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0,
426 1.204 christos "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL);
427 1.204 christos
428 1.253 skrll sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
429 1.190 mrg ehci_doorbell, sc);
430 1.211 matt KASSERT(sc->sc_doorbell_si != NULL);
431 1.253 skrll sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
432 1.190 mrg ehci_pcd, sc);
433 1.211 matt KASSERT(sc->sc_pcd_si != NULL);
434 1.190 mrg
435 1.3 augustss sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
436 1.3 augustss
437 1.104 christos vers = EREAD2(sc, EHCI_HCIVERSION);
438 1.134 drochner aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev),
439 1.249 skrll vers >> 8, vers & 0xff);
440 1.3 augustss
441 1.290 skrll const uint32_t hcsparams = EREAD4(sc, EHCI_HCSPARAMS);
442 1.290 skrll DPRINTF("hcsparams=%#jx", hcsparams, 0, 0, 0);
443 1.290 skrll sc->sc_npcomp = EHCI_HCS_N_PCC(hcsparams);
444 1.290 skrll ncomp = EHCI_HCS_N_CC(hcsparams);
445 1.89 augustss if (ncomp != sc->sc_ncomp) {
446 1.121 ad aprint_verbose("%s: wrong number of companions (%d != %d)\n",
447 1.267 maxv device_xname(sc->sc_dev), ncomp, sc->sc_ncomp);
448 1.47 augustss #if NOHCI == 0 || NUHCI == 0
449 1.47 augustss aprint_error("%s: ohci or uhci probably not configured\n",
450 1.267 maxv device_xname(sc->sc_dev));
451 1.47 augustss #endif
452 1.89 augustss if (ncomp < sc->sc_ncomp)
453 1.89 augustss sc->sc_ncomp = ncomp;
454 1.3 augustss }
455 1.3 augustss if (sc->sc_ncomp > 0) {
456 1.172 matt KASSERT(!(sc->sc_flags & EHCIF_ETTF));
457 1.265 mrg aprint_normal_dev(sc->sc_dev,
458 1.265 mrg "%d companion controller%s, %d port%s%s",
459 1.265 mrg sc->sc_ncomp,
460 1.255 jmcneill sc->sc_ncomp!=1 ? "s" : "",
461 1.290 skrll EHCI_HCS_N_PCC(hcsparams),
462 1.290 skrll EHCI_HCS_N_PCC(hcsparams)!=1 ? "s" : "",
463 1.255 jmcneill sc->sc_ncomp!=1 ? " each" : "");
464 1.255 jmcneill if (sc->sc_comps[0]) {
465 1.255 jmcneill aprint_normal(":");
466 1.255 jmcneill for (i = 0; i < sc->sc_ncomp; i++)
467 1.255 jmcneill aprint_normal(" %s",
468 1.255 jmcneill device_xname(sc->sc_comps[i]));
469 1.255 jmcneill }
470 1.41 thorpej aprint_normal("\n");
471 1.265 mrg
472 1.265 mrg mutex_init(&sc->sc_complock, MUTEX_DEFAULT, IPL_USB);
473 1.265 mrg callout_init(&sc->sc_compcallout, CALLOUT_MPSAFE);
474 1.265 mrg cv_init(&sc->sc_compcv, "ehciccv");
475 1.265 mrg sc->sc_comp_state = CO_EARLY;
476 1.3 augustss }
477 1.290 skrll sc->sc_noport = EHCI_HCS_N_PORTS(hcsparams);
478 1.290 skrll sc->sc_hasppc = EHCI_HCS_PPC(hcsparams);
479 1.249 skrll
480 1.290 skrll const uint32_t hccparams = EREAD4(sc, EHCI_HCCPARAMS);
481 1.290 skrll DPRINTF("hccparams=%#jx", hccparams, 0, 0, 0);
482 1.36 augustss
483 1.290 skrll if (EHCI_HCC_64BIT(hccparams)) {
484 1.36 augustss /* MUST clear segment register if 64 bit capable. */
485 1.242 msaitoh EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
486 1.36 augustss }
487 1.33 augustss
488 1.290 skrll if (hccparams & EHCI_HCC_IST_FULLFRAME) {
489 1.249 skrll sc->sc_istthreshold = 0;
490 1.249 skrll } else {
491 1.290 skrll sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(hccparams);
492 1.249 skrll }
493 1.3 augustss
494 1.249 skrll sc->sc_bus.ub_revision = USBREV_2_0;
495 1.249 skrll sc->sc_bus.ub_usedma = true;
496 1.249 skrll sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG;
497 1.90 fvdl
498 1.297 skrll /*
499 1.297 skrll * The bus attachment code will possibly provide a 64bit DMA
500 1.297 skrll * tag which we now limit to the bottom 4G range as
501 1.297 skrll *
502 1.297 skrll * - that's as much as ehci can address in its QH, TD, iTD, and siTD
503 1.297 skrll * structures; and
504 1.297 skrll * - the driver doesn't currently set EHCI_CTRLDSSEGMENT to anything
505 1.297 skrll * other than 0.
506 1.297 skrll */
507 1.302 macallan bus_dma_tag_t ntag = sc->sc_bus.ub_dmatag;
508 1.297 skrll sc->sc_dmatag = sc->sc_bus.ub_dmatag;
509 1.297 skrll err = bus_dmatag_subregion(sc->sc_bus.ub_dmatag, 0, UINT32_MAX,
510 1.297 skrll &ntag, 0);
511 1.297 skrll if (err == 0) {
512 1.297 skrll sc->sc_dmatag = ntag;
513 1.297 skrll aprint_normal_dev(sc->sc_dev, "Using DMA subregion for control"
514 1.297 skrll " data structures\n");
515 1.297 skrll }
516 1.297 skrll
517 1.3 augustss /* Reset the controller */
518 1.249 skrll DPRINTF("resetting", 0, 0, 0, 0);
519 1.3 augustss EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
520 1.3 augustss usb_delay_ms(&sc->sc_bus, 1);
521 1.3 augustss EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
522 1.3 augustss for (i = 0; i < 100; i++) {
523 1.34 augustss usb_delay_ms(&sc->sc_bus, 1);
524 1.3 augustss hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
525 1.3 augustss if (!hcr)
526 1.3 augustss break;
527 1.3 augustss }
528 1.3 augustss if (hcr) {
529 1.297 skrll aprint_error_dev(sc->sc_dev, "reset timeout\n");
530 1.297 skrll err = EIO;
531 1.297 skrll goto fail1;
532 1.3 augustss }
533 1.170 kiyohara if (sc->sc_vendor_init)
534 1.170 kiyohara sc->sc_vendor_init(sc);
535 1.3 augustss
536 1.78 augustss /* XXX need proper intr scheduling */
537 1.78 augustss sc->sc_rand = 96;
538 1.78 augustss
539 1.3 augustss /* frame list size at default, read back what we got and use that */
540 1.3 augustss switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
541 1.78 augustss case 0: sc->sc_flsize = 1024; break;
542 1.78 augustss case 1: sc->sc_flsize = 512; break;
543 1.78 augustss case 2: sc->sc_flsize = 256; break;
544 1.297 skrll case 3:
545 1.297 skrll err = EIO;
546 1.297 skrll goto fail1;
547 1.3 augustss }
548 1.298 skrll err = usb_allocmem(sc->sc_dmatag,
549 1.293 skrll sc->sc_flsize * sizeof(ehci_link_t),
550 1.278 skrll EHCI_FLALIGN_ALIGN, USBMALLOC_COHERENT, &sc->sc_fldma);
551 1.297 skrll if (err) {
552 1.297 skrll aprint_error_dev(sc->sc_dev, "failed to allocate frame list\n");
553 1.297 skrll goto fail1;
554 1.297 skrll }
555 1.256 pgoyette DPRINTF("flsize=%jd", sc->sc_flsize, 0, 0, 0);
556 1.78 augustss sc->sc_flist = KERNADDR(&sc->sc_fldma, 0);
557 1.139 jmcneill
558 1.139 jmcneill for (i = 0; i < sc->sc_flsize; i++) {
559 1.139 jmcneill sc->sc_flist[i] = EHCI_NULL;
560 1.139 jmcneill }
561 1.139 jmcneill
562 1.298 skrll const bus_addr_t flba = DMAADDR(&sc->sc_fldma, 0);
563 1.298 skrll const uint32_t hi32 = BUS_ADDR_HI32(flba);
564 1.298 skrll if (hi32 != 0) {
565 1.298 skrll aprint_error_dev(sc->sc_dev, "DMA memory segment error (%08x)\n",
566 1.298 skrll hi32);
567 1.298 skrll goto fail2;
568 1.298 skrll }
569 1.297 skrll
570 1.298 skrll const uint32_t lo32 = BUS_ADDR_LO32(flba);
571 1.297 skrll EOWRITE4(sc, EHCI_PERIODICLISTBASE, lo32);
572 1.3 augustss
573 1.190 mrg sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *),
574 1.267 maxv KM_SLEEP);
575 1.139 jmcneill LIST_INIT(&sc->sc_freeitds);
576 1.249 skrll LIST_INIT(&sc->sc_freesitds);
577 1.153 jmcneill TAILQ_INIT(&sc->sc_intrhead);
578 1.139 jmcneill
579 1.5 augustss /* Set up the bus struct. */
580 1.249 skrll sc->sc_bus.ub_methods = &ehci_bus_methods;
581 1.267 maxv sc->sc_bus.ub_pipesize = sizeof(struct ehci_pipe);
582 1.5 augustss
583 1.6 augustss sc->sc_eintrs = EHCI_NORMAL_INTRS;
584 1.6 augustss
585 1.78 augustss /*
586 1.78 augustss * Allocate the interrupt dummy QHs. These are arranged to give poll
587 1.78 augustss * intervals that are powers of 2 times 1ms.
588 1.78 augustss */
589 1.297 skrll memset(sc->sc_islots, 0, sizeof(sc->sc_islots));
590 1.78 augustss for (i = 0; i < EHCI_INTRQHS; i++) {
591 1.78 augustss sqh = ehci_alloc_sqh(sc);
592 1.78 augustss if (sqh == NULL) {
593 1.249 skrll err = ENOMEM;
594 1.298 skrll goto fail3;
595 1.78 augustss }
596 1.78 augustss sc->sc_islots[i].sqh = sqh;
597 1.78 augustss }
598 1.78 augustss for (i = 0; i < EHCI_INTRQHS; i++) {
599 1.78 augustss sqh = sc->sc_islots[i].sqh;
600 1.78 augustss if (i == 0) {
601 1.78 augustss /* The last (1ms) QH terminates. */
602 1.78 augustss sqh->qh.qh_link = EHCI_NULL;
603 1.78 augustss sqh->next = NULL;
604 1.78 augustss } else {
605 1.78 augustss /* Otherwise the next QH has half the poll interval */
606 1.78 augustss sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh;
607 1.78 augustss sqh->qh.qh_link = htole32(sqh->next->physaddr |
608 1.78 augustss EHCI_LINK_QH);
609 1.78 augustss }
610 1.78 augustss sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
611 1.241 skrll sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1));
612 1.78 augustss sqh->qh.qh_curqtd = EHCI_NULL;
613 1.78 augustss sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
614 1.78 augustss sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
615 1.78 augustss sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
616 1.78 augustss sqh->sqtd = NULL;
617 1.138 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
618 1.138 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
619 1.78 augustss }
620 1.78 augustss /* Point the frame list at the last level (128ms). */
621 1.78 augustss for (i = 0; i < sc->sc_flsize; i++) {
622 1.94 augustss int j;
623 1.94 augustss
624 1.94 augustss j = (i & ~(EHCI_MAX_POLLRATE-1)) |
625 1.94 augustss revbits[i & (EHCI_MAX_POLLRATE-1)];
626 1.94 augustss sc->sc_flist[j] = htole32(EHCI_LINK_QH |
627 1.78 augustss sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1,
628 1.78 augustss i)].sqh->physaddr);
629 1.78 augustss }
630 1.138 bouyer usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t),
631 1.138 bouyer BUS_DMASYNC_PREWRITE);
632 1.78 augustss
633 1.11 augustss /* Allocate dummy QH that starts the async list. */
634 1.11 augustss sqh = ehci_alloc_sqh(sc);
635 1.11 augustss if (sqh == NULL) {
636 1.249 skrll err = ENOMEM;
637 1.298 skrll goto fail3;
638 1.9 augustss }
639 1.11 augustss /* Fill the QH */
640 1.11 augustss sqh->qh.qh_endp =
641 1.11 augustss htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
642 1.11 augustss sqh->qh.qh_link =
643 1.11 augustss htole32(sqh->physaddr | EHCI_LINK_QH);
644 1.11 augustss sqh->qh.qh_curqtd = EHCI_NULL;
645 1.11 augustss sqh->next = NULL;
646 1.11 augustss /* Fill the overlay qTD */
647 1.11 augustss sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
648 1.11 augustss sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
649 1.26 augustss sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
650 1.11 augustss sqh->sqtd = NULL;
651 1.138 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
652 1.138 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
653 1.9 augustss #ifdef EHCI_DEBUG
654 1.249 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
655 1.229 skrll ehci_dump_sqh(sqh);
656 1.249 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
657 1.9 augustss #endif
658 1.9 augustss
659 1.9 augustss /* Point to async list */
660 1.11 augustss sc->sc_async_head = sqh;
661 1.11 augustss EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
662 1.9 augustss
663 1.190 mrg callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE);
664 1.10 augustss
665 1.6 augustss /* Turn on controller */
666 1.6 augustss EOWRITE4(sc, EHCI_USBCMD,
667 1.88 augustss EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */
668 1.6 augustss (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
669 1.10 augustss EHCI_CMD_ASE |
670 1.78 augustss EHCI_CMD_PSE |
671 1.6 augustss EHCI_CMD_RS);
672 1.6 augustss
673 1.6 augustss /* Take over port ownership */
674 1.6 augustss EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
675 1.6 augustss
676 1.8 augustss for (i = 0; i < 100; i++) {
677 1.34 augustss usb_delay_ms(&sc->sc_bus, 1);
678 1.8 augustss hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
679 1.8 augustss if (!hcr)
680 1.8 augustss break;
681 1.8 augustss }
682 1.8 augustss if (hcr) {
683 1.134 drochner aprint_error("%s: run timeout\n", device_xname(sc->sc_dev));
684 1.297 skrll err = EIO;
685 1.298 skrll goto fail4;
686 1.8 augustss }
687 1.8 augustss
688 1.105 augustss /* Enable interrupts */
689 1.263 skrll DPRINTF("enabling interrupts", 0, 0, 0, 0);
690 1.105 augustss EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
691 1.105 augustss
692 1.249 skrll return 0;
693 1.9 augustss
694 1.298 skrll fail4:
695 1.15 augustss ehci_free_sqh(sc, sc->sc_async_head);
696 1.297 skrll
697 1.298 skrll fail3:
698 1.297 skrll for (i = 0; i < EHCI_INTRQHS; i++) {
699 1.297 skrll sqh = sc->sc_islots[i].sqh;
700 1.297 skrll if (sqh)
701 1.297 skrll ehci_free_sqh(sc, sqh);
702 1.297 skrll }
703 1.297 skrll
704 1.297 skrll kmem_free(sc->sc_softitds, sc->sc_flsize * sizeof(ehci_soft_itd_t *));
705 1.298 skrll
706 1.298 skrll fail2:
707 1.293 skrll usb_freemem(&sc->sc_fldma);
708 1.297 skrll
709 1.297 skrll fail1:
710 1.297 skrll softint_disestablish(sc->sc_doorbell_si);
711 1.297 skrll softint_disestablish(sc->sc_pcd_si);
712 1.309 riastrad mutex_destroy(&sc->sc_rhlock);
713 1.297 skrll mutex_destroy(&sc->sc_lock);
714 1.297 skrll mutex_destroy(&sc->sc_intr_lock);
715 1.297 skrll
716 1.249 skrll return err;
717 1.1 augustss }
718 1.1 augustss
719 1.1 augustss int
720 1.1 augustss ehci_intr(void *v)
721 1.1 augustss {
722 1.6 augustss ehci_softc_t *sc = v;
723 1.190 mrg int ret = 0;
724 1.6 augustss
725 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
726 1.229 skrll
727 1.190 mrg if (sc == NULL)
728 1.190 mrg return 0;
729 1.190 mrg
730 1.190 mrg mutex_spin_enter(&sc->sc_intr_lock);
731 1.190 mrg
732 1.190 mrg if (sc->sc_dying || !device_has_power(sc->sc_dev))
733 1.190 mrg goto done;
734 1.15 augustss
735 1.6 augustss /* If we get an interrupt while polling, then just ignore it. */
736 1.249 skrll if (sc->sc_bus.ub_usepolling) {
737 1.249 skrll uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
738 1.78 augustss
739 1.78 augustss if (intrs)
740 1.78 augustss EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
741 1.249 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
742 1.190 mrg goto done;
743 1.6 augustss }
744 1.6 augustss
745 1.190 mrg ret = ehci_intr1(sc);
746 1.190 mrg
747 1.190 mrg done:
748 1.190 mrg mutex_spin_exit(&sc->sc_intr_lock);
749 1.190 mrg return ret;
750 1.6 augustss }
751 1.6 augustss
752 1.6 augustss Static int
753 1.6 augustss ehci_intr1(ehci_softc_t *sc)
754 1.6 augustss {
755 1.249 skrll uint32_t intrs, eintrs;
756 1.6 augustss
757 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
758 1.6 augustss
759 1.6 augustss /* In case the interrupt occurs before initialization has completed. */
760 1.6 augustss if (sc == NULL) {
761 1.6 augustss #ifdef DIAGNOSTIC
762 1.72 augustss printf("ehci_intr1: sc == NULL\n");
763 1.6 augustss #endif
764 1.249 skrll return 0;
765 1.6 augustss }
766 1.6 augustss
767 1.190 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
768 1.190 mrg
769 1.6 augustss intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
770 1.6 augustss if (!intrs)
771 1.249 skrll return 0;
772 1.6 augustss
773 1.6 augustss eintrs = intrs & sc->sc_eintrs;
774 1.256 pgoyette DPRINTF("sc=%#jx intrs=%#jx(%#jx) eintrs=%#jx", (uintptr_t)sc, intrs,
775 1.249 skrll EOREAD4(sc, EHCI_USBSTS), eintrs);
776 1.6 augustss if (!eintrs)
777 1.249 skrll return 0;
778 1.6 augustss
779 1.68 mycroft EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
780 1.10 augustss if (eintrs & EHCI_STS_IAA) {
781 1.249 skrll DPRINTF("door bell", 0, 0, 0, 0);
782 1.190 mrg kpreempt_disable();
783 1.211 matt KASSERT(sc->sc_doorbell_si != NULL);
784 1.190 mrg softint_schedule(sc->sc_doorbell_si);
785 1.190 mrg kpreempt_enable();
786 1.20 augustss eintrs &= ~EHCI_STS_IAA;
787 1.10 augustss }
788 1.18 augustss if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
789 1.256 pgoyette DPRINTF("INT=%jd ERRINT=%jd",
790 1.229 skrll eintrs & EHCI_STS_INT ? 1 : 0,
791 1.229 skrll eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0);
792 1.18 augustss usb_schedsoftintr(&sc->sc_bus);
793 1.21 augustss eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
794 1.6 augustss }
795 1.6 augustss if (eintrs & EHCI_STS_HSE) {
796 1.6 augustss printf("%s: unrecoverable error, controller halted\n",
797 1.134 drochner device_xname(sc->sc_dev));
798 1.6 augustss /* XXX what else */
799 1.6 augustss }
800 1.6 augustss if (eintrs & EHCI_STS_PCD) {
801 1.190 mrg kpreempt_disable();
802 1.211 matt KASSERT(sc->sc_pcd_si != NULL);
803 1.190 mrg softint_schedule(sc->sc_pcd_si);
804 1.190 mrg kpreempt_enable();
805 1.6 augustss eintrs &= ~EHCI_STS_PCD;
806 1.6 augustss }
807 1.6 augustss
808 1.6 augustss if (eintrs != 0) {
809 1.6 augustss /* Block unprocessed interrupts. */
810 1.6 augustss sc->sc_eintrs &= ~eintrs;
811 1.6 augustss EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
812 1.276 christos printf("%s: blocking intrs %#x\n",
813 1.134 drochner device_xname(sc->sc_dev), eintrs);
814 1.6 augustss }
815 1.6 augustss
816 1.249 skrll return 1;
817 1.6 augustss }
818 1.6 augustss
819 1.190 mrg Static void
820 1.190 mrg ehci_doorbell(void *addr)
821 1.190 mrg {
822 1.190 mrg ehci_softc_t *sc = addr;
823 1.260 mrg EHCIHIST_FUNC(); EHCIHIST_CALLED();
824 1.190 mrg
825 1.190 mrg mutex_enter(&sc->sc_lock);
826 1.308 riastrad if (sc->sc_doorbelllwp == NULL)
827 1.308 riastrad DPRINTF("spurious doorbell interrupt", 0, 0, 0, 0);
828 1.308 riastrad sc->sc_doorbelllwp = NULL;
829 1.308 riastrad cv_signal(&sc->sc_doorbell);
830 1.190 mrg mutex_exit(&sc->sc_lock);
831 1.190 mrg }
832 1.6 augustss
833 1.164 uebayasi Static void
834 1.190 mrg ehci_pcd(void *addr)
835 1.6 augustss {
836 1.190 mrg ehci_softc_t *sc = addr;
837 1.249 skrll struct usbd_xfer *xfer;
838 1.6 augustss u_char *p;
839 1.6 augustss int i, m;
840 1.6 augustss
841 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
842 1.229 skrll
843 1.190 mrg mutex_enter(&sc->sc_lock);
844 1.190 mrg xfer = sc->sc_intrxfer;
845 1.190 mrg
846 1.6 augustss if (xfer == NULL) {
847 1.6 augustss /* Just ignore the change. */
848 1.190 mrg goto done;
849 1.6 augustss }
850 1.273 riastrad KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
851 1.6 augustss
852 1.249 skrll p = xfer->ux_buf;
853 1.262 riastrad m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1);
854 1.249 skrll memset(p, 0, xfer->ux_length);
855 1.6 augustss for (i = 1; i <= m; i++) {
856 1.6 augustss /* Pick out CHANGE bits from the status reg. */
857 1.6 augustss if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
858 1.6 augustss p[i/8] |= 1 << (i%8);
859 1.229 skrll if (i % 8 == 7)
860 1.277 christos DPRINTF("change(%jd)=0x%02jx", i / 8, p[i/8], 0, 0);
861 1.6 augustss }
862 1.249 skrll xfer->ux_actlen = xfer->ux_length;
863 1.249 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
864 1.6 augustss
865 1.6 augustss usb_transfer_complete(xfer);
866 1.190 mrg
867 1.190 mrg done:
868 1.190 mrg mutex_exit(&sc->sc_lock);
869 1.1 augustss }
870 1.1 augustss
871 1.164 uebayasi Static void
872 1.5 augustss ehci_softintr(void *v)
873 1.5 augustss {
874 1.134 drochner struct usbd_bus *bus = v;
875 1.249 skrll ehci_softc_t *sc = EHCI_BUS2SC(bus);
876 1.53 chs struct ehci_xfer *ex, *nextex;
877 1.18 augustss
878 1.249 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
879 1.190 mrg
880 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
881 1.249 skrll
882 1.249 skrll ex_completeq_t cq;
883 1.249 skrll TAILQ_INIT(&cq);
884 1.18 augustss
885 1.18 augustss /*
886 1.18 augustss * The only explanation I can think of for why EHCI is as brain dead
887 1.18 augustss * as UHCI interrupt-wise is that Intel was involved in both.
888 1.18 augustss * An interrupt just tells us that something is done, we have no
889 1.18 augustss * clue what, so we need to scan through all active transfers. :-(
890 1.18 augustss */
891 1.249 skrll
892 1.249 skrll /*
893 1.249 skrll * ehci_idone will remove transfer from sc->sc_intrhead if it's
894 1.249 skrll * complete and add to our cq list
895 1.249 skrll *
896 1.249 skrll */
897 1.249 skrll TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) {
898 1.249 skrll switch (ex->ex_type) {
899 1.249 skrll case EX_CTRL:
900 1.249 skrll case EX_BULK:
901 1.249 skrll case EX_INTR:
902 1.249 skrll ehci_check_qh_intr(sc, ex, &cq);
903 1.249 skrll break;
904 1.249 skrll case EX_ISOC:
905 1.249 skrll ehci_check_itd_intr(sc, ex, &cq);
906 1.249 skrll break;
907 1.249 skrll case EX_FS_ISOC:
908 1.249 skrll ehci_check_sitd_intr(sc, ex, &cq);
909 1.249 skrll break;
910 1.249 skrll default:
911 1.249 skrll KASSERT(false);
912 1.249 skrll }
913 1.249 skrll
914 1.249 skrll }
915 1.249 skrll
916 1.249 skrll /*
917 1.249 skrll * We abuse ex_next for the interrupt and complete lists and
918 1.249 skrll * interrupt transfers will get re-added here so use
919 1.249 skrll * the _SAFE version of TAILQ_FOREACH.
920 1.249 skrll */
921 1.249 skrll TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) {
922 1.249 skrll usb_transfer_complete(&ex->ex_xfer);
923 1.53 chs }
924 1.18 augustss
925 1.108 xtraeme /* Schedule a callout to catch any dropped transactions. */
926 1.108 xtraeme if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) &&
927 1.153 jmcneill !TAILQ_EMPTY(&sc->sc_intrhead))
928 1.190 mrg callout_reset(&sc->sc_tmo_intrlist,
929 1.190 mrg hz, ehci_intrlist_timeout, sc);
930 1.18 augustss }
931 1.18 augustss
932 1.164 uebayasi Static void
933 1.249 skrll ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq)
934 1.18 augustss {
935 1.249 skrll ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd;
936 1.249 skrll uint32_t status;
937 1.18 augustss
938 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
939 1.18 augustss
940 1.249 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
941 1.190 mrg
942 1.249 skrll if (ex->ex_type == EX_CTRL) {
943 1.249 skrll fsqtd = ex->ex_setup;
944 1.249 skrll lsqtd = ex->ex_status;
945 1.249 skrll } else {
946 1.249 skrll fsqtd = ex->ex_sqtdstart;
947 1.249 skrll lsqtd = ex->ex_sqtdend;
948 1.18 augustss }
949 1.249 skrll KASSERTMSG(fsqtd != NULL && lsqtd != NULL,
950 1.249 skrll "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd);
951 1.139 jmcneill
952 1.33 augustss /*
953 1.18 augustss * If the last TD is still active we need to check whether there
954 1.210 skrll * is an error somewhere in the middle, or whether there was a
955 1.18 augustss * short packet (SPD and not ACTIVE).
956 1.18 augustss */
957 1.138 bouyer usb_syncmem(&lsqtd->dma,
958 1.138 bouyer lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
959 1.138 bouyer sizeof(lsqtd->qtd.qtd_status),
960 1.138 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
961 1.205 tsutsui status = le32toh(lsqtd->qtd.qtd_status);
962 1.205 tsutsui usb_syncmem(&lsqtd->dma,
963 1.205 tsutsui lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
964 1.205 tsutsui sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
965 1.205 tsutsui if (status & EHCI_QTD_ACTIVE) {
966 1.256 pgoyette DPRINTFN(10, "active ex=%#jx", (uintptr_t)ex, 0, 0, 0);
967 1.249 skrll
968 1.249 skrll /* last qTD has already been checked */
969 1.249 skrll for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) {
970 1.138 bouyer usb_syncmem(&sqtd->dma,
971 1.138 bouyer sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
972 1.138 bouyer sizeof(sqtd->qtd.qtd_status),
973 1.138 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
974 1.18 augustss status = le32toh(sqtd->qtd.qtd_status);
975 1.138 bouyer usb_syncmem(&sqtd->dma,
976 1.138 bouyer sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
977 1.138 bouyer sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
978 1.18 augustss /* If there's an active QTD the xfer isn't done. */
979 1.18 augustss if (status & EHCI_QTD_ACTIVE)
980 1.18 augustss break;
981 1.18 augustss /* Any kind of error makes the xfer done. */
982 1.18 augustss if (status & EHCI_QTD_HALTED)
983 1.18 augustss goto done;
984 1.221 skrll /* Handle short packets */
985 1.221 skrll if (EHCI_QTD_GET_BYTES(status) != 0) {
986 1.221 skrll /*
987 1.221 skrll * If we get here for a control transfer then
988 1.221 skrll * we need to let the hardware complete the
989 1.221 skrll * status phase. That is, we're not done
990 1.221 skrll * quite yet.
991 1.221 skrll *
992 1.221 skrll * Otherwise, we're done.
993 1.221 skrll */
994 1.249 skrll if (ex->ex_type == EX_CTRL) {
995 1.221 skrll break;
996 1.221 skrll }
997 1.18 augustss goto done;
998 1.221 skrll }
999 1.18 augustss }
1000 1.256 pgoyette DPRINTFN(10, "ex=%#jx std=%#jx still active",
1001 1.256 pgoyette (uintptr_t)ex, (uintptr_t)ex->ex_sqtdstart, 0, 0);
1002 1.237 skrll #ifdef EHCI_DEBUG
1003 1.249 skrll DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0);
1004 1.249 skrll ehci_dump_sqtds(ex->ex_sqtdstart);
1005 1.249 skrll DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0);
1006 1.237 skrll #endif
1007 1.18 augustss return;
1008 1.18 augustss }
1009 1.18 augustss done:
1010 1.256 pgoyette DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0);
1011 1.249 skrll ehci_idone(ex, cq);
1012 1.18 augustss }
1013 1.18 augustss
1014 1.164 uebayasi Static void
1015 1.249 skrll ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq)
1016 1.190 mrg {
1017 1.139 jmcneill ehci_soft_itd_t *itd;
1018 1.139 jmcneill int i;
1019 1.139 jmcneill
1020 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1021 1.229 skrll
1022 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
1023 1.190 mrg
1024 1.249 skrll if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue))
1025 1.153 jmcneill return;
1026 1.153 jmcneill
1027 1.249 skrll KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL,
1028 1.249 skrll "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend);
1029 1.139 jmcneill
1030 1.249 skrll itd = ex->ex_itdend;
1031 1.139 jmcneill
1032 1.139 jmcneill /*
1033 1.153 jmcneill * check no active transfers in last itd, meaning we're finished
1034 1.139 jmcneill */
1035 1.139 jmcneill
1036 1.139 jmcneill usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl),
1037 1.249 skrll sizeof(itd->itd.itd_ctl),
1038 1.249 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1039 1.139 jmcneill
1040 1.168 jakllsch for (i = 0; i < EHCI_ITD_NUFRAMES; i++) {
1041 1.139 jmcneill if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE)
1042 1.152 jmcneill break;
1043 1.139 jmcneill }
1044 1.139 jmcneill
1045 1.168 jakllsch if (i == EHCI_ITD_NUFRAMES) {
1046 1.139 jmcneill goto done; /* All 8 descriptors inactive, it's done */
1047 1.139 jmcneill }
1048 1.139 jmcneill
1049 1.249 skrll usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl),
1050 1.249 skrll sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD);
1051 1.249 skrll
1052 1.256 pgoyette DPRINTFN(10, "ex %#jx itd %#jx still active",
1053 1.256 pgoyette (uintptr_t)ex, (uintptr_t)ex->ex_itdstart, 0, 0);
1054 1.139 jmcneill return;
1055 1.139 jmcneill done:
1056 1.256 pgoyette DPRINTF("ex %#jx done", (uintptr_t)ex, 0, 0, 0);
1057 1.249 skrll ehci_idone(ex, cq);
1058 1.249 skrll }
1059 1.249 skrll
1060 1.249 skrll void
1061 1.249 skrll ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq)
1062 1.249 skrll {
1063 1.249 skrll ehci_soft_sitd_t *sitd;
1064 1.249 skrll
1065 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1066 1.249 skrll
1067 1.249 skrll KASSERT(mutex_owned(&sc->sc_lock));
1068 1.249 skrll
1069 1.249 skrll if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue))
1070 1.249 skrll return;
1071 1.249 skrll
1072 1.249 skrll KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL,
1073 1.249 skrll "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend);
1074 1.249 skrll
1075 1.249 skrll sitd = ex->ex_sitdend;
1076 1.249 skrll
1077 1.249 skrll /*
1078 1.249 skrll * check no active transfers in last sitd, meaning we're finished
1079 1.249 skrll */
1080 1.249 skrll
1081 1.249 skrll usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans),
1082 1.249 skrll sizeof(sitd->sitd.sitd_trans),
1083 1.249 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1084 1.249 skrll
1085 1.249 skrll bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0);
1086 1.249 skrll
1087 1.249 skrll usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans),
1088 1.249 skrll sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD);
1089 1.249 skrll
1090 1.249 skrll if (active)
1091 1.249 skrll return;
1092 1.249 skrll
1093 1.256 pgoyette DPRINTFN(10, "ex=%#jx done", (uintptr_t)ex, 0, 0, 0);
1094 1.249 skrll ehci_idone(ex, cq);
1095 1.139 jmcneill }
1096 1.139 jmcneill
1097 1.164 uebayasi Static void
1098 1.249 skrll ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq)
1099 1.18 augustss {
1100 1.260 mrg EHCIHIST_FUNC(); EHCIHIST_CALLED();
1101 1.249 skrll struct usbd_xfer *xfer = &ex->ex_xfer;
1102 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
1103 1.249 skrll struct ehci_softc *sc = EHCI_XFER2SC(xfer);
1104 1.249 skrll ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd;
1105 1.249 skrll uint32_t status = 0, nstatus = 0;
1106 1.249 skrll int actlen = 0;
1107 1.249 skrll
1108 1.261 jakllsch KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1109 1.229 skrll
1110 1.256 pgoyette DPRINTF("ex=%#jx", (uintptr_t)ex, 0, 0, 0);
1111 1.190 mrg
1112 1.260 mrg /*
1113 1.271 riastrad * Try to claim this xfer for completion. If it has already
1114 1.271 riastrad * completed or aborted, drop it on the floor.
1115 1.260 mrg */
1116 1.271 riastrad if (!usbd_xfer_trycomplete(xfer))
1117 1.249 skrll return;
1118 1.260 mrg
1119 1.18 augustss #ifdef DIAGNOSTIC
1120 1.18 augustss #ifdef EHCI_DEBUG
1121 1.249 skrll if (ex->ex_isdone) {
1122 1.249 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
1123 1.216 skrll ehci_dump_exfer(ex);
1124 1.249 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
1125 1.249 skrll }
1126 1.18 augustss #endif
1127 1.249 skrll KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer,
1128 1.249 skrll ex->ex_type, xfer->ux_status);
1129 1.249 skrll ex->ex_isdone = true;
1130 1.18 augustss #endif
1131 1.217 skrll
1132 1.256 pgoyette DPRINTF("xfer=%#jx, pipe=%#jx ready", (uintptr_t)xfer,
1133 1.256 pgoyette (uintptr_t)epipe, 0, 0);
1134 1.18 augustss
1135 1.18 augustss /* The transfer is done, compute actual length and status. */
1136 1.249 skrll if (ex->ex_type == EX_ISOC) {
1137 1.249 skrll /* HS isoc transfer */
1138 1.139 jmcneill
1139 1.139 jmcneill struct ehci_soft_itd *itd;
1140 1.139 jmcneill int i, nframes, len, uframes;
1141 1.139 jmcneill
1142 1.139 jmcneill nframes = 0;
1143 1.139 jmcneill
1144 1.249 skrll #ifdef EHCI_DEBUG
1145 1.249 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
1146 1.249 skrll ehci_dump_itds(ex->ex_itdstart);
1147 1.249 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
1148 1.249 skrll #endif
1149 1.249 skrll
1150 1.249 skrll i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
1151 1.262 riastrad uframes = uimin(1 << (i - 1), USB_UFRAMES_PER_FRAME);
1152 1.139 jmcneill
1153 1.249 skrll for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) {
1154 1.249 skrll usb_syncmem(&itd->dma,
1155 1.249 skrll itd->offs + offsetof(ehci_itd_t,itd_ctl),
1156 1.249 skrll sizeof(itd->itd.itd_ctl),
1157 1.249 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1158 1.139 jmcneill
1159 1.168 jakllsch for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) {
1160 1.249 skrll /*
1161 1.249 skrll * XXX - driver didn't fill in the frame full
1162 1.139 jmcneill * of uframes. This leads to scheduling
1163 1.139 jmcneill * inefficiencies, but working around
1164 1.139 jmcneill * this doubles complexity of tracking
1165 1.139 jmcneill * an xfer.
1166 1.139 jmcneill */
1167 1.249 skrll if (nframes >= xfer->ux_nframes)
1168 1.139 jmcneill break;
1169 1.139 jmcneill
1170 1.139 jmcneill status = le32toh(itd->itd.itd_ctl[i]);
1171 1.139 jmcneill len = EHCI_ITD_GET_LEN(status);
1172 1.155 jmorse if (EHCI_ITD_GET_STATUS(status) != 0)
1173 1.155 jmorse len = 0; /*No valid data on error*/
1174 1.155 jmorse
1175 1.249 skrll xfer->ux_frlengths[nframes++] = len;
1176 1.139 jmcneill actlen += len;
1177 1.139 jmcneill }
1178 1.249 skrll usb_syncmem(&itd->dma,
1179 1.249 skrll itd->offs + offsetof(ehci_itd_t,itd_ctl),
1180 1.249 skrll sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD);
1181 1.249 skrll
1182 1.249 skrll if (nframes >= xfer->ux_nframes)
1183 1.249 skrll break;
1184 1.249 skrll }
1185 1.249 skrll
1186 1.249 skrll xfer->ux_actlen = actlen;
1187 1.249 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1188 1.249 skrll goto end;
1189 1.249 skrll } else if (ex->ex_type == EX_FS_ISOC) {
1190 1.249 skrll /* FS isoc transfer */
1191 1.249 skrll struct ehci_soft_sitd *sitd;
1192 1.249 skrll int nframes, len;
1193 1.249 skrll
1194 1.249 skrll nframes = 0;
1195 1.249 skrll
1196 1.249 skrll for (sitd = ex->ex_sitdstart; sitd != NULL;
1197 1.249 skrll sitd = sitd->xfer_next) {
1198 1.249 skrll usb_syncmem(&sitd->dma,
1199 1.249 skrll sitd->offs + offsetof(ehci_sitd_t, sitd_trans),
1200 1.249 skrll sizeof(sitd->sitd.sitd_trans),
1201 1.249 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1202 1.249 skrll
1203 1.249 skrll /*
1204 1.249 skrll * XXX - driver didn't fill in the frame full
1205 1.249 skrll * of uframes. This leads to scheduling
1206 1.249 skrll * inefficiencies, but working around
1207 1.249 skrll * this doubles complexity of tracking
1208 1.249 skrll * an xfer.
1209 1.249 skrll */
1210 1.249 skrll if (nframes >= xfer->ux_nframes)
1211 1.249 skrll break;
1212 1.249 skrll
1213 1.249 skrll status = le32toh(sitd->sitd.sitd_trans);
1214 1.249 skrll usb_syncmem(&sitd->dma,
1215 1.249 skrll sitd->offs + offsetof(ehci_sitd_t, sitd_trans),
1216 1.249 skrll sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD);
1217 1.249 skrll
1218 1.249 skrll len = EHCI_SITD_GET_LEN(status);
1219 1.249 skrll if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR|
1220 1.249 skrll EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) {
1221 1.249 skrll /* No valid data on error */
1222 1.249 skrll len = xfer->ux_frlengths[nframes];
1223 1.249 skrll }
1224 1.139 jmcneill
1225 1.249 skrll /*
1226 1.249 skrll * frlengths[i]: # of bytes to send
1227 1.249 skrll * len: # of bytes host didn't send
1228 1.249 skrll */
1229 1.249 skrll xfer->ux_frlengths[nframes] -= len;
1230 1.249 skrll /* frlengths[i]: # of bytes host sent */
1231 1.249 skrll actlen += xfer->ux_frlengths[nframes++];
1232 1.249 skrll
1233 1.249 skrll if (nframes >= xfer->ux_nframes)
1234 1.139 jmcneill break;
1235 1.183 jakllsch }
1236 1.139 jmcneill
1237 1.249 skrll xfer->ux_actlen = actlen;
1238 1.249 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1239 1.139 jmcneill goto end;
1240 1.139 jmcneill }
1241 1.249 skrll KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR ||
1242 1.249 skrll ex->ex_type == EX_BULK);
1243 1.139 jmcneill
1244 1.139 jmcneill /* Continue processing xfers using queue heads */
1245 1.249 skrll if (ex->ex_type == EX_CTRL) {
1246 1.249 skrll fsqtd = ex->ex_setup;
1247 1.249 skrll lsqtd = ex->ex_status;
1248 1.249 skrll } else {
1249 1.249 skrll fsqtd = ex->ex_sqtdstart;
1250 1.249 skrll lsqtd = ex->ex_sqtdend;
1251 1.249 skrll }
1252 1.249 skrll #ifdef EHCI_DEBUG
1253 1.249 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
1254 1.249 skrll ehci_dump_sqtds(fsqtd);
1255 1.249 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
1256 1.249 skrll #endif
1257 1.139 jmcneill
1258 1.249 skrll for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) {
1259 1.138 bouyer usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd),
1260 1.138 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1261 1.18 augustss nstatus = le32toh(sqtd->qtd.qtd_status);
1262 1.249 skrll usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd),
1263 1.249 skrll BUS_DMASYNC_PREREAD);
1264 1.18 augustss if (nstatus & EHCI_QTD_ACTIVE)
1265 1.18 augustss break;
1266 1.18 augustss
1267 1.18 augustss status = nstatus;
1268 1.139 jmcneill if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
1269 1.18 augustss actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
1270 1.18 augustss }
1271 1.22 augustss
1272 1.91 perry /*
1273 1.86 augustss * If there are left over TDs we need to update the toggle.
1274 1.86 augustss * The default pipe doesn't need it since control transfers
1275 1.86 augustss * start the toggle at 0 every time.
1276 1.117 drochner * For a short transfer we need to update the toggle for the missing
1277 1.117 drochner * packets within the qTD.
1278 1.86 augustss */
1279 1.117 drochner if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) &&
1280 1.249 skrll xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) {
1281 1.277 christos DPRINTF("toggle update status=0x%08jx nstatus=0x%08jx",
1282 1.229 skrll status, nstatus, 0, 0);
1283 1.58 mycroft #if 0
1284 1.58 mycroft ehci_dump_sqh(epipe->sqh);
1285 1.249 skrll ehci_dump_sqtds(ex->ex_sqtdstart);
1286 1.58 mycroft #endif
1287 1.58 mycroft epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus);
1288 1.22 augustss }
1289 1.18 augustss
1290 1.277 christos DPRINTF("len=%jd actlen=%jd status=0x%08jx", xfer->ux_length, actlen,
1291 1.249 skrll status, 0);
1292 1.249 skrll xfer->ux_actlen = actlen;
1293 1.98 augustss if (status & EHCI_QTD_HALTED) {
1294 1.18 augustss #ifdef EHCI_DEBUG
1295 1.277 christos DPRINTF("halted addr=%jd endpt=0x%02jx",
1296 1.249 skrll xfer->ux_pipe->up_dev->ud_addr,
1297 1.249 skrll xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
1298 1.249 skrll 0, 0);
1299 1.256 pgoyette DPRINTF("cerr=%jd pid=%jd",
1300 1.236 skrll EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status),
1301 1.249 skrll 0, 0);
1302 1.256 pgoyette DPRINTF("active =%jd halted=%jd buferr=%jd babble=%jd",
1303 1.229 skrll status & EHCI_QTD_ACTIVE ? 1 : 0,
1304 1.229 skrll status & EHCI_QTD_HALTED ? 1 : 0,
1305 1.229 skrll status & EHCI_QTD_BUFERR ? 1 : 0,
1306 1.229 skrll status & EHCI_QTD_BABBLE ? 1 : 0);
1307 1.229 skrll
1308 1.256 pgoyette DPRINTF("xacterr=%jd missed=%jd split =%jd ping =%jd",
1309 1.229 skrll status & EHCI_QTD_XACTERR ? 1 : 0,
1310 1.229 skrll status & EHCI_QTD_MISSEDMICRO ? 1 : 0,
1311 1.229 skrll status & EHCI_QTD_SPLITXSTATE ? 1 : 0,
1312 1.229 skrll status & EHCI_QTD_PINGSTATE ? 1 : 0);
1313 1.218 skrll
1314 1.249 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
1315 1.229 skrll ehci_dump_sqh(epipe->sqh);
1316 1.249 skrll ehci_dump_sqtds(ex->ex_sqtdstart);
1317 1.249 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
1318 1.18 augustss #endif
1319 1.98 augustss /* low&full speed has an extra error flag */
1320 1.98 augustss if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) !=
1321 1.98 augustss EHCI_QH_SPEED_HIGH)
1322 1.98 augustss status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE;
1323 1.98 augustss else
1324 1.98 augustss status &= EHCI_QTD_STATERRS;
1325 1.139 jmcneill if (status == 0) /* no other errors means a stall */ {
1326 1.249 skrll xfer->ux_status = USBD_STALLED;
1327 1.139 jmcneill } else {
1328 1.249 skrll xfer->ux_status = USBD_IOERROR; /* more info XXX */
1329 1.139 jmcneill }
1330 1.98 augustss /* XXX need to reset TT on missed microframe */
1331 1.98 augustss if (status & EHCI_QTD_MISSEDMICRO) {
1332 1.98 augustss printf("%s: missed microframe, TT reset not "
1333 1.98 augustss "implemented, hub might be inoperational\n",
1334 1.134 drochner device_xname(sc->sc_dev));
1335 1.98 augustss }
1336 1.18 augustss } else {
1337 1.249 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1338 1.18 augustss }
1339 1.18 augustss
1340 1.139 jmcneill end:
1341 1.249 skrll
1342 1.249 skrll ehci_del_intr_list(sc, ex);
1343 1.249 skrll TAILQ_INSERT_TAIL(cq, ex, ex_next);
1344 1.249 skrll
1345 1.256 pgoyette DPRINTF("ex=%#jx done", (uintptr_t)ex, 0, 0, 0);
1346 1.5 augustss }
1347 1.5 augustss
1348 1.164 uebayasi Static void
1349 1.5 augustss ehci_poll(struct usbd_bus *bus)
1350 1.5 augustss {
1351 1.249 skrll ehci_softc_t *sc = EHCI_BUS2SC(bus);
1352 1.229 skrll
1353 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1354 1.229 skrll
1355 1.5 augustss #ifdef EHCI_DEBUG
1356 1.5 augustss static int last;
1357 1.5 augustss int new;
1358 1.6 augustss new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1359 1.5 augustss if (new != last) {
1360 1.277 christos DPRINTF("intrs=0x%04jx", new, 0, 0, 0);
1361 1.5 augustss last = new;
1362 1.5 augustss }
1363 1.5 augustss #endif
1364 1.5 augustss
1365 1.190 mrg if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) {
1366 1.190 mrg mutex_spin_enter(&sc->sc_intr_lock);
1367 1.5 augustss ehci_intr1(sc);
1368 1.190 mrg mutex_spin_exit(&sc->sc_intr_lock);
1369 1.190 mrg }
1370 1.5 augustss }
1371 1.5 augustss
1372 1.132 dyoung void
1373 1.132 dyoung ehci_childdet(device_t self, device_t child)
1374 1.132 dyoung {
1375 1.132 dyoung struct ehci_softc *sc = device_private(self);
1376 1.132 dyoung
1377 1.132 dyoung KASSERT(sc->sc_child == child);
1378 1.132 dyoung sc->sc_child = NULL;
1379 1.132 dyoung }
1380 1.132 dyoung
1381 1.1 augustss int
1382 1.1 augustss ehci_detach(struct ehci_softc *sc, int flags)
1383 1.1 augustss {
1384 1.1 augustss int rv = 0;
1385 1.1 augustss
1386 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1387 1.229 skrll
1388 1.267 maxv if (sc->sc_child != NULL) {
1389 1.1 augustss rv = config_detach(sc->sc_child, flags);
1390 1.267 maxv if (rv != 0)
1391 1.267 maxv return rv;
1392 1.267 maxv }
1393 1.1 augustss
1394 1.265 mrg if (sc->sc_ncomp > 0) {
1395 1.265 mrg mutex_enter(&sc->sc_complock);
1396 1.265 mrg /* XXX try to halt callout instead of waiting */
1397 1.265 mrg while (sc->sc_comp_state == CO_SCHED)
1398 1.265 mrg cv_wait(&sc->sc_compcv, &sc->sc_complock);
1399 1.265 mrg mutex_exit(&sc->sc_complock);
1400 1.265 mrg
1401 1.265 mrg callout_halt(&sc->sc_compcallout, NULL);
1402 1.265 mrg callout_destroy(&sc->sc_compcallout);
1403 1.265 mrg cv_destroy(&sc->sc_compcv);
1404 1.265 mrg mutex_destroy(&sc->sc_complock);
1405 1.265 mrg }
1406 1.265 mrg
1407 1.190 mrg callout_halt(&sc->sc_tmo_intrlist, NULL);
1408 1.190 mrg callout_destroy(&sc->sc_tmo_intrlist);
1409 1.190 mrg
1410 1.267 maxv /* XXX free other data structures */
1411 1.267 maxv if (sc->sc_softitds) {
1412 1.190 mrg kmem_free(sc->sc_softitds,
1413 1.190 mrg sc->sc_flsize * sizeof(ehci_soft_itd_t *));
1414 1.267 maxv }
1415 1.190 mrg cv_destroy(&sc->sc_doorbell);
1416 1.190 mrg
1417 1.190 mrg #if 0
1418 1.190 mrg /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */
1419 1.190 mrg softint_disestablish(sc->sc_doorbell_si);
1420 1.190 mrg softint_disestablish(sc->sc_pcd_si);
1421 1.309 riastrad mutex_destroy(&sc->sc_rhlock);
1422 1.190 mrg mutex_destroy(&sc->sc_lock);
1423 1.190 mrg mutex_destroy(&sc->sc_intr_lock);
1424 1.190 mrg #endif
1425 1.190 mrg
1426 1.204 christos pool_cache_destroy(sc->sc_xferpool);
1427 1.1 augustss
1428 1.128 jmcneill EOWRITE4(sc, EHCI_CONFIGFLAG, 0);
1429 1.128 jmcneill
1430 1.249 skrll return rv;
1431 1.1 augustss }
1432 1.1 augustss
1433 1.1 augustss int
1434 1.132 dyoung ehci_activate(device_t self, enum devact act)
1435 1.1 augustss {
1436 1.132 dyoung struct ehci_softc *sc = device_private(self);
1437 1.1 augustss
1438 1.1 augustss switch (act) {
1439 1.1 augustss case DVACT_DEACTIVATE:
1440 1.124 kiyohara sc->sc_dying = 1;
1441 1.163 dyoung return 0;
1442 1.163 dyoung default:
1443 1.163 dyoung return EOPNOTSUPP;
1444 1.1 augustss }
1445 1.1 augustss }
1446 1.1 augustss
1447 1.5 augustss /*
1448 1.5 augustss * Handle suspend/resume.
1449 1.5 augustss *
1450 1.127 jmcneill * Note that this power handler isn't to be registered directly; the
1451 1.127 jmcneill * bus glue needs to call out to it.
1452 1.5 augustss */
1453 1.127 jmcneill bool
1454 1.166 dyoung ehci_suspend(device_t dv, const pmf_qual_t *qual)
1455 1.5 augustss {
1456 1.132 dyoung ehci_softc_t *sc = device_private(dv);
1457 1.190 mrg int i;
1458 1.127 jmcneill uint32_t cmd, hcr;
1459 1.127 jmcneill
1460 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1461 1.229 skrll
1462 1.309 riastrad mutex_enter(&sc->sc_rhlock);
1463 1.309 riastrad
1464 1.127 jmcneill for (i = 1; i <= sc->sc_noport; i++) {
1465 1.129 jmcneill cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1466 1.127 jmcneill if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE)
1467 1.127 jmcneill EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP);
1468 1.127 jmcneill }
1469 1.127 jmcneill
1470 1.127 jmcneill sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
1471 1.127 jmcneill
1472 1.127 jmcneill cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
1473 1.127 jmcneill EOWRITE4(sc, EHCI_USBCMD, cmd);
1474 1.127 jmcneill
1475 1.127 jmcneill for (i = 0; i < 100; i++) {
1476 1.127 jmcneill hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS);
1477 1.127 jmcneill if (hcr == 0)
1478 1.127 jmcneill break;
1479 1.5 augustss
1480 1.127 jmcneill usb_delay_ms(&sc->sc_bus, 1);
1481 1.127 jmcneill }
1482 1.127 jmcneill if (hcr != 0)
1483 1.134 drochner printf("%s: reset timeout\n", device_xname(dv));
1484 1.5 augustss
1485 1.127 jmcneill cmd &= ~EHCI_CMD_RS;
1486 1.127 jmcneill EOWRITE4(sc, EHCI_USBCMD, cmd);
1487 1.74 augustss
1488 1.127 jmcneill for (i = 0; i < 100; i++) {
1489 1.127 jmcneill hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1490 1.127 jmcneill if (hcr == EHCI_STS_HCH)
1491 1.127 jmcneill break;
1492 1.74 augustss
1493 1.127 jmcneill usb_delay_ms(&sc->sc_bus, 1);
1494 1.127 jmcneill }
1495 1.127 jmcneill if (hcr != EHCI_STS_HCH)
1496 1.134 drochner printf("%s: config timeout\n", device_xname(dv));
1497 1.74 augustss
1498 1.309 riastrad mutex_exit(&sc->sc_rhlock);
1499 1.309 riastrad
1500 1.127 jmcneill return true;
1501 1.127 jmcneill }
1502 1.74 augustss
1503 1.127 jmcneill bool
1504 1.166 dyoung ehci_resume(device_t dv, const pmf_qual_t *qual)
1505 1.127 jmcneill {
1506 1.132 dyoung ehci_softc_t *sc = device_private(dv);
1507 1.132 dyoung int i;
1508 1.127 jmcneill uint32_t cmd, hcr;
1509 1.74 augustss
1510 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1511 1.229 skrll
1512 1.309 riastrad mutex_enter(&sc->sc_rhlock);
1513 1.309 riastrad
1514 1.127 jmcneill /* restore things in case the bios sucks */
1515 1.127 jmcneill EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
1516 1.127 jmcneill EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
1517 1.127 jmcneill EOWRITE4(sc, EHCI_ASYNCLISTADDR,
1518 1.127 jmcneill sc->sc_async_head->physaddr | EHCI_LINK_QH);
1519 1.130 jmcneill
1520 1.130 jmcneill EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE);
1521 1.74 augustss
1522 1.127 jmcneill EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1523 1.74 augustss
1524 1.127 jmcneill hcr = 0;
1525 1.127 jmcneill for (i = 1; i <= sc->sc_noport; i++) {
1526 1.129 jmcneill cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1527 1.127 jmcneill if ((cmd & EHCI_PS_PO) == 0 &&
1528 1.127 jmcneill (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) {
1529 1.127 jmcneill EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR);
1530 1.127 jmcneill hcr = 1;
1531 1.74 augustss }
1532 1.127 jmcneill }
1533 1.127 jmcneill
1534 1.127 jmcneill if (hcr) {
1535 1.127 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1536 1.127 jmcneill
1537 1.127 jmcneill for (i = 1; i <= sc->sc_noport; i++) {
1538 1.129 jmcneill cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1539 1.127 jmcneill if ((cmd & EHCI_PS_PO) == 0 &&
1540 1.127 jmcneill (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)
1541 1.127 jmcneill EOWRITE4(sc, EHCI_PORTSC(i),
1542 1.127 jmcneill cmd & ~EHCI_PS_FPR);
1543 1.74 augustss }
1544 1.127 jmcneill }
1545 1.127 jmcneill
1546 1.127 jmcneill EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1547 1.130 jmcneill EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1548 1.74 augustss
1549 1.127 jmcneill for (i = 0; i < 100; i++) {
1550 1.127 jmcneill hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1551 1.127 jmcneill if (hcr != EHCI_STS_HCH)
1552 1.127 jmcneill break;
1553 1.74 augustss
1554 1.127 jmcneill usb_delay_ms(&sc->sc_bus, 1);
1555 1.5 augustss }
1556 1.127 jmcneill if (hcr == EHCI_STS_HCH)
1557 1.134 drochner printf("%s: config timeout\n", device_xname(dv));
1558 1.127 jmcneill
1559 1.309 riastrad mutex_exit(&sc->sc_rhlock);
1560 1.309 riastrad
1561 1.127 jmcneill return true;
1562 1.5 augustss }
1563 1.5 augustss
1564 1.5 augustss /*
1565 1.5 augustss * Shut down the controller when the system is going down.
1566 1.5 augustss */
1567 1.133 dyoung bool
1568 1.133 dyoung ehci_shutdown(device_t self, int flags)
1569 1.5 augustss {
1570 1.133 dyoung ehci_softc_t *sc = device_private(self);
1571 1.5 augustss
1572 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1573 1.229 skrll
1574 1.8 augustss EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
1575 1.8 augustss EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
1576 1.133 dyoung return true;
1577 1.5 augustss }
1578 1.5 augustss
1579 1.249 skrll Static struct usbd_xfer *
1580 1.249 skrll ehci_allocx(struct usbd_bus *bus, unsigned int nframes)
1581 1.5 augustss {
1582 1.249 skrll struct ehci_softc *sc = EHCI_BUS2SC(bus);
1583 1.249 skrll struct usbd_xfer *xfer;
1584 1.5 augustss
1585 1.257 skrll xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
1586 1.18 augustss if (xfer != NULL) {
1587 1.177 tsutsui memset(xfer, 0, sizeof(struct ehci_xfer));
1588 1.260 mrg
1589 1.18 augustss #ifdef DIAGNOSTIC
1590 1.249 skrll struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
1591 1.249 skrll ex->ex_isdone = true;
1592 1.249 skrll xfer->ux_state = XFER_BUSY;
1593 1.18 augustss #endif
1594 1.18 augustss }
1595 1.249 skrll return xfer;
1596 1.5 augustss }
1597 1.5 augustss
1598 1.164 uebayasi Static void
1599 1.249 skrll ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
1600 1.5 augustss {
1601 1.249 skrll struct ehci_softc *sc = EHCI_BUS2SC(bus);
1602 1.249 skrll struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer);
1603 1.249 skrll
1604 1.266 rin KASSERTMSG(xfer->ux_state == XFER_BUSY ||
1605 1.266 rin xfer->ux_status == USBD_NOT_STARTED,
1606 1.266 rin "xfer %p state %d\n", xfer, xfer->ux_state);
1607 1.266 rin KASSERT(ex->ex_isdone || xfer->ux_status == USBD_NOT_STARTED);
1608 1.5 augustss
1609 1.18 augustss #ifdef DIAGNOSTIC
1610 1.249 skrll xfer->ux_state = XFER_FREE;
1611 1.18 augustss #endif
1612 1.249 skrll
1613 1.204 christos pool_cache_put(sc->sc_xferpool, xfer);
1614 1.5 augustss }
1615 1.5 augustss
1616 1.271 riastrad Static bool
1617 1.271 riastrad ehci_dying(struct usbd_bus *bus)
1618 1.271 riastrad {
1619 1.271 riastrad struct ehci_softc *sc = EHCI_BUS2SC(bus);
1620 1.271 riastrad
1621 1.271 riastrad return sc->sc_dying;
1622 1.271 riastrad }
1623 1.271 riastrad
1624 1.5 augustss Static void
1625 1.190 mrg ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
1626 1.190 mrg {
1627 1.249 skrll struct ehci_softc *sc = EHCI_BUS2SC(bus);
1628 1.190 mrg
1629 1.190 mrg *lock = &sc->sc_lock;
1630 1.190 mrg }
1631 1.190 mrg
1632 1.190 mrg Static void
1633 1.249 skrll ehci_device_clear_toggle(struct usbd_pipe *pipe)
1634 1.5 augustss {
1635 1.249 skrll struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);
1636 1.15 augustss
1637 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1638 1.229 skrll
1639 1.277 christos DPRINTF("epipe=%#jx status=0x%08jx", (uintptr_t)epipe,
1640 1.249 skrll epipe->sqh->qh.qh_qtd.qtd_status, 0, 0);
1641 1.158 sketch #ifdef EHCI_DEBUG
1642 1.22 augustss if (ehcidebug)
1643 1.22 augustss usbd_dump_pipe(pipe);
1644 1.5 augustss #endif
1645 1.55 mycroft epipe->nexttoggle = 0;
1646 1.5 augustss }
1647 1.5 augustss
1648 1.5 augustss Static void
1649 1.249 skrll ehci_noop(struct usbd_pipe *pipe)
1650 1.5 augustss {
1651 1.5 augustss }
1652 1.5 augustss
1653 1.5 augustss #ifdef EHCI_DEBUG
1654 1.40 martin /*
1655 1.40 martin * Unused function - this is meant to be called from a kernel
1656 1.40 martin * debugger.
1657 1.40 martin */
1658 1.39 martin void
1659 1.157 cegger ehci_dump(void)
1660 1.39 martin {
1661 1.229 skrll ehci_softc_t *sc = theehci;
1662 1.229 skrll int i;
1663 1.277 christos printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n",
1664 1.229 skrll EOREAD4(sc, EHCI_USBCMD),
1665 1.229 skrll EOREAD4(sc, EHCI_USBSTS),
1666 1.229 skrll EOREAD4(sc, EHCI_USBINTR));
1667 1.277 christos printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
1668 1.229 skrll EOREAD4(sc, EHCI_FRINDEX),
1669 1.229 skrll EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1670 1.229 skrll EOREAD4(sc, EHCI_PERIODICLISTBASE),
1671 1.229 skrll EOREAD4(sc, EHCI_ASYNCLISTADDR));
1672 1.229 skrll for (i = 1; i <= sc->sc_noport; i++)
1673 1.277 christos printf("port %d status=0x%08x\n", i,
1674 1.229 skrll EOREAD4(sc, EHCI_PORTSC(i)));
1675 1.6 augustss }
1676 1.6 augustss
1677 1.164 uebayasi Static void
1678 1.229 skrll ehci_dump_regs(ehci_softc_t *sc)
1679 1.9 augustss {
1680 1.229 skrll int i;
1681 1.229 skrll
1682 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1683 1.229 skrll
1684 1.277 christos DPRINTF("cmd = 0x%08jx sts = 0x%08jx ien = 0x%08jx",
1685 1.229 skrll EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS),
1686 1.229 skrll EOREAD4(sc, EHCI_USBINTR), 0);
1687 1.277 christos DPRINTF("frindex = 0x%08jx ctrdsegm = 0x%08jx periodic = 0x%08jx "
1688 1.277 christos "async = 0x%08jx",
1689 1.229 skrll EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1690 1.229 skrll EOREAD4(sc, EHCI_PERIODICLISTBASE),
1691 1.229 skrll EOREAD4(sc, EHCI_ASYNCLISTADDR));
1692 1.229 skrll for (i = 1; i <= sc->sc_noport; i += 2) {
1693 1.229 skrll if (i == sc->sc_noport) {
1694 1.277 christos DPRINTF("port %jd status = 0x%08jx", i,
1695 1.229 skrll EOREAD4(sc, EHCI_PORTSC(i)), 0, 0);
1696 1.229 skrll } else {
1697 1.277 christos DPRINTF("port %jd status = 0x%08jx port %jd "
1698 1.277 christos "status = 0x%08jx",
1699 1.229 skrll i, EOREAD4(sc, EHCI_PORTSC(i)),
1700 1.229 skrll i+1, EOREAD4(sc, EHCI_PORTSC(i+1)));
1701 1.15 augustss }
1702 1.15 augustss }
1703 1.15 augustss }
1704 1.15 augustss
1705 1.229 skrll #define ehci_dump_link(link, type) do { \
1706 1.277 christos DPRINTF(" link 0x%08jx (T = %jd):", \
1707 1.229 skrll link, \
1708 1.229 skrll link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \
1709 1.229 skrll if (type) { \
1710 1.256 pgoyette DPRINTF( \
1711 1.256 pgoyette " ITD = %jd QH = %jd SITD = %jd FSTN = %jd",\
1712 1.229 skrll EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \
1713 1.229 skrll EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \
1714 1.229 skrll EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \
1715 1.229 skrll EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \
1716 1.229 skrll } \
1717 1.229 skrll } while(0)
1718 1.229 skrll
1719 1.164 uebayasi Static void
1720 1.15 augustss ehci_dump_sqtds(ehci_soft_qtd_t *sqtd)
1721 1.15 augustss {
1722 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1723 1.29 augustss int i;
1724 1.229 skrll uint32_t stop = 0;
1725 1.29 augustss
1726 1.29 augustss for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) {
1727 1.15 augustss ehci_dump_sqtd(sqtd);
1728 1.138 bouyer usb_syncmem(&sqtd->dma,
1729 1.195 christos sqtd->offs + offsetof(ehci_qtd_t, qtd_next),
1730 1.138 bouyer sizeof(sqtd->qtd),
1731 1.138 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1732 1.72 augustss stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE);
1733 1.138 bouyer usb_syncmem(&sqtd->dma,
1734 1.195 christos sqtd->offs + offsetof(ehci_qtd_t, qtd_next),
1735 1.138 bouyer sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD);
1736 1.29 augustss }
1737 1.237 skrll if (!stop)
1738 1.249 skrll DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0);
1739 1.9 augustss }
1740 1.9 augustss
1741 1.164 uebayasi Static void
1742 1.9 augustss ehci_dump_sqtd(ehci_soft_qtd_t *sqtd)
1743 1.9 augustss {
1744 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1745 1.229 skrll
1746 1.195 christos usb_syncmem(&sqtd->dma, sqtd->offs,
1747 1.138 bouyer sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1748 1.229 skrll
1749 1.277 christos DPRINTFN(10, "QTD(%#jx) at 0x%08jx:", (uintptr_t)sqtd, sqtd->physaddr,
1750 1.256 pgoyette 0, 0);
1751 1.9 augustss ehci_dump_qtd(&sqtd->qtd);
1752 1.229 skrll
1753 1.195 christos usb_syncmem(&sqtd->dma, sqtd->offs,
1754 1.138 bouyer sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD);
1755 1.9 augustss }
1756 1.9 augustss
1757 1.164 uebayasi Static void
1758 1.9 augustss ehci_dump_qtd(ehci_qtd_t *qtd)
1759 1.9 augustss {
1760 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1761 1.229 skrll uint32_t s = le32toh(qtd->qtd_status);
1762 1.229 skrll
1763 1.249 skrll DPRINTFN(10,
1764 1.277 christos " next = 0x%08jx altnext = 0x%08jx status = 0x%08jx",
1765 1.231 skrll qtd->qtd_next, qtd->qtd_altnext, s, 0);
1766 1.249 skrll DPRINTFN(10,
1767 1.256 pgoyette " toggle = %jd ioc = %jd bytes = %#jx c_page = %#jx",
1768 1.256 pgoyette EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s),
1769 1.229 skrll EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s));
1770 1.249 skrll DPRINTFN(10,
1771 1.256 pgoyette " cerr = %jd pid = %jd stat = %jx",
1772 1.229 skrll EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s),
1773 1.229 skrll 0);
1774 1.249 skrll DPRINTFN(10,
1775 1.256 pgoyette "active =%jd halted=%jd buferr=%jd babble=%jd",
1776 1.229 skrll s & EHCI_QTD_ACTIVE ? 1 : 0,
1777 1.229 skrll s & EHCI_QTD_HALTED ? 1 : 0,
1778 1.229 skrll s & EHCI_QTD_BUFERR ? 1 : 0,
1779 1.229 skrll s & EHCI_QTD_BABBLE ? 1 : 0);
1780 1.249 skrll DPRINTFN(10,
1781 1.256 pgoyette "xacterr=%jd missed=%jd split =%jd ping =%jd",
1782 1.229 skrll s & EHCI_QTD_XACTERR ? 1 : 0,
1783 1.229 skrll s & EHCI_QTD_MISSEDMICRO ? 1 : 0,
1784 1.229 skrll s & EHCI_QTD_SPLITXSTATE ? 1 : 0,
1785 1.229 skrll s & EHCI_QTD_PINGSTATE ? 1 : 0);
1786 1.249 skrll DPRINTFN(10,
1787 1.256 pgoyette "buffer[0] = %#jx buffer[1] = %#jx "
1788 1.256 pgoyette "buffer[2] = %#jx buffer[3] = %#jx",
1789 1.229 skrll le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]),
1790 1.229 skrll le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3]));
1791 1.249 skrll DPRINTFN(10,
1792 1.256 pgoyette "buffer[4] = %#jx", le32toh(qtd->qtd_buffer[4]), 0, 0, 0);
1793 1.9 augustss }
1794 1.9 augustss
1795 1.164 uebayasi Static void
1796 1.9 augustss ehci_dump_sqh(ehci_soft_qh_t *sqh)
1797 1.9 augustss {
1798 1.9 augustss ehci_qh_t *qh = &sqh->qh;
1799 1.229 skrll ehci_link_t link;
1800 1.249 skrll uint32_t endp, endphub;
1801 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1802 1.9 augustss
1803 1.195 christos usb_syncmem(&sqh->dma, sqh->offs,
1804 1.138 bouyer sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1805 1.229 skrll
1806 1.256 pgoyette DPRINTFN(10, "QH(%#jx) at %#jx:", (uintptr_t)sqh, sqh->physaddr, 0, 0);
1807 1.229 skrll link = le32toh(qh->qh_link);
1808 1.229 skrll ehci_dump_link(link, true);
1809 1.229 skrll
1810 1.15 augustss endp = le32toh(qh->qh_endp);
1811 1.256 pgoyette DPRINTFN(10, " endp = %#jx", endp, 0, 0, 0);
1812 1.277 christos DPRINTFN(10, " addr = 0x%02jx inact = %jd endpt = %jd "
1813 1.256 pgoyette "eps = %jd",
1814 1.229 skrll EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
1815 1.236 skrll EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp));
1816 1.256 pgoyette DPRINTFN(10, " dtc = %jd hrecl = %jd",
1817 1.229 skrll EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0);
1818 1.256 pgoyette DPRINTFN(10, " ctl = %jd nrl = %jd mpl = %#jx(%jd)",
1819 1.229 skrll EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp),
1820 1.229 skrll EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp));
1821 1.229 skrll
1822 1.15 augustss endphub = le32toh(qh->qh_endphub);
1823 1.256 pgoyette DPRINTFN(10, " endphub = %#jx", endphub, 0, 0, 0);
1824 1.277 christos DPRINTFN(10, " smask = 0x%02jx cmask = 0x%02jx one %jx",
1825 1.229 skrll EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0);
1826 1.277 christos DPRINTFN(10, " huba = 0x%02jx port = %jd mult = %jd",
1827 1.229 skrll EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
1828 1.229 skrll EHCI_QH_GET_MULT(endphub), 0);
1829 1.229 skrll
1830 1.229 skrll link = le32toh(qh->qh_curqtd);
1831 1.229 skrll ehci_dump_link(link, false);
1832 1.249 skrll DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0);
1833 1.9 augustss ehci_dump_qtd(&qh->qh_qtd);
1834 1.229 skrll
1835 1.249 skrll usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1836 1.249 skrll BUS_DMASYNC_PREREAD);
1837 1.249 skrll }
1838 1.249 skrll
1839 1.249 skrll Static void
1840 1.249 skrll ehci_dump_itds(ehci_soft_itd_t *itd)
1841 1.249 skrll {
1842 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1843 1.249 skrll int i;
1844 1.249 skrll uint32_t stop = 0;
1845 1.249 skrll
1846 1.249 skrll for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) {
1847 1.249 skrll ehci_dump_itd(itd);
1848 1.249 skrll usb_syncmem(&itd->dma,
1849 1.249 skrll itd->offs + offsetof(ehci_itd_t, itd_next),
1850 1.249 skrll sizeof(itd->itd),
1851 1.249 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1852 1.249 skrll stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE);
1853 1.249 skrll usb_syncmem(&itd->dma,
1854 1.249 skrll itd->offs + offsetof(ehci_itd_t, itd_next),
1855 1.249 skrll sizeof(itd->itd), BUS_DMASYNC_PREREAD);
1856 1.249 skrll }
1857 1.249 skrll if (!stop)
1858 1.249 skrll DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0);
1859 1.9 augustss }
1860 1.9 augustss
1861 1.164 uebayasi Static void
1862 1.139 jmcneill ehci_dump_itd(struct ehci_soft_itd *itd)
1863 1.139 jmcneill {
1864 1.139 jmcneill ehci_isoc_trans_t t;
1865 1.139 jmcneill ehci_isoc_bufr_ptr_t b, b2, b3;
1866 1.139 jmcneill int i;
1867 1.139 jmcneill
1868 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1869 1.229 skrll
1870 1.256 pgoyette DPRINTF("ITD: next phys = %#jx", itd->itd.itd_next, 0, 0, 0);
1871 1.139 jmcneill
1872 1.168 jakllsch for (i = 0; i < EHCI_ITD_NUFRAMES; i++) {
1873 1.139 jmcneill t = le32toh(itd->itd.itd_ctl[i]);
1874 1.256 pgoyette DPRINTF("ITDctl %jd: stat = %jx len = %jx",
1875 1.229 skrll i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0);
1876 1.256 pgoyette DPRINTF(" ioc = %jx pg = %jx offs = %jx",
1877 1.139 jmcneill EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t),
1878 1.229 skrll EHCI_ITD_GET_OFFS(t), 0);
1879 1.139 jmcneill }
1880 1.249 skrll DPRINTF("ITDbufr: ", 0, 0, 0, 0);
1881 1.168 jakllsch for (i = 0; i < EHCI_ITD_NBUFFERS; i++)
1882 1.256 pgoyette DPRINTF(" %jx",
1883 1.229 skrll EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0);
1884 1.139 jmcneill
1885 1.139 jmcneill b = le32toh(itd->itd.itd_bufr[0]);
1886 1.139 jmcneill b2 = le32toh(itd->itd.itd_bufr[1]);
1887 1.139 jmcneill b3 = le32toh(itd->itd.itd_bufr[2]);
1888 1.256 pgoyette DPRINTF(" ep = %jx daddr = %jx dir = %jd",
1889 1.229 skrll EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0);
1890 1.256 pgoyette DPRINTF(" maxpkt = %jx multi = %jx",
1891 1.229 skrll EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0);
1892 1.139 jmcneill }
1893 1.139 jmcneill
1894 1.164 uebayasi Static void
1895 1.139 jmcneill ehci_dump_sitd(struct ehci_soft_itd *itd)
1896 1.139 jmcneill {
1897 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1898 1.229 skrll
1899 1.256 pgoyette DPRINTF("SITD %#jx next = %p prev = %#jx",
1900 1.256 pgoyette (uintptr_t)itd, (uintptr_t)itd->frame_list.next,
1901 1.256 pgoyette (uintptr_t)itd->frame_list.prev, 0);
1902 1.256 pgoyette DPRINTF(" xfernext=%#jx physaddr=%jX slot=%jd",
1903 1.256 pgoyette (uintptr_t)itd->xfer_next, itd->physaddr, itd->slot, 0);
1904 1.139 jmcneill }
1905 1.139 jmcneill
1906 1.164 uebayasi Static void
1907 1.18 augustss ehci_dump_exfer(struct ehci_xfer *ex)
1908 1.18 augustss {
1909 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1910 1.249 skrll
1911 1.256 pgoyette DPRINTF("ex = %#jx type %jd isdone %jd", (uintptr_t)ex, ex->ex_type,
1912 1.249 skrll ex->ex_isdone, 0);
1913 1.229 skrll
1914 1.249 skrll switch (ex->ex_type) {
1915 1.249 skrll case EX_CTRL:
1916 1.256 pgoyette DPRINTF(" setup = %#jx data = %#jx status = %#jx",
1917 1.256 pgoyette (uintptr_t)ex->ex_setup, (uintptr_t)ex->ex_data,
1918 1.256 pgoyette (uintptr_t)ex->ex_status, 0);
1919 1.249 skrll break;
1920 1.249 skrll case EX_BULK:
1921 1.249 skrll case EX_INTR:
1922 1.256 pgoyette DPRINTF(" qtdstart = %#jx qtdend = %#jx",
1923 1.256 pgoyette (uintptr_t)ex->ex_sqtdstart, (uintptr_t)ex->ex_sqtdend,
1924 1.256 pgoyette 0, 0);
1925 1.249 skrll break;
1926 1.249 skrll case EX_ISOC:
1927 1.256 pgoyette DPRINTF(" itdstart = %#jx itdend = %#jx",
1928 1.256 pgoyette (uintptr_t)ex->ex_itdstart, (uintptr_t)ex->ex_itdend, 0, 0);
1929 1.249 skrll break;
1930 1.249 skrll case EX_FS_ISOC:
1931 1.256 pgoyette DPRINTF(" sitdstart = %#jx sitdend = %#jx",
1932 1.256 pgoyette (uintptr_t)ex->ex_sitdstart, (uintptr_t)ex->ex_sitdend,
1933 1.256 pgoyette 0, 0);
1934 1.249 skrll break;
1935 1.249 skrll default:
1936 1.249 skrll DPRINTF(" unknown type", 0, 0, 0, 0);
1937 1.249 skrll }
1938 1.18 augustss }
1939 1.38 martin #endif
1940 1.5 augustss
1941 1.164 uebayasi Static usbd_status
1942 1.249 skrll ehci_open(struct usbd_pipe *pipe)
1943 1.5 augustss {
1944 1.249 skrll struct usbd_device *dev = pipe->up_dev;
1945 1.249 skrll ehci_softc_t *sc = EHCI_PIPE2SC(pipe);
1946 1.249 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
1947 1.249 skrll uint8_t rhaddr = dev->ud_bus->ub_rhaddr;
1948 1.249 skrll uint8_t addr = dev->ud_addr;
1949 1.249 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1950 1.249 skrll struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);
1951 1.10 augustss ehci_soft_qh_t *sqh;
1952 1.10 augustss usbd_status err;
1953 1.78 augustss int ival, speed, naks;
1954 1.80 augustss int hshubaddr, hshubport;
1955 1.5 augustss
1956 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
1957 1.229 skrll
1958 1.256 pgoyette DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, addr,
1959 1.249 skrll ed->bEndpointAddress, rhaddr);
1960 1.5 augustss
1961 1.249 skrll if (dev->ud_myhsport) {
1962 1.172 matt /*
1963 1.172 matt * When directly attached FS/LS device while doing embedded
1964 1.172 matt * transaction translations and we are the hub, set the hub
1965 1.191 skrll * address to 0 (us).
1966 1.172 matt */
1967 1.172 matt if (!(sc->sc_flags & EHCIF_ETTF)
1968 1.249 skrll || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) {
1969 1.249 skrll hshubaddr = dev->ud_myhsport->up_parent->ud_addr;
1970 1.172 matt } else {
1971 1.172 matt hshubaddr = 0;
1972 1.172 matt }
1973 1.249 skrll hshubport = dev->ud_myhsport->up_portno;
1974 1.80 augustss } else {
1975 1.80 augustss hshubaddr = 0;
1976 1.80 augustss hshubport = 0;
1977 1.80 augustss }
1978 1.80 augustss
1979 1.17 augustss if (sc->sc_dying)
1980 1.249 skrll return USBD_IOERROR;
1981 1.17 augustss
1982 1.175 drochner /* toggle state needed for bulk endpoints */
1983 1.249 skrll epipe->nexttoggle = pipe->up_endpoint->ue_toggle;
1984 1.55 mycroft
1985 1.249 skrll if (addr == rhaddr) {
1986 1.5 augustss switch (ed->bEndpointAddress) {
1987 1.5 augustss case USB_CONTROL_ENDPOINT:
1988 1.249 skrll pipe->up_methods = &roothub_ctrl_methods;
1989 1.5 augustss break;
1990 1.249 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
1991 1.249 skrll pipe->up_methods = &ehci_root_intr_methods;
1992 1.5 augustss break;
1993 1.5 augustss default:
1994 1.277 christos DPRINTF("bad bEndpointAddress 0x%02jx",
1995 1.229 skrll ed->bEndpointAddress, 0, 0, 0);
1996 1.249 skrll return USBD_INVAL;
1997 1.5 augustss }
1998 1.249 skrll return USBD_NORMAL_COMPLETION;
1999 1.10 augustss }
2000 1.10 augustss
2001 1.24 augustss /* XXX All this stuff is only valid for async. */
2002 1.249 skrll switch (dev->ud_speed) {
2003 1.11 augustss case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break;
2004 1.11 augustss case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break;
2005 1.11 augustss case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break;
2006 1.249 skrll default: panic("ehci_open: bad device speed %d", dev->ud_speed);
2007 1.11 augustss }
2008 1.249 skrll if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) {
2009 1.256 pgoyette DPRINTF("hshubaddr=%jd hshubport=%jd", hshubaddr, hshubport, 0,
2010 1.249 skrll 0);
2011 1.99 augustss return USBD_INVAL;
2012 1.80 augustss }
2013 1.80 augustss
2014 1.169 msaitoh /*
2015 1.169 msaitoh * For interrupt transfer, nak throttling must be disabled, but for
2016 1.169 msaitoh * the other transfer type, nak throttling should be enabled from the
2017 1.191 skrll * viewpoint that avoids the memory thrashing.
2018 1.169 msaitoh */
2019 1.169 msaitoh naks = (xfertype == UE_INTERRUPT) ? 0
2020 1.169 msaitoh : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0);
2021 1.10 augustss
2022 1.139 jmcneill /* Allocate sqh for everything, save isoc xfers */
2023 1.139 jmcneill if (xfertype != UE_ISOCHRONOUS) {
2024 1.139 jmcneill sqh = ehci_alloc_sqh(sc);
2025 1.139 jmcneill if (sqh == NULL)
2026 1.249 skrll return USBD_NOMEM;
2027 1.139 jmcneill /* qh_link filled when the QH is added */
2028 1.139 jmcneill sqh->qh.qh_endp = htole32(
2029 1.139 jmcneill EHCI_QH_SET_ADDR(addr) |
2030 1.139 jmcneill EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) |
2031 1.139 jmcneill EHCI_QH_SET_EPS(speed) |
2032 1.139 jmcneill EHCI_QH_DTC |
2033 1.139 jmcneill EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) |
2034 1.139 jmcneill (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ?
2035 1.139 jmcneill EHCI_QH_CTL : 0) |
2036 1.139 jmcneill EHCI_QH_SET_NRL(naks)
2037 1.139 jmcneill );
2038 1.139 jmcneill sqh->qh.qh_endphub = htole32(
2039 1.139 jmcneill EHCI_QH_SET_MULT(1) |
2040 1.317 skrll (xfertype == UE_INTERRUPT ?
2041 1.317 skrll EHCI_QH_SET_SMASK(__BIT(1)) /* Start Split Y1 */
2042 1.317 skrll : 0)
2043 1.139 jmcneill );
2044 1.167 jakllsch if (speed != EHCI_QH_SPEED_HIGH)
2045 1.167 jakllsch sqh->qh.qh_endphub |= htole32(
2046 1.167 jakllsch EHCI_QH_SET_PORT(hshubport) |
2047 1.167 jakllsch EHCI_QH_SET_HUBA(hshubaddr) |
2048 1.252 skrll (xfertype == UE_INTERRUPT ?
2049 1.317 skrll EHCI_QH_SET_CMASK(__BITS(3,5)) /* CS Y[345] */
2050 1.317 skrll : 0)
2051 1.167 jakllsch );
2052 1.139 jmcneill sqh->qh.qh_curqtd = EHCI_NULL;
2053 1.139 jmcneill /* Fill the overlay qTD */
2054 1.139 jmcneill sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
2055 1.139 jmcneill sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
2056 1.139 jmcneill sqh->qh.qh_qtd.qtd_status = htole32(0);
2057 1.139 jmcneill
2058 1.139 jmcneill usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
2059 1.139 jmcneill BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2060 1.139 jmcneill epipe->sqh = sqh;
2061 1.139 jmcneill } else {
2062 1.139 jmcneill sqh = NULL;
2063 1.139 jmcneill } /*xfertype == UE_ISOC*/
2064 1.5 augustss
2065 1.10 augustss switch (xfertype) {
2066 1.10 augustss case UE_CONTROL:
2067 1.297 skrll /* we can use 64bit DMA for the reqdma buffer */
2068 1.294 skrll err = usb_allocmem(sc->sc_bus.ub_dmatag,
2069 1.296 skrll sizeof(usb_device_request_t), 0, USBMALLOC_COHERENT,
2070 1.296 skrll &epipe->ctrl.reqdma);
2071 1.25 augustss #ifdef EHCI_DEBUG
2072 1.25 augustss if (err)
2073 1.25 augustss printf("ehci_open: usb_allocmem()=%d\n", err);
2074 1.25 augustss #endif
2075 1.10 augustss if (err)
2076 1.116 drochner goto bad;
2077 1.249 skrll pipe->up_methods = &ehci_device_ctrl_methods;
2078 1.190 mrg mutex_enter(&sc->sc_lock);
2079 1.190 mrg ehci_add_qh(sc, sqh, sc->sc_async_head);
2080 1.190 mrg mutex_exit(&sc->sc_lock);
2081 1.10 augustss break;
2082 1.10 augustss case UE_BULK:
2083 1.249 skrll pipe->up_methods = &ehci_device_bulk_methods;
2084 1.190 mrg mutex_enter(&sc->sc_lock);
2085 1.190 mrg ehci_add_qh(sc, sqh, sc->sc_async_head);
2086 1.190 mrg mutex_exit(&sc->sc_lock);
2087 1.10 augustss break;
2088 1.24 augustss case UE_INTERRUPT:
2089 1.249 skrll pipe->up_methods = &ehci_device_intr_methods;
2090 1.249 skrll ival = pipe->up_interval;
2091 1.116 drochner if (ival == USBD_DEFAULT_INTERVAL) {
2092 1.116 drochner if (speed == EHCI_QH_SPEED_HIGH) {
2093 1.116 drochner if (ed->bInterval > 16) {
2094 1.116 drochner /*
2095 1.116 drochner * illegal with high-speed, but there
2096 1.116 drochner * were documentation bugs in the spec,
2097 1.116 drochner * so be generous
2098 1.116 drochner */
2099 1.116 drochner ival = 256;
2100 1.116 drochner } else
2101 1.116 drochner ival = (1 << (ed->bInterval - 1)) / 8;
2102 1.116 drochner } else
2103 1.116 drochner ival = ed->bInterval;
2104 1.116 drochner }
2105 1.116 drochner err = ehci_device_setintr(sc, sqh, ival);
2106 1.116 drochner if (err)
2107 1.116 drochner goto bad;
2108 1.116 drochner break;
2109 1.24 augustss case UE_ISOCHRONOUS:
2110 1.249 skrll pipe->up_serialise = false;
2111 1.249 skrll if (speed == EHCI_QH_SPEED_HIGH)
2112 1.249 skrll pipe->up_methods = &ehci_device_isoc_methods;
2113 1.249 skrll else
2114 1.249 skrll pipe->up_methods = &ehci_device_fs_isoc_methods;
2115 1.142 drochner if (ed->bInterval == 0 || ed->bInterval > 16) {
2116 1.139 jmcneill printf("ehci: opening pipe with invalid bInterval\n");
2117 1.139 jmcneill err = USBD_INVAL;
2118 1.139 jmcneill goto bad;
2119 1.139 jmcneill }
2120 1.139 jmcneill if (UGETW(ed->wMaxPacketSize) == 0) {
2121 1.139 jmcneill printf("ehci: zero length endpoint open request\n");
2122 1.139 jmcneill err = USBD_INVAL;
2123 1.139 jmcneill goto bad;
2124 1.139 jmcneill }
2125 1.249 skrll epipe->isoc.next_frame = 0;
2126 1.249 skrll epipe->isoc.cur_xfers = 0;
2127 1.139 jmcneill break;
2128 1.10 augustss default:
2129 1.256 pgoyette DPRINTF("bad xfer type %jd", xfertype, 0, 0, 0);
2130 1.116 drochner err = USBD_INVAL;
2131 1.116 drochner goto bad;
2132 1.5 augustss }
2133 1.249 skrll return USBD_NORMAL_COMPLETION;
2134 1.5 augustss
2135 1.116 drochner bad:
2136 1.249 skrll if (sqh != NULL) {
2137 1.249 skrll mutex_enter(&sc->sc_lock);
2138 1.139 jmcneill ehci_free_sqh(sc, sqh);
2139 1.249 skrll mutex_exit(&sc->sc_lock);
2140 1.249 skrll }
2141 1.249 skrll return err;
2142 1.10 augustss }
2143 1.10 augustss
2144 1.10 augustss /*
2145 1.190 mrg * Add an ED to the schedule. Called with USB lock held.
2146 1.10 augustss */
2147 1.164 uebayasi Static void
2148 1.190 mrg ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
2149 1.10 augustss {
2150 1.10 augustss
2151 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
2152 1.190 mrg
2153 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
2154 1.229 skrll
2155 1.138 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link),
2156 1.138 bouyer sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE);
2157 1.229 skrll
2158 1.10 augustss sqh->next = head->next;
2159 1.10 augustss sqh->qh.qh_link = head->qh.qh_link;
2160 1.229 skrll
2161 1.138 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link),
2162 1.138 bouyer sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE);
2163 1.229 skrll
2164 1.10 augustss head->next = sqh;
2165 1.15 augustss head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH);
2166 1.229 skrll
2167 1.138 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link),
2168 1.138 bouyer sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE);
2169 1.10 augustss
2170 1.10 augustss #ifdef EHCI_DEBUG
2171 1.249 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
2172 1.229 skrll ehci_dump_sqh(sqh);
2173 1.249 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
2174 1.5 augustss #endif
2175 1.5 augustss }
2176 1.5 augustss
2177 1.10 augustss /*
2178 1.190 mrg * Remove an ED from the schedule. Called with USB lock held.
2179 1.10 augustss */
2180 1.164 uebayasi Static void
2181 1.10 augustss ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
2182 1.10 augustss {
2183 1.33 augustss ehci_soft_qh_t *p;
2184 1.10 augustss
2185 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
2186 1.190 mrg
2187 1.10 augustss /* XXX */
2188 1.42 augustss for (p = head; p != NULL && p->next != sqh; p = p->next)
2189 1.10 augustss ;
2190 1.10 augustss if (p == NULL)
2191 1.37 provos panic("ehci_rem_qh: ED not found");
2192 1.138 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link),
2193 1.138 bouyer sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE);
2194 1.10 augustss p->next = sqh->next;
2195 1.10 augustss p->qh.qh_link = sqh->qh.qh_link;
2196 1.138 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link),
2197 1.138 bouyer sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE);
2198 1.10 augustss
2199 1.11 augustss ehci_sync_hc(sc);
2200 1.11 augustss }
2201 1.11 augustss
2202 1.164 uebayasi Static void
2203 1.23 augustss ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd)
2204 1.23 augustss {
2205 1.85 augustss int i;
2206 1.249 skrll uint32_t status;
2207 1.85 augustss
2208 1.87 augustss /* Save toggle bit and ping status. */
2209 1.138 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
2210 1.138 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2211 1.87 augustss status = sqh->qh.qh_qtd.qtd_status &
2212 1.87 augustss htole32(EHCI_QTD_TOGGLE_MASK |
2213 1.87 augustss EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE));
2214 1.85 augustss /* Set HALTED to make hw leave it alone. */
2215 1.85 augustss sqh->qh.qh_qtd.qtd_status =
2216 1.85 augustss htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED));
2217 1.138 bouyer usb_syncmem(&sqh->dma,
2218 1.138 bouyer sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
2219 1.138 bouyer sizeof(sqh->qh.qh_qtd.qtd_status),
2220 1.138 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2221 1.23 augustss sqh->qh.qh_curqtd = 0;
2222 1.23 augustss sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr);
2223 1.179 jmcneill sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
2224 1.85 augustss for (i = 0; i < EHCI_QTD_NBUFFERS; i++)
2225 1.85 augustss sqh->qh.qh_qtd.qtd_buffer[i] = 0;
2226 1.23 augustss sqh->sqtd = sqtd;
2227 1.138 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
2228 1.138 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2229 1.87 augustss /* Set !HALTED && !ACTIVE to start execution, preserve some fields */
2230 1.87 augustss sqh->qh.qh_qtd.qtd_status = status;
2231 1.138 bouyer usb_syncmem(&sqh->dma,
2232 1.138 bouyer sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
2233 1.138 bouyer sizeof(sqh->qh.qh_qtd.qtd_status),
2234 1.138 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2235 1.23 augustss }
2236 1.23 augustss
2237 1.11 augustss /*
2238 1.11 augustss * Ensure that the HC has released all references to the QH. We do this
2239 1.11 augustss * by asking for a Async Advance Doorbell interrupt and then we wait for
2240 1.11 augustss * the interrupt.
2241 1.11 augustss * To make this easier we first obtain exclusive use of the doorbell.
2242 1.308 riastrad *
2243 1.308 riastrad * Releases the bus lock to sleep while waiting for interrupt.
2244 1.11 augustss */
2245 1.164 uebayasi Static void
2246 1.11 augustss ehci_sync_hc(ehci_softc_t *sc)
2247 1.11 augustss {
2248 1.308 riastrad unsigned delta = hz;
2249 1.308 riastrad unsigned starttime = getticks();
2250 1.308 riastrad unsigned endtime = starttime + delta;
2251 1.308 riastrad unsigned now;
2252 1.190 mrg
2253 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
2254 1.11 augustss
2255 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
2256 1.229 skrll
2257 1.12 augustss if (sc->sc_dying) {
2258 1.249 skrll DPRINTF("dying", 0, 0, 0, 0);
2259 1.12 augustss return;
2260 1.12 augustss }
2261 1.260 mrg
2262 1.308 riastrad /*
2263 1.308 riastrad * Wait until any concurrent ehci_sync_hc has completed so we
2264 1.308 riastrad * have exclusive access to the doorbell.
2265 1.308 riastrad */
2266 1.308 riastrad while (sc->sc_doorbelllwp)
2267 1.308 riastrad cv_wait(&sc->sc_doorbell, &sc->sc_lock);
2268 1.308 riastrad sc->sc_doorbelllwp = curlwp;
2269 1.308 riastrad
2270 1.10 augustss /* ask for doorbell */
2271 1.311 mlelstv EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD);
2272 1.277 christos DPRINTF("cmd = 0x%08jx sts = 0x%08jx",
2273 1.249 skrll EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0);
2274 1.229 skrll
2275 1.308 riastrad /*
2276 1.308 riastrad * Wait for the ehci to ring our doorbell.
2277 1.308 riastrad */
2278 1.308 riastrad while (sc->sc_doorbelllwp == curlwp) {
2279 1.308 riastrad now = getticks();
2280 1.318 riastrad if (now - starttime >= delta) {
2281 1.308 riastrad sc->sc_doorbelllwp = NULL;
2282 1.308 riastrad cv_signal(&sc->sc_doorbell);
2283 1.308 riastrad DPRINTF("doorbell timeout", 0, 0, 0, 0);
2284 1.308 riastrad #ifdef DIAGNOSTIC /* XXX DIAGNOSTIC abuse, do this differently */
2285 1.308 riastrad printf("ehci_sync_hc: timed out\n");
2286 1.308 riastrad #endif
2287 1.308 riastrad break;
2288 1.308 riastrad }
2289 1.308 riastrad (void)cv_timedwait(&sc->sc_doorbell, &sc->sc_lock,
2290 1.308 riastrad endtime - now);
2291 1.308 riastrad }
2292 1.229 skrll
2293 1.277 christos DPRINTF("cmd = 0x%08jx sts = 0x%08jx ... done",
2294 1.249 skrll EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0);
2295 1.10 augustss }
2296 1.10 augustss
2297 1.164 uebayasi Static void
2298 1.249 skrll ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd)
2299 1.139 jmcneill {
2300 1.139 jmcneill
2301 1.249 skrll KASSERT(mutex_owned(&sc->sc_lock));
2302 1.139 jmcneill
2303 1.249 skrll for (; itd != NULL; itd = itd->xfer_next) {
2304 1.249 skrll struct ehci_soft_itd *prev = itd->frame_list.prev;
2305 1.139 jmcneill
2306 1.139 jmcneill /* Unlink itd from hardware chain, or frame array */
2307 1.139 jmcneill if (prev == NULL) { /* We're at the table head */
2308 1.249 skrll sc->sc_softitds[itd->slot] = itd->frame_list.next;
2309 1.139 jmcneill sc->sc_flist[itd->slot] = itd->itd.itd_next;
2310 1.139 jmcneill usb_syncmem(&sc->sc_fldma,
2311 1.139 jmcneill sizeof(ehci_link_t) * itd->slot,
2312 1.249 skrll sizeof(ehci_link_t),
2313 1.139 jmcneill BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2314 1.139 jmcneill
2315 1.249 skrll if (itd->frame_list.next != NULL)
2316 1.249 skrll itd->frame_list.next->frame_list.prev = NULL;
2317 1.139 jmcneill } else {
2318 1.139 jmcneill /* XXX this part is untested... */
2319 1.139 jmcneill prev->itd.itd_next = itd->itd.itd_next;
2320 1.139 jmcneill usb_syncmem(&itd->dma,
2321 1.139 jmcneill itd->offs + offsetof(ehci_itd_t, itd_next),
2322 1.249 skrll sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE);
2323 1.139 jmcneill
2324 1.249 skrll prev->frame_list.next = itd->frame_list.next;
2325 1.249 skrll if (itd->frame_list.next != NULL)
2326 1.249 skrll itd->frame_list.next->frame_list.prev = prev;
2327 1.139 jmcneill }
2328 1.139 jmcneill }
2329 1.249 skrll }
2330 1.139 jmcneill
2331 1.249 skrll Static void
2332 1.249 skrll ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd)
2333 1.249 skrll {
2334 1.249 skrll struct ehci_soft_itd *next;
2335 1.249 skrll
2336 1.249 skrll mutex_enter(&sc->sc_lock);
2337 1.249 skrll next = NULL;
2338 1.249 skrll for (; itd != NULL; itd = next) {
2339 1.249 skrll next = itd->xfer_next;
2340 1.249 skrll ehci_free_itd_locked(sc, itd);
2341 1.139 jmcneill }
2342 1.249 skrll mutex_exit(&sc->sc_lock);
2343 1.139 jmcneill }
2344 1.139 jmcneill
2345 1.249 skrll Static void
2346 1.249 skrll ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd)
2347 1.249 skrll {
2348 1.5 augustss
2349 1.249 skrll KASSERT(mutex_owned(&sc->sc_lock));
2350 1.5 augustss
2351 1.249 skrll for (; sitd != NULL; sitd = sitd->xfer_next) {
2352 1.249 skrll struct ehci_soft_sitd *prev = sitd->frame_list.prev;
2353 1.11 augustss
2354 1.249 skrll /* Unlink sitd from hardware chain, or frame array */
2355 1.249 skrll if (prev == NULL) { /* We're at the table head */
2356 1.249 skrll sc->sc_softsitds[sitd->slot] = sitd->frame_list.next;
2357 1.249 skrll sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next;
2358 1.249 skrll usb_syncmem(&sc->sc_fldma,
2359 1.249 skrll sizeof(ehci_link_t) * sitd->slot,
2360 1.249 skrll sizeof(ehci_link_t),
2361 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2362 1.5 augustss
2363 1.249 skrll if (sitd->frame_list.next != NULL)
2364 1.249 skrll sitd->frame_list.next->frame_list.prev = NULL;
2365 1.249 skrll } else {
2366 1.249 skrll /* XXX this part is untested... */
2367 1.249 skrll prev->sitd.sitd_next = sitd->sitd.sitd_next;
2368 1.249 skrll usb_syncmem(&sitd->dma,
2369 1.249 skrll sitd->offs + offsetof(ehci_sitd_t, sitd_next),
2370 1.249 skrll sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE);
2371 1.5 augustss
2372 1.249 skrll prev->frame_list.next = sitd->frame_list.next;
2373 1.249 skrll if (sitd->frame_list.next != NULL)
2374 1.249 skrll sitd->frame_list.next->frame_list.prev = prev;
2375 1.249 skrll }
2376 1.249 skrll }
2377 1.249 skrll }
2378 1.5 augustss
2379 1.249 skrll Static void
2380 1.249 skrll ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd)
2381 1.5 augustss {
2382 1.5 augustss
2383 1.190 mrg mutex_enter(&sc->sc_lock);
2384 1.249 skrll struct ehci_soft_sitd *next = NULL;
2385 1.249 skrll for (; sitd != NULL; sitd = next) {
2386 1.249 skrll next = sitd->xfer_next;
2387 1.249 skrll ehci_free_sitd_locked(sc, sitd);
2388 1.249 skrll }
2389 1.190 mrg mutex_exit(&sc->sc_lock);
2390 1.249 skrll }
2391 1.5 augustss
2392 1.249 skrll /***********/
2393 1.5 augustss
2394 1.309 riastrad static int
2395 1.309 riastrad ehci_roothub_ctrl_locked(struct usbd_bus *bus, usb_device_request_t *req,
2396 1.249 skrll void *buf, int buflen)
2397 1.5 augustss {
2398 1.249 skrll ehci_softc_t *sc = EHCI_BUS2SC(bus);
2399 1.249 skrll usb_hub_descriptor_t hubd;
2400 1.249 skrll usb_port_status_t ps;
2401 1.249 skrll uint16_t len, value, index;
2402 1.249 skrll int l, totlen = 0;
2403 1.5 augustss int port, i;
2404 1.249 skrll uint32_t v;
2405 1.5 augustss
2406 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
2407 1.229 skrll
2408 1.309 riastrad KASSERT(mutex_owned(&sc->sc_rhlock));
2409 1.305 riastrad
2410 1.5 augustss if (sc->sc_dying)
2411 1.249 skrll return -1;
2412 1.5 augustss
2413 1.277 christos DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, req->bRequest,
2414 1.249 skrll 0, 0);
2415 1.5 augustss
2416 1.5 augustss len = UGETW(req->wLength);
2417 1.5 augustss value = UGETW(req->wValue);
2418 1.5 augustss index = UGETW(req->wIndex);
2419 1.5 augustss
2420 1.5 augustss #define C(x,y) ((x) | ((y) << 8))
2421 1.249 skrll switch (C(req->bRequest, req->bmRequestType)) {
2422 1.5 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2423 1.109 christos if (len == 0)
2424 1.109 christos break;
2425 1.249 skrll switch (value) {
2426 1.249 skrll #define sd ((usb_string_descriptor_t *)buf)
2427 1.249 skrll case C(2, UDESC_STRING):
2428 1.249 skrll /* Product */
2429 1.249 skrll totlen = usb_makestrdesc(sd, len, "EHCI root hub");
2430 1.5 augustss break;
2431 1.131 drochner #undef sd
2432 1.5 augustss default:
2433 1.249 skrll /* default from usbroothub */
2434 1.249 skrll return buflen;
2435 1.5 augustss }
2436 1.5 augustss break;
2437 1.249 skrll
2438 1.5 augustss /* Hub requests */
2439 1.5 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2440 1.5 augustss break;
2441 1.5 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2442 1.256 pgoyette DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index,
2443 1.249 skrll value, 0, 0);
2444 1.5 augustss if (index < 1 || index > sc->sc_noport) {
2445 1.249 skrll return -1;
2446 1.5 augustss }
2447 1.5 augustss port = EHCI_PORTSC(index);
2448 1.106 augustss v = EOREAD4(sc, port);
2449 1.277 christos DPRINTF("portsc=0x%08jx", v, 0, 0, 0);
2450 1.106 augustss v &= ~EHCI_PS_CLEAR;
2451 1.249 skrll switch (value) {
2452 1.5 augustss case UHF_PORT_ENABLE:
2453 1.5 augustss EOWRITE4(sc, port, v &~ EHCI_PS_PE);
2454 1.5 augustss break;
2455 1.5 augustss case UHF_PORT_SUSPEND:
2456 1.137 drochner if (!(v & EHCI_PS_SUSP)) /* not suspended */
2457 1.137 drochner break;
2458 1.137 drochner v &= ~EHCI_PS_SUSP;
2459 1.137 drochner EOWRITE4(sc, port, v | EHCI_PS_FPR);
2460 1.137 drochner /* see USB2 spec ch. 7.1.7.7 */
2461 1.137 drochner usb_delay_ms(&sc->sc_bus, 20);
2462 1.137 drochner EOWRITE4(sc, port, v);
2463 1.137 drochner usb_delay_ms(&sc->sc_bus, 2);
2464 1.137 drochner #ifdef DEBUG
2465 1.137 drochner v = EOREAD4(sc, port);
2466 1.137 drochner if (v & (EHCI_PS_FPR | EHCI_PS_SUSP))
2467 1.137 drochner printf("ehci: resume failed: %x\n", v);
2468 1.137 drochner #endif
2469 1.5 augustss break;
2470 1.5 augustss case UHF_PORT_POWER:
2471 1.106 augustss if (sc->sc_hasppc)
2472 1.106 augustss EOWRITE4(sc, port, v &~ EHCI_PS_PP);
2473 1.5 augustss break;
2474 1.14 augustss case UHF_PORT_TEST:
2475 1.256 pgoyette DPRINTF("clear port test %jd", index, 0, 0, 0);
2476 1.14 augustss break;
2477 1.14 augustss case UHF_PORT_INDICATOR:
2478 1.256 pgoyette DPRINTF("clear port ind %jd", index, 0, 0, 0);
2479 1.14 augustss EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
2480 1.14 augustss break;
2481 1.5 augustss case UHF_C_PORT_CONNECTION:
2482 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_CSC);
2483 1.5 augustss break;
2484 1.5 augustss case UHF_C_PORT_ENABLE:
2485 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_PEC);
2486 1.5 augustss break;
2487 1.5 augustss case UHF_C_PORT_SUSPEND:
2488 1.5 augustss /* how? */
2489 1.5 augustss break;
2490 1.5 augustss case UHF_C_PORT_OVER_CURRENT:
2491 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_OCC);
2492 1.5 augustss break;
2493 1.5 augustss case UHF_C_PORT_RESET:
2494 1.106 augustss sc->sc_isreset[index] = 0;
2495 1.5 augustss break;
2496 1.5 augustss default:
2497 1.249 skrll return -1;
2498 1.5 augustss }
2499 1.5 augustss #if 0
2500 1.5 augustss switch(value) {
2501 1.5 augustss case UHF_C_PORT_CONNECTION:
2502 1.5 augustss case UHF_C_PORT_ENABLE:
2503 1.5 augustss case UHF_C_PORT_SUSPEND:
2504 1.5 augustss case UHF_C_PORT_OVER_CURRENT:
2505 1.5 augustss case UHF_C_PORT_RESET:
2506 1.5 augustss default:
2507 1.5 augustss break;
2508 1.5 augustss }
2509 1.5 augustss #endif
2510 1.5 augustss break;
2511 1.5 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2512 1.109 christos if (len == 0)
2513 1.109 christos break;
2514 1.51 toshii if ((value & 0xff) != 0) {
2515 1.249 skrll return -1;
2516 1.5 augustss }
2517 1.262 riastrad totlen = uimin(buflen, sizeof(hubd));
2518 1.249 skrll memcpy(&hubd, buf, totlen);
2519 1.5 augustss hubd.bNbrPorts = sc->sc_noport;
2520 1.291 skrll v = EREAD4(sc, EHCI_HCSPARAMS);
2521 1.5 augustss USETW(hubd.wHubCharacteristics,
2522 1.291 skrll (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) |
2523 1.291 skrll (EHCI_HCS_P_INDICATOR(v) ? UHD_PORT_IND : 0));
2524 1.5 augustss hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */
2525 1.33 augustss for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2526 1.5 augustss hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
2527 1.5 augustss hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2528 1.262 riastrad totlen = uimin(totlen, hubd.bDescLength);
2529 1.249 skrll memcpy(buf, &hubd, totlen);
2530 1.5 augustss break;
2531 1.5 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2532 1.5 augustss if (len != 4) {
2533 1.249 skrll return -1;
2534 1.5 augustss }
2535 1.5 augustss memset(buf, 0, len); /* ? XXX */
2536 1.5 augustss totlen = len;
2537 1.5 augustss break;
2538 1.5 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2539 1.256 pgoyette DPRINTF("get port status i=%jd", index, 0, 0, 0);
2540 1.5 augustss if (index < 1 || index > sc->sc_noport) {
2541 1.249 skrll return -1;
2542 1.5 augustss }
2543 1.5 augustss if (len != 4) {
2544 1.249 skrll return -1;
2545 1.5 augustss }
2546 1.5 augustss v = EOREAD4(sc, EHCI_PORTSC(index));
2547 1.277 christos DPRINTF("port status=0x%04jx", v, 0, 0, 0);
2548 1.172 matt
2549 1.178 matt i = UPS_HIGH_SPEED;
2550 1.172 matt if (sc->sc_flags & EHCIF_ETTF) {
2551 1.172 matt /*
2552 1.172 matt * If we are doing embedded transaction translation,
2553 1.172 matt * then directly attached LS/FS devices are reset by
2554 1.172 matt * the EHCI controller itself. PSPD is encoded
2555 1.195 christos * the same way as in USBSTATUS.
2556 1.172 matt */
2557 1.172 matt i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED;
2558 1.172 matt }
2559 1.5 augustss if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
2560 1.5 augustss if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
2561 1.5 augustss if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
2562 1.5 augustss if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
2563 1.5 augustss if (v & EHCI_PS_PR) i |= UPS_RESET;
2564 1.5 augustss if (v & EHCI_PS_PP) i |= UPS_PORT_POWER;
2565 1.170 kiyohara if (sc->sc_vendor_port_status)
2566 1.170 kiyohara i = sc->sc_vendor_port_status(sc, v, i);
2567 1.5 augustss USETW(ps.wPortStatus, i);
2568 1.5 augustss i = 0;
2569 1.5 augustss if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
2570 1.5 augustss if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
2571 1.5 augustss if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
2572 1.106 augustss if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET;
2573 1.5 augustss USETW(ps.wPortChange, i);
2574 1.262 riastrad totlen = uimin(len, sizeof(ps));
2575 1.249 skrll memcpy(buf, &ps, totlen);
2576 1.5 augustss break;
2577 1.5 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2578 1.249 skrll return -1;
2579 1.5 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2580 1.5 augustss break;
2581 1.5 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2582 1.5 augustss if (index < 1 || index > sc->sc_noport) {
2583 1.249 skrll return -1;
2584 1.5 augustss }
2585 1.5 augustss port = EHCI_PORTSC(index);
2586 1.106 augustss v = EOREAD4(sc, port);
2587 1.277 christos DPRINTF("portsc=0x%08jx", v, 0, 0, 0);
2588 1.106 augustss v &= ~EHCI_PS_CLEAR;
2589 1.5 augustss switch(value) {
2590 1.5 augustss case UHF_PORT_ENABLE:
2591 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_PE);
2592 1.5 augustss break;
2593 1.5 augustss case UHF_PORT_SUSPEND:
2594 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_SUSP);
2595 1.5 augustss break;
2596 1.5 augustss case UHF_PORT_RESET:
2597 1.256 pgoyette DPRINTF("reset port %jd", index, 0, 0, 0);
2598 1.172 matt if (EHCI_PS_IS_LOWSPEED(v)
2599 1.172 matt && sc->sc_ncomp > 0
2600 1.172 matt && !(sc->sc_flags & EHCIF_ETTF)) {
2601 1.172 matt /*
2602 1.172 matt * Low speed device on non-ETTF controller or
2603 1.172 matt * unaccompanied controller, give up ownership.
2604 1.172 matt */
2605 1.6 augustss ehci_disown(sc, index, 1);
2606 1.6 augustss break;
2607 1.6 augustss }
2608 1.8 augustss /* Start reset sequence. */
2609 1.8 augustss v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
2610 1.5 augustss EOWRITE4(sc, port, v | EHCI_PS_PR);
2611 1.8 augustss /* Wait for reset to complete. */
2612 1.13 augustss usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
2613 1.17 augustss if (sc->sc_dying) {
2614 1.249 skrll return -1;
2615 1.17 augustss }
2616 1.172 matt /*
2617 1.207 jakllsch * An embedded transaction translator will automatically
2618 1.172 matt * terminate the reset sequence so there's no need to
2619 1.172 matt * it.
2620 1.172 matt */
2621 1.178 matt v = EOREAD4(sc, port);
2622 1.178 matt if (v & EHCI_PS_PR) {
2623 1.172 matt /* Terminate reset sequence. */
2624 1.173 jmcneill EOWRITE4(sc, port, v & ~EHCI_PS_PR);
2625 1.172 matt /* Wait for HC to complete reset. */
2626 1.172 matt usb_delay_ms(&sc->sc_bus,
2627 1.172 matt EHCI_PORT_RESET_COMPLETE);
2628 1.172 matt if (sc->sc_dying) {
2629 1.249 skrll return -1;
2630 1.172 matt }
2631 1.17 augustss }
2632 1.172 matt
2633 1.8 augustss v = EOREAD4(sc, port);
2634 1.277 christos DPRINTF("ehci after reset, status=0x%08jx", v, 0, 0, 0);
2635 1.8 augustss if (v & EHCI_PS_PR) {
2636 1.8 augustss printf("%s: port reset timeout\n",
2637 1.134 drochner device_xname(sc->sc_dev));
2638 1.249 skrll return USBD_TIMEOUT;
2639 1.5 augustss }
2640 1.8 augustss if (!(v & EHCI_PS_PE)) {
2641 1.6 augustss /* Not a high speed device, give up ownership.*/
2642 1.6 augustss ehci_disown(sc, index, 0);
2643 1.6 augustss break;
2644 1.6 augustss }
2645 1.106 augustss sc->sc_isreset[index] = 1;
2646 1.277 christos DPRINTF("ehci port %jd reset, status = 0x%08jx", index,
2647 1.249 skrll v, 0, 0);
2648 1.5 augustss break;
2649 1.5 augustss case UHF_PORT_POWER:
2650 1.256 pgoyette DPRINTF("set port power %jd (has PPC = %jd)", index,
2651 1.229 skrll sc->sc_hasppc, 0, 0);
2652 1.106 augustss if (sc->sc_hasppc)
2653 1.106 augustss EOWRITE4(sc, port, v | EHCI_PS_PP);
2654 1.5 augustss break;
2655 1.11 augustss case UHF_PORT_TEST:
2656 1.256 pgoyette DPRINTF("set port test %jd", index, 0, 0, 0);
2657 1.11 augustss break;
2658 1.11 augustss case UHF_PORT_INDICATOR:
2659 1.256 pgoyette DPRINTF("set port ind %jd", index, 0, 0, 0);
2660 1.14 augustss EOWRITE4(sc, port, v | EHCI_PS_PIC);
2661 1.11 augustss break;
2662 1.5 augustss default:
2663 1.249 skrll return -1;
2664 1.5 augustss }
2665 1.5 augustss break;
2666 1.11 augustss case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
2667 1.11 augustss case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
2668 1.11 augustss case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
2669 1.11 augustss case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
2670 1.11 augustss break;
2671 1.5 augustss default:
2672 1.249 skrll /* default from usbroothub */
2673 1.256 pgoyette DPRINTF("returning %jd (usbroothub default)", buflen, 0, 0, 0);
2674 1.249 skrll
2675 1.249 skrll return buflen;
2676 1.5 augustss }
2677 1.249 skrll
2678 1.256 pgoyette DPRINTF("returning %jd", totlen, 0, 0, 0);
2679 1.249 skrll
2680 1.249 skrll return totlen;
2681 1.6 augustss }
2682 1.6 augustss
2683 1.309 riastrad Static int
2684 1.309 riastrad ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
2685 1.309 riastrad void *buf, int buflen)
2686 1.309 riastrad {
2687 1.309 riastrad struct ehci_softc *sc = EHCI_BUS2SC(bus);
2688 1.309 riastrad int actlen;
2689 1.309 riastrad
2690 1.309 riastrad mutex_enter(&sc->sc_rhlock);
2691 1.309 riastrad actlen = ehci_roothub_ctrl_locked(bus, req, buf, buflen);
2692 1.309 riastrad mutex_exit(&sc->sc_rhlock);
2693 1.309 riastrad
2694 1.309 riastrad return actlen;
2695 1.309 riastrad }
2696 1.309 riastrad
2697 1.265 mrg /*
2698 1.265 mrg * Handle ehci hand-off in early boot vs RB_ASKNAME/RB_SINGLE.
2699 1.265 mrg *
2700 1.265 mrg * This pile of garbage below works around the following problem without
2701 1.265 mrg * holding boots with no hand-over devices present, while penalising
2702 1.265 mrg * boots where the first ehci probe hands off devices with a 5 second
2703 1.265 mrg * delay, if RB_ASKNAME/RB_SINGLE is set. This is typically not a problem
2704 1.265 mrg * for RB_SINGLE, but the same basic issue exists.
2705 1.265 mrg *
2706 1.265 mrg * The way ehci hand-off works, the companion controller does not get the
2707 1.268 skrll * device until after its initial bus explore, so the reference dropped
2708 1.265 mrg * after the first explore is not enough. 5 seconds should be enough,
2709 1.265 mrg * and EHCI_DISOWN_DELAY_SECONDS can be set to another value.
2710 1.265 mrg *
2711 1.265 mrg * There are 3 states. CO_EARLY is set during attach. CO_SCHED is set
2712 1.265 mrg * if the callback is scheduled. CO_DONE is set when the callout has
2713 1.265 mrg * called config_pending_decr().
2714 1.265 mrg *
2715 1.265 mrg * There's a mutex, a cv and a callout here, and we delay detach if the
2716 1.265 mrg * callout has been set.
2717 1.265 mrg */
2718 1.265 mrg #ifndef EHCI_DISOWN_DELAY_SECONDS
2719 1.265 mrg #define EHCI_DISOWN_DELAY_SECONDS 5
2720 1.265 mrg #endif
2721 1.265 mrg static int ehci_disown_delay_seconds = EHCI_DISOWN_DELAY_SECONDS;
2722 1.265 mrg
2723 1.265 mrg static void
2724 1.265 mrg ehci_disown_callback(void *arg)
2725 1.265 mrg {
2726 1.265 mrg ehci_softc_t *sc = arg;
2727 1.265 mrg
2728 1.265 mrg config_pending_decr(sc->sc_dev);
2729 1.265 mrg
2730 1.265 mrg mutex_enter(&sc->sc_complock);
2731 1.265 mrg KASSERT(sc->sc_comp_state == CO_SCHED);
2732 1.265 mrg sc->sc_comp_state = CO_DONE;
2733 1.265 mrg cv_signal(&sc->sc_compcv);
2734 1.265 mrg mutex_exit(&sc->sc_complock);
2735 1.265 mrg }
2736 1.265 mrg
2737 1.265 mrg static void
2738 1.265 mrg ehci_disown_sched_callback(ehci_softc_t *sc)
2739 1.265 mrg {
2740 1.265 mrg extern bool root_is_mounted;
2741 1.265 mrg
2742 1.265 mrg mutex_enter(&sc->sc_complock);
2743 1.265 mrg
2744 1.265 mrg if (root_is_mounted ||
2745 1.265 mrg (boothowto & (RB_ASKNAME|RB_SINGLE)) == 0 ||
2746 1.265 mrg sc->sc_comp_state != CO_EARLY) {
2747 1.265 mrg mutex_exit(&sc->sc_complock);
2748 1.265 mrg return;
2749 1.265 mrg }
2750 1.265 mrg
2751 1.265 mrg callout_reset(&sc->sc_compcallout, ehci_disown_delay_seconds * hz,
2752 1.265 mrg ehci_disown_callback, &sc->sc_dev);
2753 1.265 mrg sc->sc_comp_state = CO_SCHED;
2754 1.265 mrg
2755 1.265 mrg mutex_exit(&sc->sc_complock);
2756 1.265 mrg
2757 1.265 mrg config_pending_incr(sc->sc_dev);
2758 1.300 mrg aprint_normal_dev(sc->sc_dev,
2759 1.300 mrg "delaying %s by %u seconds due to USB owner change.\n",
2760 1.286 mrg (boothowto & RB_ASKNAME) != 0 ? "ask root" : "single user",
2761 1.265 mrg ehci_disown_delay_seconds);
2762 1.265 mrg }
2763 1.265 mrg
2764 1.164 uebayasi Static void
2765 1.115 christos ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
2766 1.6 augustss {
2767 1.24 augustss int port;
2768 1.249 skrll uint32_t v;
2769 1.6 augustss
2770 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
2771 1.229 skrll
2772 1.256 pgoyette DPRINTF("index=%jd lowspeed=%jd", index, lowspeed, 0, 0);
2773 1.6 augustss if (sc->sc_npcomp != 0) {
2774 1.24 augustss int i = (index-1) / sc->sc_npcomp;
2775 1.265 mrg if (i < sc->sc_ncomp) {
2776 1.265 mrg ehci_disown_sched_callback(sc);
2777 1.265 mrg #ifdef DIAGNOSTIC
2778 1.6 augustss printf("%s: handing over %s speed device on "
2779 1.6 augustss "port %d to %s\n",
2780 1.134 drochner device_xname(sc->sc_dev),
2781 1.6 augustss lowspeed ? "low" : "full",
2782 1.255 jmcneill index, sc->sc_comps[i] ?
2783 1.255 jmcneill device_xname(sc->sc_comps[i]) :
2784 1.255 jmcneill "companion controller");
2785 1.265 mrg } else {
2786 1.265 mrg printf("%s: strange port\n",
2787 1.265 mrg device_xname(sc->sc_dev));
2788 1.265 mrg #endif
2789 1.265 mrg }
2790 1.6 augustss } else {
2791 1.265 mrg #ifdef DIAGNOSTIC
2792 1.134 drochner printf("%s: npcomp == 0\n", device_xname(sc->sc_dev));
2793 1.265 mrg #endif
2794 1.6 augustss }
2795 1.6 augustss port = EHCI_PORTSC(index);
2796 1.6 augustss v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
2797 1.6 augustss EOWRITE4(sc, port, v | EHCI_PS_PO);
2798 1.5 augustss }
2799 1.5 augustss
2800 1.5 augustss Static usbd_status
2801 1.249 skrll ehci_root_intr_transfer(struct usbd_xfer *xfer)
2802 1.5 augustss {
2803 1.5 augustss
2804 1.5 augustss /* Pipe isn't running, start first */
2805 1.249 skrll return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2806 1.5 augustss }
2807 1.5 augustss
2808 1.5 augustss Static usbd_status
2809 1.249 skrll ehci_root_intr_start(struct usbd_xfer *xfer)
2810 1.5 augustss {
2811 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
2812 1.305 riastrad
2813 1.305 riastrad KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
2814 1.5 augustss
2815 1.5 augustss if (sc->sc_dying)
2816 1.249 skrll return USBD_IOERROR;
2817 1.5 augustss
2818 1.272 riastrad KASSERT(sc->sc_intrxfer == NULL);
2819 1.5 augustss sc->sc_intrxfer = xfer;
2820 1.273 riastrad xfer->ux_status = USBD_IN_PROGRESS;
2821 1.5 augustss
2822 1.273 riastrad return USBD_IN_PROGRESS;
2823 1.5 augustss }
2824 1.5 augustss
2825 1.5 augustss /* Abort a root interrupt request. */
2826 1.5 augustss Static void
2827 1.249 skrll ehci_root_intr_abort(struct usbd_xfer *xfer)
2828 1.5 augustss {
2829 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
2830 1.5 augustss
2831 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
2832 1.249 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2833 1.227 skrll
2834 1.272 riastrad /* If xfer has already completed, nothing to do here. */
2835 1.272 riastrad if (sc->sc_intrxfer == NULL)
2836 1.272 riastrad return;
2837 1.227 skrll
2838 1.272 riastrad /*
2839 1.272 riastrad * Otherwise, sc->sc_intrxfer had better be this transfer.
2840 1.272 riastrad * Cancel it.
2841 1.272 riastrad */
2842 1.272 riastrad KASSERT(sc->sc_intrxfer == xfer);
2843 1.272 riastrad KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
2844 1.249 skrll xfer->ux_status = USBD_CANCELLED;
2845 1.5 augustss usb_transfer_complete(xfer);
2846 1.5 augustss }
2847 1.5 augustss
2848 1.5 augustss /* Close the root pipe. */
2849 1.5 augustss Static void
2850 1.249 skrll ehci_root_intr_close(struct usbd_pipe *pipe)
2851 1.5 augustss {
2852 1.272 riastrad ehci_softc_t *sc __diagused = EHCI_PIPE2SC(pipe);
2853 1.33 augustss
2854 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
2855 1.229 skrll
2856 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
2857 1.190 mrg
2858 1.272 riastrad /*
2859 1.272 riastrad * Caller must guarantee the xfer has completed first, by
2860 1.272 riastrad * closing the pipe only after normal completion or an abort.
2861 1.272 riastrad */
2862 1.272 riastrad KASSERT(sc->sc_intrxfer == NULL);
2863 1.5 augustss }
2864 1.5 augustss
2865 1.164 uebayasi Static void
2866 1.249 skrll ehci_root_intr_done(struct usbd_xfer *xfer)
2867 1.5 augustss {
2868 1.272 riastrad struct ehci_softc *sc = EHCI_XFER2SC(xfer);
2869 1.272 riastrad
2870 1.272 riastrad KASSERT(mutex_owned(&sc->sc_lock));
2871 1.272 riastrad
2872 1.272 riastrad /* Claim the xfer so it doesn't get completed again. */
2873 1.272 riastrad KASSERT(sc->sc_intrxfer == xfer);
2874 1.272 riastrad KASSERT(xfer->ux_status != USBD_IN_PROGRESS);
2875 1.272 riastrad sc->sc_intrxfer = NULL;
2876 1.9 augustss }
2877 1.9 augustss
2878 1.9 augustss /************************/
2879 1.9 augustss
2880 1.164 uebayasi Static ehci_soft_qh_t *
2881 1.9 augustss ehci_alloc_sqh(ehci_softc_t *sc)
2882 1.9 augustss {
2883 1.9 augustss ehci_soft_qh_t *sqh;
2884 1.9 augustss
2885 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
2886 1.229 skrll
2887 1.249 skrll mutex_enter(&sc->sc_lock);
2888 1.9 augustss if (sc->sc_freeqhs == NULL) {
2889 1.249 skrll DPRINTF("allocating chunk", 0, 0, 0, 0);
2890 1.249 skrll mutex_exit(&sc->sc_lock);
2891 1.249 skrll
2892 1.292 skrll usb_dma_t dma;
2893 1.297 skrll int err = usb_allocmem(sc->sc_dmatag,
2894 1.288 skrll EHCI_SQH_SIZE * EHCI_SQH_CHUNK,
2895 1.278 skrll EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma);
2896 1.288 skrll
2897 1.288 skrll if (err) {
2898 1.288 skrll DPRINTF("alloc returned %jd", err, 0, 0, 0);
2899 1.249 skrll return NULL;
2900 1.288 skrll }
2901 1.249 skrll
2902 1.249 skrll mutex_enter(&sc->sc_lock);
2903 1.292 skrll for (size_t i = 0; i < EHCI_SQH_CHUNK; i++) {
2904 1.292 skrll const int offs = i * EHCI_SQH_SIZE;
2905 1.292 skrll const bus_addr_t baddr = DMAADDR(&dma, offs);
2906 1.292 skrll
2907 1.292 skrll KASSERT(BUS_ADDR_HI32(baddr) == 0);
2908 1.292 skrll
2909 1.30 augustss sqh = KERNADDR(&dma, offs);
2910 1.292 skrll sqh->physaddr = BUS_ADDR_LO32(baddr);
2911 1.138 bouyer sqh->dma = dma;
2912 1.138 bouyer sqh->offs = offs;
2913 1.292 skrll
2914 1.9 augustss sqh->next = sc->sc_freeqhs;
2915 1.9 augustss sc->sc_freeqhs = sqh;
2916 1.9 augustss }
2917 1.9 augustss }
2918 1.9 augustss sqh = sc->sc_freeqhs;
2919 1.9 augustss sc->sc_freeqhs = sqh->next;
2920 1.249 skrll mutex_exit(&sc->sc_lock);
2921 1.249 skrll
2922 1.9 augustss memset(&sqh->qh, 0, sizeof(ehci_qh_t));
2923 1.11 augustss sqh->next = NULL;
2924 1.249 skrll return sqh;
2925 1.9 augustss }
2926 1.9 augustss
2927 1.164 uebayasi Static void
2928 1.9 augustss ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
2929 1.9 augustss {
2930 1.249 skrll KASSERT(mutex_owned(&sc->sc_lock));
2931 1.249 skrll
2932 1.9 augustss sqh->next = sc->sc_freeqhs;
2933 1.9 augustss sc->sc_freeqhs = sqh;
2934 1.9 augustss }
2935 1.9 augustss
2936 1.164 uebayasi Static ehci_soft_qtd_t *
2937 1.9 augustss ehci_alloc_sqtd(ehci_softc_t *sc)
2938 1.9 augustss {
2939 1.190 mrg ehci_soft_qtd_t *sqtd = NULL;
2940 1.9 augustss
2941 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
2942 1.229 skrll
2943 1.249 skrll mutex_enter(&sc->sc_lock);
2944 1.9 augustss if (sc->sc_freeqtds == NULL) {
2945 1.249 skrll DPRINTF("allocating chunk", 0, 0, 0, 0);
2946 1.249 skrll mutex_exit(&sc->sc_lock);
2947 1.190 mrg
2948 1.292 skrll usb_dma_t dma;
2949 1.297 skrll int err = usb_allocmem(sc->sc_dmatag,
2950 1.288 skrll EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK,
2951 1.288 skrll EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma);
2952 1.288 skrll
2953 1.288 skrll if (err) {
2954 1.288 skrll DPRINTF("alloc returned %jd", err, 0, 0, 0);
2955 1.288 skrll return NULL;
2956 1.288 skrll }
2957 1.190 mrg
2958 1.249 skrll mutex_enter(&sc->sc_lock);
2959 1.292 skrll for (size_t i = 0; i < EHCI_SQTD_CHUNK; i++) {
2960 1.292 skrll const int offs = i * EHCI_SQTD_SIZE;
2961 1.292 skrll const bus_addr_t baddr = DMAADDR(&dma, offs);
2962 1.292 skrll
2963 1.292 skrll KASSERT(BUS_ADDR_HI32(baddr) == 0);
2964 1.292 skrll
2965 1.30 augustss sqtd = KERNADDR(&dma, offs);
2966 1.292 skrll sqtd->physaddr = BUS_ADDR_LO32(baddr);
2967 1.138 bouyer sqtd->dma = dma;
2968 1.138 bouyer sqtd->offs = offs;
2969 1.190 mrg
2970 1.9 augustss sqtd->nextqtd = sc->sc_freeqtds;
2971 1.9 augustss sc->sc_freeqtds = sqtd;
2972 1.9 augustss }
2973 1.9 augustss }
2974 1.9 augustss
2975 1.9 augustss sqtd = sc->sc_freeqtds;
2976 1.9 augustss sc->sc_freeqtds = sqtd->nextqtd;
2977 1.249 skrll mutex_exit(&sc->sc_lock);
2978 1.249 skrll
2979 1.9 augustss memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t));
2980 1.9 augustss sqtd->nextqtd = NULL;
2981 1.9 augustss sqtd->xfer = NULL;
2982 1.9 augustss
2983 1.249 skrll return sqtd;
2984 1.9 augustss }
2985 1.9 augustss
2986 1.164 uebayasi Static void
2987 1.9 augustss ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
2988 1.9 augustss {
2989 1.9 augustss
2990 1.249 skrll mutex_enter(&sc->sc_lock);
2991 1.9 augustss sqtd->nextqtd = sc->sc_freeqtds;
2992 1.9 augustss sc->sc_freeqtds = sqtd;
2993 1.249 skrll mutex_exit(&sc->sc_lock);
2994 1.249 skrll }
2995 1.249 skrll
2996 1.249 skrll Static int
2997 1.249 skrll ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer,
2998 1.249 skrll int alen, int rd, ehci_soft_qtd_t **sp)
2999 1.249 skrll {
3000 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3001 1.249 skrll uint16_t flags = xfer->ux_flags;
3002 1.249 skrll
3003 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3004 1.249 skrll
3005 1.249 skrll ASSERT_SLEEPABLE();
3006 1.249 skrll KASSERT(sp);
3007 1.249 skrll KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER)));
3008 1.249 skrll
3009 1.249 skrll size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0;
3010 1.275 skrll nsqtd += howmany(alen, EHCI_PAGE_SIZE);
3011 1.249 skrll exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd,
3012 1.249 skrll KM_SLEEP);
3013 1.249 skrll exfer->ex_nsqtd = nsqtd;
3014 1.249 skrll
3015 1.256 pgoyette DPRINTF("xfer %#jx len %jd nsqtd %jd flags %jx", (uintptr_t)xfer,
3016 1.256 pgoyette alen, nsqtd, flags);
3017 1.249 skrll
3018 1.249 skrll for (size_t j = 0; j < exfer->ex_nsqtd;) {
3019 1.249 skrll ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc);
3020 1.249 skrll if (cur == NULL)
3021 1.249 skrll goto nomem;
3022 1.249 skrll exfer->ex_sqtds[j++] = cur;
3023 1.249 skrll
3024 1.249 skrll cur->xfer = xfer;
3025 1.249 skrll cur->len = 0;
3026 1.249 skrll
3027 1.249 skrll }
3028 1.249 skrll
3029 1.249 skrll *sp = exfer->ex_sqtds[0];
3030 1.256 pgoyette DPRINTF("return sqtd=%#jx", (uintptr_t)*sp, 0, 0, 0);
3031 1.249 skrll
3032 1.249 skrll return 0;
3033 1.249 skrll
3034 1.249 skrll nomem:
3035 1.249 skrll ehci_free_sqtds(sc, exfer);
3036 1.249 skrll kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd);
3037 1.249 skrll DPRINTF("no memory", 0, 0, 0, 0);
3038 1.249 skrll return ENOMEM;
3039 1.249 skrll }
3040 1.249 skrll
3041 1.249 skrll Static void
3042 1.249 skrll ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer)
3043 1.249 skrll {
3044 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3045 1.256 pgoyette DPRINTF("exfer=%#jx", (uintptr_t)exfer, 0, 0, 0);
3046 1.249 skrll
3047 1.249 skrll mutex_enter(&sc->sc_lock);
3048 1.249 skrll for (size_t i = 0; i < exfer->ex_nsqtd; i++) {
3049 1.249 skrll ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i];
3050 1.249 skrll
3051 1.249 skrll if (sqtd == NULL)
3052 1.249 skrll break;
3053 1.249 skrll
3054 1.249 skrll sqtd->nextqtd = sc->sc_freeqtds;
3055 1.249 skrll sc->sc_freeqtds = sqtd;
3056 1.249 skrll }
3057 1.249 skrll mutex_exit(&sc->sc_lock);
3058 1.9 augustss }
3059 1.9 augustss
3060 1.249 skrll Static void
3061 1.249 skrll ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev)
3062 1.249 skrll {
3063 1.249 skrll if (prev) {
3064 1.249 skrll prev->nextqtd = sqtd;
3065 1.249 skrll prev->qtd.qtd_next = htole32(sqtd->physaddr);
3066 1.249 skrll prev->qtd.qtd_altnext = prev->qtd.qtd_next;
3067 1.249 skrll usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd),
3068 1.249 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3069 1.249 skrll }
3070 1.249 skrll }
3071 1.249 skrll
3072 1.249 skrll Static void
3073 1.249 skrll ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer,
3074 1.249 skrll int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd)
3075 1.249 skrll {
3076 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3077 1.249 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
3078 1.249 skrll uint16_t flags = xfer->ux_flags;
3079 1.249 skrll ehci_soft_qtd_t *sqtd, *prev;
3080 1.249 skrll int tog = *toggle;
3081 1.249 skrll int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
3082 1.249 skrll int len = length;
3083 1.249 skrll
3084 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3085 1.256 pgoyette DPRINTF("xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer,
3086 1.256 pgoyette len, isread, tog);
3087 1.256 pgoyette DPRINTF(" VA %#jx", (uintptr_t)KERNADDR(&xfer->ux_dmabuf, 0),
3088 1.256 pgoyette 0, 0, 0);
3089 1.249 skrll
3090 1.249 skrll KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER)));
3091 1.249 skrll
3092 1.249 skrll const uint32_t qtdstatus = EHCI_QTD_ACTIVE |
3093 1.249 skrll EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
3094 1.15 augustss EHCI_QTD_SET_CERR(3)
3095 1.67 mycroft ;
3096 1.197 prlw1
3097 1.249 skrll sqtd = prev = NULL;
3098 1.249 skrll size_t curoffs = 0;
3099 1.249 skrll size_t j = 0;
3100 1.249 skrll for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) {
3101 1.249 skrll sqtd = exfer->ex_sqtds[j++];
3102 1.256 pgoyette DPRINTF("sqtd[%jd]=%#jx prev %#jx", j, (uintptr_t)sqtd,
3103 1.256 pgoyette (uintptr_t)prev, 0);
3104 1.15 augustss
3105 1.102 augustss /*
3106 1.249 skrll * The EHCI hardware can handle at most 5 pages and they do
3107 1.249 skrll * not have to be contiguous
3108 1.102 augustss */
3109 1.249 skrll vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs);
3110 1.249 skrll vaddr_t va_offs = EHCI_PAGE_OFFSET(va);
3111 1.249 skrll size_t curlen = len;
3112 1.249 skrll if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) {
3113 1.249 skrll /* must use multiple TDs, fill as much as possible. */
3114 1.249 skrll curlen = EHCI_QTD_MAXTRANSFER - va_offs;
3115 1.197 prlw1
3116 1.249 skrll /* the length must be a multiple of the max size */
3117 1.249 skrll curlen -= curlen % mps;
3118 1.15 augustss }
3119 1.249 skrll KASSERT(curlen != 0);
3120 1.256 pgoyette DPRINTF(" len=%jd curlen=%jd curoffs=%ju", len, curlen,
3121 1.249 skrll curoffs, 0);
3122 1.249 skrll
3123 1.249 skrll /* Fill the qTD */
3124 1.249 skrll sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL;
3125 1.249 skrll sqtd->qtd.qtd_status = htole32(
3126 1.249 skrll qtdstatus |
3127 1.249 skrll EHCI_QTD_SET_BYTES(curlen) |
3128 1.249 skrll EHCI_QTD_SET_TOGGLE(tog));
3129 1.15 augustss
3130 1.197 prlw1 /* Find number of pages we'll be using, insert dma addresses */
3131 1.249 skrll size_t pages = EHCI_NPAGES(curlen);
3132 1.197 prlw1 KASSERT(pages <= EHCI_QTD_NBUFFERS);
3133 1.249 skrll size_t pageoffs = EHCI_PAGE(curoffs);
3134 1.249 skrll for (size_t i = 0; i < pages; i++) {
3135 1.280 skrll paddr_t a = EHCI_PAGE(DMAADDR(dma,
3136 1.280 skrll pageoffs + i * EHCI_PAGE_SIZE));
3137 1.280 skrll sqtd->qtd.qtd_buffer[i] = htole32(BUS_ADDR_LO32(a));
3138 1.280 skrll sqtd->qtd.qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a));
3139 1.277 christos DPRINTF(" buffer[%jd/%jd] 0x%08jx 0x%08jx",
3140 1.256 pgoyette i, pages,
3141 1.249 skrll le32toh(sqtd->qtd.qtd_buffer_hi[i]),
3142 1.249 skrll le32toh(sqtd->qtd.qtd_buffer[i]));
3143 1.15 augustss }
3144 1.249 skrll /* First buffer pointer requires a page offset to start at */
3145 1.249 skrll sqtd->qtd.qtd_buffer[0] |= htole32(va_offs);
3146 1.249 skrll
3147 1.249 skrll usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd),
3148 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3149 1.197 prlw1
3150 1.249 skrll sqtd->len = curlen;
3151 1.197 prlw1
3152 1.256 pgoyette DPRINTF(" va %#jx pa %#jx len %jd", (uintptr_t)va,
3153 1.256 pgoyette (uintptr_t)DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0);
3154 1.138 bouyer
3155 1.249 skrll ehci_append_sqtd(sqtd, prev);
3156 1.197 prlw1
3157 1.275 skrll if (howmany(curlen, mps) & 1) {
3158 1.55 mycroft tog ^= 1;
3159 1.55 mycroft }
3160 1.249 skrll
3161 1.249 skrll curoffs += curlen;
3162 1.249 skrll len -= curlen;
3163 1.15 augustss }
3164 1.249 skrll KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu",
3165 1.249 skrll xfer, length, len, mps, exfer->ex_nsqtd, j);
3166 1.15 augustss
3167 1.249 skrll if (!isread &&
3168 1.249 skrll (flags & USBD_FORCE_SHORT_XFER) &&
3169 1.249 skrll length % mps == 0) {
3170 1.249 skrll /* Force a 0 length transfer at the end. */
3171 1.249 skrll
3172 1.249 skrll KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j,
3173 1.249 skrll exfer->ex_nsqtd);
3174 1.249 skrll prev = sqtd;
3175 1.249 skrll sqtd = exfer->ex_sqtds[j++];
3176 1.249 skrll memset(&sqtd->qtd, 0, sizeof(sqtd->qtd));
3177 1.249 skrll sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL;
3178 1.249 skrll sqtd->qtd.qtd_status = htole32(
3179 1.249 skrll qtdstatus |
3180 1.249 skrll EHCI_QTD_SET_BYTES(0) |
3181 1.249 skrll EHCI_QTD_SET_TOGGLE(tog));
3182 1.29 augustss
3183 1.249 skrll usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd),
3184 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3185 1.15 augustss
3186 1.249 skrll ehci_append_sqtd(sqtd, prev);
3187 1.249 skrll tog ^= 1;
3188 1.249 skrll }
3189 1.229 skrll
3190 1.249 skrll *lsqtd = sqtd;
3191 1.249 skrll *toggle = tog;
3192 1.18 augustss }
3193 1.18 augustss
3194 1.164 uebayasi Static ehci_soft_itd_t *
3195 1.139 jmcneill ehci_alloc_itd(ehci_softc_t *sc)
3196 1.139 jmcneill {
3197 1.139 jmcneill struct ehci_soft_itd *itd, *freeitd;
3198 1.139 jmcneill
3199 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3200 1.229 skrll
3201 1.192 mrg mutex_enter(&sc->sc_lock);
3202 1.139 jmcneill
3203 1.249 skrll freeitd = LIST_FIRST(&sc->sc_freeitds);
3204 1.139 jmcneill if (freeitd == NULL) {
3205 1.249 skrll DPRINTF("allocating chunk", 0, 0, 0, 0);
3206 1.249 skrll mutex_exit(&sc->sc_lock);
3207 1.288 skrll
3208 1.292 skrll usb_dma_t dma;
3209 1.297 skrll int err = usb_allocmem(sc->sc_dmatag,
3210 1.288 skrll EHCI_ITD_SIZE * EHCI_ITD_CHUNK,
3211 1.278 skrll EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma);
3212 1.139 jmcneill
3213 1.139 jmcneill if (err) {
3214 1.256 pgoyette DPRINTF("alloc returned %jd", err, 0, 0, 0);
3215 1.139 jmcneill return NULL;
3216 1.139 jmcneill }
3217 1.288 skrll
3218 1.249 skrll mutex_enter(&sc->sc_lock);
3219 1.292 skrll for (size_t i = 0; i < EHCI_ITD_CHUNK; i++) {
3220 1.292 skrll const int offs = i * EHCI_ITD_SIZE;
3221 1.292 skrll const bus_addr_t baddr = DMAADDR(&dma, offs);
3222 1.292 skrll
3223 1.292 skrll KASSERT(BUS_ADDR_HI32(baddr) == 0);
3224 1.292 skrll
3225 1.139 jmcneill itd = KERNADDR(&dma, offs);
3226 1.292 skrll itd->physaddr = BUS_ADDR_LO32(baddr);
3227 1.183 jakllsch itd->dma = dma;
3228 1.139 jmcneill itd->offs = offs;
3229 1.292 skrll
3230 1.249 skrll LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list);
3231 1.139 jmcneill }
3232 1.139 jmcneill freeitd = LIST_FIRST(&sc->sc_freeitds);
3233 1.139 jmcneill }
3234 1.139 jmcneill
3235 1.139 jmcneill itd = freeitd;
3236 1.249 skrll LIST_REMOVE(itd, free_list);
3237 1.249 skrll mutex_exit(&sc->sc_lock);
3238 1.139 jmcneill memset(&itd->itd, 0, sizeof(ehci_itd_t));
3239 1.139 jmcneill
3240 1.249 skrll itd->frame_list.next = NULL;
3241 1.249 skrll itd->frame_list.prev = NULL;
3242 1.139 jmcneill itd->xfer_next = NULL;
3243 1.139 jmcneill itd->slot = 0;
3244 1.139 jmcneill
3245 1.139 jmcneill return itd;
3246 1.139 jmcneill }
3247 1.139 jmcneill
3248 1.249 skrll Static ehci_soft_sitd_t *
3249 1.249 skrll ehci_alloc_sitd(ehci_softc_t *sc)
3250 1.139 jmcneill {
3251 1.249 skrll struct ehci_soft_sitd *sitd, *freesitd;
3252 1.249 skrll
3253 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3254 1.249 skrll
3255 1.249 skrll mutex_enter(&sc->sc_lock);
3256 1.249 skrll freesitd = LIST_FIRST(&sc->sc_freesitds);
3257 1.249 skrll if (freesitd == NULL) {
3258 1.249 skrll DPRINTF("allocating chunk", 0, 0, 0, 0);
3259 1.249 skrll mutex_exit(&sc->sc_lock);
3260 1.288 skrll
3261 1.292 skrll usb_dma_t dma;
3262 1.298 skrll int err = usb_allocmem(sc->sc_dmatag,
3263 1.288 skrll EHCI_SITD_SIZE * EHCI_SITD_CHUNK,
3264 1.278 skrll EHCI_PAGE_SIZE, USBMALLOC_COHERENT, &dma);
3265 1.249 skrll
3266 1.249 skrll if (err) {
3267 1.288 skrll DPRINTF("alloc returned %jd", err, 0, 0, 0);
3268 1.249 skrll return NULL;
3269 1.249 skrll }
3270 1.249 skrll
3271 1.249 skrll mutex_enter(&sc->sc_lock);
3272 1.292 skrll for (size_t i = 0; i < EHCI_SITD_CHUNK; i++) {
3273 1.292 skrll const int offs = i * EHCI_SITD_SIZE;
3274 1.292 skrll const bus_addr_t baddr = DMAADDR(&dma, offs);
3275 1.292 skrll
3276 1.292 skrll KASSERT(BUS_ADDR_HI32(baddr) == 0);
3277 1.292 skrll
3278 1.249 skrll sitd = KERNADDR(&dma, offs);
3279 1.292 skrll sitd->physaddr = BUS_ADDR_LO32(baddr);
3280 1.249 skrll sitd->dma = dma;
3281 1.249 skrll sitd->offs = offs;
3282 1.292 skrll
3283 1.249 skrll LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list);
3284 1.249 skrll }
3285 1.249 skrll freesitd = LIST_FIRST(&sc->sc_freesitds);
3286 1.249 skrll }
3287 1.139 jmcneill
3288 1.249 skrll sitd = freesitd;
3289 1.249 skrll LIST_REMOVE(sitd, free_list);
3290 1.249 skrll mutex_exit(&sc->sc_lock);
3291 1.249 skrll
3292 1.249 skrll memset(&sitd->sitd, 0, sizeof(ehci_sitd_t));
3293 1.249 skrll
3294 1.249 skrll sitd->frame_list.next = NULL;
3295 1.249 skrll sitd->frame_list.prev = NULL;
3296 1.249 skrll sitd->xfer_next = NULL;
3297 1.249 skrll sitd->slot = 0;
3298 1.190 mrg
3299 1.249 skrll return sitd;
3300 1.139 jmcneill }
3301 1.139 jmcneill
3302 1.15 augustss /****************/
3303 1.15 augustss
3304 1.9 augustss /*
3305 1.10 augustss * Close a reqular pipe.
3306 1.10 augustss * Assumes that there are no pending transactions.
3307 1.10 augustss */
3308 1.164 uebayasi Static void
3309 1.249 skrll ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head)
3310 1.10 augustss {
3311 1.249 skrll struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);
3312 1.249 skrll ehci_softc_t *sc = EHCI_PIPE2SC(pipe);
3313 1.10 augustss ehci_soft_qh_t *sqh = epipe->sqh;
3314 1.10 augustss
3315 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
3316 1.190 mrg
3317 1.10 augustss ehci_rem_qh(sc, sqh, head);
3318 1.10 augustss ehci_free_sqh(sc, epipe->sqh);
3319 1.10 augustss }
3320 1.10 augustss
3321 1.33 augustss /*
3322 1.282 gson * Arrange for the hardware to tells us that it is not still
3323 1.260 mrg * processing the TDs by setting the QH halted bit and wait for the ehci
3324 1.260 mrg * door bell
3325 1.10 augustss */
3326 1.164 uebayasi Static void
3327 1.271 riastrad ehci_abortx(struct usbd_xfer *xfer)
3328 1.10 augustss {
3329 1.260 mrg EHCIHIST_FUNC(); EHCIHIST_CALLED();
3330 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
3331 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3332 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3333 1.26 augustss ehci_soft_qh_t *sqh = epipe->sqh;
3334 1.249 skrll ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd;
3335 1.26 augustss ehci_physaddr_t cur;
3336 1.249 skrll uint32_t qhstatus;
3337 1.26 augustss int hit;
3338 1.10 augustss
3339 1.256 pgoyette DPRINTF("xfer=%#jx pipe=%#jx", (uintptr_t)xfer, (uintptr_t)epipe, 0, 0);
3340 1.10 augustss
3341 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
3342 1.249 skrll ASSERT_SLEEPABLE();
3343 1.190 mrg
3344 1.271 riastrad KASSERTMSG((xfer->ux_status == USBD_CANCELLED ||
3345 1.271 riastrad xfer->ux_status == USBD_TIMEOUT),
3346 1.271 riastrad "bad abort status: %d", xfer->ux_status);
3347 1.260 mrg
3348 1.260 mrg /*
3349 1.260 mrg * If we're dying, skip the hardware action and just notify the
3350 1.260 mrg * software that we're done.
3351 1.260 mrg */
3352 1.260 mrg if (sc->sc_dying) {
3353 1.260 mrg goto dying;
3354 1.96 augustss }
3355 1.96 augustss
3356 1.96 augustss /*
3357 1.260 mrg * HC Step 1: Make interrupt routine and hardware ignore xfer.
3358 1.11 augustss */
3359 1.249 skrll ehci_del_intr_list(sc, exfer);
3360 1.138 bouyer
3361 1.138 bouyer usb_syncmem(&sqh->dma,
3362 1.138 bouyer sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
3363 1.138 bouyer sizeof(sqh->qh.qh_qtd.qtd_status),
3364 1.138 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3365 1.26 augustss qhstatus = sqh->qh.qh_qtd.qtd_status;
3366 1.26 augustss sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED);
3367 1.138 bouyer usb_syncmem(&sqh->dma,
3368 1.138 bouyer sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
3369 1.138 bouyer sizeof(sqh->qh.qh_qtd.qtd_status),
3370 1.138 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3371 1.249 skrll
3372 1.249 skrll if (exfer->ex_type == EX_CTRL) {
3373 1.249 skrll fsqtd = exfer->ex_setup;
3374 1.249 skrll lsqtd = exfer->ex_status;
3375 1.249 skrll } else {
3376 1.249 skrll fsqtd = exfer->ex_sqtdstart;
3377 1.249 skrll lsqtd = exfer->ex_sqtdend;
3378 1.249 skrll }
3379 1.249 skrll for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) {
3380 1.138 bouyer usb_syncmem(&sqtd->dma,
3381 1.138 bouyer sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
3382 1.138 bouyer sizeof(sqtd->qtd.qtd_status),
3383 1.138 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3384 1.26 augustss sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED);
3385 1.138 bouyer usb_syncmem(&sqtd->dma,
3386 1.138 bouyer sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
3387 1.138 bouyer sizeof(sqtd->qtd.qtd_status),
3388 1.138 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3389 1.249 skrll if (sqtd == lsqtd)
3390 1.26 augustss break;
3391 1.26 augustss }
3392 1.11 augustss
3393 1.33 augustss /*
3394 1.260 mrg * HC Step 2: Wait until we know hardware has finished any possible
3395 1.260 mrg * use of the xfer.
3396 1.11 augustss */
3397 1.26 augustss ehci_sync_hc(sc);
3398 1.33 augustss
3399 1.33 augustss /*
3400 1.260 mrg * HC Step 3: Remove any vestiges of the xfer from the hardware.
3401 1.11 augustss * The complication here is that the hardware may have executed
3402 1.11 augustss * beyond the xfer we're trying to abort. So as we're scanning
3403 1.11 augustss * the TDs of this xfer we check if the hardware points to
3404 1.11 augustss * any of them.
3405 1.11 augustss */
3406 1.138 bouyer
3407 1.138 bouyer usb_syncmem(&sqh->dma,
3408 1.138 bouyer sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
3409 1.138 bouyer sizeof(sqh->qh.qh_curqtd),
3410 1.138 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3411 1.26 augustss cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd));
3412 1.26 augustss hit = 0;
3413 1.249 skrll for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) {
3414 1.26 augustss hit |= cur == sqtd->physaddr;
3415 1.249 skrll if (sqtd == lsqtd)
3416 1.26 augustss break;
3417 1.26 augustss }
3418 1.26 augustss sqtd = sqtd->nextqtd;
3419 1.26 augustss /* Zap curqtd register if hardware pointed inside the xfer. */
3420 1.26 augustss if (hit && sqtd != NULL) {
3421 1.277 christos DPRINTF("cur=0x%08jx", sqtd->physaddr, 0, 0, 0);
3422 1.26 augustss sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */
3423 1.138 bouyer usb_syncmem(&sqh->dma,
3424 1.138 bouyer sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
3425 1.138 bouyer sizeof(sqh->qh.qh_curqtd),
3426 1.138 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3427 1.26 augustss sqh->qh.qh_qtd.qtd_status = qhstatus;
3428 1.138 bouyer usb_syncmem(&sqh->dma,
3429 1.138 bouyer sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
3430 1.138 bouyer sizeof(sqh->qh.qh_qtd.qtd_status),
3431 1.138 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3432 1.26 augustss } else {
3433 1.249 skrll DPRINTF("no hit", 0, 0, 0, 0);
3434 1.249 skrll usb_syncmem(&sqh->dma,
3435 1.249 skrll sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
3436 1.249 skrll sizeof(sqh->qh.qh_curqtd),
3437 1.249 skrll BUS_DMASYNC_PREREAD);
3438 1.26 augustss }
3439 1.11 augustss
3440 1.260 mrg dying:
3441 1.18 augustss #ifdef DIAGNOSTIC
3442 1.249 skrll exfer->ex_isdone = true;
3443 1.18 augustss #endif
3444 1.260 mrg DPRINTFN(14, "end", 0, 0, 0, 0);
3445 1.11 augustss
3446 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
3447 1.10 augustss }
3448 1.10 augustss
3449 1.164 uebayasi Static void
3450 1.249 skrll ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status)
3451 1.139 jmcneill {
3452 1.260 mrg EHCIHIST_FUNC(); EHCIHIST_CALLED();
3453 1.139 jmcneill ehci_isoc_trans_t trans_status;
3454 1.139 jmcneill struct ehci_xfer *exfer;
3455 1.139 jmcneill ehci_softc_t *sc;
3456 1.139 jmcneill struct ehci_soft_itd *itd;
3457 1.249 skrll struct ehci_soft_sitd *sitd;
3458 1.260 mrg int i;
3459 1.139 jmcneill
3460 1.260 mrg KASSERTMSG(status == USBD_CANCELLED,
3461 1.260 mrg "invalid status for abort: %d", (int)status);
3462 1.229 skrll
3463 1.249 skrll exfer = EHCI_XFER2EXFER(xfer);
3464 1.249 skrll sc = EHCI_XFER2SC(xfer);
3465 1.139 jmcneill
3466 1.256 pgoyette DPRINTF("xfer %#jx pipe %#jx", (uintptr_t)xfer,
3467 1.256 pgoyette (uintptr_t)xfer->ux_pipe, 0, 0);
3468 1.139 jmcneill
3469 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
3470 1.260 mrg ASSERT_SLEEPABLE();
3471 1.260 mrg
3472 1.260 mrg /* No timeout or task here. */
3473 1.260 mrg
3474 1.260 mrg /*
3475 1.260 mrg * The xfer cannot have been cancelled already. It is the
3476 1.260 mrg * responsibility of the caller of usbd_abort_pipe not to try
3477 1.260 mrg * to abort a pipe multiple times, whether concurrently or
3478 1.260 mrg * sequentially.
3479 1.260 mrg */
3480 1.260 mrg KASSERT(xfer->ux_status != USBD_CANCELLED);
3481 1.190 mrg
3482 1.260 mrg /* If anyone else beat us, we're done. */
3483 1.260 mrg if (xfer->ux_status != USBD_IN_PROGRESS)
3484 1.139 jmcneill return;
3485 1.139 jmcneill
3486 1.260 mrg /* We beat everyone else. Claim the status. */
3487 1.260 mrg xfer->ux_status = status;
3488 1.139 jmcneill
3489 1.260 mrg /*
3490 1.260 mrg * If we're dying, skip the hardware action and just notify the
3491 1.260 mrg * software that we're done.
3492 1.260 mrg */
3493 1.260 mrg if (sc->sc_dying) {
3494 1.260 mrg goto dying;
3495 1.139 jmcneill }
3496 1.139 jmcneill
3497 1.260 mrg /*
3498 1.260 mrg * HC Step 1: Make interrupt routine and hardware ignore xfer.
3499 1.260 mrg */
3500 1.249 skrll ehci_del_intr_list(sc, exfer);
3501 1.249 skrll
3502 1.249 skrll if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) {
3503 1.249 skrll for (itd = exfer->ex_itdstart; itd != NULL;
3504 1.249 skrll itd = itd->xfer_next) {
3505 1.249 skrll usb_syncmem(&itd->dma,
3506 1.249 skrll itd->offs + offsetof(ehci_itd_t, itd_ctl),
3507 1.249 skrll sizeof(itd->itd.itd_ctl),
3508 1.249 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3509 1.139 jmcneill
3510 1.249 skrll for (i = 0; i < 8; i++) {
3511 1.249 skrll trans_status = le32toh(itd->itd.itd_ctl[i]);
3512 1.249 skrll trans_status &= ~EHCI_ITD_ACTIVE;
3513 1.249 skrll itd->itd.itd_ctl[i] = htole32(trans_status);
3514 1.249 skrll }
3515 1.139 jmcneill
3516 1.249 skrll usb_syncmem(&itd->dma,
3517 1.249 skrll itd->offs + offsetof(ehci_itd_t, itd_ctl),
3518 1.249 skrll sizeof(itd->itd.itd_ctl),
3519 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3520 1.139 jmcneill }
3521 1.249 skrll } else {
3522 1.249 skrll for (sitd = exfer->ex_sitdstart; sitd != NULL;
3523 1.249 skrll sitd = sitd->xfer_next) {
3524 1.249 skrll usb_syncmem(&sitd->dma,
3525 1.249 skrll sitd->offs + offsetof(ehci_sitd_t, sitd_buffer),
3526 1.249 skrll sizeof(sitd->sitd.sitd_buffer),
3527 1.249 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3528 1.139 jmcneill
3529 1.249 skrll trans_status = le32toh(sitd->sitd.sitd_trans);
3530 1.249 skrll trans_status &= ~EHCI_SITD_ACTIVE;
3531 1.249 skrll sitd->sitd.sitd_trans = htole32(trans_status);
3532 1.249 skrll
3533 1.249 skrll usb_syncmem(&sitd->dma,
3534 1.249 skrll sitd->offs + offsetof(ehci_sitd_t, sitd_buffer),
3535 1.249 skrll sizeof(sitd->sitd.sitd_buffer),
3536 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3537 1.249 skrll }
3538 1.139 jmcneill }
3539 1.139 jmcneill
3540 1.260 mrg dying:
3541 1.139 jmcneill #ifdef DIAGNOSTIC
3542 1.249 skrll exfer->ex_isdone = true;
3543 1.139 jmcneill #endif
3544 1.139 jmcneill usb_transfer_complete(xfer);
3545 1.260 mrg DPRINTFN(14, "end", 0, 0, 0, 0);
3546 1.139 jmcneill
3547 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
3548 1.139 jmcneill }
3549 1.139 jmcneill
3550 1.5 augustss /************************/
3551 1.5 augustss
3552 1.249 skrll Static int
3553 1.249 skrll ehci_device_ctrl_init(struct usbd_xfer *xfer)
3554 1.249 skrll {
3555 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3556 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
3557 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3558 1.249 skrll usb_device_request_t *req = &xfer->ux_request;
3559 1.249 skrll ehci_soft_qtd_t *setup, *status, *next;
3560 1.249 skrll int isread = req->bmRequestType & UT_READ;
3561 1.249 skrll int len = xfer->ux_bufsize;
3562 1.249 skrll int err;
3563 1.249 skrll
3564 1.249 skrll exfer->ex_type = EX_CTRL;
3565 1.249 skrll exfer->ex_status = NULL;
3566 1.249 skrll exfer->ex_data = NULL;
3567 1.249 skrll exfer->ex_setup = ehci_alloc_sqtd(sc);
3568 1.249 skrll if (exfer->ex_setup == NULL) {
3569 1.249 skrll err = ENOMEM;
3570 1.249 skrll goto bad1;
3571 1.249 skrll }
3572 1.249 skrll exfer->ex_status = ehci_alloc_sqtd(sc);
3573 1.249 skrll if (exfer->ex_status == NULL) {
3574 1.249 skrll err = ENOMEM;
3575 1.249 skrll goto bad2;
3576 1.249 skrll }
3577 1.249 skrll setup = exfer->ex_setup;
3578 1.249 skrll status = exfer->ex_status;
3579 1.249 skrll exfer->ex_nsqtd = 0;
3580 1.249 skrll next = status;
3581 1.249 skrll /* Set up data transaction */
3582 1.249 skrll if (len != 0) {
3583 1.249 skrll err = ehci_alloc_sqtd_chain(sc, xfer, len, isread,
3584 1.249 skrll &exfer->ex_data);
3585 1.249 skrll if (err)
3586 1.249 skrll goto bad3;
3587 1.249 skrll next = exfer->ex_data;
3588 1.249 skrll }
3589 1.249 skrll
3590 1.249 skrll /* Clear toggle */
3591 1.249 skrll setup->qtd.qtd_status = htole32(
3592 1.249 skrll EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
3593 1.249 skrll EHCI_QTD_SET_TOGGLE(0) |
3594 1.249 skrll EHCI_QTD_SET_BYTES(sizeof(*req))
3595 1.249 skrll );
3596 1.280 skrll
3597 1.280 skrll const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0);
3598 1.280 skrll setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba));
3599 1.280 skrll setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba));
3600 1.249 skrll setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
3601 1.249 skrll setup->nextqtd = next;
3602 1.249 skrll setup->xfer = xfer;
3603 1.249 skrll setup->len = sizeof(*req);
3604 1.249 skrll
3605 1.249 skrll status->qtd.qtd_status = htole32(
3606 1.249 skrll EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
3607 1.249 skrll EHCI_QTD_SET_TOGGLE(1) |
3608 1.249 skrll EHCI_QTD_IOC
3609 1.249 skrll );
3610 1.249 skrll status->qtd.qtd_buffer[0] = 0;
3611 1.249 skrll status->qtd.qtd_buffer_hi[0] = 0;
3612 1.249 skrll status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL;
3613 1.249 skrll status->nextqtd = NULL;
3614 1.249 skrll status->xfer = xfer;
3615 1.249 skrll status->len = 0;
3616 1.249 skrll
3617 1.249 skrll return 0;
3618 1.249 skrll bad3:
3619 1.249 skrll ehci_free_sqtd(sc, exfer->ex_status);
3620 1.249 skrll bad2:
3621 1.249 skrll ehci_free_sqtd(sc, exfer->ex_setup);
3622 1.249 skrll bad1:
3623 1.249 skrll return err;
3624 1.249 skrll }
3625 1.249 skrll
3626 1.249 skrll Static void
3627 1.249 skrll ehci_device_ctrl_fini(struct usbd_xfer *xfer)
3628 1.249 skrll {
3629 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3630 1.249 skrll struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
3631 1.249 skrll
3632 1.249 skrll KASSERT(ex->ex_type == EX_CTRL);
3633 1.249 skrll
3634 1.249 skrll ehci_free_sqtd(sc, ex->ex_setup);
3635 1.249 skrll ehci_free_sqtd(sc, ex->ex_status);
3636 1.249 skrll ehci_free_sqtds(sc, ex);
3637 1.249 skrll if (ex->ex_nsqtd)
3638 1.249 skrll kmem_free(ex->ex_sqtds,
3639 1.249 skrll sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd);
3640 1.249 skrll }
3641 1.249 skrll
3642 1.10 augustss Static usbd_status
3643 1.249 skrll ehci_device_ctrl_transfer(struct usbd_xfer *xfer)
3644 1.10 augustss {
3645 1.10 augustss
3646 1.10 augustss /* Pipe isn't running, start first */
3647 1.249 skrll return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3648 1.10 augustss }
3649 1.10 augustss
3650 1.12 augustss Static usbd_status
3651 1.249 skrll ehci_device_ctrl_start(struct usbd_xfer *xfer)
3652 1.12 augustss {
3653 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
3654 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3655 1.249 skrll usb_device_request_t *req = &xfer->ux_request;
3656 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3657 1.249 skrll ehci_soft_qtd_t *setup, *status, *next;
3658 1.249 skrll ehci_soft_qh_t *sqh;
3659 1.249 skrll
3660 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3661 1.249 skrll
3662 1.305 riastrad KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3663 1.249 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
3664 1.15 augustss
3665 1.15 augustss if (sc->sc_dying)
3666 1.249 skrll return USBD_IOERROR;
3667 1.249 skrll
3668 1.249 skrll const int isread = req->bmRequestType & UT_READ;
3669 1.249 skrll const int len = UGETW(req->wLength);
3670 1.249 skrll
3671 1.277 christos DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx",
3672 1.249 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
3673 1.249 skrll UGETW(req->wIndex));
3674 1.256 pgoyette DPRINTF("len=%jd, addr=%jd, endpt=%jd",
3675 1.256 pgoyette len, epipe->pipe.up_dev->ud_addr,
3676 1.249 skrll epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0);
3677 1.249 skrll
3678 1.249 skrll sqh = epipe->sqh;
3679 1.15 augustss
3680 1.249 skrll KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr,
3681 1.249 skrll "address QH %" __PRIuBIT " pipe %d\n",
3682 1.249 skrll EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)),
3683 1.249 skrll epipe->pipe.up_dev->ud_addr);
3684 1.249 skrll KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) ==
3685 1.249 skrll UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
3686 1.249 skrll "MPS QH %" __PRIuBIT " pipe %d\n",
3687 1.249 skrll EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)),
3688 1.249 skrll UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
3689 1.15 augustss
3690 1.249 skrll setup = exfer->ex_setup;
3691 1.249 skrll status = exfer->ex_status;
3692 1.15 augustss
3693 1.256 pgoyette DPRINTF("setup %#jx status %#jx data %#jx",
3694 1.256 pgoyette (uintptr_t)setup, (uintptr_t)status, (uintptr_t)exfer->ex_data, 0);
3695 1.249 skrll KASSERTMSG(setup != NULL && status != NULL,
3696 1.249 skrll "Failed memory allocation, setup %p status %p",
3697 1.249 skrll setup, status);
3698 1.190 mrg
3699 1.249 skrll memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req));
3700 1.249 skrll usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
3701 1.10 augustss
3702 1.249 skrll /* Clear toggle */
3703 1.249 skrll setup->qtd.qtd_status &= ~htole32(
3704 1.249 skrll EHCI_QTD_STATUS_MASK |
3705 1.249 skrll EHCI_QTD_BYTES_MASK |
3706 1.249 skrll EHCI_QTD_TOGGLE_MASK |
3707 1.249 skrll EHCI_QTD_CERR_MASK
3708 1.249 skrll );
3709 1.249 skrll setup->qtd.qtd_status |= htole32(
3710 1.249 skrll EHCI_QTD_ACTIVE |
3711 1.249 skrll EHCI_QTD_SET_CERR(3) |
3712 1.249 skrll EHCI_QTD_SET_TOGGLE(0) |
3713 1.249 skrll EHCI_QTD_SET_BYTES(sizeof(*req))
3714 1.249 skrll );
3715 1.280 skrll
3716 1.280 skrll const bus_addr_t ba = DMAADDR(&epipe->ctrl.reqdma, 0);
3717 1.280 skrll setup->qtd.qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba));
3718 1.280 skrll setup->qtd.qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba));
3719 1.18 augustss
3720 1.249 skrll next = status;
3721 1.249 skrll status->qtd.qtd_status &= ~htole32(
3722 1.249 skrll EHCI_QTD_STATUS_MASK |
3723 1.249 skrll EHCI_QTD_PID_MASK |
3724 1.249 skrll EHCI_QTD_BYTES_MASK |
3725 1.249 skrll EHCI_QTD_TOGGLE_MASK |
3726 1.249 skrll EHCI_QTD_CERR_MASK
3727 1.249 skrll );
3728 1.249 skrll status->qtd.qtd_status |= htole32(
3729 1.249 skrll EHCI_QTD_ACTIVE |
3730 1.249 skrll EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
3731 1.249 skrll EHCI_QTD_SET_CERR(3) |
3732 1.249 skrll EHCI_QTD_SET_TOGGLE(1) |
3733 1.249 skrll EHCI_QTD_SET_BYTES(0) |
3734 1.249 skrll EHCI_QTD_IOC
3735 1.249 skrll );
3736 1.249 skrll KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK));
3737 1.190 mrg
3738 1.249 skrll KASSERT(exfer->ex_isdone);
3739 1.10 augustss #ifdef DIAGNOSTIC
3740 1.249 skrll exfer->ex_isdone = false;
3741 1.10 augustss #endif
3742 1.18 augustss
3743 1.15 augustss /* Set up data transaction */
3744 1.15 augustss if (len != 0) {
3745 1.15 augustss ehci_soft_qtd_t *end;
3746 1.15 augustss
3747 1.55 mycroft /* Start toggle at 1. */
3748 1.249 skrll int toggle = 1;
3749 1.249 skrll next = exfer->ex_data;
3750 1.249 skrll KASSERTMSG(next != NULL, "Failed memory allocation");
3751 1.249 skrll ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end);
3752 1.249 skrll end->nextqtd = status;
3753 1.214 skrll end->qtd.qtd_next = end->qtd.qtd_altnext =
3754 1.249 skrll htole32(status->physaddr);
3755 1.249 skrll
3756 1.138 bouyer usb_syncmem(&end->dma, end->offs, sizeof(end->qtd),
3757 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3758 1.249 skrll
3759 1.249 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
3760 1.249 skrll isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
3761 1.15 augustss }
3762 1.15 augustss
3763 1.15 augustss setup->nextqtd = next;
3764 1.15 augustss setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
3765 1.249 skrll
3766 1.138 bouyer usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd),
3767 1.138 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3768 1.15 augustss
3769 1.249 skrll usb_syncmem(&status->dma, status->offs, sizeof(status->qtd),
3770 1.138 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3771 1.15 augustss
3772 1.249 skrll KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK));
3773 1.249 skrll
3774 1.15 augustss #ifdef EHCI_DEBUG
3775 1.249 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3776 1.229 skrll ehci_dump_sqh(sqh);
3777 1.229 skrll ehci_dump_sqtds(setup);
3778 1.249 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3779 1.15 augustss #endif
3780 1.15 augustss
3781 1.249 skrll /* Insert qTD in QH list - also does usb_syncmem(sqh) */
3782 1.249 skrll ehci_set_qh_qtd(sqh, setup);
3783 1.271 riastrad usbd_xfer_schedule_timeout(xfer);
3784 1.18 augustss ehci_add_intr_list(sc, exfer);
3785 1.249 skrll xfer->ux_status = USBD_IN_PROGRESS;
3786 1.15 augustss
3787 1.249 skrll #if 0
3788 1.17 augustss #ifdef EHCI_DEBUG
3789 1.256 pgoyette DPRINTFN(10, "status=%jx, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0);
3790 1.229 skrll // delay(10000);
3791 1.229 skrll ehci_dump_regs(sc);
3792 1.229 skrll ehci_dump_sqh(sc->sc_async_head);
3793 1.229 skrll ehci_dump_sqh(sqh);
3794 1.229 skrll ehci_dump_sqtds(setup);
3795 1.15 augustss #endif
3796 1.249 skrll #endif
3797 1.249 skrll
3798 1.249 skrll return USBD_IN_PROGRESS;
3799 1.249 skrll }
3800 1.249 skrll
3801 1.249 skrll Static void
3802 1.249 skrll ehci_device_ctrl_done(struct usbd_xfer *xfer)
3803 1.249 skrll {
3804 1.249 skrll ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer);
3805 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
3806 1.249 skrll usb_device_request_t *req = &xfer->ux_request;
3807 1.249 skrll int len = UGETW(req->wLength);
3808 1.249 skrll int rd = req->bmRequestType & UT_READ;
3809 1.249 skrll
3810 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3811 1.256 pgoyette DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3812 1.249 skrll
3813 1.249 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3814 1.249 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
3815 1.249 skrll
3816 1.249 skrll usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req),
3817 1.249 skrll BUS_DMASYNC_POSTWRITE);
3818 1.249 skrll if (len)
3819 1.249 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
3820 1.249 skrll rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3821 1.15 augustss
3822 1.256 pgoyette DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0);
3823 1.249 skrll }
3824 1.249 skrll
3825 1.249 skrll /* Abort a device control request. */
3826 1.249 skrll Static void
3827 1.249 skrll ehci_device_ctrl_abort(struct usbd_xfer *xfer)
3828 1.249 skrll {
3829 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3830 1.249 skrll
3831 1.256 pgoyette DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3832 1.271 riastrad usbd_xfer_abort(xfer);
3833 1.249 skrll }
3834 1.249 skrll
3835 1.249 skrll /* Close a device control pipe. */
3836 1.249 skrll Static void
3837 1.249 skrll ehci_device_ctrl_close(struct usbd_pipe *pipe)
3838 1.249 skrll {
3839 1.249 skrll ehci_softc_t *sc = EHCI_PIPE2SC(pipe);
3840 1.274 skrll struct ehci_pipe * const epipe = EHCI_PIPE2EPIPE(pipe);
3841 1.249 skrll
3842 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3843 1.249 skrll
3844 1.249 skrll KASSERT(mutex_owned(&sc->sc_lock));
3845 1.15 augustss
3846 1.256 pgoyette DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0);
3847 1.249 skrll
3848 1.249 skrll ehci_close_pipe(pipe, sc->sc_async_head);
3849 1.274 skrll
3850 1.293 skrll usb_freemem(&epipe->ctrl.reqdma);
3851 1.10 augustss }
3852 1.10 augustss
3853 1.108 xtraeme /*
3854 1.108 xtraeme * Some EHCI chips from VIA seem to trigger interrupts before writing back the
3855 1.108 xtraeme * qTD status, or miss signalling occasionally under heavy load. If the host
3856 1.283 msaitoh * machine is too fast, we can miss transaction completion - when we scan
3857 1.108 xtraeme * the active list the transaction still seems to be active. This generally
3858 1.108 xtraeme * exhibits itself as a umass stall that never recovers.
3859 1.108 xtraeme *
3860 1.108 xtraeme * We work around this behaviour by setting up this callback after any softintr
3861 1.108 xtraeme * that completes with transactions still pending, giving us another chance to
3862 1.108 xtraeme * check for completion after the writeback has taken place.
3863 1.108 xtraeme */
3864 1.164 uebayasi Static void
3865 1.108 xtraeme ehci_intrlist_timeout(void *arg)
3866 1.108 xtraeme {
3867 1.108 xtraeme ehci_softc_t *sc = arg;
3868 1.108 xtraeme
3869 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3870 1.229 skrll
3871 1.108 xtraeme usb_schedsoftintr(&sc->sc_bus);
3872 1.108 xtraeme }
3873 1.108 xtraeme
3874 1.10 augustss /************************/
3875 1.5 augustss
3876 1.249 skrll Static int
3877 1.249 skrll ehci_device_bulk_init(struct usbd_xfer *xfer)
3878 1.249 skrll {
3879 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3880 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3881 1.249 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
3882 1.249 skrll int endpt = ed->bEndpointAddress;
3883 1.249 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3884 1.249 skrll int len = xfer->ux_bufsize;
3885 1.249 skrll int err = 0;
3886 1.249 skrll
3887 1.249 skrll exfer->ex_type = EX_BULK;
3888 1.249 skrll exfer->ex_nsqtd = 0;
3889 1.249 skrll err = ehci_alloc_sqtd_chain(sc, xfer, len, isread,
3890 1.249 skrll &exfer->ex_sqtdstart);
3891 1.249 skrll
3892 1.249 skrll return err;
3893 1.249 skrll }
3894 1.249 skrll
3895 1.249 skrll Static void
3896 1.249 skrll ehci_device_bulk_fini(struct usbd_xfer *xfer)
3897 1.249 skrll {
3898 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3899 1.249 skrll struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
3900 1.249 skrll
3901 1.249 skrll KASSERT(ex->ex_type == EX_BULK);
3902 1.249 skrll
3903 1.249 skrll ehci_free_sqtds(sc, ex);
3904 1.249 skrll if (ex->ex_nsqtd)
3905 1.249 skrll kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd);
3906 1.249 skrll }
3907 1.249 skrll
3908 1.19 augustss Static usbd_status
3909 1.249 skrll ehci_device_bulk_transfer(struct usbd_xfer *xfer)
3910 1.19 augustss {
3911 1.19 augustss
3912 1.19 augustss /* Pipe isn't running, start first */
3913 1.249 skrll return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3914 1.19 augustss }
3915 1.19 augustss
3916 1.164 uebayasi Static usbd_status
3917 1.249 skrll ehci_device_bulk_start(struct usbd_xfer *xfer)
3918 1.19 augustss {
3919 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
3920 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
3921 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
3922 1.19 augustss ehci_soft_qh_t *sqh;
3923 1.249 skrll ehci_soft_qtd_t *end;
3924 1.19 augustss int len, isread, endpt;
3925 1.19 augustss
3926 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3927 1.229 skrll
3928 1.256 pgoyette DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length,
3929 1.249 skrll xfer->ux_flags, 0);
3930 1.19 augustss
3931 1.305 riastrad KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3932 1.305 riastrad
3933 1.19 augustss if (sc->sc_dying)
3934 1.249 skrll return USBD_IOERROR;
3935 1.249 skrll
3936 1.249 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3937 1.249 skrll KASSERT(xfer->ux_length <= xfer->ux_bufsize);
3938 1.19 augustss
3939 1.249 skrll len = xfer->ux_length;
3940 1.249 skrll endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
3941 1.249 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3942 1.249 skrll sqh = epipe->sqh;
3943 1.249 skrll
3944 1.249 skrll KASSERT(exfer->ex_isdone);
3945 1.19 augustss #ifdef DIAGNOSTIC
3946 1.249 skrll exfer->ex_isdone = false;
3947 1.19 augustss #endif
3948 1.19 augustss
3949 1.249 skrll ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end);
3950 1.19 augustss
3951 1.249 skrll exfer->ex_sqtdend = end;
3952 1.249 skrll end->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
3953 1.249 skrll usb_syncmem(&end->dma, end->offs, sizeof(end->qtd),
3954 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3955 1.19 augustss
3956 1.19 augustss #ifdef EHCI_DEBUG
3957 1.249 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3958 1.229 skrll ehci_dump_sqh(sqh);
3959 1.249 skrll ehci_dump_sqtds(exfer->ex_sqtdstart);
3960 1.249 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3961 1.19 augustss #endif
3962 1.19 augustss
3963 1.269 mrg if (xfer->ux_length)
3964 1.269 mrg usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
3965 1.269 mrg isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
3966 1.19 augustss
3967 1.249 skrll /* also does usb_syncmem(sqh) */
3968 1.249 skrll ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart);
3969 1.271 riastrad usbd_xfer_schedule_timeout(xfer);
3970 1.19 augustss ehci_add_intr_list(sc, exfer);
3971 1.249 skrll xfer->ux_status = USBD_IN_PROGRESS;
3972 1.19 augustss
3973 1.249 skrll #if 0
3974 1.19 augustss #ifdef EHCI_DEBUG
3975 1.249 skrll DPRINTFN(5, "data(2)", 0, 0, 0, 0);
3976 1.229 skrll // delay(10000);
3977 1.249 skrll DPRINTFN(5, "data(3)", 0, 0, 0, 0);
3978 1.229 skrll ehci_dump_regs(sc);
3979 1.29 augustss #if 0
3980 1.229 skrll printf("async_head:\n");
3981 1.229 skrll ehci_dump_sqh(sc->sc_async_head);
3982 1.29 augustss #endif
3983 1.249 skrll DPRINTF("sqh:", 0, 0, 0, 0);
3984 1.229 skrll ehci_dump_sqh(sqh);
3985 1.249 skrll ehci_dump_sqtds(exfer->ex_sqtdstart);
3986 1.249 skrll #endif
3987 1.19 augustss #endif
3988 1.19 augustss
3989 1.249 skrll return USBD_IN_PROGRESS;
3990 1.19 augustss }
3991 1.19 augustss
3992 1.19 augustss Static void
3993 1.249 skrll ehci_device_bulk_abort(struct usbd_xfer *xfer)
3994 1.19 augustss {
3995 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
3996 1.229 skrll
3997 1.256 pgoyette DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0);
3998 1.271 riastrad usbd_xfer_abort(xfer);
3999 1.19 augustss }
4000 1.19 augustss
4001 1.33 augustss /*
4002 1.19 augustss * Close a device bulk pipe.
4003 1.19 augustss */
4004 1.19 augustss Static void
4005 1.249 skrll ehci_device_bulk_close(struct usbd_pipe *pipe)
4006 1.19 augustss {
4007 1.249 skrll ehci_softc_t *sc = EHCI_PIPE2SC(pipe);
4008 1.249 skrll struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);
4009 1.19 augustss
4010 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4011 1.229 skrll
4012 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
4013 1.190 mrg
4014 1.256 pgoyette DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0);
4015 1.249 skrll pipe->up_endpoint->ue_toggle = epipe->nexttoggle;
4016 1.19 augustss ehci_close_pipe(pipe, sc->sc_async_head);
4017 1.19 augustss }
4018 1.19 augustss
4019 1.164 uebayasi Static void
4020 1.249 skrll ehci_device_bulk_done(struct usbd_xfer *xfer)
4021 1.19 augustss {
4022 1.249 skrll ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer);
4023 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4024 1.249 skrll int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4025 1.138 bouyer int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
4026 1.19 augustss
4027 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4028 1.229 skrll
4029 1.256 pgoyette DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0);
4030 1.19 augustss
4031 1.251 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
4032 1.190 mrg
4033 1.269 mrg if (xfer->ux_length)
4034 1.269 mrg usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
4035 1.269 mrg rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
4036 1.19 augustss
4037 1.256 pgoyette DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0);
4038 1.19 augustss }
4039 1.5 augustss
4040 1.10 augustss /************************/
4041 1.10 augustss
4042 1.78 augustss Static usbd_status
4043 1.78 augustss ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival)
4044 1.78 augustss {
4045 1.78 augustss struct ehci_soft_islot *isp;
4046 1.78 augustss int islot, lev;
4047 1.78 augustss
4048 1.78 augustss /* Find a poll rate that is large enough. */
4049 1.78 augustss for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--)
4050 1.78 augustss if (EHCI_ILEV_IVAL(lev) <= ival)
4051 1.78 augustss break;
4052 1.78 augustss
4053 1.78 augustss /* Pick an interrupt slot at the right level. */
4054 1.78 augustss /* XXX could do better than picking at random */
4055 1.78 augustss sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize;
4056 1.78 augustss islot = EHCI_IQHIDX(lev, sc->sc_rand);
4057 1.78 augustss
4058 1.78 augustss sqh->islot = islot;
4059 1.78 augustss isp = &sc->sc_islots[islot];
4060 1.190 mrg mutex_enter(&sc->sc_lock);
4061 1.190 mrg ehci_add_qh(sc, sqh, isp->sqh);
4062 1.190 mrg mutex_exit(&sc->sc_lock);
4063 1.78 augustss
4064 1.249 skrll return USBD_NORMAL_COMPLETION;
4065 1.249 skrll }
4066 1.249 skrll
4067 1.249 skrll Static int
4068 1.249 skrll ehci_device_intr_init(struct usbd_xfer *xfer)
4069 1.249 skrll {
4070 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4071 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4072 1.249 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
4073 1.249 skrll int endpt = ed->bEndpointAddress;
4074 1.249 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
4075 1.249 skrll int len = xfer->ux_bufsize;
4076 1.249 skrll int err;
4077 1.249 skrll
4078 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4079 1.249 skrll
4080 1.256 pgoyette DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length,
4081 1.249 skrll xfer->ux_flags, 0);
4082 1.249 skrll
4083 1.249 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4084 1.249 skrll KASSERT(len != 0);
4085 1.249 skrll
4086 1.249 skrll exfer->ex_type = EX_INTR;
4087 1.249 skrll exfer->ex_nsqtd = 0;
4088 1.249 skrll err = ehci_alloc_sqtd_chain(sc, xfer, len, isread,
4089 1.249 skrll &exfer->ex_sqtdstart);
4090 1.249 skrll
4091 1.249 skrll return err;
4092 1.249 skrll }
4093 1.249 skrll
4094 1.249 skrll Static void
4095 1.249 skrll ehci_device_intr_fini(struct usbd_xfer *xfer)
4096 1.249 skrll {
4097 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4098 1.249 skrll struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
4099 1.249 skrll
4100 1.249 skrll KASSERT(ex->ex_type == EX_INTR);
4101 1.249 skrll
4102 1.249 skrll ehci_free_sqtds(sc, ex);
4103 1.249 skrll if (ex->ex_nsqtd)
4104 1.249 skrll kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd);
4105 1.78 augustss }
4106 1.78 augustss
4107 1.78 augustss Static usbd_status
4108 1.249 skrll ehci_device_intr_transfer(struct usbd_xfer *xfer)
4109 1.78 augustss {
4110 1.78 augustss
4111 1.303 riastrad /* Pipe isn't running, so start it first. */
4112 1.249 skrll return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
4113 1.78 augustss }
4114 1.78 augustss
4115 1.78 augustss Static usbd_status
4116 1.249 skrll ehci_device_intr_start(struct usbd_xfer *xfer)
4117 1.78 augustss {
4118 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4119 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4120 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4121 1.249 skrll ehci_soft_qtd_t *end;
4122 1.78 augustss ehci_soft_qh_t *sqh;
4123 1.78 augustss int len, isread, endpt;
4124 1.78 augustss
4125 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4126 1.229 skrll
4127 1.256 pgoyette DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length,
4128 1.249 skrll xfer->ux_flags, 0);
4129 1.78 augustss
4130 1.305 riastrad KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
4131 1.305 riastrad
4132 1.78 augustss if (sc->sc_dying)
4133 1.249 skrll return USBD_IOERROR;
4134 1.78 augustss
4135 1.249 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4136 1.249 skrll KASSERT(xfer->ux_length <= xfer->ux_bufsize);
4137 1.249 skrll
4138 1.249 skrll len = xfer->ux_length;
4139 1.249 skrll endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4140 1.249 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
4141 1.249 skrll sqh = epipe->sqh;
4142 1.249 skrll
4143 1.249 skrll KASSERT(exfer->ex_isdone);
4144 1.78 augustss #ifdef DIAGNOSTIC
4145 1.249 skrll exfer->ex_isdone = false;
4146 1.78 augustss #endif
4147 1.78 augustss
4148 1.249 skrll ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end);
4149 1.78 augustss
4150 1.249 skrll end->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
4151 1.249 skrll usb_syncmem(&end->dma, end->offs, sizeof(end->qtd),
4152 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4153 1.249 skrll exfer->ex_sqtdend = end;
4154 1.78 augustss
4155 1.78 augustss #ifdef EHCI_DEBUG
4156 1.249 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
4157 1.229 skrll ehci_dump_sqh(sqh);
4158 1.249 skrll ehci_dump_sqtds(exfer->ex_sqtdstart);
4159 1.249 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
4160 1.78 augustss #endif
4161 1.78 augustss
4162 1.269 mrg if (xfer->ux_length)
4163 1.269 mrg usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
4164 1.269 mrg isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
4165 1.78 augustss
4166 1.249 skrll /* also does usb_syncmem(sqh) */
4167 1.249 skrll ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart);
4168 1.271 riastrad usbd_xfer_schedule_timeout(xfer);
4169 1.78 augustss ehci_add_intr_list(sc, exfer);
4170 1.249 skrll xfer->ux_status = USBD_IN_PROGRESS;
4171 1.78 augustss
4172 1.249 skrll #if 0
4173 1.78 augustss #ifdef EHCI_DEBUG
4174 1.249 skrll DPRINTFN(5, "data(2)", 0, 0, 0, 0);
4175 1.229 skrll // delay(10000);
4176 1.249 skrll DPRINTFN(5, "data(3)", 0, 0, 0, 0);
4177 1.229 skrll ehci_dump_regs(sc);
4178 1.249 skrll DPRINTFN(5, "sqh:", 0, 0, 0, 0);
4179 1.229 skrll ehci_dump_sqh(sqh);
4180 1.249 skrll ehci_dump_sqtds(exfer->ex_sqtdstart);
4181 1.249 skrll #endif
4182 1.78 augustss #endif
4183 1.78 augustss
4184 1.249 skrll return USBD_IN_PROGRESS;
4185 1.78 augustss }
4186 1.78 augustss
4187 1.78 augustss Static void
4188 1.249 skrll ehci_device_intr_abort(struct usbd_xfer *xfer)
4189 1.78 augustss {
4190 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4191 1.229 skrll
4192 1.256 pgoyette DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
4193 1.227 skrll
4194 1.139 jmcneill /*
4195 1.139 jmcneill * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance
4196 1.180 wiz * async doorbell. That's dependent on the async list, wheras
4197 1.139 jmcneill * intr xfers are periodic, should not use this?
4198 1.139 jmcneill */
4199 1.271 riastrad usbd_xfer_abort(xfer);
4200 1.78 augustss }
4201 1.78 augustss
4202 1.78 augustss Static void
4203 1.249 skrll ehci_device_intr_close(struct usbd_pipe *pipe)
4204 1.78 augustss {
4205 1.249 skrll ehci_softc_t *sc = EHCI_PIPE2SC(pipe);
4206 1.249 skrll struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);
4207 1.78 augustss struct ehci_soft_islot *isp;
4208 1.78 augustss
4209 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
4210 1.190 mrg
4211 1.78 augustss isp = &sc->sc_islots[epipe->sqh->islot];
4212 1.78 augustss ehci_close_pipe(pipe, isp->sqh);
4213 1.78 augustss }
4214 1.78 augustss
4215 1.78 augustss Static void
4216 1.249 skrll ehci_device_intr_done(struct usbd_xfer *xfer)
4217 1.78 augustss {
4218 1.249 skrll ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer);
4219 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4220 1.249 skrll
4221 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4222 1.249 skrll
4223 1.256 pgoyette DPRINTF("xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 0, 0);
4224 1.249 skrll
4225 1.249 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
4226 1.249 skrll
4227 1.269 mrg if (xfer->ux_length) {
4228 1.269 mrg int isread, endpt;
4229 1.269 mrg
4230 1.269 mrg endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4231 1.269 mrg isread = UE_GET_DIR(endpt) == UE_DIR_IN;
4232 1.269 mrg usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
4233 1.269 mrg isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
4234 1.269 mrg }
4235 1.249 skrll }
4236 1.249 skrll
4237 1.249 skrll /************************/
4238 1.249 skrll Static int
4239 1.249 skrll ehci_device_fs_isoc_init(struct usbd_xfer *xfer)
4240 1.249 skrll {
4241 1.249 skrll struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe);
4242 1.249 skrll struct usbd_device *dev = xfer->ux_pipe->up_dev;
4243 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4244 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4245 1.249 skrll ehci_soft_sitd_t *sitd, *prev, *start, *stop;
4246 1.249 skrll int i, k, frames;
4247 1.249 skrll u_int huba, dir;
4248 1.249 skrll int err;
4249 1.249 skrll
4250 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4251 1.249 skrll
4252 1.249 skrll start = NULL;
4253 1.249 skrll sitd = NULL;
4254 1.249 skrll
4255 1.256 pgoyette DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length,
4256 1.249 skrll xfer->ux_flags, 0);
4257 1.249 skrll
4258 1.249 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4259 1.249 skrll KASSERT(xfer->ux_nframes != 0);
4260 1.249 skrll KASSERT(exfer->ex_isdone);
4261 1.249 skrll
4262 1.249 skrll exfer->ex_type = EX_FS_ISOC;
4263 1.249 skrll /*
4264 1.249 skrll * Step 1: Allocate and initialize sitds.
4265 1.249 skrll */
4266 1.249 skrll i = epipe->pipe.up_endpoint->ue_edesc->bInterval;
4267 1.249 skrll if (i > 16 || i == 0) {
4268 1.249 skrll /* Spec page 271 says intervals > 16 are invalid */
4269 1.256 pgoyette DPRINTF("bInterval %jd invalid", i, 0, 0, 0);
4270 1.249 skrll return EINVAL;
4271 1.249 skrll }
4272 1.229 skrll
4273 1.249 skrll frames = xfer->ux_nframes;
4274 1.249 skrll for (i = 0, prev = NULL; i < frames; i++, prev = sitd) {
4275 1.249 skrll sitd = ehci_alloc_sitd(sc);
4276 1.249 skrll if (sitd == NULL) {
4277 1.249 skrll err = ENOMEM;
4278 1.249 skrll goto fail;
4279 1.249 skrll }
4280 1.78 augustss
4281 1.249 skrll if (prev)
4282 1.249 skrll prev->xfer_next = sitd;
4283 1.249 skrll else
4284 1.249 skrll start = sitd;
4285 1.190 mrg
4286 1.249 skrll huba = dev->ud_myhsport->up_parent->ud_addr;
4287 1.78 augustss
4288 1.249 skrll #if 0
4289 1.249 skrll if (sc->sc_flags & EHCIF_FREESCALE) {
4290 1.249 skrll // Set hub address to 0 if embedded TT is used.
4291 1.249 skrll if (huba == sc->sc_addr)
4292 1.249 skrll huba = 0;
4293 1.78 augustss }
4294 1.249 skrll #endif
4295 1.249 skrll
4296 1.249 skrll k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4297 1.249 skrll dir = UE_GET_DIR(k) ? 1 : 0;
4298 1.249 skrll sitd->sitd.sitd_endp =
4299 1.249 skrll htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) |
4300 1.249 skrll EHCI_SITD_SET_DADDR(dev->ud_addr) |
4301 1.249 skrll EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) |
4302 1.249 skrll EHCI_SITD_SET_HUBA(huba) |
4303 1.249 skrll EHCI_SITD_SET_DIR(dir));
4304 1.249 skrll
4305 1.249 skrll sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE);
4306 1.249 skrll } /* End of frame */
4307 1.249 skrll
4308 1.249 skrll sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC);
4309 1.249 skrll
4310 1.249 skrll stop = sitd;
4311 1.249 skrll stop->xfer_next = NULL;
4312 1.249 skrll exfer->ex_sitdstart = start;
4313 1.249 skrll exfer->ex_sitdend = stop;
4314 1.78 augustss
4315 1.249 skrll return 0;
4316 1.249 skrll
4317 1.249 skrll fail:
4318 1.249 skrll mutex_enter(&sc->sc_lock);
4319 1.249 skrll ehci_soft_sitd_t *next;
4320 1.249 skrll for (sitd = start; sitd; sitd = next) {
4321 1.249 skrll next = sitd->xfer_next;
4322 1.249 skrll ehci_free_sitd_locked(sc, sitd);
4323 1.249 skrll }
4324 1.249 skrll mutex_exit(&sc->sc_lock);
4325 1.249 skrll
4326 1.249 skrll return err;
4327 1.249 skrll }
4328 1.249 skrll
4329 1.249 skrll Static void
4330 1.249 skrll ehci_device_fs_isoc_fini(struct usbd_xfer *xfer)
4331 1.249 skrll {
4332 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4333 1.249 skrll struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
4334 1.249 skrll
4335 1.249 skrll KASSERT(ex->ex_type == EX_FS_ISOC);
4336 1.249 skrll
4337 1.249 skrll ehci_free_sitd_chain(sc, ex->ex_sitdstart);
4338 1.249 skrll }
4339 1.249 skrll
4340 1.249 skrll Static usbd_status
4341 1.249 skrll ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer)
4342 1.249 skrll {
4343 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4344 1.259 maya struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4345 1.259 maya struct usbd_device *dev = xfer->ux_pipe->up_dev;
4346 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4347 1.249 skrll ehci_soft_sitd_t *sitd;
4348 1.249 skrll usb_dma_t *dma_buf;
4349 1.249 skrll int i, j, k, frames;
4350 1.279 skrll int offs;
4351 1.249 skrll int frindex;
4352 1.249 skrll u_int dir;
4353 1.249 skrll
4354 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4355 1.249 skrll
4356 1.249 skrll sitd = NULL;
4357 1.249 skrll
4358 1.256 pgoyette DPRINTF("xfer %#jx len %jd flags %jd", (uintptr_t)xfer, xfer->ux_length,
4359 1.249 skrll xfer->ux_flags, 0);
4360 1.249 skrll
4361 1.305 riastrad KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
4362 1.305 riastrad
4363 1.249 skrll if (sc->sc_dying)
4364 1.249 skrll return USBD_IOERROR;
4365 1.249 skrll
4366 1.249 skrll /*
4367 1.249 skrll * To avoid complication, don't allow a request right now that'll span
4368 1.249 skrll * the entire frame table. To within 4 frames, to allow some leeway
4369 1.249 skrll * on either side of where the hc currently is.
4370 1.249 skrll */
4371 1.249 skrll if (epipe->pipe.up_endpoint->ue_edesc->bInterval *
4372 1.249 skrll xfer->ux_nframes >= sc->sc_flsize - 4) {
4373 1.249 skrll printf("ehci: isoc descriptor requested that spans the entire"
4374 1.312 jakllsch " frametable, too many frames\n");
4375 1.249 skrll return USBD_INVAL;
4376 1.249 skrll }
4377 1.249 skrll
4378 1.249 skrll KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths);
4379 1.249 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4380 1.249 skrll KASSERT(exfer->ex_isdone);
4381 1.78 augustss #ifdef DIAGNOSTIC
4382 1.249 skrll exfer->ex_isdone = false;
4383 1.249 skrll #endif
4384 1.249 skrll
4385 1.249 skrll /*
4386 1.249 skrll * Step 1: Initialize sitds.
4387 1.249 skrll */
4388 1.249 skrll
4389 1.249 skrll frames = xfer->ux_nframes;
4390 1.249 skrll dma_buf = &xfer->ux_dmabuf;
4391 1.249 skrll offs = 0;
4392 1.249 skrll
4393 1.249 skrll for (sitd = exfer->ex_sitdstart, i = 0; i < frames;
4394 1.249 skrll i++, sitd = sitd->xfer_next) {
4395 1.249 skrll KASSERT(sitd != NULL);
4396 1.249 skrll KASSERT(xfer->ux_frlengths[i] <= 0x3ff);
4397 1.249 skrll
4398 1.249 skrll sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE |
4399 1.249 skrll EHCI_SITD_SET_LEN(xfer->ux_frlengths[i]));
4400 1.249 skrll
4401 1.249 skrll /* Set page0 index and offset - TP and T-offset are set below */
4402 1.299 nia const bus_addr_t sba = DMAADDR(dma_buf, offs);
4403 1.299 nia sitd->sitd.sitd_buffer[0] = htole32(BUS_ADDR_LO32(sba));
4404 1.299 nia sitd->sitd.sitd_buffer_hi[0] = htole32(BUS_ADDR_HI32(sba));
4405 1.249 skrll
4406 1.249 skrll offs += xfer->ux_frlengths[i];
4407 1.249 skrll
4408 1.299 nia const bus_addr_t eba = DMAADDR(dma_buf, offs - 1);
4409 1.249 skrll sitd->sitd.sitd_buffer[1] =
4410 1.299 nia htole32(EHCI_SITD_SET_BPTR(BUS_ADDR_LO32(eba)));
4411 1.299 nia sitd->sitd.sitd_buffer_hi[1] = htole32(BUS_ADDR_HI32(eba));
4412 1.249 skrll
4413 1.249 skrll u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr;
4414 1.249 skrll
4415 1.249 skrll #if 0
4416 1.249 skrll if (sc->sc_flags & EHCIF_FREESCALE) {
4417 1.249 skrll // Set hub address to 0 if embedded TT is used.
4418 1.249 skrll if (huba == sc->sc_addr)
4419 1.249 skrll huba = 0;
4420 1.249 skrll }
4421 1.249 skrll #endif
4422 1.249 skrll
4423 1.249 skrll k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4424 1.249 skrll dir = UE_GET_DIR(k) ? 1 : 0;
4425 1.249 skrll KASSERT(sitd->sitd.sitd_endp == htole32(
4426 1.249 skrll EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) |
4427 1.249 skrll EHCI_SITD_SET_DADDR(dev->ud_addr) |
4428 1.249 skrll EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) |
4429 1.249 skrll EHCI_SITD_SET_HUBA(huba) |
4430 1.249 skrll EHCI_SITD_SET_DIR(dir)));
4431 1.249 skrll KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE));
4432 1.249 skrll
4433 1.249 skrll uint8_t sa = 0;
4434 1.249 skrll uint8_t sb = 0;
4435 1.249 skrll u_int temp, tlen;
4436 1.249 skrll
4437 1.249 skrll if (dir == 0) { /* OUT */
4438 1.249 skrll temp = 0;
4439 1.249 skrll tlen = xfer->ux_frlengths[i];
4440 1.249 skrll if (tlen <= 188) {
4441 1.249 skrll temp |= 1; /* T-count = 1, TP = ALL */
4442 1.249 skrll tlen = 1;
4443 1.249 skrll } else {
4444 1.249 skrll tlen += 187;
4445 1.249 skrll tlen /= 188;
4446 1.249 skrll temp |= tlen; /* T-count = [1..6] */
4447 1.249 skrll temp |= 8; /* TP = Begin */
4448 1.249 skrll }
4449 1.249 skrll sitd->sitd.sitd_buffer[1] |= htole32(temp);
4450 1.249 skrll
4451 1.249 skrll tlen += sa;
4452 1.249 skrll
4453 1.249 skrll if (tlen >= 8) {
4454 1.249 skrll sb = 0;
4455 1.249 skrll } else {
4456 1.249 skrll sb = (1 << tlen);
4457 1.249 skrll }
4458 1.249 skrll
4459 1.249 skrll sa = (1 << sa);
4460 1.249 skrll sa = (sb - sa) & 0x3F;
4461 1.249 skrll sb = 0;
4462 1.249 skrll } else {
4463 1.249 skrll sb = (-(4 << sa)) & 0xFE;
4464 1.249 skrll sa = (1 << sa) & 0x3F;
4465 1.249 skrll sa = 0x01;
4466 1.249 skrll sb = 0xfc;
4467 1.249 skrll }
4468 1.249 skrll
4469 1.249 skrll sitd->sitd.sitd_sched = htole32(
4470 1.249 skrll EHCI_SITD_SET_SMASK(sa) |
4471 1.249 skrll EHCI_SITD_SET_CMASK(sb)
4472 1.249 skrll );
4473 1.249 skrll
4474 1.249 skrll usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t),
4475 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4476 1.249 skrll } /* End of frame */
4477 1.249 skrll
4478 1.249 skrll sitd = exfer->ex_sitdend;
4479 1.249 skrll sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC);
4480 1.249 skrll
4481 1.249 skrll usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans),
4482 1.249 skrll sizeof(sitd->sitd.sitd_trans),
4483 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4484 1.249 skrll
4485 1.279 skrll if (xfer->ux_length)
4486 1.279 skrll usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length,
4487 1.269 mrg BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4488 1.249 skrll
4489 1.249 skrll /*
4490 1.249 skrll * Part 2: Transfer descriptors have now been set up, now they must
4491 1.249 skrll * be scheduled into the periodic frame list. Erk. Not wanting to
4492 1.249 skrll * complicate matters, transfer is denied if the transfer spans
4493 1.313 jakllsch * more than the periodic frame list.
4494 1.249 skrll */
4495 1.249 skrll
4496 1.249 skrll /* Start inserting frames */
4497 1.249 skrll if (epipe->isoc.cur_xfers > 0) {
4498 1.249 skrll frindex = epipe->isoc.next_frame;
4499 1.249 skrll } else {
4500 1.249 skrll frindex = EOREAD4(sc, EHCI_FRINDEX);
4501 1.249 skrll frindex = frindex >> 3; /* Erase microframe index */
4502 1.249 skrll frindex += 2;
4503 1.78 augustss }
4504 1.249 skrll
4505 1.249 skrll if (frindex >= sc->sc_flsize)
4506 1.249 skrll frindex &= (sc->sc_flsize - 1);
4507 1.249 skrll
4508 1.315 jakllsch /* What's the frame interval? */
4509 1.249 skrll i = epipe->pipe.up_endpoint->ue_edesc->bInterval;
4510 1.249 skrll
4511 1.249 skrll for (sitd = exfer->ex_sitdstart, j = 0; j < frames;
4512 1.249 skrll j++, sitd = sitd->xfer_next) {
4513 1.249 skrll KASSERT(sitd);
4514 1.249 skrll
4515 1.249 skrll usb_syncmem(&sc->sc_fldma,
4516 1.249 skrll sizeof(ehci_link_t) * frindex,
4517 1.249 skrll sizeof(ehci_link_t),
4518 1.249 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
4519 1.249 skrll
4520 1.249 skrll sitd->sitd.sitd_next = sc->sc_flist[frindex];
4521 1.249 skrll if (sitd->sitd.sitd_next == 0)
4522 1.249 skrll /*
4523 1.249 skrll * FIXME: frindex table gets initialized to NULL
4524 1.249 skrll * or EHCI_NULL?
4525 1.249 skrll */
4526 1.249 skrll sitd->sitd.sitd_next = EHCI_NULL;
4527 1.249 skrll
4528 1.249 skrll usb_syncmem(&sitd->dma,
4529 1.249 skrll sitd->offs + offsetof(ehci_sitd_t, sitd_next),
4530 1.249 skrll sizeof(ehci_sitd_t),
4531 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4532 1.249 skrll
4533 1.249 skrll sc->sc_flist[frindex] =
4534 1.249 skrll htole32(EHCI_LINK_SITD | sitd->physaddr);
4535 1.249 skrll
4536 1.249 skrll usb_syncmem(&sc->sc_fldma,
4537 1.249 skrll sizeof(ehci_link_t) * frindex,
4538 1.249 skrll sizeof(ehci_link_t),
4539 1.249 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4540 1.249 skrll
4541 1.249 skrll sitd->frame_list.next = sc->sc_softsitds[frindex];
4542 1.249 skrll sc->sc_softsitds[frindex] = sitd;
4543 1.249 skrll if (sitd->frame_list.next != NULL)
4544 1.249 skrll sitd->frame_list.next->frame_list.prev = sitd;
4545 1.249 skrll sitd->slot = frindex;
4546 1.249 skrll sitd->frame_list.prev = NULL;
4547 1.249 skrll
4548 1.249 skrll frindex += i;
4549 1.249 skrll if (frindex >= sc->sc_flsize)
4550 1.249 skrll frindex -= sc->sc_flsize;
4551 1.249 skrll }
4552 1.249 skrll
4553 1.249 skrll epipe->isoc.cur_xfers++;
4554 1.249 skrll epipe->isoc.next_frame = frindex;
4555 1.249 skrll
4556 1.249 skrll ehci_add_intr_list(sc, exfer);
4557 1.249 skrll xfer->ux_status = USBD_IN_PROGRESS;
4558 1.249 skrll
4559 1.249 skrll return USBD_IN_PROGRESS;
4560 1.249 skrll }
4561 1.249 skrll
4562 1.249 skrll Static void
4563 1.249 skrll ehci_device_fs_isoc_abort(struct usbd_xfer *xfer)
4564 1.249 skrll {
4565 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4566 1.249 skrll
4567 1.256 pgoyette DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0);
4568 1.249 skrll ehci_abort_isoc_xfer(xfer, USBD_CANCELLED);
4569 1.78 augustss }
4570 1.10 augustss
4571 1.249 skrll Static void
4572 1.249 skrll ehci_device_fs_isoc_close(struct usbd_pipe *pipe)
4573 1.249 skrll {
4574 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4575 1.249 skrll
4576 1.249 skrll DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0);
4577 1.249 skrll }
4578 1.249 skrll
4579 1.249 skrll Static void
4580 1.249 skrll ehci_device_fs_isoc_done(struct usbd_xfer *xfer)
4581 1.249 skrll {
4582 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4583 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4584 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4585 1.249 skrll
4586 1.249 skrll KASSERT(mutex_owned(&sc->sc_lock));
4587 1.249 skrll
4588 1.249 skrll epipe->isoc.cur_xfers--;
4589 1.249 skrll ehci_remove_sitd_chain(sc, exfer->ex_itdstart);
4590 1.249 skrll
4591 1.269 mrg if (xfer->ux_length)
4592 1.269 mrg usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
4593 1.269 mrg BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
4594 1.249 skrll }
4595 1.249 skrll
4596 1.267 maxv /* -------------------------------------------------------------------------- */
4597 1.249 skrll
4598 1.249 skrll Static int
4599 1.249 skrll ehci_device_isoc_init(struct usbd_xfer *xfer)
4600 1.113 christos {
4601 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4602 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4603 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4604 1.249 skrll ehci_soft_itd_t *itd, *prev, *start, *stop;
4605 1.249 skrll int i, j, k;
4606 1.249 skrll int frames, ufrperframe;
4607 1.249 skrll int err;
4608 1.249 skrll
4609 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4610 1.249 skrll
4611 1.249 skrll start = NULL;
4612 1.249 skrll prev = NULL;
4613 1.249 skrll itd = NULL;
4614 1.249 skrll
4615 1.249 skrll KASSERT(xfer->ux_nframes != 0);
4616 1.249 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4617 1.249 skrll KASSERT(exfer->ex_isdone);
4618 1.249 skrll
4619 1.249 skrll exfer->ex_type = EX_ISOC;
4620 1.249 skrll
4621 1.249 skrll /*
4622 1.249 skrll * Step 1: Allocate and initialize itds, how many do we need?
4623 1.249 skrll * One per transfer if interval >= 8 microframes, less if we use
4624 1.249 skrll * multiple microframes per frame.
4625 1.249 skrll */
4626 1.249 skrll i = epipe->pipe.up_endpoint->ue_edesc->bInterval;
4627 1.249 skrll if (i > 16 || i == 0) {
4628 1.249 skrll /* Spec page 271 says intervals > 16 are invalid */
4629 1.256 pgoyette DPRINTF("bInterval %jd invalid", i, 0, 0, 0);
4630 1.314 jakllsch return EINVAL;
4631 1.249 skrll }
4632 1.249 skrll
4633 1.262 riastrad ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1)));
4634 1.275 skrll frames = howmany(xfer->ux_nframes, ufrperframe);
4635 1.249 skrll
4636 1.249 skrll for (i = 0, prev = NULL; i < frames; i++, prev = itd) {
4637 1.249 skrll itd = ehci_alloc_itd(sc);
4638 1.249 skrll if (itd == NULL) {
4639 1.249 skrll err = ENOMEM;
4640 1.249 skrll goto fail;
4641 1.249 skrll }
4642 1.249 skrll
4643 1.249 skrll if (prev != NULL) {
4644 1.249 skrll /* Maybe not as it's updated by the scheduling? */
4645 1.249 skrll prev->itd.itd_next =
4646 1.249 skrll htole32(itd->physaddr | EHCI_LINK_ITD);
4647 1.249 skrll
4648 1.249 skrll prev->xfer_next = itd;
4649 1.249 skrll } else {
4650 1.249 skrll start = itd;
4651 1.249 skrll }
4652 1.249 skrll
4653 1.249 skrll /*
4654 1.249 skrll * Other special values
4655 1.249 skrll */
4656 1.249 skrll k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4657 1.249 skrll itd->itd.itd_bufr[0] = htole32(
4658 1.249 skrll EHCI_ITD_SET_EP(UE_GET_ADDR(k)) |
4659 1.249 skrll EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr));
4660 1.249 skrll
4661 1.249 skrll k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress))
4662 1.249 skrll ? 1 : 0;
4663 1.249 skrll j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
4664 1.249 skrll itd->itd.itd_bufr[1] |= htole32(
4665 1.249 skrll EHCI_ITD_SET_DIR(k) |
4666 1.249 skrll EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j)));
4667 1.249 skrll
4668 1.249 skrll /* FIXME: handle invalid trans - should be done in openpipe */
4669 1.249 skrll itd->itd.itd_bufr[2] |=
4670 1.249 skrll htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1));
4671 1.249 skrll } /* End of frame */
4672 1.249 skrll
4673 1.249 skrll stop = itd;
4674 1.249 skrll stop->xfer_next = NULL;
4675 1.249 skrll
4676 1.249 skrll exfer->ex_itdstart = start;
4677 1.249 skrll exfer->ex_itdend = stop;
4678 1.139 jmcneill
4679 1.249 skrll return 0;
4680 1.249 skrll fail:
4681 1.190 mrg mutex_enter(&sc->sc_lock);
4682 1.249 skrll ehci_soft_itd_t *next;
4683 1.249 skrll for (itd = start; itd; itd = next) {
4684 1.249 skrll next = itd->xfer_next;
4685 1.249 skrll ehci_free_itd_locked(sc, itd);
4686 1.249 skrll }
4687 1.190 mrg mutex_exit(&sc->sc_lock);
4688 1.139 jmcneill
4689 1.249 skrll return err;
4690 1.249 skrll
4691 1.249 skrll }
4692 1.249 skrll
4693 1.249 skrll Static void
4694 1.249 skrll ehci_device_isoc_fini(struct usbd_xfer *xfer)
4695 1.249 skrll {
4696 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4697 1.249 skrll struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer);
4698 1.249 skrll
4699 1.249 skrll KASSERT(ex->ex_type == EX_ISOC);
4700 1.249 skrll
4701 1.249 skrll ehci_free_itd_chain(sc, ex->ex_itdstart);
4702 1.113 christos }
4703 1.139 jmcneill
4704 1.113 christos Static usbd_status
4705 1.249 skrll ehci_device_isoc_transfer(struct usbd_xfer *xfer)
4706 1.113 christos {
4707 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4708 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4709 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4710 1.249 skrll ehci_soft_itd_t *itd, *prev;
4711 1.139 jmcneill usb_dma_t *dma_buf;
4712 1.249 skrll int i, j;
4713 1.249 skrll int frames, uframes, ufrperframe;
4714 1.279 skrll int trans_count, offs;
4715 1.139 jmcneill int frindex;
4716 1.139 jmcneill
4717 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4718 1.229 skrll
4719 1.139 jmcneill prev = NULL;
4720 1.139 jmcneill itd = NULL;
4721 1.139 jmcneill trans_count = 0;
4722 1.139 jmcneill
4723 1.256 pgoyette DPRINTF("xfer %#jx flags %jd", (uintptr_t)xfer, xfer->ux_flags, 0, 0);
4724 1.139 jmcneill
4725 1.305 riastrad KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
4726 1.305 riastrad
4727 1.139 jmcneill if (sc->sc_dying)
4728 1.139 jmcneill return USBD_IOERROR;
4729 1.139 jmcneill
4730 1.139 jmcneill /*
4731 1.139 jmcneill * To avoid complication, don't allow a request right now that'll span
4732 1.139 jmcneill * the entire frame table. To within 4 frames, to allow some leeway
4733 1.139 jmcneill * on either side of where the hc currently is.
4734 1.139 jmcneill */
4735 1.249 skrll if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) *
4736 1.249 skrll xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) {
4737 1.249 skrll DPRINTF(
4738 1.229 skrll "isoc descriptor spans entire frametable", 0, 0, 0, 0);
4739 1.139 jmcneill printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n");
4740 1.139 jmcneill return USBD_INVAL;
4741 1.139 jmcneill }
4742 1.139 jmcneill
4743 1.249 skrll KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths);
4744 1.249 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
4745 1.249 skrll KASSERT(exfer->ex_isdone);
4746 1.139 jmcneill #ifdef DIAGNOSTIC
4747 1.249 skrll exfer->ex_isdone = false;
4748 1.139 jmcneill #endif
4749 1.139 jmcneill
4750 1.139 jmcneill /*
4751 1.249 skrll * Step 1: Re-Initialize itds
4752 1.139 jmcneill */
4753 1.139 jmcneill
4754 1.249 skrll i = epipe->pipe.up_endpoint->ue_edesc->bInterval;
4755 1.139 jmcneill if (i > 16 || i == 0) {
4756 1.139 jmcneill /* Spec page 271 says intervals > 16 are invalid */
4757 1.256 pgoyette DPRINTF("bInterval %jd invalid", i, 0, 0, 0);
4758 1.139 jmcneill return USBD_INVAL;
4759 1.139 jmcneill }
4760 1.139 jmcneill
4761 1.262 riastrad ufrperframe = uimax(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1)));
4762 1.275 skrll frames = howmany(xfer->ux_nframes, ufrperframe);
4763 1.168 jakllsch uframes = USB_UFRAMES_PER_FRAME / ufrperframe;
4764 1.142 drochner
4765 1.139 jmcneill if (frames == 0) {
4766 1.249 skrll DPRINTF("frames == 0", 0, 0, 0, 0);
4767 1.139 jmcneill return USBD_INVAL;
4768 1.139 jmcneill }
4769 1.139 jmcneill
4770 1.249 skrll dma_buf = &xfer->ux_dmabuf;
4771 1.139 jmcneill offs = 0;
4772 1.139 jmcneill
4773 1.249 skrll itd = exfer->ex_itdstart;
4774 1.249 skrll for (i = 0; i < frames; i++, itd = itd->xfer_next) {
4775 1.139 jmcneill int froffs = offs;
4776 1.139 jmcneill
4777 1.139 jmcneill if (prev != NULL) {
4778 1.139 jmcneill prev->itd.itd_next =
4779 1.139 jmcneill htole32(itd->physaddr | EHCI_LINK_ITD);
4780 1.249 skrll usb_syncmem(&prev->dma,
4781 1.249 skrll prev->offs + offsetof(ehci_itd_t, itd_next),
4782 1.249 skrll sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE);
4783 1.139 jmcneill prev->xfer_next = itd;
4784 1.139 jmcneill }
4785 1.139 jmcneill
4786 1.139 jmcneill /*
4787 1.139 jmcneill * Step 1.5, initialize uframes
4788 1.139 jmcneill */
4789 1.168 jakllsch for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) {
4790 1.139 jmcneill /* Calculate which page in the list this starts in */
4791 1.139 jmcneill int addr = DMAADDR(dma_buf, froffs);
4792 1.139 jmcneill addr = EHCI_PAGE_OFFSET(addr);
4793 1.139 jmcneill addr += (offs - froffs);
4794 1.139 jmcneill addr = EHCI_PAGE(addr);
4795 1.139 jmcneill addr /= EHCI_PAGE_SIZE;
4796 1.139 jmcneill
4797 1.249 skrll /*
4798 1.249 skrll * This gets the initial offset into the first page,
4799 1.139 jmcneill * looks how far further along the current uframe
4800 1.139 jmcneill * offset is. Works out how many pages that is.
4801 1.139 jmcneill */
4802 1.139 jmcneill
4803 1.139 jmcneill itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE |
4804 1.249 skrll EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) |
4805 1.139 jmcneill EHCI_ITD_SET_PG(addr) |
4806 1.139 jmcneill EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs))));
4807 1.139 jmcneill
4808 1.249 skrll offs += xfer->ux_frlengths[trans_count];
4809 1.139 jmcneill trans_count++;
4810 1.139 jmcneill
4811 1.249 skrll if (trans_count >= xfer->ux_nframes) { /*Set IOC*/
4812 1.139 jmcneill itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC);
4813 1.145 drochner break;
4814 1.139 jmcneill }
4815 1.195 christos }
4816 1.139 jmcneill
4817 1.249 skrll /*
4818 1.249 skrll * Step 1.75, set buffer pointers. To simplify matters, all
4819 1.139 jmcneill * pointers are filled out for the next 7 hardware pages in
4820 1.139 jmcneill * the dma block, so no need to worry what pages to cover
4821 1.139 jmcneill * and what to not.
4822 1.139 jmcneill */
4823 1.139 jmcneill
4824 1.168 jakllsch for (j = 0; j < EHCI_ITD_NBUFFERS; j++) {
4825 1.139 jmcneill /*
4826 1.139 jmcneill * Don't try to lookup a page that's past the end
4827 1.139 jmcneill * of buffer
4828 1.139 jmcneill */
4829 1.139 jmcneill int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j));
4830 1.249 skrll if (page_offs >= dma_buf->udma_block->size)
4831 1.139 jmcneill break;
4832 1.139 jmcneill
4833 1.249 skrll uint64_t page = DMAADDR(dma_buf, page_offs);
4834 1.139 jmcneill page = EHCI_PAGE(page);
4835 1.249 skrll itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page));
4836 1.249 skrll itd->itd.itd_bufr_hi[j] = htole32(page >> 32);
4837 1.139 jmcneill }
4838 1.139 jmcneill /*
4839 1.139 jmcneill * Other special values
4840 1.139 jmcneill */
4841 1.139 jmcneill
4842 1.249 skrll int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
4843 1.139 jmcneill itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) |
4844 1.249 skrll EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr));
4845 1.139 jmcneill
4846 1.249 skrll k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress))
4847 1.139 jmcneill ? 1 : 0;
4848 1.249 skrll j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
4849 1.139 jmcneill itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) |
4850 1.139 jmcneill EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j)));
4851 1.139 jmcneill
4852 1.139 jmcneill /* FIXME: handle invalid trans */
4853 1.195 christos itd->itd.itd_bufr[2] |=
4854 1.139 jmcneill htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1));
4855 1.139 jmcneill
4856 1.249 skrll usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t),
4857 1.139 jmcneill BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4858 1.139 jmcneill
4859 1.139 jmcneill prev = itd;
4860 1.139 jmcneill } /* End of frame */
4861 1.139 jmcneill
4862 1.279 skrll if (xfer->ux_length)
4863 1.279 skrll usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, xfer->ux_length,
4864 1.269 mrg BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4865 1.155 jmorse
4866 1.139 jmcneill /*
4867 1.139 jmcneill * Part 2: Transfer descriptors have now been set up, now they must
4868 1.313 jakllsch * be scheduled into the periodic frame list. Erk. Not wanting to
4869 1.139 jmcneill * complicate matters, transfer is denied if the transfer spans
4870 1.313 jakllsch * more than the periodic frame list.
4871 1.139 jmcneill */
4872 1.139 jmcneill
4873 1.139 jmcneill /* Start inserting frames */
4874 1.249 skrll if (epipe->isoc.cur_xfers > 0) {
4875 1.249 skrll frindex = epipe->isoc.next_frame;
4876 1.139 jmcneill } else {
4877 1.139 jmcneill frindex = EOREAD4(sc, EHCI_FRINDEX);
4878 1.139 jmcneill frindex = frindex >> 3; /* Erase microframe index */
4879 1.139 jmcneill frindex += 2;
4880 1.139 jmcneill }
4881 1.139 jmcneill
4882 1.139 jmcneill if (frindex >= sc->sc_flsize)
4883 1.139 jmcneill frindex &= (sc->sc_flsize - 1);
4884 1.139 jmcneill
4885 1.168 jakllsch /* What's the frame interval? */
4886 1.249 skrll i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1));
4887 1.168 jakllsch if (i / USB_UFRAMES_PER_FRAME == 0)
4888 1.139 jmcneill i = 1;
4889 1.139 jmcneill else
4890 1.168 jakllsch i /= USB_UFRAMES_PER_FRAME;
4891 1.139 jmcneill
4892 1.249 skrll itd = exfer->ex_itdstart;
4893 1.139 jmcneill for (j = 0; j < frames; j++) {
4894 1.249 skrll KASSERTMSG(itd != NULL, "frame %d\n", j);
4895 1.249 skrll
4896 1.249 skrll usb_syncmem(&sc->sc_fldma,
4897 1.249 skrll sizeof(ehci_link_t) * frindex,
4898 1.249 skrll sizeof(ehci_link_t),
4899 1.249 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
4900 1.139 jmcneill
4901 1.139 jmcneill itd->itd.itd_next = sc->sc_flist[frindex];
4902 1.139 jmcneill if (itd->itd.itd_next == 0)
4903 1.249 skrll /*
4904 1.249 skrll * FIXME: frindex table gets initialized to NULL
4905 1.249 skrll * or EHCI_NULL?
4906 1.249 skrll */
4907 1.162 uebayasi itd->itd.itd_next = EHCI_NULL;
4908 1.139 jmcneill
4909 1.139 jmcneill usb_syncmem(&itd->dma,
4910 1.139 jmcneill itd->offs + offsetof(ehci_itd_t, itd_next),
4911 1.249 skrll sizeof(itd->itd.itd_next),
4912 1.139 jmcneill BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4913 1.139 jmcneill
4914 1.139 jmcneill sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr);
4915 1.139 jmcneill
4916 1.139 jmcneill usb_syncmem(&sc->sc_fldma,
4917 1.139 jmcneill sizeof(ehci_link_t) * frindex,
4918 1.249 skrll sizeof(ehci_link_t),
4919 1.139 jmcneill BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4920 1.139 jmcneill
4921 1.249 skrll itd->frame_list.next = sc->sc_softitds[frindex];
4922 1.139 jmcneill sc->sc_softitds[frindex] = itd;
4923 1.249 skrll if (itd->frame_list.next != NULL)
4924 1.249 skrll itd->frame_list.next->frame_list.prev = itd;
4925 1.139 jmcneill itd->slot = frindex;
4926 1.249 skrll itd->frame_list.prev = NULL;
4927 1.139 jmcneill
4928 1.139 jmcneill frindex += i;
4929 1.139 jmcneill if (frindex >= sc->sc_flsize)
4930 1.139 jmcneill frindex -= sc->sc_flsize;
4931 1.139 jmcneill
4932 1.139 jmcneill itd = itd->xfer_next;
4933 1.139 jmcneill }
4934 1.139 jmcneill
4935 1.249 skrll epipe->isoc.cur_xfers++;
4936 1.249 skrll epipe->isoc.next_frame = frindex;
4937 1.139 jmcneill
4938 1.249 skrll ehci_add_intr_list(sc, exfer);
4939 1.249 skrll xfer->ux_status = USBD_IN_PROGRESS;
4940 1.139 jmcneill
4941 1.139 jmcneill return USBD_IN_PROGRESS;
4942 1.113 christos }
4943 1.139 jmcneill
4944 1.113 christos Static void
4945 1.249 skrll ehci_device_isoc_abort(struct usbd_xfer *xfer)
4946 1.113 christos {
4947 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4948 1.229 skrll
4949 1.256 pgoyette DPRINTF("xfer = %#jx", (uintptr_t)xfer, 0, 0, 0);
4950 1.139 jmcneill ehci_abort_isoc_xfer(xfer, USBD_CANCELLED);
4951 1.113 christos }
4952 1.139 jmcneill
4953 1.113 christos Static void
4954 1.249 skrll ehci_device_isoc_close(struct usbd_pipe *pipe)
4955 1.113 christos {
4956 1.249 skrll EHCIHIST_FUNC(); EHCIHIST_CALLED();
4957 1.229 skrll
4958 1.249 skrll DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0);
4959 1.113 christos }
4960 1.139 jmcneill
4961 1.113 christos Static void
4962 1.249 skrll ehci_device_isoc_done(struct usbd_xfer *xfer)
4963 1.113 christos {
4964 1.249 skrll struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer);
4965 1.249 skrll ehci_softc_t *sc = EHCI_XFER2SC(xfer);
4966 1.249 skrll struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);
4967 1.139 jmcneill
4968 1.190 mrg KASSERT(mutex_owned(&sc->sc_lock));
4969 1.190 mrg
4970 1.249 skrll epipe->isoc.cur_xfers--;
4971 1.249 skrll ehci_remove_itd_chain(sc, exfer->ex_sitdstart);
4972 1.269 mrg if (xfer->ux_length)
4973 1.269 mrg usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
4974 1.269 mrg BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
4975 1.113 christos }
4976